1 /* $NetBSD: rt2860.c,v 1.21 2016/07/13 00:01:27 christos Exp $ */ 2 /* $OpenBSD: rt2860.c,v 1.90 2016/04/13 10:49:26 mpi Exp $ */ 3 /* $FreeBSD: head/sys/dev/ral/rt2860.c 297793 2016-04-10 23:07:00Z pfg $ */ 4 5 /*- 6 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 7 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 24 * http://www.ralinktech.com/ 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: rt2860.c,v 1.21 2016/07/13 00:01:27 christos Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/sockio.h> 32 #include <sys/sysctl.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/queue.h> 39 #include <sys/callout.h> 40 #include <sys/module.h> 41 #include <sys/conf.h> 42 #include <sys/device.h> 43 #include <sys/endian.h> 44 #include <sys/cprng.h> 45 46 #include <sys/bus.h> 47 #include <sys/intr.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_ether.h> 53 #include <net/if_media.h> 54 55 #include <net80211/ieee80211_var.h> 56 #include <net80211/ieee80211_amrr.h> 57 #include <net80211/ieee80211_radiotap.h> 58 59 #include <dev/firmload.h> 60 61 #include <dev/ic/rt2860var.h> 62 #include <dev/ic/rt2860reg.h> 63 64 #include <dev/pci/pcidevs.h> 65 66 #ifdef RAL_DEBUG 67 #define DPRINTF(x) do { if (rt2860_debug > 0) printf x; } while (0) 68 #define DPRINTFN(n, x) do { if (rt2860_debug >= (n)) printf x; } while (0) 69 int rt2860_debug = 0; 70 #else 71 #define DPRINTF(x) 72 #define DPRINTFN(n, x) 73 #endif 74 #define MAXQS 6 /* Tx (4 EDCAs + HCCA + Mgt) and Rx rings */ 75 76 static void rt2860_attachhook(device_t); 77 static int rt2860_alloc_tx_ring(struct rt2860_softc *, 78 struct rt2860_tx_ring *); 79 static void rt2860_reset_tx_ring(struct rt2860_softc *, 80 struct rt2860_tx_ring *); 81 static void rt2860_free_tx_ring(struct rt2860_softc *, 82 struct rt2860_tx_ring *); 83 static int rt2860_alloc_tx_pool(struct rt2860_softc *); 84 static void rt2860_free_tx_pool(struct rt2860_softc *); 85 static int rt2860_alloc_rx_ring(struct rt2860_softc *, 86 struct rt2860_rx_ring *); 87 static void rt2860_reset_rx_ring(struct rt2860_softc *, 88 struct rt2860_rx_ring *); 89 static void rt2860_free_rx_ring(struct rt2860_softc *, 90 struct rt2860_rx_ring *); 91 static struct ieee80211_node *rt2860_node_alloc(struct ieee80211_node_table *); 92 static int rt2860_media_change(struct ifnet *); 93 static void rt2860_iter_func(void *, struct ieee80211_node *); 94 static void rt2860_updatestats(struct rt2860_softc *); 95 static void rt2860_update_promisc(struct ifnet *); 96 static void rt2860_newassoc(struct ieee80211_node *, 97 int); 98 #ifdef notyet 99 static int rt2860_ampdu_rx_start(struct ieee80211com *, 100 struct ieee80211_node *, uint8_t); 101 static void rt2860_ampdu_rx_stop(struct ieee80211com *, 102 struct ieee80211_node *, uint8_t); 103 #endif 104 static int rt2860_newstate(struct ieee80211com *, enum ieee80211_state, 105 int); 106 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 107 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 108 static void rt2860_intr_coherent(struct rt2860_softc *); 109 static void rt2860_drain_stats_fifo(struct rt2860_softc *); 110 static void rt2860_tx_intr(struct rt2860_softc *, int); 111 static void rt2860_rx_intr(struct rt2860_softc *); 112 static void rt2860_tbtt_intr(struct rt2860_softc *); 113 static void rt2860_gp_intr(struct rt2860_softc *); 114 static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 115 struct ieee80211_node *); 116 static void rt2860_start(struct ifnet *); 117 static void rt2860_watchdog(struct ifnet *); 118 static int rt2860_ioctl(struct ifnet *, u_long, void *); 119 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 120 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 121 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 122 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 123 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 124 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 125 static void rt2860_enable_mrr(struct rt2860_softc *); 126 static void rt2860_set_txpreamble(struct rt2860_softc *); 127 static void rt2860_set_basicrates(struct rt2860_softc *); 128 static void rt2860_select_chan_group(struct rt2860_softc *, int); 129 static void rt2860_set_chan(struct rt2860_softc *, u_int); 130 static void rt3090_set_chan(struct rt2860_softc *, u_int); 131 static void rt5390_set_chan(struct rt2860_softc *, u_int); 132 static void rt3090_rf_init(struct rt2860_softc *); 133 static void rt5390_rf_init(struct rt2860_softc *); 134 static void rt3090_rf_wakeup(struct rt2860_softc *); 135 static void rt5390_rf_wakeup(struct rt2860_softc *); 136 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 137 uint8_t *); 138 static void rt3090_rf_setup(struct rt2860_softc *); 139 static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 140 static void rt2860_set_gp_timer(struct rt2860_softc *, int); 141 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 142 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 143 static void rt2860_updateslot(struct ifnet *); 144 static void rt2860_updateprot(struct ieee80211com *); 145 static int rt2860_updateedca(struct ieee80211com *); 146 147 #ifdef HW_CRYPTO 148 static int rt2860_set_key(struct ieee80211com *, 149 const struct ieee80211_key *, const uint8_t *); 150 static int rt2860_delete_key(struct ieee80211com *, 151 const struct ieee80211_key *); 152 #endif 153 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 154 static const char * rt2860_get_rf(uint32_t); 155 static int rt2860_read_eeprom(struct rt2860_softc *); 156 static int rt2860_bbp_init(struct rt2860_softc *); 157 static int rt5390_bbp_init(struct rt2860_softc *); 158 static int rt2860_txrx_enable(struct rt2860_softc *); 159 static int rt2860_init(struct ifnet *); 160 static void rt2860_stop(struct ifnet *, int); 161 static int rt2860_load_microcode(struct rt2860_softc *); 162 #if 0 163 static void rt2860_calib(struct rt2860_softc *); 164 #endif 165 static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 166 static void rt2860_switch_chan(struct rt2860_softc *, 167 struct ieee80211_channel *); 168 #ifndef IEEE80211_STA_ONLY 169 static int rt2860_setup_beacon(struct rt2860_softc *); 170 #endif 171 static void rt2860_enable_tsf_sync(struct rt2860_softc *); 172 173 static const struct { 174 uint32_t reg; 175 uint32_t val; 176 } rt2860_def_mac[] = { 177 RT2860_DEF_MAC 178 }; 179 180 static const struct { 181 uint8_t reg; 182 uint8_t val; 183 } rt2860_def_bbp[] = { 184 RT2860_DEF_BBP 185 }, rt5390_def_bbp[] = { 186 RT5390_DEF_BBP 187 }; 188 189 static const struct rfprog { 190 uint8_t chan; 191 uint32_t r1, r2, r3, r4; 192 } rt2860_rf2850[] = { 193 RT2860_RF2850 194 }; 195 196 struct { 197 uint8_t n, r, k; 198 } rt3090_freqs[] = { 199 RT3070_RF3052 200 }; 201 202 static const struct { 203 uint8_t reg; 204 uint8_t val; 205 } rt3090_def_rf[] = { 206 RT3070_DEF_RF 207 }, rt3572_def_rf[] = { 208 RT3572_DEF_RF 209 }, rt5390_def_rf[] = { 210 RT5390_DEF_RF 211 }, rt5392_def_rf[] = { 212 RT5392_DEF_RF 213 }; 214 215 int 216 rt2860_attach(void *xsc, int id) 217 { 218 struct rt2860_softc *sc = xsc; 219 struct ieee80211com *ic = &sc->sc_ic; 220 int qid, ntries, error; 221 uint32_t tmp; 222 223 sc->amrr.amrr_min_success_threshold = 1; 224 sc->amrr.amrr_max_success_threshold = 15; 225 226 /* wait for NIC to initialize */ 227 for (ntries = 0; ntries < 100; ntries++) { 228 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 229 if (tmp != 0 && tmp != 0xffffffff) 230 break; 231 DELAY(10); 232 } 233 if (ntries == 100) { 234 aprint_error_dev(sc->sc_dev, 235 "timeout waiting for NIC to initialize\n"); 236 return ETIMEDOUT; 237 } 238 sc->mac_ver = tmp >> 16; 239 sc->mac_rev = tmp & 0xffff; 240 241 if (sc->mac_ver != 0x2860 && 242 (id == PCI_PRODUCT_RALINK_RT2890 || 243 id == PCI_PRODUCT_RALINK_RT2790 || 244 id == PCI_PRODUCT_AWT_RT2890)) 245 sc->sc_flags |= RT2860_ADVANCED_PS; 246 247 /* retrieve RF rev. no and various other things from EEPROM */ 248 rt2860_read_eeprom(sc); 249 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 250 ether_sprintf(ic->ic_myaddr)); 251 aprint_normal_dev(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 252 "RF %s (MIMO %dT%dR)\n", 253 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 254 sc->ntxchains, sc->nrxchains); 255 256 /* 257 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 258 */ 259 for (qid = 0; qid < MAXQS; qid++) { 260 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 261 aprint_error_dev(sc->sc_dev, 262 "could not allocate Tx ring %d\n", qid); 263 goto fail1; 264 } 265 } 266 267 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 268 aprint_error_dev(sc->sc_dev, "could not allocate Rx ring\n"); 269 goto fail1; 270 } 271 272 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 273 aprint_error_dev(sc->sc_dev, "could not allocate Tx pool\n"); 274 goto fail2; 275 } 276 277 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 278 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 279 WME_AC_VO : 5; 280 281 config_mountroot(sc->sc_dev, rt2860_attachhook); 282 283 return 0; 284 285 fail2: rt2860_free_rx_ring(sc, &sc->rxq); 286 fail1: while (--qid >= 0) 287 rt2860_free_tx_ring(sc, &sc->txq[qid]); 288 return error; 289 } 290 291 static int 292 firmware_load(const char *dname, const char *iname, uint8_t **ucodep, 293 size_t *sizep) 294 { 295 firmware_handle_t fh; 296 int error; 297 298 if ((error = firmware_open(dname, iname, &fh)) != 0) 299 return (error); 300 *sizep = firmware_get_size(fh); 301 if ((*ucodep = firmware_malloc(*sizep)) == NULL) { 302 firmware_close(fh); 303 return (ENOMEM); 304 } 305 if ((error = firmware_read(fh, 0, *ucodep, *sizep)) != 0) 306 firmware_free(*ucodep, *sizep); 307 firmware_close(fh); 308 309 return (error); 310 } 311 312 static void 313 rt2860_attachhook(device_t self) 314 { 315 struct rt2860_softc *sc = device_private(self); 316 struct ieee80211com *ic = &sc->sc_ic; 317 struct ifnet *ifp = &sc->sc_if; 318 int i, error; 319 320 error = firmware_load("ral", "ral-rt2860", &sc->ucode, &sc->ucsize); 321 if (error != 0) { 322 aprint_error_dev(sc->sc_dev, 323 "error %d, could not read firmware file %s\n", 324 error, "ral-rt2860"); 325 return; 326 } 327 328 ic->ic_ifp = ifp; 329 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 330 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 331 ic->ic_state = IEEE80211_S_INIT; 332 333 /* set device capabilities */ 334 ic->ic_caps = 335 IEEE80211_C_MONITOR | /* monitor mode supported */ 336 #ifndef IEEE80211_STA_ONLY 337 IEEE80211_C_IBSS | /* IBSS mode supported */ 338 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 339 #ifdef IEEE80211_C_APPMGT 340 IEEE80211_C_APPMGT | /* HostAP power management */ 341 #endif 342 #endif 343 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 344 IEEE80211_C_SHSLOT | /* short slot time supported */ 345 IEEE80211_C_WEP | /* s/w WEP */ 346 IEEE80211_C_WPA; /* WPA/RSN */ 347 348 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 349 /* set supported .11a rates */ 350 ic->ic_sup_rates[IEEE80211_MODE_11A] = 351 ieee80211_std_rateset_11a; 352 353 /* set supported .11a channels */ 354 for (i = 14; i < (int)__arraycount(rt2860_rf2850); i++) { 355 uint8_t chan = rt2860_rf2850[i].chan; 356 ic->ic_channels[chan].ic_freq = 357 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 358 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 359 } 360 } 361 362 /* set supported .11b and .11g rates */ 363 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 364 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 365 366 /* set supported .11b and .11g channels (1 through 14) */ 367 for (i = 1; i <= 14; i++) { 368 ic->ic_channels[i].ic_freq = 369 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 370 ic->ic_channels[i].ic_flags = 371 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 372 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 373 } 374 375 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 376 ic->ic_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 377 378 ifp->if_softc = sc; 379 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 380 ifp->if_init = rt2860_init; 381 ifp->if_ioctl = rt2860_ioctl; 382 ifp->if_start = rt2860_start; 383 ifp->if_watchdog = rt2860_watchdog; 384 IFQ_SET_READY(&ifp->if_snd); 385 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 386 387 if_attach(ifp); 388 ieee80211_ifattach(ic); 389 ic->ic_node_alloc = rt2860_node_alloc; 390 ic->ic_newassoc = rt2860_newassoc; 391 #ifdef notyet 392 ic->ic_ampdu_rx_start = rt2860_ampdu_rx_start; 393 ic->ic_ampdu_rx_stop = rt2860_ampdu_rx_stop; 394 #endif 395 ic->ic_updateslot = rt2860_updateslot; 396 ic->ic_wme.wme_update = rt2860_updateedca; 397 #ifdef HW_CRYPTO 398 ic->ic_crypto.cs_key_set = rt2860_set_key; 399 ic->ic_crypto.cs_key_delete = rt2860_delete_key; 400 #endif 401 /* override state transition machine */ 402 sc->sc_newstate = ic->ic_newstate; 403 ic->ic_newstate = rt2860_newstate; 404 ieee80211_media_init(ic, rt2860_media_change, ieee80211_media_status); 405 406 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 407 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 408 409 sc->sc_rxtap_len = roundup(sizeof(sc->sc_rxtap), sizeof(u_int32_t)); 410 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 411 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2860_RX_RADIOTAP_PRESENT); 412 413 sc->sc_txtap_len = roundup(sizeof(sc->sc_txtap), sizeof(u_int32_t)); 414 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 415 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2860_TX_RADIOTAP_PRESENT); 416 417 ieee80211_announce(ic); 418 419 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 420 pmf_class_network_register(sc->sc_dev, ifp); 421 else 422 aprint_error_dev(sc->sc_dev, 423 "couldn't establish power handler\n"); 424 } 425 426 int 427 rt2860_detach(void *xsc) 428 { 429 struct rt2860_softc *sc = xsc; 430 struct ifnet *ifp = &sc->sc_if; 431 int qid; 432 433 pmf_device_deregister(sc->sc_dev); 434 435 rt2860_stop(ifp, 1); 436 437 ieee80211_ifdetach(&sc->sc_ic); /* free all nodes */ 438 if_detach(ifp); 439 440 for (qid = 0; qid < MAXQS; qid++) 441 rt2860_free_tx_ring(sc, &sc->txq[qid]); 442 rt2860_free_rx_ring(sc, &sc->rxq); 443 rt2860_free_tx_pool(sc); 444 445 if (sc->ucode != NULL) 446 free(sc->ucode, M_DEVBUF); 447 448 return 0; 449 } 450 451 void 452 rt2860_suspend(void *xsc) 453 { 454 struct rt2860_softc *sc = xsc; 455 struct ifnet *ifp = &sc->sc_if; 456 457 if (ifp->if_flags & IFF_RUNNING) 458 rt2860_stop(ifp, 1); 459 } 460 461 void 462 rt2860_wakeup(void *xsc) 463 { 464 struct rt2860_softc *sc = xsc; 465 struct ifnet *ifp = &sc->sc_if; 466 467 if (ifp->if_flags & IFF_UP) 468 rt2860_init(ifp); 469 } 470 471 static int 472 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 473 { 474 int nsegs, size, error; 475 476 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 477 478 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 479 BUS_DMA_NOWAIT, &ring->map); 480 if (error != 0) { 481 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 482 goto fail; 483 } 484 485 /* Tx rings must be 4-DWORD aligned */ 486 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 487 &nsegs, BUS_DMA_NOWAIT); 488 if (error != 0) { 489 aprint_error_dev(sc->sc_dev, 490 "could not allocate DMA memory\n"); 491 goto fail; 492 } 493 494 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 495 (void **)&ring->txd, BUS_DMA_NOWAIT); 496 if (error != 0) { 497 aprint_error_dev(sc->sc_dev, "can't map DMA memory\n"); 498 goto fail; 499 } 500 501 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->txd, size, NULL, 502 BUS_DMA_NOWAIT); 503 if (error != 0) { 504 aprint_error_dev(sc->sc_dev, "could not load DMA map\n"); 505 goto fail; 506 } 507 508 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 509 510 ring->paddr = ring->map->dm_segs[0].ds_addr; 511 512 return 0; 513 514 fail: rt2860_free_tx_ring(sc, ring); 515 return error; 516 } 517 518 static void 519 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 520 { 521 struct rt2860_tx_data *data; 522 int i; 523 524 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 525 if ((data = ring->data[i]) == NULL) 526 continue; /* nothing mapped in this slot */ 527 528 if (data->ni != NULL) { 529 ieee80211_free_node(data->ni); 530 data->ni = NULL; 531 } 532 533 if (data->m != NULL) { 534 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 535 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 536 bus_dmamap_unload(sc->sc_dmat, data->map); 537 m_freem(data->m); 538 data->m = NULL; 539 } 540 541 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 542 ring->data[i] = NULL; 543 } 544 545 ring->queued = 0; 546 ring->cur = ring->next = 0; 547 } 548 549 static void 550 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 551 { 552 struct rt2860_tx_data *data; 553 int i; 554 555 if (ring->txd != NULL) { 556 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 557 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 558 bus_dmamap_unload(sc->sc_dmat, ring->map); 559 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->txd, 560 RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd)); 561 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 562 } 563 if (ring->map != NULL) 564 bus_dmamap_destroy(sc->sc_dmat, ring->map); 565 566 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 567 if ((data = ring->data[i]) == NULL) 568 continue; /* nothing mapped in this slot */ 569 570 if (data->ni != NULL) { 571 ieee80211_free_node(data->ni); 572 data->ni = NULL; 573 } 574 if (data->m != NULL) { 575 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 576 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 577 bus_dmamap_unload(sc->sc_dmat, data->map); 578 m_freem(data->m); 579 data->m = NULL; 580 } 581 582 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 583 ring->data[i] = NULL; 584 } 585 ring->queued = 0; 586 ring->cur = ring->next = 0; 587 } 588 589 /* 590 * Allocate a pool of TX Wireless Information blocks. 591 */ 592 static int 593 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 594 { 595 char *vaddr; 596 bus_addr_t paddr; 597 int i, nsegs, size, error; 598 599 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 600 601 /* init data_pool early in case of failure.. */ 602 SLIST_INIT(&sc->data_pool); 603 604 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 605 BUS_DMA_NOWAIT, &sc->txwi_map); 606 if (error != 0) { 607 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 608 goto fail; 609 } 610 611 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 612 &sc->txwi_seg, 1, &nsegs, BUS_DMA_NOWAIT); 613 if (error != 0) { 614 aprint_error_dev(sc->sc_dev, 615 "could not allocate DMA memory\n"); 616 goto fail; 617 } 618 619 error = bus_dmamem_map(sc->sc_dmat, &sc->txwi_seg, nsegs, size, 620 &sc->txwi_vaddr, BUS_DMA_NOWAIT); 621 if (error != 0) { 622 aprint_error_dev(sc->sc_dev, "can't map DMA memory\n"); 623 goto fail; 624 } 625 626 error = bus_dmamap_load(sc->sc_dmat, sc->txwi_map, sc->txwi_vaddr, 627 size, NULL, BUS_DMA_NOWAIT); 628 if (error != 0) { 629 aprint_error_dev(sc->sc_dev, "could not load DMA map\n"); 630 goto fail; 631 } 632 633 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, size, 634 BUS_DMASYNC_PREWRITE); 635 636 vaddr = sc->txwi_vaddr; 637 paddr = sc->txwi_map->dm_segs[0].ds_addr; 638 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 639 struct rt2860_tx_data *data = &sc->data[i]; 640 641 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 642 RT2860_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 643 &data->map); /* <0> */ 644 if (error != 0) { 645 aprint_error_dev(sc->sc_dev, 646 "could not create DMA map\n"); 647 goto fail; 648 } 649 data->txwi = (struct rt2860_txwi *)vaddr; 650 data->paddr = paddr; 651 vaddr += RT2860_TXWI_DMASZ; 652 paddr += RT2860_TXWI_DMASZ; 653 654 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 655 } 656 657 return 0; 658 659 fail: rt2860_free_tx_pool(sc); 660 return error; 661 } 662 663 static void 664 rt2860_free_tx_pool(struct rt2860_softc *sc) 665 { 666 if (sc->txwi_vaddr != NULL) { 667 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, 668 sc->txwi_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 669 bus_dmamap_unload(sc->sc_dmat, sc->txwi_map); 670 bus_dmamem_unmap(sc->sc_dmat, sc->txwi_vaddr, 671 RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ); 672 bus_dmamem_free(sc->sc_dmat, &sc->txwi_seg, 1); 673 } 674 if (sc->txwi_map != NULL) 675 bus_dmamap_destroy(sc->sc_dmat, sc->txwi_map); 676 677 while (!SLIST_EMPTY(&sc->data_pool)) { 678 struct rt2860_tx_data *data; 679 data = SLIST_FIRST(&sc->data_pool); 680 bus_dmamap_destroy(sc->sc_dmat, data->map); 681 SLIST_REMOVE_HEAD(&sc->data_pool, next); 682 } 683 } 684 685 static int 686 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 687 { 688 int i, nsegs, size, error; 689 690 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 691 692 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 693 BUS_DMA_NOWAIT, &ring->map); 694 if (error != 0) { 695 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 696 goto fail; 697 } 698 699 /* Rx ring must be 4-DWORD aligned */ 700 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 701 &nsegs, BUS_DMA_NOWAIT); 702 if (error != 0) { 703 aprint_error_dev(sc->sc_dev, 704 "could not allocate DMA memory\n"); 705 goto fail; 706 } 707 708 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 709 (void **)&ring->rxd, BUS_DMA_NOWAIT); 710 if (error != 0) { 711 aprint_error_dev(sc->sc_dev, "can't map DMA memory\n"); 712 goto fail; 713 } 714 715 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->rxd, size, NULL, 716 BUS_DMA_NOWAIT); 717 if (error != 0) { 718 aprint_error_dev(sc->sc_dev, "could not load DMA map\n"); 719 goto fail; 720 } 721 722 ring->paddr = ring->map->dm_segs[0].ds_addr; 723 724 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 725 struct rt2860_rx_data *data = &ring->data[i]; 726 struct rt2860_rxd *rxd = &ring->rxd[i]; 727 const char *msg; 728 729 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 730 0, BUS_DMA_NOWAIT, &data->map); 731 if (error != 0) { 732 aprint_error_dev(sc->sc_dev, 733 "could not create DMA map\n"); 734 goto fail; 735 } 736 737 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 738 if (data->m == NULL) { 739 msg = "allocate Rx mbuf"; 740 goto fail1; 741 } 742 MCLGET(data->m, M_DONTWAIT); 743 if ((data->m->m_flags & M_EXT) == 0) { 744 msg = "allocate Rx mbuf cluster"; 745 goto fail1; 746 } 747 748 749 error = bus_dmamap_load(sc->sc_dmat, data->map, 750 mtod(data->m, void *), MCLBYTES, NULL, 751 BUS_DMA_READ | BUS_DMA_NOWAIT); 752 if (error != 0) { 753 msg = "load DMA map"; 754 fail1: 755 aprint_error_dev(sc->sc_dev, "could not %s\n", msg); 756 m_freem(data->m); 757 data->m = NULL; 758 error = ENOBUFS; 759 goto fail; 760 } 761 762 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 763 rxd->sdl0 = htole16(MCLBYTES); 764 } 765 766 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 767 768 return 0; 769 fail: rt2860_free_rx_ring(sc, ring); 770 return error; 771 } 772 773 static void 774 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 775 { 776 int i; 777 778 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 779 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 780 781 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 782 BUS_DMASYNC_PREWRITE); 783 784 ring->cur = 0; 785 } 786 787 static void 788 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 789 { 790 int i; 791 792 if (ring->rxd != NULL) { 793 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 794 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 795 bus_dmamap_unload(sc->sc_dmat, ring->map); 796 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->rxd, 797 RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd)); 798 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 799 ring->rxd = NULL; 800 } 801 if (ring->map != NULL) { 802 bus_dmamap_destroy(sc->sc_dmat, ring->map); 803 ring->map = NULL; 804 } 805 806 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 807 struct rt2860_rx_data *data = &ring->data[i]; 808 809 if (data->m != NULL) { 810 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 811 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 812 bus_dmamap_unload(sc->sc_dmat, data->map); 813 m_freem(data->m); 814 data->m = NULL; 815 } 816 if (data->map != NULL) { 817 bus_dmamap_destroy(sc->sc_dmat, data->map); 818 data->map = NULL; 819 } 820 } 821 } 822 823 static struct ieee80211_node * 824 rt2860_node_alloc(struct ieee80211_node_table *nt) 825 { 826 struct rt2860_node *rn = malloc(sizeof(*rn), M_80211_NODE, 827 M_NOWAIT | M_ZERO); 828 return rn ? &rn->ni : NULL; 829 } 830 831 static int 832 rt2860_media_change(struct ifnet *ifp) 833 { 834 struct rt2860_softc *sc = ifp->if_softc; 835 struct ieee80211com *ic = &sc->sc_ic; 836 uint8_t rate, ridx; 837 int error; 838 839 error = ieee80211_media_change(ifp); 840 if (error != ENETRESET) 841 return error; 842 843 if (ic->ic_fixed_rate != -1) { 844 rate = ic->ic_sup_rates[ic->ic_curmode]. 845 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 846 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 847 if (rt2860_rates[ridx].rate == rate) 848 break; 849 sc->fixed_ridx = ridx; 850 } 851 852 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 853 (IFF_UP | IFF_RUNNING)) { 854 rt2860_stop(ifp, 0); 855 rt2860_init(ifp); 856 } 857 return 0; 858 } 859 860 static void 861 rt2860_iter_func(void *arg, struct ieee80211_node *ni) 862 { 863 struct rt2860_softc *sc = arg; 864 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 865 866 ieee80211_amrr_choose(&sc->amrr, ni, &sc->amn[wcid]); 867 } 868 869 static void 870 rt2860_updatestats(struct rt2860_softc *sc) 871 { 872 struct ieee80211com *ic = &sc->sc_ic; 873 874 #ifndef IEEE80211_STA_ONLY 875 /* 876 * In IBSS or HostAP modes (when the hardware sends beacons), the 877 * MAC can run into a livelock and start sending CTS-to-self frames 878 * like crazy if protection is enabled. Fortunately, we can detect 879 * when such a situation occurs and reset the MAC. 880 */ 881 if (ic->ic_curmode != IEEE80211_M_STA) { 882 /* check if we're in a livelock situation.. */ 883 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 884 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 885 /* ..and reset MAC/BBP for a while.. */ 886 DPRINTF(("CTS-to-self livelock detected\n")); 887 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 888 RAL_BARRIER_WRITE(sc); 889 DELAY(1); 890 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 891 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 892 } 893 } 894 #endif 895 if (ic->ic_opmode == IEEE80211_M_STA) 896 rt2860_iter_func(sc, ic->ic_bss); 897 #ifndef IEEE80211_STA_ONLY 898 else 899 ieee80211_iterate_nodes(&ic->ic_sta, rt2860_iter_func, sc); 900 #endif 901 } 902 903 static void 904 rt2860_newassoc(struct ieee80211_node *ni, int isnew) 905 { 906 struct rt2860_softc *sc = ni->ni_ic->ic_ifp->if_softc; 907 struct rt2860_node *rn = (void *)ni; 908 struct ieee80211_rateset *rs = &ni->ni_rates; 909 uint8_t rate, wcid = 0; 910 int ridx, i, j; 911 912 if (isnew && ni->ni_associd != 0) { 913 /* only interested in true associations */ 914 wcid = rn->wcid = IEEE80211_AID(ni->ni_associd); 915 916 /* init WCID table entry */ 917 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 918 ni->ni_macaddr, IEEE80211_ADDR_LEN); 919 } 920 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 921 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 922 923 ieee80211_amrr_node_init(&sc->amrr, &sc->amn[wcid]); 924 /* start at lowest available bit-rate, AMRR will raise */ 925 ni->ni_txrate = 0; 926 927 for (i = 0; i < rs->rs_nrates; i++) { 928 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 929 /* convert 802.11 rate to hardware rate index */ 930 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 931 if (rt2860_rates[ridx].rate == rate) 932 break; 933 rn->ridx[i] = ridx; 934 /* determine rate of control response frames */ 935 for (j = i; j >= 0; j--) { 936 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 937 rt2860_rates[rn->ridx[i]].phy == 938 rt2860_rates[rn->ridx[j]].phy) 939 break; 940 } 941 if (j >= 0) { 942 rn->ctl_ridx[i] = rn->ridx[j]; 943 } else { 944 /* no basic rate found, use mandatory one */ 945 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 946 } 947 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 948 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 949 } 950 } 951 952 #ifdef notyet 953 static int 954 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 955 uint8_t tid) 956 { 957 struct rt2860_softc *sc = ic->ic_softc; 958 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 959 uint32_t tmp; 960 961 /* update BA session mask */ 962 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 963 tmp |= (1 << tid) << 16; 964 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 965 return 0; 966 } 967 968 static void 969 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 970 uint8_t tid) 971 { 972 struct rt2860_softc *sc = ic->ic_softc; 973 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 974 uint32_t tmp; 975 976 /* update BA session mask */ 977 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 978 tmp &= ~((1 << tid) << 16); 979 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 980 } 981 #endif 982 983 static int 984 rt2860_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 985 { 986 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 987 enum ieee80211_state ostate; 988 uint32_t tmp; 989 990 ostate = ic->ic_state; 991 992 DPRINTF(("ostate = %d nstate = %d\n", ostate, nstate)); 993 if (ostate == IEEE80211_S_RUN) { 994 /* turn link LED off */ 995 rt2860_set_leds(sc, RT2860_LED_RADIO); 996 } 997 998 switch (nstate) { 999 case IEEE80211_S_INIT: 1000 if (ostate == IEEE80211_S_RUN) { 1001 /* abort TSF synchronization */ 1002 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 1003 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 1004 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 1005 RT2860_TBTT_TIMER_EN)); 1006 } 1007 rt2860_set_gp_timer(sc, 0); 1008 break; 1009 1010 case IEEE80211_S_SCAN: 1011 rt2860_switch_chan(sc, ic->ic_curchan); 1012 if (ostate != IEEE80211_S_SCAN) 1013 rt2860_set_gp_timer(sc, 150); 1014 break; 1015 1016 case IEEE80211_S_AUTH: 1017 case IEEE80211_S_ASSOC: 1018 rt2860_set_gp_timer(sc, 0); 1019 rt2860_switch_chan(sc, ic->ic_curchan); 1020 break; 1021 1022 case IEEE80211_S_RUN: 1023 rt2860_set_gp_timer(sc, 0); 1024 rt2860_switch_chan(sc, ic->ic_curchan); 1025 1026 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1027 rt2860_updateslot(ic->ic_ifp); 1028 rt2860_enable_mrr(sc); 1029 rt2860_set_txpreamble(sc); 1030 rt2860_set_basicrates(sc); 1031 rt2860_set_bssid(sc, ic->ic_bss->ni_bssid); 1032 } 1033 1034 #ifndef IEEE80211_STA_ONLY 1035 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1036 ic->ic_opmode == IEEE80211_M_IBSS) 1037 (void)rt2860_setup_beacon(sc); 1038 #endif 1039 1040 if (ic->ic_opmode == IEEE80211_M_STA) { 1041 /* fake a join to init the tx rate */ 1042 rt2860_newassoc(ic->ic_bss, 1); 1043 } 1044 1045 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1046 rt2860_enable_tsf_sync(sc); 1047 rt2860_set_gp_timer(sc, 500); 1048 } 1049 1050 /* turn link LED on */ 1051 rt2860_set_leds(sc, RT2860_LED_RADIO | 1052 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan) ? 1053 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1054 break; 1055 } 1056 1057 return sc->sc_newstate(ic, nstate, arg); 1058 } 1059 1060 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 1061 static uint16_t 1062 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 1063 { 1064 uint32_t tmp; 1065 uint16_t reg; 1066 int ntries; 1067 1068 addr *= 2; 1069 /*- 1070 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1071 * DATA0: F E D C 1072 * DATA1: B A 9 8 1073 * DATA2: 7 6 5 4 1074 * DATA3: 3 2 1 0 1075 */ 1076 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1077 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1078 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1079 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 1080 for (ntries = 0; ntries < 500; ntries++) { 1081 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1082 if (!(tmp & RT3070_EFSROM_KICK)) 1083 break; 1084 DELAY(2); 1085 } 1086 if (ntries == 500) 1087 return 0xffff; 1088 1089 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 1090 return 0xffff; /* address not found */ 1091 1092 /* determine to which 32-bit register our 16-bit word belongs */ 1093 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1094 tmp = RAL_READ(sc, reg); 1095 1096 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1097 } 1098 1099 /* 1100 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1101 * 93C66 or 93C86). 1102 */ 1103 static uint16_t 1104 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1105 { 1106 uint32_t tmp; 1107 uint16_t val; 1108 int n; 1109 1110 /* clock C once before the first command */ 1111 RT2860_EEPROM_CTL(sc, 0); 1112 1113 RT2860_EEPROM_CTL(sc, RT2860_S); 1114 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1115 RT2860_EEPROM_CTL(sc, RT2860_S); 1116 1117 /* write start bit (1) */ 1118 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1119 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1120 1121 /* write READ opcode (10) */ 1122 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1123 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1124 RT2860_EEPROM_CTL(sc, RT2860_S); 1125 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1126 1127 /* write address (A5-A0 or A7-A0) */ 1128 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1129 for (; n >= 0; n--) { 1130 RT2860_EEPROM_CTL(sc, RT2860_S | 1131 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1132 RT2860_EEPROM_CTL(sc, RT2860_S | 1133 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1134 } 1135 1136 RT2860_EEPROM_CTL(sc, RT2860_S); 1137 1138 /* read data Q15-Q0 */ 1139 val = 0; 1140 for (n = 15; n >= 0; n--) { 1141 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1142 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1143 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1144 RT2860_EEPROM_CTL(sc, RT2860_S); 1145 } 1146 1147 RT2860_EEPROM_CTL(sc, 0); 1148 1149 /* clear Chip Select and clock C */ 1150 RT2860_EEPROM_CTL(sc, RT2860_S); 1151 RT2860_EEPROM_CTL(sc, 0); 1152 RT2860_EEPROM_CTL(sc, RT2860_C); 1153 1154 return val; 1155 } 1156 1157 static __inline uint16_t 1158 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1159 { 1160 /* either eFUSE ROM or EEPROM */ 1161 return sc->sc_srom_read(sc, addr); 1162 } 1163 1164 static void 1165 rt2860_intr_coherent(struct rt2860_softc *sc) 1166 { 1167 uint32_t tmp; 1168 1169 /* DMA finds data coherent event when checking the DDONE bit */ 1170 1171 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1172 1173 /* restart DMA engine */ 1174 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1175 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1176 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1177 1178 (void)rt2860_txrx_enable(sc); 1179 } 1180 1181 static void 1182 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1183 { 1184 struct ifnet *ifp = &sc->sc_if; 1185 struct ieee80211_amrr_node *amn; 1186 uint32_t stat; 1187 uint8_t wcid, mcs, pid; 1188 1189 /* drain Tx status FIFO (maxsize = 16) */ 1190 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1191 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1192 1193 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1194 1195 /* if no ACK was requested, no feedback is available */ 1196 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff) 1197 continue; 1198 1199 /* update per-STA AMRR stats */ 1200 amn = &sc->amn[wcid]; 1201 amn->amn_txcnt++; 1202 if (stat & RT2860_TXQ_OK) { 1203 /* 1204 * Check if there were retries, ie if the Tx success 1205 * rate is different from the requested rate. Note 1206 * that it works only because we do not allow rate 1207 * fallback from OFDM to CCK. 1208 */ 1209 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1210 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1211 if (mcs + 1 != pid) 1212 amn->amn_retrycnt++; 1213 } else { 1214 amn->amn_retrycnt++; 1215 ifp->if_oerrors++; 1216 } 1217 } 1218 } 1219 1220 static void 1221 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1222 { 1223 struct ifnet *ifp = &sc->sc_if; 1224 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1225 uint32_t hw; 1226 1227 rt2860_drain_stats_fifo(sc); 1228 1229 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1230 while (ring->next != hw) { 1231 struct rt2860_tx_data *data = ring->data[ring->next]; 1232 1233 if (data != NULL) { 1234 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1235 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1236 bus_dmamap_unload(sc->sc_dmat, data->map); 1237 m_freem(data->m); 1238 data->m= NULL; 1239 ieee80211_free_node(data->ni); 1240 data->ni = NULL; 1241 1242 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1243 ring->data[ring->next] = NULL; 1244 1245 ifp->if_opackets++; 1246 } 1247 ring->queued--; 1248 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1249 } 1250 1251 sc->sc_tx_timer = 0; 1252 if (ring->queued <= RT2860_TX_RING_ONEMORE) 1253 sc->qfullmsk &= ~(1 << qid); 1254 ifp->if_flags &= ~IFF_OACTIVE; 1255 rt2860_start(ifp); 1256 } 1257 1258 /* 1259 * Return the Rx chain with the highest RSSI for a given frame. 1260 */ 1261 static __inline uint8_t 1262 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1263 { 1264 uint8_t rxchain = 0; 1265 1266 if (sc->nrxchains > 1) { 1267 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1268 rxchain = 1; 1269 if (sc->nrxchains > 2) 1270 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1271 rxchain = 2; 1272 } 1273 return rxchain; 1274 } 1275 1276 static void 1277 rt2860_rx_intr(struct rt2860_softc *sc) 1278 { 1279 struct ieee80211com *ic = &sc->sc_ic; 1280 struct ifnet *ifp = &sc->sc_if; 1281 struct ieee80211_frame *wh; 1282 struct ieee80211_node *ni; 1283 struct mbuf *m, *m1; 1284 uint32_t hw; 1285 uint8_t ant, rssi; 1286 int error; 1287 struct rt2860_rx_radiotap_header *tap; 1288 uint16_t phy; 1289 1290 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1291 DPRINTF(("rx mbuf %#x\n", hw)); 1292 while (sc->rxq.cur != hw) { 1293 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1294 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1295 struct rt2860_rxwi *rxwi; 1296 1297 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1298 sc->rxq.cur * sizeof (struct rt2860_rxd), 1299 sizeof (struct rt2860_rxd), BUS_DMASYNC_POSTREAD); 1300 1301 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1302 DPRINTF(("RXD DDONE bit not set!\n")); 1303 break; /* should not happen */ 1304 } 1305 1306 if (__predict_false(rxd->flags & 1307 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1308 DPRINTF(("error %#x\n", rxd->flags)); 1309 ifp->if_ierrors++; 1310 goto skip; 1311 } 1312 1313 1314 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1315 if (__predict_false(m1 == NULL)) { 1316 DPRINTF(("error2 %#x\n", rxd->flags)); 1317 ifp->if_ierrors++; 1318 goto skip; 1319 } 1320 MCLGET(m1, M_DONTWAIT); 1321 if (__predict_false((m1->m_flags & M_EXT) == 0)) { 1322 DPRINTF(("no mbuf\n")); 1323 m_freem(m1); 1324 ifp->if_ierrors++; 1325 goto skip; 1326 } 1327 1328 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1329 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1330 bus_dmamap_unload(sc->sc_dmat, data->map); 1331 1332 error = bus_dmamap_load(sc->sc_dmat, data->map, 1333 mtod(m1, void *), MCLBYTES, NULL, 1334 BUS_DMA_READ | BUS_DMA_NOWAIT); 1335 if (__predict_false(error != 0)) { 1336 DPRINTF(("dma error %d\n", error)); 1337 m_freem(m1); 1338 1339 /* try to reload the old mbuf */ 1340 error = bus_dmamap_load(sc->sc_dmat, data->map, 1341 mtod(data->m, void *), MCLBYTES, NULL, 1342 BUS_DMA_READ | BUS_DMA_NOWAIT); 1343 if (__predict_false(error != 0)) { 1344 panic("%s: could not load old rx mbuf", 1345 device_xname(sc->sc_dev)); 1346 } 1347 /* physical address may have changed */ 1348 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1349 ifp->if_ierrors++; 1350 goto skip; 1351 } 1352 1353 /* 1354 * New mbuf successfully loaded, update Rx ring and continue 1355 * processing. 1356 */ 1357 m = data->m; 1358 data->m = m1; 1359 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1360 1361 rxwi = mtod(m, struct rt2860_rxwi *); 1362 1363 /* finalize mbuf */ 1364 m->m_data = (void *)(rxwi + 1); 1365 m_set_rcvif(m, ifp); 1366 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1367 1368 wh = mtod(m, struct ieee80211_frame *); 1369 #ifdef HW_CRYPTO 1370 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1371 /* frame is decrypted by hardware */ 1372 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1373 } 1374 #endif 1375 1376 /* HW may insert 2 padding bytes after 802.11 header */ 1377 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1378 u_int hdrlen = ieee80211_hdrspace(ic, wh); 1379 memmove((char *)wh + 2, wh, hdrlen); 1380 m->m_data += 2; 1381 wh = mtod(m, struct ieee80211_frame *); 1382 } 1383 1384 #ifdef HW_CRYPTO 1385 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1386 /* report MIC failures to net80211 for TKIP */ 1387 ieee80211_notify_michael_failure(ic, wh, 0/* XXX */); 1388 DPRINTF(("error2 %#x\n", rxd->flags)); 1389 ifp->if_ierrors++; 1390 goto skip; 1391 } 1392 #endif 1393 ant = rt2860_maxrssi_chain(sc, rxwi); 1394 rssi = rxwi->rssi[ant]; 1395 1396 if (__predict_true(sc->sc_drvbpf == NULL)) 1397 goto skipbpf; 1398 1399 tap = &sc->sc_rxtap; 1400 tap->wr_flags = 0; 1401 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1402 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1403 tap->wr_antsignal = rssi; 1404 tap->wr_antenna = ant; 1405 tap->wr_dbm_antsignal = rt2860_rssi2dbm(sc, rssi, ant); 1406 tap->wr_rate = 2; /* in case it can't be found below */ 1407 phy = le16toh(rxwi->phy); 1408 switch (phy & RT2860_PHY_MODE) { 1409 case RT2860_PHY_CCK: 1410 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1411 case 0: tap->wr_rate = 2; break; 1412 case 1: tap->wr_rate = 4; break; 1413 case 2: tap->wr_rate = 11; break; 1414 case 3: tap->wr_rate = 22; break; 1415 } 1416 if (phy & RT2860_PHY_SHPRE) 1417 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1418 break; 1419 case RT2860_PHY_OFDM: 1420 switch (phy & RT2860_PHY_MCS) { 1421 case 0: tap->wr_rate = 12; break; 1422 case 1: tap->wr_rate = 18; break; 1423 case 2: tap->wr_rate = 24; break; 1424 case 3: tap->wr_rate = 36; break; 1425 case 4: tap->wr_rate = 48; break; 1426 case 5: tap->wr_rate = 72; break; 1427 case 6: tap->wr_rate = 96; break; 1428 case 7: tap->wr_rate = 108; break; 1429 } 1430 break; 1431 } 1432 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1433 skipbpf: 1434 wh = mtod(m, struct ieee80211_frame *); 1435 /* grab a reference to the source node */ 1436 ni = ieee80211_find_rxnode(ic, 1437 (struct ieee80211_frame_min *)wh); 1438 1439 /* send the frame to the 802.11 layer */ 1440 ieee80211_input(ic, m, ni, rssi, 0); 1441 1442 /* node is no longer needed */ 1443 ieee80211_free_node(ni); 1444 1445 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1446 1447 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1448 sc->rxq.cur * sizeof (struct rt2860_rxd), 1449 sizeof (struct rt2860_rxd), BUS_DMASYNC_PREWRITE); 1450 1451 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1452 } 1453 1454 /* tell HW what we have processed */ 1455 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1456 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1457 } 1458 1459 static void 1460 rt2860_tbtt_intr(struct rt2860_softc *sc) 1461 { 1462 struct ieee80211com *ic = &sc->sc_ic; 1463 1464 #ifndef IEEE80211_STA_ONLY 1465 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1466 /* one less beacon until next DTIM */ 1467 if (ic->ic_dtim_count == 0) 1468 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1469 else 1470 ic->ic_dtim_count--; 1471 1472 /* update dynamic parts of beacon */ 1473 rt2860_setup_beacon(sc); 1474 1475 #if 0 1476 /* flush buffered multicast frames */ 1477 if (ic->ic_dtim_count == 0) 1478 ieee80211_notify_dtim(ic); 1479 #endif 1480 } 1481 #endif 1482 /* check if protection mode has changed */ 1483 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1484 rt2860_updateprot(ic); 1485 sc->sc_ic_flags = ic->ic_flags; 1486 } 1487 } 1488 1489 static void 1490 rt2860_gp_intr(struct rt2860_softc *sc) 1491 { 1492 struct ieee80211com *ic = &sc->sc_ic; 1493 1494 DPRINTFN(2, ("GP timeout state=%d\n", ic->ic_state)); 1495 1496 if (ic->ic_state == IEEE80211_S_SCAN) 1497 ieee80211_next_scan(ic); 1498 else if (ic->ic_state == IEEE80211_S_RUN) 1499 rt2860_updatestats(sc); 1500 } 1501 1502 int 1503 rt2860_intr(void *arg) 1504 { 1505 struct rt2860_softc *sc = arg; 1506 uint32_t r; 1507 1508 r = RAL_READ(sc, RT2860_INT_STATUS); 1509 if (__predict_false(r == 0xffffffff)) 1510 return 0; /* device likely went away */ 1511 if (r == 0) 1512 return 0; /* not for us */ 1513 1514 /* acknowledge interrupts */ 1515 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1516 1517 if (r & RT2860_TX_RX_COHERENT) 1518 rt2860_intr_coherent(sc); 1519 1520 if (r & RT2860_MAC_INT_2) /* TX status */ 1521 rt2860_drain_stats_fifo(sc); 1522 1523 if (r & RT2860_TX_DONE_INT5) 1524 rt2860_tx_intr(sc, 5); 1525 1526 if (r & RT2860_RX_DONE_INT) 1527 rt2860_rx_intr(sc); 1528 1529 if (r & RT2860_TX_DONE_INT4) 1530 rt2860_tx_intr(sc, 4); 1531 1532 if (r & RT2860_TX_DONE_INT3) 1533 rt2860_tx_intr(sc, 3); 1534 1535 if (r & RT2860_TX_DONE_INT2) 1536 rt2860_tx_intr(sc, 2); 1537 1538 if (r & RT2860_TX_DONE_INT1) 1539 rt2860_tx_intr(sc, 1); 1540 1541 if (r & RT2860_TX_DONE_INT0) 1542 rt2860_tx_intr(sc, 0); 1543 1544 if (r & RT2860_MAC_INT_0) /* TBTT */ 1545 rt2860_tbtt_intr(sc); 1546 1547 if (r & RT2860_MAC_INT_3) { /* Auto wakeup */ 1548 /* TBD wakeup */ 1549 } 1550 1551 if (r & RT2860_MAC_INT_4) /* GP timer */ 1552 rt2860_gp_intr(sc); 1553 1554 return 1; 1555 } 1556 1557 static int 1558 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1559 { 1560 struct ieee80211com *ic = &sc->sc_ic; 1561 struct rt2860_node *rn = (void *)ni; 1562 struct rt2860_tx_ring *ring; 1563 struct rt2860_tx_data *data; 1564 struct rt2860_txd *txd; 1565 struct rt2860_txwi *txwi; 1566 struct ieee80211_frame *wh; 1567 bus_dma_segment_t *seg; 1568 u_int hdrlen; 1569 uint16_t qos, dur; 1570 uint8_t type, qsel, mcs, pid, tid, qid; 1571 int nsegs, hasqos, ridx, ctl_ridx; 1572 1573 /* the data pool contains at least one element, pick the first */ 1574 data = SLIST_FIRST(&sc->data_pool); 1575 1576 wh = mtod(m, struct ieee80211_frame *); 1577 #if 0 1578 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1579 struct ieee80211_key *k = ieee80211_crypto_encap(ic, ni, m); 1580 if (k == NULL) { 1581 m_freem(m); 1582 return ENOBUFS; 1583 } 1584 1585 /* packet header may have moved, reset our local pointer */ 1586 wh = mtod(m, struct ieee80211_frame *); 1587 } 1588 #endif 1589 1590 hdrlen = ieee80211_hdrspace(ic, wh); 1591 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1592 1593 if ((hasqos = ieee80211_has_qos(wh))) { 1594 qos = ieee80211_get_qos(wh); 1595 tid = qos & IEEE80211_QOS_TID; 1596 qid = TID_TO_WME_AC(tid); 1597 } else { 1598 qos = 0; 1599 tid = 0; 1600 qid = (type == IEEE80211_FC0_TYPE_MGT) ? 1601 sc->mgtqid : WME_AC_BE; 1602 } 1603 KASSERT(qid < MAXQS); 1604 ring = &sc->txq[qid]; 1605 1606 /* pickup a rate index */ 1607 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1608 type != IEEE80211_FC0_TYPE_DATA) { 1609 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1610 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 1611 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1612 } else if (ic->ic_fixed_rate != -1) { 1613 ridx = sc->fixed_ridx; 1614 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1615 } else { 1616 ridx = rn->ridx[ni->ni_txrate]; 1617 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 1618 } 1619 1620 /* get MCS code from rate index */ 1621 mcs = rt2860_rates[ridx].mcs; 1622 1623 /* setup TX Wireless Information */ 1624 txwi = data->txwi; 1625 txwi->flags = 0; 1626 /* let HW generate seq numbers for non-QoS frames */ 1627 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 1628 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? rn->wcid : 0xff; 1629 txwi->len = htole16(m->m_pkthdr.len); 1630 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1631 txwi->phy = htole16(RT2860_PHY_CCK); 1632 if (ridx != RT2860_RIDX_CCK1 && 1633 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1634 mcs |= RT2860_PHY_SHPRE; 1635 } else 1636 txwi->phy = htole16(RT2860_PHY_OFDM); 1637 txwi->phy |= htole16(mcs); 1638 1639 /* 1640 * We store the MCS code into the driver-private PacketID field. 1641 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1642 * that we know at which initial rate the frame was transmitted. 1643 * We add 1 to the MCS code because setting the PacketID field to 1644 * 0 means that we don't want feedback in TX_STAT_FIFO. 1645 */ 1646 pid = (mcs + 1) & 0xf; 1647 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1648 1649 /* check if RTS/CTS or CTS-to-self protection is required */ 1650 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1651 (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold || 1652 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1653 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1654 txwi->txop = RT2860_TX_TXOP_HT; 1655 else 1656 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1657 1658 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1659 (!hasqos || (qos & IEEE80211_QOS_ACKPOLICY) != 1660 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1661 txwi->xflags |= RT2860_TX_ACK; 1662 1663 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1664 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 1665 else 1666 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 1667 *(uint16_t *)wh->i_dur = htole16(dur); 1668 } 1669 #ifndef IEEE80211_STA_ONLY 1670 /* ask MAC to insert timestamp into probe responses */ 1671 if ((wh->i_fc[0] & 1672 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1673 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1674 /* NOTE: beacons do not pass through tx_data() */ 1675 txwi->flags |= RT2860_TX_TS; 1676 #endif 1677 1678 if (__predict_false(sc->sc_drvbpf != NULL)) { 1679 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1680 1681 tap->wt_flags = 0; 1682 tap->wt_rate = rt2860_rates[ridx].rate; 1683 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1684 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1685 tap->wt_hwqueue = qid; 1686 if (mcs & RT2860_PHY_SHPRE) 1687 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1688 1689 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 1690 } 1691 1692 /* copy and trim 802.11 header */ 1693 memcpy(txwi + 1, wh, hdrlen); 1694 m_adj(m, hdrlen); 1695 1696 KASSERT (ring->queued <= RT2860_TX_RING_ONEMORE); /* <1> */ 1697 if (bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, BUS_DMA_NOWAIT)) { 1698 if (m_defrag(m, M_DONTWAIT)) 1699 return (ENOBUFS); 1700 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1701 data->map, m, BUS_DMA_NOWAIT)) 1702 return (EFBIG); 1703 } 1704 1705 /* The map will fit into the tx ring: (a "full" ring may have a few 1706 * unused descriptors, at most (txds(MAX_SCATTER) - 1)) 1707 * 1708 * ring->queued + txds(data->map->nsegs) 1709 * <= { <0> data->map->nsegs <= MAX_SCATTER } 1710 * ring->queued + txds(MAX_SCATTER) 1711 * <= { <1> ring->queued <= TX_RING_MAX - txds(MAX_SCATTER) } 1712 * TX_RING_MAX - txds(MAX_SCATTER) + txds(MAX_SCATTER) 1713 * <= { arithmetic } 1714 * TX_RING_MAX 1715 */ 1716 1717 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1718 1719 /* first segment is TXWI + 802.11 header */ 1720 txd = &ring->txd[ring->cur]; 1721 txd->sdp0 = htole32(data->paddr); 1722 int pad = (hdrlen + 3) & ~3; 1723 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1724 txd->flags = qsel; 1725 1726 /* setup payload segments */ 1727 seg = data->map->dm_segs; 1728 for (nsegs = data->map->dm_nsegs; nsegs >= 2; nsegs -= 2) { 1729 txd->sdp1 = htole32(seg->ds_addr); 1730 txd->sdl1 = htole16(seg->ds_len); 1731 seg++; 1732 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1733 /* grab a new Tx descriptor */ 1734 txd = &ring->txd[ring->cur]; 1735 txd->sdp0 = htole32(seg->ds_addr); 1736 txd->sdl0 = htole16(seg->ds_len); 1737 txd->flags = qsel; 1738 seg++; 1739 } 1740 /* finalize last segment */ 1741 if (nsegs > 0) { 1742 txd->sdp1 = htole32(seg->ds_addr); 1743 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1744 } else { 1745 txd->sdl0 |= htole16(RT2860_TX_LS0); 1746 txd->sdl1 = 0; 1747 } 1748 1749 /* remove from the free pool and link it into the SW Tx slot */ 1750 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1751 data->m = m; 1752 data->ni = ni; 1753 ring->data[ring->cur] = data; 1754 1755 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 1756 (uintptr_t)txwi - (uintptr_t)sc->txwi_vaddr, RT2860_TXWI_DMASZ, 1757 BUS_DMASYNC_PREWRITE); 1758 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1759 BUS_DMASYNC_PREWRITE); 1760 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1761 BUS_DMASYNC_PREWRITE); 1762 1763 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1764 qid, txwi->wcid, data->map->dm_nsegs, ridx)); 1765 1766 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1767 ring->queued += 1 + (data->map->dm_nsegs / 2); 1768 if (ring->queued > RT2860_TX_RING_ONEMORE) 1769 sc->qfullmsk |= 1 << qid; 1770 1771 /* kick Tx */ 1772 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1773 1774 return 0; 1775 } 1776 1777 static void 1778 rt2860_start(struct ifnet *ifp) 1779 { 1780 struct rt2860_softc *sc = ifp->if_softc; 1781 struct ieee80211com *ic = &sc->sc_ic; 1782 struct ether_header *eh; 1783 struct ieee80211_node *ni; 1784 struct mbuf *m; 1785 1786 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1787 return; 1788 1789 for (;;) { 1790 if (SLIST_EMPTY(&sc->data_pool) || sc->qfullmsk != 0) { 1791 ifp->if_flags |= IFF_OACTIVE; 1792 break; 1793 } 1794 /* send pending management frames first */ 1795 IF_DEQUEUE(&ic->ic_mgtq, m); 1796 if (m != NULL) { 1797 ni = M_GETCTX(m, struct ieee80211_node *); 1798 M_CLEARCTX(m); 1799 goto sendit; 1800 } 1801 if (ic->ic_state != IEEE80211_S_RUN) 1802 break; 1803 1804 /* encapsulate and send data frames */ 1805 IFQ_DEQUEUE(&ifp->if_snd, m); 1806 if (m == NULL) 1807 break; 1808 if (m->m_len < (int)sizeof(*eh) && 1809 (m = m_pullup(m, sizeof(*eh))) == NULL) { 1810 ifp->if_oerrors++; 1811 continue; 1812 } 1813 1814 bpf_mtap(ifp, m); 1815 1816 eh = mtod(m, struct ether_header *); 1817 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1818 if (ni == NULL) { 1819 m_freem(m); 1820 ifp->if_oerrors++; 1821 continue; 1822 } 1823 1824 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 1825 ieee80211_free_node(ni); 1826 ifp->if_oerrors++; 1827 continue; 1828 } 1829 sendit: 1830 bpf_mtap3(ic->ic_rawbpf, m); 1831 1832 if (rt2860_tx(sc, m, ni) != 0) { 1833 m_freem(m); 1834 ieee80211_free_node(ni); 1835 ifp->if_oerrors++; 1836 continue; 1837 } 1838 1839 sc->sc_tx_timer = 5; 1840 ifp->if_timer = 1; 1841 } 1842 } 1843 1844 static void 1845 rt2860_watchdog(struct ifnet *ifp) 1846 { 1847 struct rt2860_softc *sc = ifp->if_softc; 1848 struct ieee80211com *ic = &sc->sc_ic; 1849 1850 ifp->if_timer = 0; 1851 1852 if (sc->sc_tx_timer > 0) { 1853 if (--sc->sc_tx_timer == 0) { 1854 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1855 rt2860_stop(ifp, 0); 1856 rt2860_init(ifp); 1857 ifp->if_oerrors++; 1858 return; 1859 } 1860 ifp->if_timer = 1; 1861 } 1862 1863 ieee80211_watchdog(ic); 1864 } 1865 1866 static int 1867 rt2860_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1868 { 1869 struct rt2860_softc *sc = ifp->if_softc; 1870 struct ieee80211com *ic = &sc->sc_ic; 1871 int s, error = 0; 1872 1873 s = splnet(); 1874 1875 switch (cmd) { 1876 case SIOCSIFFLAGS: 1877 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1878 break; 1879 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1880 case IFF_UP|IFF_RUNNING: 1881 rt2860_update_promisc(ifp); 1882 break; 1883 case IFF_UP: 1884 rt2860_init(ifp); 1885 break; 1886 case IFF_RUNNING: 1887 rt2860_stop(ifp, 1); 1888 break; 1889 case 0: 1890 break; 1891 } 1892 break; 1893 1894 case SIOCADDMULTI: 1895 case SIOCDELMULTI: 1896 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1897 /* setup multicast filter, etc */ 1898 error = 0; 1899 } 1900 break; 1901 1902 case SIOCS80211CHANNEL: 1903 /* 1904 * This allows for fast channel switching in monitor mode 1905 * (used by kismet). In IBSS mode, we must explicitly reset 1906 * the interface to generate a new beacon frame. 1907 */ 1908 error = ieee80211_ioctl(ic, cmd, data); 1909 if (error == ENETRESET && 1910 ic->ic_opmode == IEEE80211_M_MONITOR) { 1911 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1912 (IFF_UP | IFF_RUNNING)) 1913 rt2860_switch_chan(sc, ic->ic_ibss_chan); 1914 error = 0; 1915 } 1916 break; 1917 1918 default: 1919 error = ieee80211_ioctl(ic, cmd, data); 1920 } 1921 1922 if (error == ENETRESET) { 1923 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1924 (IFF_UP | IFF_RUNNING)) { 1925 rt2860_stop(ifp, 0); 1926 rt2860_init(ifp); 1927 } 1928 error = 0; 1929 } 1930 1931 splx(s); 1932 1933 return error; 1934 } 1935 1936 /* 1937 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 1938 * We access the BBP through the 8051 microcontroller unit which means that 1939 * the microcode must be loaded first. 1940 */ 1941 static void 1942 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 1943 { 1944 int ntries; 1945 1946 for (ntries = 0; ntries < 100; ntries++) { 1947 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 1948 break; 1949 DELAY(1); 1950 } 1951 if (ntries == 100) { 1952 aprint_error_dev(sc->sc_dev, 1953 "could not write to BBP through MCU\n"); 1954 return; 1955 } 1956 1957 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 1958 RT2860_BBP_CSR_KICK | reg << 8 | val); 1959 RAL_BARRIER_WRITE(sc); 1960 1961 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 1962 DELAY(1000); 1963 } 1964 1965 static uint8_t 1966 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 1967 { 1968 uint32_t val; 1969 int ntries; 1970 1971 for (ntries = 0; ntries < 100; ntries++) { 1972 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 1973 break; 1974 DELAY(1); 1975 } 1976 if (ntries == 100) { 1977 aprint_error_dev(sc->sc_dev, 1978 "could not read from BBP through MCU\n"); 1979 return 0; 1980 } 1981 1982 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 1983 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 1984 RAL_BARRIER_WRITE(sc); 1985 1986 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 1987 DELAY(1000); 1988 1989 for (ntries = 0; ntries < 100; ntries++) { 1990 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 1991 if (!(val & RT2860_BBP_CSR_KICK)) 1992 return val & 0xff; 1993 DELAY(1); 1994 } 1995 aprint_error_dev(sc->sc_dev, "could not read from BBP through MCU\n"); 1996 1997 return 0; 1998 } 1999 2000 /* 2001 * Write to one of the 4 programmable 24-bit RF registers. 2002 */ 2003 static void 2004 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2005 { 2006 uint32_t tmp; 2007 int ntries; 2008 2009 for (ntries = 0; ntries < 100; ntries++) { 2010 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2011 break; 2012 DELAY(1); 2013 } 2014 if (ntries == 100) { 2015 aprint_error_dev(sc->sc_dev, "could not write to RF\n"); 2016 return; 2017 } 2018 2019 /* RF registers are 24-bit on the RT2860 */ 2020 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2021 (val & 0x3fffff) << 2 | (reg & 3); 2022 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2023 } 2024 2025 static uint8_t 2026 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2027 { 2028 uint32_t tmp; 2029 int ntries; 2030 2031 for (ntries = 0; ntries < 100; ntries++) { 2032 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2033 break; 2034 DELAY(1); 2035 } 2036 if (ntries == 100) { 2037 aprint_error_dev(sc->sc_dev, "could not read RF register\n"); 2038 return 0xff; 2039 } 2040 tmp = RT3070_RF_KICK | reg << 8; 2041 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2042 2043 for (ntries = 0; ntries < 100; ntries++) { 2044 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2045 if (!(tmp & RT3070_RF_KICK)) 2046 break; 2047 DELAY(1); 2048 } 2049 if (ntries == 100) { 2050 aprint_error_dev(sc->sc_dev, "could not read RF register\n"); 2051 return 0xff; 2052 } 2053 return tmp & 0xff; 2054 } 2055 2056 static void 2057 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2058 { 2059 uint32_t tmp; 2060 int ntries; 2061 2062 for (ntries = 0; ntries < 10; ntries++) { 2063 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2064 break; 2065 DELAY(10); 2066 } 2067 if (ntries == 10) { 2068 aprint_error_dev(sc->sc_dev, "could not write to RF\n"); 2069 return; 2070 } 2071 2072 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2073 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2074 } 2075 2076 /* 2077 * Send a command to the 8051 microcontroller unit. 2078 */ 2079 static int 2080 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2081 { 2082 int slot, ntries; 2083 uint32_t tmp; 2084 uint8_t cid; 2085 2086 for (ntries = 0; ntries < 100; ntries++) { 2087 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2088 break; 2089 DELAY(2); 2090 } 2091 if (ntries == 100) 2092 return EIO; 2093 2094 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2095 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2096 RAL_BARRIER_WRITE(sc); 2097 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2098 2099 if (!wait) 2100 return 0; 2101 /* wait for the command to complete */ 2102 for (ntries = 0; ntries < 200; ntries++) { 2103 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2104 /* find the command slot */ 2105 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2106 if ((tmp & 0xff) == cid) 2107 break; 2108 if (slot < 4) 2109 break; 2110 DELAY(100); 2111 } 2112 if (ntries == 200) { 2113 /* clear command and status */ 2114 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2115 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2116 return ETIMEDOUT; 2117 } 2118 /* get command status (1 means success) */ 2119 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2120 tmp = (tmp >> (slot * 8)) & 0xff; 2121 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2122 cmd, slot, tmp)); 2123 /* clear command and status */ 2124 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2125 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2126 return (tmp == 1) ? 0 : EIO; 2127 } 2128 2129 static void 2130 rt2860_enable_mrr(struct rt2860_softc *sc) 2131 { 2132 #define CCK(mcs) (mcs) 2133 #define OFDM(mcs) (1 << 3 | (mcs)) 2134 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2135 OFDM(6) << 28 | /* 54->48 */ 2136 OFDM(5) << 24 | /* 48->36 */ 2137 OFDM(4) << 20 | /* 36->24 */ 2138 OFDM(3) << 16 | /* 24->18 */ 2139 OFDM(2) << 12 | /* 18->12 */ 2140 OFDM(1) << 8 | /* 12-> 9 */ 2141 OFDM(0) << 4 | /* 9-> 6 */ 2142 OFDM(0)); /* 6-> 6 */ 2143 2144 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2145 CCK(2) << 12 | /* 11->5.5 */ 2146 CCK(1) << 8 | /* 5.5-> 2 */ 2147 CCK(0) << 4 | /* 2-> 1 */ 2148 CCK(0)); /* 1-> 1 */ 2149 #undef OFDM 2150 #undef CCK 2151 } 2152 2153 static void 2154 rt2860_set_txpreamble(struct rt2860_softc *sc) 2155 { 2156 uint32_t tmp; 2157 2158 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2159 tmp &= ~RT2860_CCK_SHORT_EN; 2160 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2161 tmp |= RT2860_CCK_SHORT_EN; 2162 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2163 } 2164 2165 static void 2166 rt2860_set_basicrates(struct rt2860_softc *sc) 2167 { 2168 struct ieee80211com *ic = &sc->sc_ic; 2169 2170 /* set basic rates mask */ 2171 if (ic->ic_curmode == IEEE80211_MODE_11B) 2172 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 2173 else if (ic->ic_curmode == IEEE80211_MODE_11A) 2174 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 2175 else /* 11g */ 2176 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 2177 } 2178 2179 static void 2180 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2181 { 2182 uint32_t tmp; 2183 uint8_t agc; 2184 2185 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2186 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2187 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2188 rt2860_mcu_bbp_write(sc, 86, 0x00); 2189 2190 if (group == 0) { 2191 if (sc->ext_2ghz_lna) { 2192 rt2860_mcu_bbp_write(sc, 82, 0x62); 2193 rt2860_mcu_bbp_write(sc, 75, 0x46); 2194 } else { 2195 rt2860_mcu_bbp_write(sc, 82, 0x84); 2196 rt2860_mcu_bbp_write(sc, 75, 0x50); 2197 } 2198 } else { 2199 if (sc->mac_ver == 0x3572) 2200 rt2860_mcu_bbp_write(sc, 82, 0x94); 2201 else 2202 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2203 2204 if (sc->ext_5ghz_lna) 2205 rt2860_mcu_bbp_write(sc, 75, 0x46); 2206 else 2207 rt2860_mcu_bbp_write(sc, 75, 0x50); 2208 } 2209 2210 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2211 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2212 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2213 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2214 2215 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2216 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2217 if (sc->nrxchains > 1) 2218 tmp |= RT2860_LNA_PE1_EN; 2219 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2220 tmp |= RT3593_LNA_PE2_EN; 2221 if (group == 0) { /* 2GHz */ 2222 tmp |= RT2860_PA_PE_G0_EN; 2223 if (sc->ntxchains > 1) 2224 tmp |= RT2860_PA_PE_G1_EN; 2225 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2226 tmp |= RT3593_PA_PE_G2_EN; 2227 } else { /* 5GHz */ 2228 tmp |= RT2860_PA_PE_A0_EN; 2229 if (sc->ntxchains > 1) 2230 tmp |= RT2860_PA_PE_A1_EN; 2231 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2232 tmp |= RT3593_PA_PE_A2_EN; 2233 } 2234 if (sc->mac_ver == 0x3572) { 2235 rt3090_rf_write(sc, 8, 0x00); 2236 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2237 rt3090_rf_write(sc, 8, 0x80); 2238 } else 2239 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2240 2241 if (sc->mac_ver == 0x3593) { 2242 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2243 if (sc->sc_flags & RT2860_PCIE) { 2244 tmp &= ~0x01010000; 2245 if (group == 0) 2246 tmp |= 0x00010000; 2247 } else { 2248 tmp &= ~0x00008080; 2249 if (group == 0) 2250 tmp |= 0x00000080; 2251 } 2252 tmp = (tmp & ~0x00001000) | 0x00000010; 2253 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2254 } 2255 2256 /* set initial AGC value */ 2257 if (group == 0) { /* 2GHz band */ 2258 if (sc->mac_ver >= 0x3071) 2259 agc = 0x1c + sc->lna[0] * 2; 2260 else 2261 agc = 0x2e + sc->lna[0]; 2262 } else { /* 5GHz band */ 2263 if (sc->mac_ver == 0x3572) 2264 agc = 0x22 + (sc->lna[group] * 5) / 3; 2265 else 2266 agc = 0x32 + (sc->lna[group] * 5) / 3; 2267 } 2268 rt2860_mcu_bbp_write(sc, 66, agc); 2269 2270 DELAY(1000); 2271 } 2272 2273 static void 2274 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2275 { 2276 const struct rfprog *rfprog = rt2860_rf2850; 2277 uint32_t r2, r3, r4; 2278 int8_t txpow1, txpow2; 2279 u_int i; 2280 2281 /* find the settings for this channel (we know it exists) */ 2282 for (i = 0; rfprog[i].chan != chan; i++); 2283 2284 r2 = rfprog[i].r2; 2285 if (sc->ntxchains == 1) 2286 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2287 if (sc->nrxchains == 1) 2288 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2289 else if (sc->nrxchains == 2) 2290 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2291 2292 /* use Tx power values from EEPROM */ 2293 txpow1 = sc->txpow1[i]; 2294 txpow2 = sc->txpow2[i]; 2295 if (chan > 14) { 2296 if (txpow1 >= 0) 2297 txpow1 = txpow1 << 1 | 1; 2298 else 2299 txpow1 = (7 + txpow1) << 1; 2300 if (txpow2 >= 0) 2301 txpow2 = txpow2 << 1 | 1; 2302 else 2303 txpow2 = (7 + txpow2) << 1; 2304 } 2305 r3 = rfprog[i].r3 | txpow1 << 7; 2306 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2307 2308 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2309 rt2860_rf_write(sc, RT2860_RF2, r2); 2310 rt2860_rf_write(sc, RT2860_RF3, r3); 2311 rt2860_rf_write(sc, RT2860_RF4, r4); 2312 2313 DELAY(200); 2314 2315 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2316 rt2860_rf_write(sc, RT2860_RF2, r2); 2317 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2318 rt2860_rf_write(sc, RT2860_RF4, r4); 2319 2320 DELAY(200); 2321 2322 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2323 rt2860_rf_write(sc, RT2860_RF2, r2); 2324 rt2860_rf_write(sc, RT2860_RF3, r3); 2325 rt2860_rf_write(sc, RT2860_RF4, r4); 2326 } 2327 2328 static void 2329 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2330 { 2331 int8_t txpow1, txpow2; 2332 uint8_t rf; 2333 int i; 2334 2335 KASSERT(chan >= 1 && chan <= 14); /* RT3090 is 2GHz only */ 2336 2337 /* find the settings for this channel (we know it exists) */ 2338 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2339 2340 /* use Tx power values from EEPROM */ 2341 txpow1 = sc->txpow1[i]; 2342 txpow2 = sc->txpow2[i]; 2343 2344 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2345 rf = rt3090_rf_read(sc, 3); 2346 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2347 rt3090_rf_write(sc, 3, rf); 2348 rf = rt3090_rf_read(sc, 6); 2349 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2350 rt3090_rf_write(sc, 6, rf); 2351 2352 /* set Tx0 power */ 2353 rf = rt3090_rf_read(sc, 12); 2354 rf = (rf & ~0x1f) | txpow1; 2355 rt3090_rf_write(sc, 12, rf); 2356 2357 /* set Tx1 power */ 2358 rf = rt3090_rf_read(sc, 13); 2359 rf = (rf & ~0x1f) | txpow2; 2360 rt3090_rf_write(sc, 13, rf); 2361 2362 rf = rt3090_rf_read(sc, 1); 2363 rf &= ~0xfc; 2364 if (sc->ntxchains == 1) 2365 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2366 else if (sc->ntxchains == 2) 2367 rf |= RT3070_TX2_PD; 2368 if (sc->nrxchains == 1) 2369 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2370 else if (sc->nrxchains == 2) 2371 rf |= RT3070_RX2_PD; 2372 rt3090_rf_write(sc, 1, rf); 2373 2374 /* set RF offset */ 2375 rf = rt3090_rf_read(sc, 23); 2376 rf = (rf & ~0x7f) | sc->freq; 2377 rt3090_rf_write(sc, 23, rf); 2378 2379 /* program RF filter */ 2380 rf = rt3090_rf_read(sc, 24); /* Tx */ 2381 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2382 rt3090_rf_write(sc, 24, rf); 2383 rf = rt3090_rf_read(sc, 31); /* Rx */ 2384 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2385 rt3090_rf_write(sc, 31, rf); 2386 2387 /* enable RF tuning */ 2388 rf = rt3090_rf_read(sc, 7); 2389 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2390 } 2391 2392 static void 2393 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2394 { 2395 uint8_t h20mhz, rf, tmp; 2396 int8_t txpow1, txpow2; 2397 int i; 2398 2399 /* RT5390 is 2GHz only */ 2400 KASSERT(chan >= 1 && chan <= 14); 2401 2402 /* find the settings for this channel (we know it exists) */ 2403 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2404 2405 /* use Tx power values from EEPROM */ 2406 txpow1 = sc->txpow1[i]; 2407 txpow2 = sc->txpow2[i]; 2408 2409 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2410 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2411 rf = rt3090_rf_read(sc, 11); 2412 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2413 rt3090_rf_write(sc, 11, rf); 2414 2415 rf = rt3090_rf_read(sc, 49); 2416 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2417 /* the valid range of the RF R49 is 0x00~0x27 */ 2418 if ((rf & 0x3f) > 0x27) 2419 rf = (rf & ~0x3f) | 0x27; 2420 rt3090_rf_write(sc, 49, rf); 2421 if (sc->mac_ver == 0x5392) { 2422 rf = rt3090_rf_read(sc, 50); 2423 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2424 /* the valid range of the RF R50 is 0x00~0x27 */ 2425 if ((rf & 0x3f) > 0x27) 2426 rf = (rf & ~0x3f) | 0x27; 2427 rt3090_rf_write(sc, 50, rf); 2428 } 2429 2430 rf = rt3090_rf_read(sc, 1); 2431 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2432 if (sc->mac_ver == 0x5392) 2433 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2434 rt3090_rf_write(sc, 1, rf); 2435 2436 rf = rt3090_rf_read(sc, 2); 2437 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2438 DELAY(1000); 2439 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2440 2441 rf = rt3090_rf_read(sc, 17); 2442 tmp = rf; 2443 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2444 rf = MIN(rf, 0x5f); 2445 if (tmp != rf) 2446 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2447 2448 if (sc->mac_ver == 0x5390) { 2449 if (chan <= 4) 2450 rf = 0x73; 2451 else if (chan >= 5 && chan <= 6) 2452 rf = 0x63; 2453 else if (chan >= 7 && chan <= 10) 2454 rf = 0x53; 2455 else 2456 rf = 43; 2457 rt3090_rf_write(sc, 55, rf); 2458 2459 if (chan == 1) 2460 rf = 0x0c; 2461 else if (chan == 2) 2462 rf = 0x0b; 2463 else if (chan == 3) 2464 rf = 0x0a; 2465 else if (chan >= 4 && chan <= 6) 2466 rf = 0x09; 2467 else if (chan >= 7 && chan <= 12) 2468 rf = 0x08; 2469 else if (chan == 13) 2470 rf = 0x07; 2471 else 2472 rf = 0x06; 2473 rt3090_rf_write(sc, 59, rf); 2474 } 2475 2476 /* Tx/Rx h20M */ 2477 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2478 rf = rt3090_rf_read(sc, 30); 2479 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2480 rt3090_rf_write(sc, 30, rf); 2481 2482 /* Rx BB filter VCM */ 2483 rf = rt3090_rf_read(sc, 30); 2484 rf = (rf & ~0x18) | 0x10; 2485 rt3090_rf_write(sc, 30, rf); 2486 2487 /* Initiate VCO calibration. */ 2488 rf = rt3090_rf_read(sc, 3); 2489 rf |= RT3593_VCOCAL; 2490 rt3090_rf_write(sc, 3, rf); 2491 } 2492 2493 static void 2494 rt3090_rf_init(struct rt2860_softc *sc) 2495 { 2496 uint32_t tmp; 2497 uint8_t rf, bbp; 2498 int i; 2499 2500 rf = rt3090_rf_read(sc, 30); 2501 /* toggle RF R30 bit 7 */ 2502 rt3090_rf_write(sc, 30, rf | 0x80); 2503 DELAY(1000); 2504 rt3090_rf_write(sc, 30, rf & ~0x80); 2505 2506 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2507 tmp &= ~0x1f000000; 2508 if (sc->patch_dac && sc->mac_rev < 0x0211) 2509 tmp |= 0x0d000000; /* 1.35V */ 2510 else 2511 tmp |= 0x01000000; /* 1.2V */ 2512 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2513 2514 /* patch LNA_PE_G1 */ 2515 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2516 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2517 2518 /* initialize RF registers to default value */ 2519 if (sc->mac_ver == 0x3572) { 2520 for (i = 0; i < (int)__arraycount(rt3572_def_rf); i++) { 2521 rt3090_rf_write(sc, rt3572_def_rf[i].reg, 2522 rt3572_def_rf[i].val); 2523 } 2524 } else { 2525 for (i = 0; i < (int)__arraycount(rt3090_def_rf); i++) { 2526 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2527 rt3090_def_rf[i].val); 2528 } 2529 } 2530 2531 /* select 20MHz bandwidth */ 2532 rt3090_rf_write(sc, 31, 0x14); 2533 2534 rf = rt3090_rf_read(sc, 6); 2535 rt3090_rf_write(sc, 6, rf | 0x40); 2536 2537 if (sc->mac_ver != 0x3593) { 2538 /* calibrate filter for 20MHz bandwidth */ 2539 sc->rf24_20mhz = 0x1f; /* default value */ 2540 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2541 2542 /* select 40MHz bandwidth */ 2543 bbp = rt2860_mcu_bbp_read(sc, 4); 2544 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2545 rf = rt3090_rf_read(sc, 31); 2546 rt3090_rf_write(sc, 31, rf | 0x20); 2547 2548 /* calibrate filter for 40MHz bandwidth */ 2549 sc->rf24_40mhz = 0x2f; /* default value */ 2550 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2551 2552 /* go back to 20MHz bandwidth */ 2553 bbp = rt2860_mcu_bbp_read(sc, 4); 2554 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2555 } 2556 if (sc->mac_rev < 0x0211) 2557 rt3090_rf_write(sc, 27, 0x03); 2558 2559 tmp = RAL_READ(sc, RT3070_OPT_14); 2560 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2561 2562 if (sc->rf_rev == RT3070_RF_3020) 2563 rt3090_set_rx_antenna(sc, 0); 2564 2565 bbp = rt2860_mcu_bbp_read(sc, 138); 2566 if (sc->mac_ver == 0x3593) { 2567 if (sc->ntxchains == 1) 2568 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2569 else if (sc->ntxchains == 2) 2570 bbp |= 0x40; /* turn off DAC2 */ 2571 if (sc->nrxchains == 1) 2572 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2573 else if (sc->nrxchains == 2) 2574 bbp &= ~0x04; /* turn off ADC2 */ 2575 } else { 2576 if (sc->ntxchains == 1) 2577 bbp |= 0x20; /* turn off DAC1 */ 2578 if (sc->nrxchains == 1) 2579 bbp &= ~0x02; /* turn off ADC1 */ 2580 } 2581 rt2860_mcu_bbp_write(sc, 138, bbp); 2582 2583 rf = rt3090_rf_read(sc, 1); 2584 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2585 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2586 rt3090_rf_write(sc, 1, rf); 2587 2588 rf = rt3090_rf_read(sc, 15); 2589 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2590 2591 rf = rt3090_rf_read(sc, 17); 2592 rf &= ~RT3070_TX_LO1; 2593 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2594 rf |= 0x20; /* fix for long range Rx issue */ 2595 if (sc->txmixgain_2ghz >= 2) 2596 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2597 rt3090_rf_write(sc, 17, rf); 2598 2599 rf = rt3090_rf_read(sc, 20); 2600 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2601 2602 rf = rt3090_rf_read(sc, 21); 2603 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2604 } 2605 2606 static void 2607 rt5390_rf_init(struct rt2860_softc *sc) 2608 { 2609 uint8_t rf, bbp; 2610 int i; 2611 2612 rf = rt3090_rf_read(sc, 2); 2613 /* Toggle RF R2 bit 7. */ 2614 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2615 DELAY(1000); 2616 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2617 2618 /* Initialize RF registers to default value. */ 2619 if (sc->mac_ver == 0x5392) { 2620 for (i = 0; i < __arraycount(rt5392_def_rf); i++) { 2621 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2622 rt5392_def_rf[i].val); 2623 } 2624 } else { 2625 for (i = 0; i < __arraycount(rt5390_def_rf); i++) { 2626 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2627 rt5390_def_rf[i].val); 2628 } 2629 } 2630 2631 sc->rf24_20mhz = 0x1f; 2632 sc->rf24_40mhz = 0x2f; 2633 2634 if (sc->mac_rev < 0x0211) 2635 rt3090_rf_write(sc, 27, 0x03); 2636 2637 /* Set led open drain enable. */ 2638 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2639 2640 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2641 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2642 2643 if (sc->mac_ver == 0x5390) 2644 rt3090_set_rx_antenna(sc, 0); 2645 2646 /* Patch RSSI inaccurate issue. */ 2647 rt2860_mcu_bbp_write(sc, 79, 0x13); 2648 rt2860_mcu_bbp_write(sc, 80, 0x05); 2649 rt2860_mcu_bbp_write(sc, 81, 0x33); 2650 2651 /* Enable DC filter. */ 2652 if (sc->mac_rev >= 0x0211) 2653 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2654 2655 bbp = rt2860_mcu_bbp_read(sc, 138); 2656 if (sc->ntxchains == 1) 2657 bbp |= 0x20; /* Turn off DAC1. */ 2658 if (sc->nrxchains == 1) 2659 bbp &= ~0x02; /* Turn off ADC1. */ 2660 rt2860_mcu_bbp_write(sc, 138, bbp); 2661 2662 /* Enable RX LO1 and LO2. */ 2663 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2664 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2665 2666 /* Avoid data lost and CRC error. */ 2667 rt2860_mcu_bbp_write(sc, 4, 2668 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2669 2670 rf = rt3090_rf_read(sc, 30); 2671 rf = (rf & ~0x18) | 0x10; 2672 rt3090_rf_write(sc, 30, rf); 2673 } 2674 2675 static void 2676 rt3090_rf_wakeup(struct rt2860_softc *sc) 2677 { 2678 uint32_t tmp; 2679 uint8_t rf; 2680 2681 if (sc->mac_ver == 0x3593) { 2682 /* enable VCO */ 2683 rf = rt3090_rf_read(sc, 1); 2684 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2685 2686 /* initiate VCO calibration */ 2687 rf = rt3090_rf_read(sc, 3); 2688 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2689 2690 /* enable VCO bias current control */ 2691 rf = rt3090_rf_read(sc, 6); 2692 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2693 2694 /* initiate res calibration */ 2695 rf = rt3090_rf_read(sc, 2); 2696 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2697 2698 /* set reference current control to 0.33 mA */ 2699 rf = rt3090_rf_read(sc, 22); 2700 rf &= ~RT3593_CP_IC_MASK; 2701 rf |= 1 << RT3593_CP_IC_SHIFT; 2702 rt3090_rf_write(sc, 22, rf); 2703 2704 /* enable RX CTB */ 2705 rf = rt3090_rf_read(sc, 46); 2706 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2707 2708 rf = rt3090_rf_read(sc, 20); 2709 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2710 rt3090_rf_write(sc, 20, rf); 2711 } else { 2712 /* enable RF block */ 2713 rf = rt3090_rf_read(sc, 1); 2714 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2715 2716 /* enable VCO bias current control */ 2717 rf = rt3090_rf_read(sc, 7); 2718 rt3090_rf_write(sc, 7, rf | 0x30); 2719 2720 rf = rt3090_rf_read(sc, 9); 2721 rt3090_rf_write(sc, 9, rf | 0x0e); 2722 2723 /* enable RX CTB */ 2724 rf = rt3090_rf_read(sc, 21); 2725 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2726 2727 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2728 rf = rt3090_rf_read(sc, 27); 2729 rf &= ~0x77; 2730 if (sc->mac_rev < 0x0211) 2731 rf |= 0x03; 2732 rt3090_rf_write(sc, 27, rf); 2733 } 2734 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2735 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2736 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2737 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2738 } 2739 } 2740 2741 static void 2742 rt5390_rf_wakeup(struct rt2860_softc *sc) 2743 { 2744 uint32_t tmp; 2745 uint8_t rf; 2746 2747 rf = rt3090_rf_read(sc, 1); 2748 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2749 RT3070_TX0_PD; 2750 if (sc->mac_ver == 0x5392) 2751 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2752 rt3090_rf_write(sc, 1, rf); 2753 2754 rf = rt3090_rf_read(sc, 6); 2755 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2756 if (sc->mac_ver == 0x5390) 2757 rf &= ~RT3593_VCO_IC; 2758 rt3090_rf_write(sc, 6, rf); 2759 2760 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2761 2762 rf = rt3090_rf_read(sc, 22); 2763 rf = (rf & ~0xe0) | 0x20; 2764 rt3090_rf_write(sc, 22, rf); 2765 2766 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2767 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2768 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2769 2770 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2771 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2772 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2773 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2774 } 2775 } 2776 2777 static int 2778 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2779 uint8_t *val) 2780 { 2781 uint8_t rf22, rf24; 2782 uint8_t bbp55_pb, bbp55_sb, delta; 2783 int ntries; 2784 2785 /* program filter */ 2786 rf24 = rt3090_rf_read(sc, 24); 2787 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2788 rt3090_rf_write(sc, 24, rf24); 2789 2790 /* enable baseband loopback mode */ 2791 rf22 = rt3090_rf_read(sc, 22); 2792 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2793 2794 /* set power and frequency of passband test tone */ 2795 rt2860_mcu_bbp_write(sc, 24, 0x00); 2796 for (ntries = 0; ntries < 100; ntries++) { 2797 /* transmit test tone */ 2798 rt2860_mcu_bbp_write(sc, 25, 0x90); 2799 DELAY(1000); 2800 /* read received power */ 2801 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2802 if (bbp55_pb != 0) 2803 break; 2804 } 2805 if (ntries == 100) 2806 return ETIMEDOUT; 2807 2808 /* set power and frequency of stopband test tone */ 2809 rt2860_mcu_bbp_write(sc, 24, 0x06); 2810 for (ntries = 0; ntries < 100; ntries++) { 2811 /* transmit test tone */ 2812 rt2860_mcu_bbp_write(sc, 25, 0x90); 2813 DELAY(1000); 2814 /* read received power */ 2815 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2816 2817 delta = bbp55_pb - bbp55_sb; 2818 if (delta > target) 2819 break; 2820 2821 /* reprogram filter */ 2822 rf24++; 2823 rt3090_rf_write(sc, 24, rf24); 2824 } 2825 if (ntries < 100) { 2826 if (rf24 != init) 2827 rf24--; /* backtrack */ 2828 *val = rf24; 2829 rt3090_rf_write(sc, 24, rf24); 2830 } 2831 2832 /* restore initial state */ 2833 rt2860_mcu_bbp_write(sc, 24, 0x00); 2834 2835 /* disable baseband loopback mode */ 2836 rf22 = rt3090_rf_read(sc, 22); 2837 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2838 2839 return 0; 2840 } 2841 2842 static void 2843 rt3090_rf_setup(struct rt2860_softc *sc) 2844 { 2845 uint8_t bbp; 2846 int i; 2847 2848 if (sc->mac_rev >= 0x0211) { 2849 /* enable DC filter */ 2850 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2851 2852 /* improve power consumption */ 2853 bbp = rt2860_mcu_bbp_read(sc, 31); 2854 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2855 } 2856 2857 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2858 if (sc->mac_rev < 0x0211) { 2859 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2860 sc->patch_dac ? 0x2c : 0x0f); 2861 } else 2862 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2863 2864 /* initialize RF registers from ROM */ 2865 if (sc->mac_ver < 0x5390) { 2866 for (i = 0; i < 10; i++) { 2867 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 2868 continue; 2869 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 2870 } 2871 } 2872 } 2873 2874 static void 2875 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 2876 { 2877 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 2878 which | (sc->leds & 0x7f), 0); 2879 } 2880 2881 /* 2882 * Hardware has a general-purpose programmable timer interrupt that can 2883 * periodically raise MAC_INT_4. 2884 */ 2885 static void 2886 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 2887 { 2888 uint32_t tmp; 2889 2890 /* disable GP timer before reprogramming it */ 2891 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2892 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 2893 2894 if (ms == 0) 2895 return; 2896 2897 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 2898 ms *= 16; /* Unit: 64us */ 2899 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 2900 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 2901 2902 /* enable GP timer */ 2903 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2904 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 2905 } 2906 2907 static void 2908 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 2909 { 2910 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 2911 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 2912 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 2913 bssid[4] | bssid[5] << 8); 2914 } 2915 2916 static void 2917 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 2918 { 2919 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 2920 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2921 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 2922 addr[4] | addr[5] << 8 | 0xff << 16); 2923 } 2924 2925 static void 2926 rt2860_updateslot(struct ifnet *ifp) 2927 { 2928 struct rt2860_softc *sc = ifp->if_softc; 2929 struct ieee80211com *ic = &sc->sc_ic; 2930 uint32_t tmp; 2931 2932 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 2933 tmp &= ~0xff; 2934 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2935 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 2936 } 2937 2938 static void 2939 rt2860_updateprot(struct ieee80211com *ic) 2940 { 2941 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 2942 uint32_t tmp; 2943 2944 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 2945 /* setup protection frame rate (MCS code) */ 2946 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 2947 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 2948 rt2860_rates[RT2860_RIDX_CCK11].mcs; 2949 2950 /* CCK frames don't require protection */ 2951 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 2952 2953 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2954 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2955 tmp |= RT2860_PROT_CTRL_RTS_CTS; 2956 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2957 tmp |= RT2860_PROT_CTRL_CTS; 2958 } 2959 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 2960 } 2961 2962 static void 2963 rt2860_update_promisc(struct ifnet *ifp) 2964 { 2965 struct rt2860_softc *sc = ifp->if_softc; 2966 uint32_t tmp; 2967 2968 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 2969 tmp &= ~RT2860_DROP_NOT_MYBSS; 2970 if (!(ifp->if_flags & IFF_PROMISC)) 2971 tmp |= RT2860_DROP_NOT_MYBSS; 2972 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 2973 } 2974 2975 static int 2976 rt2860_updateedca(struct ieee80211com *ic) 2977 { 2978 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 2979 int aci; 2980 2981 /* update MAC TX configuration registers */ 2982 for (aci = 0; aci < WME_NUM_AC; aci++) { 2983 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 2984 ic->ic_wme.wme_params[aci].wmep_logcwmax << 16 | 2985 ic->ic_wme.wme_params[aci].wmep_logcwmin << 12 | 2986 ic->ic_wme.wme_params[aci].wmep_aifsn << 8 | 2987 ic->ic_wme.wme_params[aci].wmep_txopLimit); 2988 } 2989 2990 /* update SCH/DMA registers too */ 2991 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 2992 ic->ic_wme.wme_params[WME_AC_VO].wmep_aifsn << 12 | 2993 ic->ic_wme.wme_params[WME_AC_VI].wmep_aifsn << 8 | 2994 ic->ic_wme.wme_params[WME_AC_BK].wmep_aifsn << 4 | 2995 ic->ic_wme.wme_params[WME_AC_BE].wmep_aifsn); 2996 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 2997 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmin << 12 | 2998 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmin << 8 | 2999 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmin << 4 | 3000 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmin); 3001 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 3002 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmax << 12 | 3003 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmax << 8 | 3004 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmax << 4 | 3005 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmax); 3006 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 3007 ic->ic_wme.wme_params[WME_AC_BK].wmep_txopLimit << 16 | 3008 ic->ic_wme.wme_params[WME_AC_BE].wmep_txopLimit); 3009 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 3010 ic->ic_wme.wme_params[WME_AC_VO].wmep_txopLimit << 16 | 3011 ic->ic_wme.wme_params[WME_AC_VI].wmep_txopLimit); 3012 return 0; 3013 } 3014 3015 #ifdef HW_CRYPTO 3016 static int 3017 rt2860_set_key(struct ieee80211com *ic, const struct ieee80211_key *ck, 3018 const uint8_t *mac) 3019 { 3020 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 3021 struct ieee80211_node *ni = ic->ic_bss; 3022 bus_size_t base; 3023 uint32_t attr; 3024 uint8_t mode, wcid, iv[8]; 3025 struct ieee80211_key *k = __UNCONST(ck); /* XXX */ 3026 3027 /* map net80211 cipher to RT2860 security mode */ 3028 switch (k->wk_cipher->ic_cipher) { 3029 case IEEE80211_CIPHER_WEP: 3030 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 3031 if (k->wk_keylen == 5) 3032 mode = RT2860_MODE_WEP40; 3033 else 3034 mode = RT2860_MODE_WEP104; 3035 break; 3036 case IEEE80211_CIPHER_TKIP: 3037 mode = RT2860_MODE_TKIP; 3038 break; 3039 case IEEE80211_CIPHER_AES_CCM: 3040 mode = RT2860_MODE_AES_CCMP; 3041 break; 3042 default: 3043 return EINVAL; 3044 } 3045 3046 if (k->wk_flags & IEEE80211_KEY_GROUP) { 3047 wcid = 0; /* NB: update WCID0 for group keys */ 3048 base = RT2860_SKEY(0, k->wk_keyix); 3049 } else { 3050 wcid = ((struct rt2860_node *)ni)->wcid; 3051 base = RT2860_PKEY(wcid); 3052 } 3053 3054 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 3055 RAL_WRITE_REGION_1(sc, base, k->wk_key, 16); 3056 #ifndef IEEE80211_STA_ONLY 3057 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3058 RAL_WRITE_REGION_1(sc, base + 16, &k->wk_key[16], 8); 3059 RAL_WRITE_REGION_1(sc, base + 24, &k->wk_key[24], 8); 3060 } else 3061 #endif 3062 { 3063 RAL_WRITE_REGION_1(sc, base + 16, &k->wk_key[24], 8); 3064 RAL_WRITE_REGION_1(sc, base + 24, &k->wk_key[16], 8); 3065 } 3066 } else 3067 RAL_WRITE_REGION_1(sc, base, k->wk_key, k->wk_keylen); 3068 3069 if (!(k->wk_flags & IEEE80211_KEY_GROUP) || 3070 (k->wk_flags & IEEE80211_KEY_XMIT)) { 3071 /* set initial packet number in IV+EIV */ 3072 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) { 3073 uint32_t val = cprng_fast32(); 3074 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3075 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3076 val += 0x000100; 3077 iv[0] = val; 3078 iv[1] = val >> 8; 3079 iv[2] = val >> 16; 3080 iv[3] = k->wk_keyix << 6; 3081 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3082 } else { 3083 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 3084 iv[0] = k->wk_keytsc >> 8; 3085 iv[1] = (iv[0] | 0x20) & 0x7f; 3086 iv[2] = k->wk_keytsc; 3087 } else /* CCMP */ { 3088 iv[0] = k->wk_keytsc; 3089 iv[1] = k->wk_keytsc >> 8; 3090 iv[2] = 0; 3091 } 3092 iv[3] = k->wk_keyix << 6 | IEEE80211_WEP_EXTIV; 3093 iv[4] = k->wk_keytsc >> 16; 3094 iv[5] = k->wk_keytsc >> 24; 3095 iv[6] = k->wk_keytsc >> 32; 3096 iv[7] = k->wk_keytsc >> 40; 3097 } 3098 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3099 } 3100 3101 if (k->wk_flags & IEEE80211_KEY_GROUP) { 3102 /* install group key */ 3103 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3104 attr &= ~(0xf << (k->wk_keyix * 4)); 3105 attr |= mode << (k->wk_keyix * 4); 3106 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3107 } else { 3108 /* install pairwise key */ 3109 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3110 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3111 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3112 } 3113 return 0; 3114 } 3115 3116 static int 3117 rt2860_delete_key(struct ieee80211com *ic, const struct ieee80211_key *k) 3118 { 3119 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 3120 struct ieee80211_node *ni = ic->ic_bss; 3121 uint32_t attr; 3122 uint8_t wcid; 3123 3124 if (k->wk_flags & IEEE80211_KEY_GROUP) { 3125 /* remove group key */ 3126 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3127 attr &= ~(0xf << (k->wk_keyix * 4)); 3128 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3129 3130 } else { 3131 /* remove pairwise key */ 3132 wcid = ((struct rt2860_node *)ni)->wcid; 3133 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3134 attr &= ~0xf; 3135 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3136 } 3137 return 1; 3138 } 3139 #endif 3140 3141 static int8_t 3142 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3143 { 3144 struct ieee80211com *ic = &sc->sc_ic; 3145 struct ieee80211_channel *c = ic->ic_curchan; 3146 int delta; 3147 3148 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3149 u_int chan = ieee80211_chan2ieee(ic, c); 3150 delta = sc->rssi_5ghz[rxchain]; 3151 3152 /* determine channel group */ 3153 if (chan <= 64) 3154 delta -= sc->lna[1]; 3155 else if (chan <= 128) 3156 delta -= sc->lna[2]; 3157 else 3158 delta -= sc->lna[3]; 3159 } else 3160 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3161 3162 return -12 - delta - rssi; 3163 } 3164 3165 /* 3166 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3167 * Used to adjust per-rate Tx power registers. 3168 */ 3169 static __inline uint32_t 3170 b4inc(uint32_t b32, int8_t delta) 3171 { 3172 int8_t i, b4; 3173 3174 for (i = 0; i < 8; i++) { 3175 b4 = b32 & 0xf; 3176 b4 += delta; 3177 if (b4 < 0) 3178 b4 = 0; 3179 else if (b4 > 0xf) 3180 b4 = 0xf; 3181 b32 = b32 >> 4 | b4 << 28; 3182 } 3183 return b32; 3184 } 3185 3186 static const char * 3187 rt2860_get_rf(uint32_t rev) 3188 { 3189 switch (rev) { 3190 case RT2860_RF_2820: return "RT2820"; 3191 case RT2860_RF_2850: return "RT2850"; 3192 case RT2860_RF_2720: return "RT2720"; 3193 case RT2860_RF_2750: return "RT2750"; 3194 case RT3070_RF_3020: return "RT3020"; 3195 case RT3070_RF_2020: return "RT2020"; 3196 case RT3070_RF_3021: return "RT3021"; 3197 case RT3070_RF_3022: return "RT3022"; 3198 case RT3070_RF_3052: return "RT3052"; 3199 case RT3070_RF_3320: return "RT3320"; 3200 case RT3070_RF_3053: return "RT3053"; 3201 case RT5390_RF_5360: return "RT5360"; 3202 case RT5390_RF_5390: return "RT5390"; 3203 default: return "unknown"; 3204 } 3205 } 3206 3207 static int 3208 rt2860_read_eeprom(struct rt2860_softc *sc) 3209 { 3210 struct ieee80211com *ic = &sc->sc_ic; 3211 int8_t delta_2ghz, delta_5ghz; 3212 uint32_t tmp; 3213 uint16_t val; 3214 int ridx, ant, i; 3215 3216 /* check whether the ROM is eFUSE ROM or EEPROM */ 3217 sc->sc_srom_read = rt2860_eeprom_read_2; 3218 if (sc->mac_ver >= 0x3071) { 3219 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3220 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3221 if (tmp & RT3070_SEL_EFUSE) 3222 sc->sc_srom_read = rt3090_efuse_read_2; 3223 } 3224 3225 /* read EEPROM version */ 3226 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3227 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 3228 3229 /* read MAC address */ 3230 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3231 ic->ic_myaddr[0] = val & 0xff; 3232 ic->ic_myaddr[1] = val >> 8; 3233 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3234 ic->ic_myaddr[2] = val & 0xff; 3235 ic->ic_myaddr[3] = val >> 8; 3236 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3237 ic->ic_myaddr[4] = val & 0xff; 3238 ic->ic_myaddr[5] = val >> 8; 3239 3240 /* read country code */ 3241 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3242 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3243 3244 /* read vendor BBP settings */ 3245 for (i = 0; i < 8; i++) { 3246 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3247 sc->bbp[i].val = val & 0xff; 3248 sc->bbp[i].reg = val >> 8; 3249 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3250 } 3251 if (sc->mac_ver >= 0x3071) { 3252 /* read vendor RF settings */ 3253 for (i = 0; i < 10; i++) { 3254 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3255 sc->rf[i].val = val & 0xff; 3256 sc->rf[i].reg = val >> 8; 3257 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3258 sc->rf[i].val)); 3259 } 3260 } 3261 3262 /* read RF frequency offset from EEPROM */ 3263 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3264 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3265 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3266 if ((val >> 8) != 0xff) { 3267 /* read LEDs operating mode */ 3268 sc->leds = val >> 8; 3269 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3270 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3271 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3272 } else { 3273 /* broken EEPROM, use default settings */ 3274 sc->leds = 0x01; 3275 sc->led[0] = 0x5555; 3276 sc->led[1] = 0x2221; 3277 sc->led[2] = 0xa9f8; 3278 } 3279 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3280 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3281 3282 /* read RF information */ 3283 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3284 if (sc->mac_ver >= 0x5390) { 3285 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); 3286 sc->ntxchains = (val >> 4) & 0xf; 3287 sc->nrxchains = val & 0xf; 3288 } else if (val == 0xffff) { 3289 DPRINTF(("invalid EEPROM antenna info, using default\n")); 3290 if (sc->mac_ver == 0x3593) { 3291 /* default to RF3053 3T3R */ 3292 sc->rf_rev = RT3070_RF_3053; 3293 sc->ntxchains = 3; 3294 sc->nrxchains = 3; 3295 } else if (sc->mac_ver >= 0x3071) { 3296 /* default to RF3020 1T1R */ 3297 sc->rf_rev = RT3070_RF_3020; 3298 sc->ntxchains = 1; 3299 sc->nrxchains = 1; 3300 } else { 3301 /* default to RF2820 1T2R */ 3302 sc->rf_rev = RT2860_RF_2820; 3303 sc->ntxchains = 1; 3304 sc->nrxchains = 2; 3305 } 3306 } else { 3307 sc->rf_rev = (val >> 8) & 0xf; 3308 sc->ntxchains = (val >> 4) & 0xf; 3309 sc->nrxchains = val & 0xf; 3310 } 3311 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3312 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3313 3314 /* check if RF supports automatic Tx access gain control */ 3315 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3316 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3317 /* check if driver should patch the DAC issue */ 3318 if ((val >> 8) != 0xff) 3319 sc->patch_dac = (val >> 15) & 1; 3320 if ((val & 0xff) != 0xff) { 3321 sc->ext_5ghz_lna = (val >> 3) & 1; 3322 sc->ext_2ghz_lna = (val >> 2) & 1; 3323 /* check if RF supports automatic Tx access gain control */ 3324 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */ 3325 /* check if we have a hardware radio switch */ 3326 sc->rfswitch = val & 1; 3327 } 3328 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3329 /* read PCIe power save level */ 3330 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3331 if ((val & 0xff) != 0xff) { 3332 sc->pslevel = val & 0x3; 3333 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3334 if ((val & 0xff80) != 0x9280) 3335 sc->pslevel = MIN(sc->pslevel, 1); 3336 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3337 } 3338 } 3339 3340 /* read power settings for 2GHz channels */ 3341 for (i = 0; i < 14; i += 2) { 3342 val = rt2860_srom_read(sc, 3343 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3344 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3345 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3346 3347 if (sc->mac_ver != 0x5390) { 3348 val = rt2860_srom_read(sc, 3349 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3350 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3351 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3352 } 3353 } 3354 /* fix broken Tx power entries */ 3355 for (i = 0; i < 14; i++) { 3356 if (sc->txpow1[i] < 0 || 3357 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3358 sc->txpow1[i] = 5; 3359 if (sc->mac_ver != 0x5390) { 3360 if (sc->txpow2[i] < 0 || 3361 sc->txpow2[i] > ((sc->mac_ver >= 0x5392) ? 39 : 31)) 3362 sc->txpow2[i] = 5; 3363 } 3364 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3365 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3366 } 3367 /* read power settings for 5GHz channels */ 3368 for (i = 0; i < 40; i += 2) { 3369 val = rt2860_srom_read(sc, 3370 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3371 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3372 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3373 3374 val = rt2860_srom_read(sc, 3375 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3376 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3377 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3378 } 3379 /* fix broken Tx power entries */ 3380 for (i = 0; i < 40; i++) { 3381 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3382 sc->txpow1[14 + i] = 5; 3383 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3384 sc->txpow2[14 + i] = 5; 3385 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3386 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3387 sc->txpow2[14 + i])); 3388 } 3389 3390 /* read Tx power compensation for each Tx rate */ 3391 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3392 delta_2ghz = delta_5ghz = 0; 3393 if ((val & 0xff) != 0xff && (val & 0x80)) { 3394 delta_2ghz = val & 0xf; 3395 if (!(val & 0x40)) /* negative number */ 3396 delta_2ghz = -delta_2ghz; 3397 } 3398 val >>= 8; 3399 if ((val & 0xff) != 0xff && (val & 0x80)) { 3400 delta_5ghz = val & 0xf; 3401 if (!(val & 0x40)) /* negative number */ 3402 delta_5ghz = -delta_5ghz; 3403 } 3404 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3405 delta_2ghz, delta_5ghz)); 3406 3407 for (ridx = 0; ridx < 5; ridx++) { 3408 uint32_t reg; 3409 3410 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3411 reg = val; 3412 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3413 reg |= (uint32_t)val << 16; 3414 3415 sc->txpow20mhz[ridx] = reg; 3416 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3417 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3418 3419 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3420 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3421 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3422 } 3423 3424 /* read factory-calibrated samples for temperature compensation */ 3425 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3426 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3427 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3428 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3429 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3430 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3431 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3432 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3433 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3434 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3435 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3436 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3437 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3438 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3439 sc->step_2ghz = val >> 8; 3440 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3441 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3442 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3443 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3444 sc->tssi_2ghz[8], sc->step_2ghz)); 3445 /* check that ref value is correct, otherwise disable calibration */ 3446 if (sc->tssi_2ghz[4] == 0xff) 3447 sc->calib_2ghz = 0; 3448 3449 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3450 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3451 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3452 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3453 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3454 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3455 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3456 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3457 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3458 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3459 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3460 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3461 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3462 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3463 sc->step_5ghz = val >> 8; 3464 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3465 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3466 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3467 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3468 sc->tssi_5ghz[8], sc->step_5ghz)); 3469 /* check that ref value is correct, otherwise disable calibration */ 3470 if (sc->tssi_5ghz[4] == 0xff) 3471 sc->calib_5ghz = 0; 3472 3473 /* read RSSI offsets and LNA gains from EEPROM */ 3474 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3475 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3476 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3477 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3478 if (sc->mac_ver >= 0x3071) { 3479 /* 3480 * On RT3090 chips (limited to 2 Rx chains), this ROM 3481 * field contains the Tx mixer gain for the 2GHz band. 3482 */ 3483 if ((val & 0xff) != 0xff) 3484 sc->txmixgain_2ghz = val & 0x7; 3485 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3486 } else 3487 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3488 sc->lna[2] = val >> 8; /* channel group 2 */ 3489 3490 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3491 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3492 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3493 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3494 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3495 sc->lna[3] = val >> 8; /* channel group 3 */ 3496 3497 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3498 if (sc->mac_ver >= 0x3071) 3499 sc->lna[0] = RT3090_DEF_LNA; 3500 else /* channel group 0 */ 3501 sc->lna[0] = val & 0xff; 3502 sc->lna[1] = val >> 8; /* channel group 1 */ 3503 3504 /* fix broken 5GHz LNA entries */ 3505 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3506 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3507 sc->lna[2] = sc->lna[1]; 3508 } 3509 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3510 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3511 sc->lna[3] = sc->lna[1]; 3512 } 3513 3514 /* fix broken RSSI offset entries */ 3515 for (ant = 0; ant < 3; ant++) { 3516 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3517 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3518 ant + 1, sc->rssi_2ghz[ant])); 3519 sc->rssi_2ghz[ant] = 0; 3520 } 3521 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3522 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3523 ant + 1, sc->rssi_5ghz[ant])); 3524 sc->rssi_5ghz[ant] = 0; 3525 } 3526 } 3527 3528 return 0; 3529 } 3530 3531 static int 3532 rt2860_bbp_init(struct rt2860_softc *sc) 3533 { 3534 int i, ntries; 3535 3536 /* wait for BBP to wake up */ 3537 for (ntries = 0; ntries < 20; ntries++) { 3538 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3539 if (bbp0 != 0 && bbp0 != 0xff) 3540 break; 3541 } 3542 if (ntries == 20) { 3543 aprint_error_dev(sc->sc_dev, 3544 "timeout waiting for BBP to wake up\n"); 3545 return ETIMEDOUT; 3546 } 3547 3548 /* initialize BBP registers to default values */ 3549 if (sc->mac_ver >= 0x5390) 3550 rt5390_bbp_init(sc); 3551 else { 3552 for (i = 0; i < (int)__arraycount(rt2860_def_bbp); i++) { 3553 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3554 rt2860_def_bbp[i].val); 3555 } 3556 } 3557 3558 /* fix BBP84 for RT2860E */ 3559 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3560 rt2860_mcu_bbp_write(sc, 84, 0x19); 3561 3562 if (sc->mac_ver >= 0x3071) { 3563 rt2860_mcu_bbp_write(sc, 79, 0x13); 3564 rt2860_mcu_bbp_write(sc, 80, 0x05); 3565 rt2860_mcu_bbp_write(sc, 81, 0x33); 3566 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3567 rt2860_mcu_bbp_write(sc, 69, 0x16); 3568 rt2860_mcu_bbp_write(sc, 73, 0x12); 3569 } 3570 3571 return 0; 3572 } 3573 3574 static int 3575 rt5390_bbp_init(struct rt2860_softc *sc) 3576 { 3577 uint8_t bbp; 3578 int i; 3579 3580 /* Apply maximum likelihood detection for 2 stream case. */ 3581 if (sc->nrxchains > 1) { 3582 bbp = rt2860_mcu_bbp_read(sc, 105); 3583 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3584 } 3585 3586 /* Avoid data lost and CRC error. */ 3587 bbp = rt2860_mcu_bbp_read(sc, 4); 3588 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3589 3590 for (i = 0; i < __arraycount(rt5390_def_bbp); i++) { 3591 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3592 rt5390_def_bbp[i].val); 3593 } 3594 3595 if (sc->mac_ver == 0x5392) { 3596 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3597 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3598 rt2860_mcu_bbp_write(sc, 98, 0x12); 3599 rt2860_mcu_bbp_write(sc, 106, 0x05); 3600 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3601 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3602 } 3603 3604 bbp = rt2860_mcu_bbp_read(sc, 152); 3605 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3606 3607 /* Disable hardware antenna diversity. */ 3608 if (sc->mac_ver == 0x5390) 3609 rt2860_mcu_bbp_write(sc, 154, 0); 3610 3611 return 0; 3612 } 3613 3614 static int 3615 rt2860_txrx_enable(struct rt2860_softc *sc) 3616 { 3617 uint32_t tmp; 3618 int ntries; 3619 3620 /* enable Tx/Rx DMA engine */ 3621 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3622 RAL_BARRIER_READ_WRITE(sc); 3623 for (ntries = 0; ntries < 200; ntries++) { 3624 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3625 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3626 break; 3627 DELAY(1000); 3628 } 3629 if (ntries == 200) { 3630 aprint_error_dev(sc->sc_dev, 3631 "timeout waiting for DMA engine\n"); 3632 return ETIMEDOUT; 3633 } 3634 3635 DELAY(50); 3636 3637 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3638 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3639 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3640 3641 /* set Rx filter */ 3642 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3643 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 3644 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3645 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3646 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3647 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3648 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 3649 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3650 } 3651 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3652 3653 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3654 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3655 3656 return 0; 3657 } 3658 3659 static int 3660 rt2860_init(struct ifnet *ifp) 3661 { 3662 struct rt2860_softc *sc = ifp->if_softc; 3663 struct ieee80211com *ic = &sc->sc_ic; 3664 uint32_t tmp; 3665 uint8_t bbp1, bbp3; 3666 int i, qid, ridx, ntries, error; 3667 3668 /* for CardBus, power on the socket */ 3669 if (!(sc->sc_flags & RT2860_ENABLED)) { 3670 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 3671 aprint_error_dev(sc->sc_dev, 3672 "could not enable device\n"); 3673 return EIO; 3674 } 3675 sc->sc_flags |= RT2860_ENABLED; 3676 } 3677 3678 if (sc->rfswitch) { 3679 /* hardware has a radio switch on GPIO pin 2 */ 3680 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3681 aprint_normal_dev(sc->sc_dev, 3682 "radio is disabled by hardware switch\n"); 3683 #ifdef notyet 3684 rt2860_stop(ifp, 1); 3685 return EPERM; 3686 #endif 3687 } 3688 } 3689 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3690 3691 /* disable DMA */ 3692 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3693 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3694 RT2860_TX_DMA_EN); 3695 tmp |= RT2860_TX_WB_DDONE; 3696 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3697 3698 /* reset DMA indexes */ 3699 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, RT2860_RST_DRX_IDX0 | 3700 RT2860_RST_DTX_IDX5 | RT2860_RST_DTX_IDX4 | RT2860_RST_DTX_IDX3 | 3701 RT2860_RST_DTX_IDX2 | RT2860_RST_DTX_IDX1 | RT2860_RST_DTX_IDX0); 3702 3703 /* PBF hardware reset */ 3704 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3705 RAL_BARRIER_WRITE(sc); 3706 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3707 3708 if ((error = rt2860_load_microcode(sc)) != 0) { 3709 aprint_error_dev(sc->sc_dev, 3710 "could not load 8051 microcode\n"); 3711 rt2860_stop(ifp, 1); 3712 return error; 3713 } 3714 3715 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3716 rt2860_set_macaddr(sc, ic->ic_myaddr); 3717 3718 /* init Tx power for all Tx rates (from EEPROM) */ 3719 for (ridx = 0; ridx < 5; ridx++) { 3720 if (sc->txpow20mhz[ridx] == 0xffffffff) 3721 continue; 3722 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3723 } 3724 3725 for (ntries = 0; ntries < 100; ntries++) { 3726 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3727 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3728 break; 3729 DELAY(1000); 3730 } 3731 if (ntries == 100) { 3732 aprint_error_dev(sc->sc_dev, 3733 "timeout waiting for DMA engine\n"); 3734 rt2860_stop(ifp, 1); 3735 return ETIMEDOUT; 3736 } 3737 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3738 RT2860_TX_DMA_EN); 3739 tmp |= RT2860_TX_WB_DDONE; 3740 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3741 3742 /* reset Rx ring and all 6 Tx rings */ 3743 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3744 3745 /* PBF hardware reset */ 3746 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3747 RAL_BARRIER_WRITE(sc); 3748 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3749 3750 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3751 3752 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3753 RAL_BARRIER_WRITE(sc); 3754 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3755 3756 for (i = 0; i < (int)__arraycount(rt2860_def_mac); i++) 3757 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3758 if (sc->mac_ver >= 0x5390) 3759 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3760 else if (sc->mac_ver >= 0x3071) { 3761 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3762 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3763 4 << RT2860_DLY_PAPE_EN_SHIFT); 3764 } 3765 3766 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3767 sc->sc_flags |= RT2860_PCIE; 3768 /* PCIe has different clock cycle count than PCI */ 3769 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3770 tmp = (tmp & ~0xff) | 0x7d; 3771 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3772 } 3773 3774 /* wait while MAC is busy */ 3775 for (ntries = 0; ntries < 100; ntries++) { 3776 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3777 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3778 break; 3779 DELAY(1000); 3780 } 3781 if (ntries == 100) { 3782 aprint_error_dev(sc->sc_dev, "timeout waiting for MAC\n"); 3783 rt2860_stop(ifp, 1); 3784 return ETIMEDOUT; 3785 } 3786 3787 /* clear Host to MCU mailbox */ 3788 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3789 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3790 3791 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3792 DELAY(1000); 3793 3794 if ((error = rt2860_bbp_init(sc)) != 0) { 3795 rt2860_stop(ifp, 1); 3796 return error; 3797 } 3798 3799 /* clear RX WCID search table */ 3800 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3801 /* clear pairwise key table */ 3802 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3803 /* clear IV/EIV table */ 3804 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3805 /* clear WCID attribute table */ 3806 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3807 /* clear shared key table */ 3808 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3809 /* clear shared key mode */ 3810 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3811 3812 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3813 for (qid = 0; qid < MAXQS; qid++) { 3814 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3815 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3816 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3817 } 3818 3819 /* init Rx ring */ 3820 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3821 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3822 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3823 3824 /* setup maximum buffer sizes */ 3825 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3826 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3827 3828 for (ntries = 0; ntries < 100; ntries++) { 3829 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3830 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3831 break; 3832 DELAY(1000); 3833 } 3834 if (ntries == 100) { 3835 aprint_error_dev(sc->sc_dev, 3836 "timeout waiting for DMA engine\n"); 3837 rt2860_stop(ifp, 1); 3838 return ETIMEDOUT; 3839 } 3840 tmp &= 0xff0; 3841 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3842 3843 /* disable interrupts mitigation */ 3844 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3845 3846 /* write vendor-specific BBP values (from EEPROM) */ 3847 for (i = 0; i < 8; i++) { 3848 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3849 continue; 3850 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3851 } 3852 3853 /* select Main antenna for 1T1R devices */ 3854 if (sc->rf_rev == RT3070_RF_2020 || 3855 sc->rf_rev == RT3070_RF_3020 || 3856 sc->rf_rev == RT3070_RF_3320 || 3857 sc->mac_ver == 0x5390) 3858 rt3090_set_rx_antenna(sc, 0); 3859 3860 /* send LEDs operating mode to microcontroller */ 3861 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3862 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3863 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3864 3865 if (sc->mac_ver >= 0x5390) 3866 rt5390_rf_init(sc); 3867 else if (sc->mac_ver >= 0x3071) 3868 rt3090_rf_init(sc); 3869 3870 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 3871 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 3872 3873 if (sc->mac_ver >= 0x5390) 3874 rt5390_rf_wakeup(sc); 3875 else if (sc->mac_ver >= 0x3071) 3876 rt3090_rf_wakeup(sc); 3877 3878 /* disable non-existing Rx chains */ 3879 bbp3 = rt2860_mcu_bbp_read(sc, 3); 3880 bbp3 &= ~(1 << 3 | 1 << 4); 3881 if (sc->nrxchains == 2) 3882 bbp3 |= 1 << 3; 3883 else if (sc->nrxchains == 3) 3884 bbp3 |= 1 << 4; 3885 rt2860_mcu_bbp_write(sc, 3, bbp3); 3886 3887 /* disable non-existing Tx chains */ 3888 bbp1 = rt2860_mcu_bbp_read(sc, 1); 3889 if (sc->ntxchains == 1) 3890 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 3891 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 3892 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 3893 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 3894 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 3895 rt2860_mcu_bbp_write(sc, 1, bbp1); 3896 3897 if (sc->mac_ver >= 0x3071) 3898 rt3090_rf_setup(sc); 3899 3900 /* select default channel */ 3901 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 3902 rt2860_switch_chan(sc, ic->ic_ibss_chan); 3903 3904 /* reset RF from MCU */ 3905 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3906 3907 /* set RTS threshold */ 3908 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 3909 tmp &= ~0xffff00; 3910 tmp |= ic->ic_rtsthreshold << 8; 3911 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 3912 3913 /* setup initial protection mode */ 3914 sc->sc_ic_flags = ic->ic_flags; 3915 rt2860_updateprot(ic); 3916 3917 /* turn radio LED on */ 3918 rt2860_set_leds(sc, RT2860_LED_RADIO); 3919 3920 /* enable Tx/Rx DMA engine */ 3921 if ((error = rt2860_txrx_enable(sc)) != 0) { 3922 rt2860_stop(ifp, 1); 3923 return error; 3924 } 3925 3926 /* clear pending interrupts */ 3927 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 3928 /* enable interrupts */ 3929 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 3930 3931 if (sc->sc_flags & RT2860_ADVANCED_PS) 3932 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 3933 3934 ifp->if_flags |= IFF_RUNNING; 3935 ifp->if_flags &= ~IFF_OACTIVE; 3936 3937 if (ic->ic_opmode != IEEE80211_M_MONITOR) 3938 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3939 else 3940 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3941 3942 return 0; 3943 } 3944 3945 static void 3946 rt2860_stop(struct ifnet *ifp, int disable) 3947 { 3948 struct rt2860_softc *sc = ifp->if_softc; 3949 struct ieee80211com *ic = &sc->sc_ic; 3950 uint32_t tmp; 3951 int qid; 3952 3953 if (ifp->if_flags & IFF_RUNNING) 3954 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 3955 3956 sc->sc_tx_timer = 0; 3957 ifp->if_timer = 0; 3958 ifp->if_flags &= ~IFF_RUNNING; 3959 ifp->if_flags &= ~IFF_OACTIVE; 3960 3961 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 3962 3963 /* disable interrupts */ 3964 RAL_WRITE(sc, RT2860_INT_MASK, 0); 3965 3966 /* disable GP timer */ 3967 rt2860_set_gp_timer(sc, 0); 3968 3969 /* disable Rx */ 3970 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 3971 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3972 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 3973 3974 /* reset adapter */ 3975 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3976 RAL_BARRIER_WRITE(sc); 3977 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3978 3979 /* reset Tx and Rx rings (and reclaim TXWIs) */ 3980 sc->qfullmsk = 0; 3981 for (qid = 0; qid < MAXQS; qid++) 3982 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 3983 rt2860_reset_rx_ring(sc, &sc->rxq); 3984 3985 /* for CardBus, power down the socket */ 3986 if (disable && sc->sc_disable != NULL) { 3987 if (sc->sc_flags & RT2860_ENABLED) { 3988 (*sc->sc_disable)(sc); 3989 sc->sc_flags &= ~RT2860_ENABLED; 3990 } 3991 } 3992 } 3993 3994 static int 3995 rt2860_load_microcode(struct rt2860_softc *sc) 3996 { 3997 int ntries; 3998 3999 /* set "host program ram write selection" bit */ 4000 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4001 /* write microcode image */ 4002 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, sc->ucode, sc->ucsize); 4003 /* kick microcontroller unit */ 4004 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4005 RAL_BARRIER_WRITE(sc); 4006 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4007 4008 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4009 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4010 4011 /* wait until microcontroller is ready */ 4012 RAL_BARRIER_READ_WRITE(sc); 4013 for (ntries = 0; ntries < 1000; ntries++) { 4014 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4015 break; 4016 DELAY(1000); 4017 } 4018 if (ntries == 1000) { 4019 aprint_error_dev(sc->sc_dev, 4020 "timeout waiting for MCU to initialize\n"); 4021 return ETIMEDOUT; 4022 } 4023 return 0; 4024 } 4025 4026 #if 0 4027 /* 4028 * This function is called periodically to adjust Tx power based on 4029 * temperature variation. 4030 */ 4031 static void 4032 rt2860_calib(struct rt2860_softc *sc) 4033 { 4034 struct ieee80211com *ic = &sc->sc_ic; 4035 const uint8_t *tssi; 4036 uint8_t step, bbp49; 4037 int8_t ridx, d; 4038 4039 /* read current temperature */ 4040 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4041 4042 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4043 tssi = &sc->tssi_2ghz[4]; 4044 step = sc->step_2ghz; 4045 } else { 4046 tssi = &sc->tssi_5ghz[4]; 4047 step = sc->step_5ghz; 4048 } 4049 4050 if (bbp49 < tssi[0]) { /* lower than reference */ 4051 /* use higher Tx power than default */ 4052 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4053 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4054 /* use lower Tx power than default */ 4055 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4056 } else { 4057 /* use default Tx power */ 4058 d = 0; 4059 } 4060 d *= step; 4061 4062 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4063 4064 /* write adjusted Tx power values for each Tx rate */ 4065 for (ridx = 0; ridx < 5; ridx++) { 4066 if (sc->txpow20mhz[ridx] == 0xffffffff) 4067 continue; 4068 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4069 b4inc(sc->txpow20mhz[ridx], d)); 4070 } 4071 } 4072 #endif /* 0 */ 4073 4074 static void 4075 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4076 { 4077 uint32_t tmp; 4078 4079 if (aux) { 4080 if (sc->mac_ver == 0x5390) { 4081 rt2860_mcu_bbp_write(sc, 152, 4082 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4083 } else { 4084 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4085 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 4086 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4087 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 4088 } 4089 } else { 4090 if (sc->mac_ver == 0x5390) { 4091 rt2860_mcu_bbp_write(sc, 152, 4092 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4093 } else { 4094 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4095 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4096 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4097 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4098 } 4099 } 4100 } 4101 4102 static void 4103 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4104 { 4105 struct ieee80211com *ic = &sc->sc_ic; 4106 u_int chan, group; 4107 4108 chan = ieee80211_chan2ieee(ic, c); 4109 DPRINTF(("switch channel %u\n", chan)); 4110 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4111 return; 4112 4113 if (sc->mac_ver >= 0x5390) 4114 rt5390_set_chan(sc, chan); 4115 else if (sc->mac_ver >= 0x3071) 4116 rt3090_set_chan(sc, chan); 4117 else 4118 rt2860_set_chan(sc, chan); 4119 4120 /* determine channel group */ 4121 if (chan <= 14) 4122 group = 0; 4123 else if (chan <= 64) 4124 group = 1; 4125 else if (chan <= 128) 4126 group = 2; 4127 else 4128 group = 3; 4129 4130 /* XXX necessary only when group has changed! */ 4131 if (sc->mac_ver < 0x5390) 4132 rt2860_select_chan_group(sc, group); 4133 4134 DELAY(1000); 4135 } 4136 4137 #ifndef IEEE80211_STA_ONLY 4138 static int 4139 rt2860_setup_beacon(struct rt2860_softc *sc) 4140 { 4141 struct ieee80211com *ic = &sc->sc_ic; 4142 struct rt2860_txwi txwi; 4143 struct mbuf *m; 4144 int ridx; 4145 4146 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss, &sc->sc_bo)) == NULL) 4147 return ENOBUFS; 4148 4149 memset(&txwi, 0, sizeof txwi); 4150 txwi.wcid = 0xff; 4151 txwi.len = htole16(m->m_pkthdr.len); 4152 /* send beacons at the lowest available rate */ 4153 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 4154 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4155 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4156 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4157 txwi.phy |= htole16(RT2860_PHY_OFDM); 4158 txwi.txop = RT2860_TX_TXOP_HT; 4159 txwi.flags = RT2860_TX_TS; 4160 txwi.xflags = RT2860_TX_NSEQ; 4161 4162 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4163 (uint8_t *)&txwi, sizeof txwi); 4164 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4165 mtod(m, uint8_t *), m->m_pkthdr.len); 4166 4167 m_freem(m); 4168 4169 return 0; 4170 } 4171 #endif 4172 4173 static void 4174 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4175 { 4176 struct ieee80211com *ic = &sc->sc_ic; 4177 uint32_t tmp; 4178 4179 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4180 4181 tmp &= ~0x1fffff; 4182 tmp |= ic->ic_bss->ni_intval * 16; 4183 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4184 if (ic->ic_opmode == IEEE80211_M_STA) { 4185 /* 4186 * Local TSF is always updated with remote TSF on beacon 4187 * reception. 4188 */ 4189 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4190 } 4191 #ifndef IEEE80211_STA_ONLY 4192 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 4193 tmp |= RT2860_BCN_TX_EN; 4194 /* 4195 * Local TSF is updated with remote TSF on beacon reception 4196 * only if the remote TSF is greater than local TSF. 4197 */ 4198 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4199 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4200 tmp |= RT2860_BCN_TX_EN; 4201 /* SYNC with nobody */ 4202 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4203 } 4204 #endif 4205 4206 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4207 } 4208