1 /* $NetBSD: rt2860.c,v 1.25 2017/02/02 10:05:35 nonaka Exp $ */ 2 /* $OpenBSD: rt2860.c,v 1.90 2016/04/13 10:49:26 mpi Exp $ */ 3 /* $FreeBSD: head/sys/dev/ral/rt2860.c 306591 2016-10-02 20:35:55Z avos $ */ 4 5 /*- 6 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 7 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 24 * http://www.ralinktech.com/ 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: rt2860.c,v 1.25 2017/02/02 10:05:35 nonaka Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/sockio.h> 32 #include <sys/sysctl.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/queue.h> 39 #include <sys/callout.h> 40 #include <sys/module.h> 41 #include <sys/conf.h> 42 #include <sys/device.h> 43 #include <sys/endian.h> 44 #include <sys/cprng.h> 45 46 #include <sys/bus.h> 47 #include <sys/intr.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_ether.h> 53 #include <net/if_media.h> 54 55 #include <net80211/ieee80211_var.h> 56 #include <net80211/ieee80211_amrr.h> 57 #include <net80211/ieee80211_radiotap.h> 58 59 #include <dev/firmload.h> 60 61 #include <dev/ic/rt2860var.h> 62 #include <dev/ic/rt2860reg.h> 63 64 #include <dev/pci/pcidevs.h> 65 66 #ifdef RAL_DEBUG 67 #define DPRINTF(x) do { if (rt2860_debug > 0) printf x; } while (0) 68 #define DPRINTFN(n, x) do { if (rt2860_debug >= (n)) printf x; } while (0) 69 int rt2860_debug = 0; 70 #else 71 #define DPRINTF(x) 72 #define DPRINTFN(n, x) 73 #endif 74 #define MAXQS 6 /* Tx (4 EDCAs + HCCA + Mgt) and Rx rings */ 75 76 static void rt2860_attachhook(device_t); 77 static int rt2860_alloc_tx_ring(struct rt2860_softc *, 78 struct rt2860_tx_ring *); 79 static void rt2860_reset_tx_ring(struct rt2860_softc *, 80 struct rt2860_tx_ring *); 81 static void rt2860_free_tx_ring(struct rt2860_softc *, 82 struct rt2860_tx_ring *); 83 static int rt2860_alloc_tx_pool(struct rt2860_softc *); 84 static void rt2860_free_tx_pool(struct rt2860_softc *); 85 static int rt2860_alloc_rx_ring(struct rt2860_softc *, 86 struct rt2860_rx_ring *); 87 static void rt2860_reset_rx_ring(struct rt2860_softc *, 88 struct rt2860_rx_ring *); 89 static void rt2860_free_rx_ring(struct rt2860_softc *, 90 struct rt2860_rx_ring *); 91 static struct ieee80211_node *rt2860_node_alloc(struct ieee80211_node_table *); 92 static int rt2860_media_change(struct ifnet *); 93 static void rt2860_iter_func(void *, struct ieee80211_node *); 94 static void rt2860_updatestats(struct rt2860_softc *); 95 static void rt2860_update_promisc(struct ifnet *); 96 static void rt2860_newassoc(struct ieee80211_node *, 97 int); 98 #ifdef notyet 99 static int rt2860_ampdu_rx_start(struct ieee80211com *, 100 struct ieee80211_node *, uint8_t); 101 static void rt2860_ampdu_rx_stop(struct ieee80211com *, 102 struct ieee80211_node *, uint8_t); 103 #endif 104 static int rt2860_newstate(struct ieee80211com *, enum ieee80211_state, 105 int); 106 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 107 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 108 static void rt2860_intr_coherent(struct rt2860_softc *); 109 static void rt2860_drain_stats_fifo(struct rt2860_softc *); 110 static void rt2860_tx_intr(struct rt2860_softc *, int); 111 static void rt2860_rx_intr(struct rt2860_softc *); 112 static void rt2860_tbtt_intr(struct rt2860_softc *); 113 static void rt2860_gp_intr(struct rt2860_softc *); 114 static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 115 struct ieee80211_node *); 116 static void rt2860_start(struct ifnet *); 117 static void rt2860_watchdog(struct ifnet *); 118 static int rt2860_ioctl(struct ifnet *, u_long, void *); 119 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 120 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 121 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 122 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 123 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 124 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 125 static void rt2860_enable_mrr(struct rt2860_softc *); 126 static void rt2860_set_txpreamble(struct rt2860_softc *); 127 static void rt2860_set_basicrates(struct rt2860_softc *); 128 static void rt2860_select_chan_group(struct rt2860_softc *, int); 129 static void rt2860_set_chan(struct rt2860_softc *, u_int); 130 static void rt3090_set_chan(struct rt2860_softc *, u_int); 131 static void rt5390_set_chan(struct rt2860_softc *, u_int); 132 static void rt3090_rf_init(struct rt2860_softc *); 133 static void rt5390_rf_init(struct rt2860_softc *); 134 static void rt3090_rf_wakeup(struct rt2860_softc *); 135 static void rt5390_rf_wakeup(struct rt2860_softc *); 136 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 137 uint8_t *); 138 static void rt3090_rf_setup(struct rt2860_softc *); 139 static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 140 static void rt2860_set_gp_timer(struct rt2860_softc *, int); 141 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 142 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 143 static void rt2860_updateslot(struct ifnet *); 144 static void rt2860_updateprot(struct ieee80211com *); 145 static int rt2860_updateedca(struct ieee80211com *); 146 147 #ifdef HW_CRYPTO 148 static int rt2860_set_key(struct ieee80211com *, 149 const struct ieee80211_key *, const uint8_t *); 150 static int rt2860_delete_key(struct ieee80211com *, 151 const struct ieee80211_key *); 152 #endif 153 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 154 static const char * rt2860_get_rf(uint32_t); 155 static int rt2860_read_eeprom(struct rt2860_softc *); 156 static int rt2860_bbp_init(struct rt2860_softc *); 157 static int rt5390_bbp_init(struct rt2860_softc *); 158 static int rt2860_txrx_enable(struct rt2860_softc *); 159 static int rt2860_init(struct ifnet *); 160 static void rt2860_stop(struct ifnet *, int); 161 static int rt2860_load_microcode(struct rt2860_softc *); 162 #if 0 163 static void rt2860_calib(struct rt2860_softc *); 164 #endif 165 static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 166 static void rt2860_switch_chan(struct rt2860_softc *, 167 struct ieee80211_channel *); 168 #ifndef IEEE80211_STA_ONLY 169 static int rt2860_setup_beacon(struct rt2860_softc *); 170 #endif 171 static void rt2860_enable_tsf_sync(struct rt2860_softc *); 172 static void rt2860_softintr(void *); 173 174 static const struct { 175 uint32_t reg; 176 uint32_t val; 177 } rt2860_def_mac[] = { 178 RT2860_DEF_MAC 179 }; 180 181 static const struct { 182 uint8_t reg; 183 uint8_t val; 184 } rt2860_def_bbp[] = { 185 RT2860_DEF_BBP 186 }, rt5390_def_bbp[] = { 187 RT5390_DEF_BBP 188 }; 189 190 static const struct rfprog { 191 uint8_t chan; 192 uint32_t r1, r2, r3, r4; 193 } rt2860_rf2850[] = { 194 RT2860_RF2850 195 }; 196 197 struct { 198 uint8_t n, r, k; 199 } rt3090_freqs[] = { 200 RT3070_RF3052 201 }; 202 203 static const struct { 204 uint8_t reg; 205 uint8_t val; 206 } rt3090_def_rf[] = { 207 RT3070_DEF_RF 208 }, rt3572_def_rf[] = { 209 RT3572_DEF_RF 210 }, rt5390_def_rf[] = { 211 RT5390_DEF_RF 212 }, rt5392_def_rf[] = { 213 RT5392_DEF_RF 214 }; 215 216 int 217 rt2860_attach(void *xsc, int id) 218 { 219 struct rt2860_softc *sc = xsc; 220 struct ieee80211com *ic = &sc->sc_ic; 221 int qid, ntries, error; 222 uint32_t tmp; 223 224 sc->amrr.amrr_min_success_threshold = 1; 225 sc->amrr.amrr_max_success_threshold = 15; 226 227 /* wait for NIC to initialize */ 228 for (ntries = 0; ntries < 100; ntries++) { 229 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 230 if (tmp != 0 && tmp != 0xffffffff) 231 break; 232 DELAY(10); 233 } 234 if (ntries == 100) { 235 aprint_error_dev(sc->sc_dev, 236 "timeout waiting for NIC to initialize\n"); 237 return ETIMEDOUT; 238 } 239 sc->mac_ver = tmp >> 16; 240 sc->mac_rev = tmp & 0xffff; 241 242 if (sc->mac_ver != 0x2860 && 243 (id == PCI_PRODUCT_RALINK_RT2890 || 244 id == PCI_PRODUCT_RALINK_RT2790 || 245 id == PCI_PRODUCT_AWT_RT2890)) 246 sc->sc_flags |= RT2860_ADVANCED_PS; 247 248 /* retrieve RF rev. no and various other things from EEPROM */ 249 rt2860_read_eeprom(sc); 250 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 251 ether_sprintf(ic->ic_myaddr)); 252 aprint_normal_dev(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 253 "RF %s (MIMO %dT%dR)\n", 254 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 255 sc->ntxchains, sc->nrxchains); 256 257 sc->sc_soft_ih = softint_establish(SOFTINT_NET, rt2860_softintr, sc); 258 if (sc->sc_soft_ih == NULL) { 259 aprint_error_dev(sc->sc_dev, "could not establish softint\n"); 260 error = EINVAL; 261 goto fail0; 262 } 263 264 /* 265 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 266 */ 267 for (qid = 0; qid < MAXQS; qid++) { 268 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 269 aprint_error_dev(sc->sc_dev, 270 "could not allocate Tx ring %d\n", qid); 271 goto fail1; 272 } 273 } 274 275 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 276 aprint_error_dev(sc->sc_dev, "could not allocate Rx ring\n"); 277 goto fail1; 278 } 279 280 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 281 aprint_error_dev(sc->sc_dev, "could not allocate Tx pool\n"); 282 goto fail2; 283 } 284 285 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 286 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 287 WME_AC_VO : 5; 288 289 config_mountroot(sc->sc_dev, rt2860_attachhook); 290 291 return 0; 292 293 fail2: rt2860_free_rx_ring(sc, &sc->rxq); 294 fail1: while (--qid >= 0) 295 rt2860_free_tx_ring(sc, &sc->txq[qid]); 296 fail0: softint_disestablish(sc->sc_soft_ih); 297 sc->sc_soft_ih = NULL; 298 return error; 299 } 300 301 static int 302 firmware_load(const char *dname, const char *iname, uint8_t **ucodep, 303 size_t *sizep) 304 { 305 firmware_handle_t fh; 306 int error; 307 308 if ((error = firmware_open(dname, iname, &fh)) != 0) 309 return (error); 310 *sizep = firmware_get_size(fh); 311 if ((*ucodep = firmware_malloc(*sizep)) == NULL) { 312 firmware_close(fh); 313 return (ENOMEM); 314 } 315 if ((error = firmware_read(fh, 0, *ucodep, *sizep)) != 0) 316 firmware_free(*ucodep, *sizep); 317 firmware_close(fh); 318 319 return (error); 320 } 321 322 static void 323 rt2860_attachhook(device_t self) 324 { 325 struct rt2860_softc *sc = device_private(self); 326 struct ieee80211com *ic = &sc->sc_ic; 327 struct ifnet *ifp = &sc->sc_if; 328 int i, error; 329 330 error = firmware_load("ral", "ral-rt2860", &sc->ucode, &sc->ucsize); 331 if (error != 0) { 332 aprint_error_dev(sc->sc_dev, 333 "error %d, could not read firmware file %s\n", 334 error, "ral-rt2860"); 335 return; 336 } 337 338 ic->ic_ifp = ifp; 339 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 340 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 341 ic->ic_state = IEEE80211_S_INIT; 342 343 /* set device capabilities */ 344 ic->ic_caps = 345 IEEE80211_C_MONITOR | /* monitor mode supported */ 346 #ifndef IEEE80211_STA_ONLY 347 IEEE80211_C_IBSS | /* IBSS mode supported */ 348 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 349 #ifdef IEEE80211_C_APPMGT 350 IEEE80211_C_APPMGT | /* HostAP power management */ 351 #endif 352 #endif 353 IEEE80211_C_WDS | /* 4-address traffic works */ 354 IEEE80211_C_WME | /* 802.11e */ 355 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 356 IEEE80211_C_SHSLOT | /* short slot time supported */ 357 #ifdef HW_CRYPTO 358 IEEE80211_C_WEP | /* WEP */ 359 #endif 360 IEEE80211_C_WPA; /* 802.11i */ 361 362 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 363 /* set supported .11a rates */ 364 ic->ic_sup_rates[IEEE80211_MODE_11A] = 365 ieee80211_std_rateset_11a; 366 367 /* set supported .11a channels */ 368 for (i = 14; i < (int)__arraycount(rt2860_rf2850); i++) { 369 uint8_t chan = rt2860_rf2850[i].chan; 370 ic->ic_channels[chan].ic_freq = 371 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 372 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 373 } 374 } 375 376 /* set supported .11b and .11g rates */ 377 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 378 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 379 380 /* set supported .11b and .11g channels (1 through 14) */ 381 for (i = 1; i <= 14; i++) { 382 ic->ic_channels[i].ic_freq = 383 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 384 ic->ic_channels[i].ic_flags = 385 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 386 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 387 } 388 389 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 390 ic->ic_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 391 392 ifp->if_softc = sc; 393 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 394 ifp->if_init = rt2860_init; 395 ifp->if_ioctl = rt2860_ioctl; 396 ifp->if_start = rt2860_start; 397 ifp->if_watchdog = rt2860_watchdog; 398 IFQ_SET_READY(&ifp->if_snd); 399 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 400 401 if_initialize(ifp); 402 ieee80211_ifattach(ic); 403 /* Use common softint-based if_input */ 404 ifp->if_percpuq = if_percpuq_create(ifp); 405 if_register(ifp); 406 407 ic->ic_node_alloc = rt2860_node_alloc; 408 ic->ic_newassoc = rt2860_newassoc; 409 #ifdef notyet 410 ic->ic_ampdu_rx_start = rt2860_ampdu_rx_start; 411 ic->ic_ampdu_rx_stop = rt2860_ampdu_rx_stop; 412 #endif 413 ic->ic_updateslot = rt2860_updateslot; 414 ic->ic_wme.wme_update = rt2860_updateedca; 415 #ifdef HW_CRYPTO 416 ic->ic_crypto.cs_key_set = rt2860_set_key; 417 ic->ic_crypto.cs_key_delete = rt2860_delete_key; 418 #endif 419 /* override state transition machine */ 420 sc->sc_newstate = ic->ic_newstate; 421 ic->ic_newstate = rt2860_newstate; 422 ieee80211_media_init(ic, rt2860_media_change, ieee80211_media_status); 423 424 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 425 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 426 427 sc->sc_rxtap_len = roundup(sizeof(sc->sc_rxtap), sizeof(u_int32_t)); 428 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 429 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2860_RX_RADIOTAP_PRESENT); 430 431 sc->sc_txtap_len = roundup(sizeof(sc->sc_txtap), sizeof(u_int32_t)); 432 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 433 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2860_TX_RADIOTAP_PRESENT); 434 435 ieee80211_announce(ic); 436 437 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 438 pmf_class_network_register(sc->sc_dev, ifp); 439 else 440 aprint_error_dev(sc->sc_dev, 441 "couldn't establish power handler\n"); 442 } 443 444 int 445 rt2860_detach(void *xsc) 446 { 447 struct rt2860_softc *sc = xsc; 448 struct ifnet *ifp = &sc->sc_if; 449 int qid; 450 451 pmf_device_deregister(sc->sc_dev); 452 453 rt2860_stop(ifp, 1); 454 455 ieee80211_ifdetach(&sc->sc_ic); /* free all nodes */ 456 if_detach(ifp); 457 458 for (qid = 0; qid < MAXQS; qid++) 459 rt2860_free_tx_ring(sc, &sc->txq[qid]); 460 rt2860_free_rx_ring(sc, &sc->rxq); 461 rt2860_free_tx_pool(sc); 462 463 if (sc->sc_soft_ih != NULL) { 464 softint_disestablish(sc->sc_soft_ih); 465 sc->sc_soft_ih = NULL; 466 } 467 468 if (sc->ucode != NULL) 469 free(sc->ucode, M_DEVBUF); 470 471 return 0; 472 } 473 474 void 475 rt2860_suspend(void *xsc) 476 { 477 struct rt2860_softc *sc = xsc; 478 struct ifnet *ifp = &sc->sc_if; 479 480 if (ifp->if_flags & IFF_RUNNING) 481 rt2860_stop(ifp, 1); 482 } 483 484 void 485 rt2860_wakeup(void *xsc) 486 { 487 struct rt2860_softc *sc = xsc; 488 struct ifnet *ifp = &sc->sc_if; 489 490 if (ifp->if_flags & IFF_UP) 491 rt2860_init(ifp); 492 } 493 494 static int 495 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 496 { 497 int nsegs, size, error; 498 499 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 500 501 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 502 BUS_DMA_NOWAIT, &ring->map); 503 if (error != 0) { 504 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 505 goto fail; 506 } 507 508 /* Tx rings must be 4-DWORD aligned */ 509 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 510 &nsegs, BUS_DMA_NOWAIT); 511 if (error != 0) { 512 aprint_error_dev(sc->sc_dev, 513 "could not allocate DMA memory\n"); 514 goto fail; 515 } 516 517 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 518 (void **)&ring->txd, BUS_DMA_NOWAIT); 519 if (error != 0) { 520 aprint_error_dev(sc->sc_dev, "can't map DMA memory\n"); 521 goto fail; 522 } 523 524 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->txd, size, NULL, 525 BUS_DMA_NOWAIT); 526 if (error != 0) { 527 aprint_error_dev(sc->sc_dev, "could not load DMA map\n"); 528 goto fail; 529 } 530 531 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 532 533 ring->paddr = ring->map->dm_segs[0].ds_addr; 534 535 return 0; 536 537 fail: rt2860_free_tx_ring(sc, ring); 538 return error; 539 } 540 541 static void 542 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 543 { 544 struct rt2860_tx_data *data; 545 int i; 546 547 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 548 if ((data = ring->data[i]) == NULL) 549 continue; /* nothing mapped in this slot */ 550 551 if (data->ni != NULL) { 552 ieee80211_free_node(data->ni); 553 data->ni = NULL; 554 } 555 556 if (data->m != NULL) { 557 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 558 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 559 bus_dmamap_unload(sc->sc_dmat, data->map); 560 m_freem(data->m); 561 data->m = NULL; 562 } 563 564 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 565 ring->data[i] = NULL; 566 } 567 568 ring->queued = 0; 569 ring->cur = ring->next = 0; 570 } 571 572 static void 573 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 574 { 575 struct rt2860_tx_data *data; 576 int i; 577 578 if (ring->txd != NULL) { 579 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 580 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 581 bus_dmamap_unload(sc->sc_dmat, ring->map); 582 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->txd, 583 RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd)); 584 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 585 } 586 if (ring->map != NULL) 587 bus_dmamap_destroy(sc->sc_dmat, ring->map); 588 589 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 590 if ((data = ring->data[i]) == NULL) 591 continue; /* nothing mapped in this slot */ 592 593 if (data->ni != NULL) { 594 ieee80211_free_node(data->ni); 595 data->ni = NULL; 596 } 597 if (data->m != NULL) { 598 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 599 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 600 bus_dmamap_unload(sc->sc_dmat, data->map); 601 m_freem(data->m); 602 data->m = NULL; 603 } 604 605 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 606 ring->data[i] = NULL; 607 } 608 ring->queued = 0; 609 ring->cur = ring->next = 0; 610 } 611 612 /* 613 * Allocate a pool of TX Wireless Information blocks. 614 */ 615 static int 616 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 617 { 618 char *vaddr; 619 bus_addr_t paddr; 620 int i, nsegs, size, error; 621 622 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 623 624 /* init data_pool early in case of failure.. */ 625 SLIST_INIT(&sc->data_pool); 626 627 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 628 BUS_DMA_NOWAIT, &sc->txwi_map); 629 if (error != 0) { 630 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 631 goto fail; 632 } 633 634 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 635 &sc->txwi_seg, 1, &nsegs, BUS_DMA_NOWAIT); 636 if (error != 0) { 637 aprint_error_dev(sc->sc_dev, 638 "could not allocate DMA memory\n"); 639 goto fail; 640 } 641 642 error = bus_dmamem_map(sc->sc_dmat, &sc->txwi_seg, nsegs, size, 643 &sc->txwi_vaddr, BUS_DMA_NOWAIT); 644 if (error != 0) { 645 aprint_error_dev(sc->sc_dev, "can't map DMA memory\n"); 646 goto fail; 647 } 648 649 error = bus_dmamap_load(sc->sc_dmat, sc->txwi_map, sc->txwi_vaddr, 650 size, NULL, BUS_DMA_NOWAIT); 651 if (error != 0) { 652 aprint_error_dev(sc->sc_dev, "could not load DMA map\n"); 653 goto fail; 654 } 655 656 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, size, 657 BUS_DMASYNC_PREWRITE); 658 659 vaddr = sc->txwi_vaddr; 660 paddr = sc->txwi_map->dm_segs[0].ds_addr; 661 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 662 struct rt2860_tx_data *data = &sc->data[i]; 663 664 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 665 RT2860_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 666 &data->map); /* <0> */ 667 if (error != 0) { 668 aprint_error_dev(sc->sc_dev, 669 "could not create DMA map\n"); 670 goto fail; 671 } 672 data->txwi = (struct rt2860_txwi *)vaddr; 673 data->paddr = paddr; 674 vaddr += RT2860_TXWI_DMASZ; 675 paddr += RT2860_TXWI_DMASZ; 676 677 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 678 } 679 680 return 0; 681 682 fail: rt2860_free_tx_pool(sc); 683 return error; 684 } 685 686 static void 687 rt2860_free_tx_pool(struct rt2860_softc *sc) 688 { 689 if (sc->txwi_vaddr != NULL) { 690 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, 691 sc->txwi_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 692 bus_dmamap_unload(sc->sc_dmat, sc->txwi_map); 693 bus_dmamem_unmap(sc->sc_dmat, sc->txwi_vaddr, 694 RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ); 695 bus_dmamem_free(sc->sc_dmat, &sc->txwi_seg, 1); 696 } 697 if (sc->txwi_map != NULL) 698 bus_dmamap_destroy(sc->sc_dmat, sc->txwi_map); 699 700 while (!SLIST_EMPTY(&sc->data_pool)) { 701 struct rt2860_tx_data *data; 702 data = SLIST_FIRST(&sc->data_pool); 703 bus_dmamap_destroy(sc->sc_dmat, data->map); 704 SLIST_REMOVE_HEAD(&sc->data_pool, next); 705 } 706 } 707 708 static int 709 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 710 { 711 int i, nsegs, size, error; 712 713 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 714 715 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 716 BUS_DMA_NOWAIT, &ring->map); 717 if (error != 0) { 718 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 719 goto fail; 720 } 721 722 /* Rx ring must be 4-DWORD aligned */ 723 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 724 &nsegs, BUS_DMA_NOWAIT); 725 if (error != 0) { 726 aprint_error_dev(sc->sc_dev, 727 "could not allocate DMA memory\n"); 728 goto fail; 729 } 730 731 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 732 (void **)&ring->rxd, BUS_DMA_NOWAIT); 733 if (error != 0) { 734 aprint_error_dev(sc->sc_dev, "can't map DMA memory\n"); 735 goto fail; 736 } 737 738 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->rxd, size, NULL, 739 BUS_DMA_NOWAIT); 740 if (error != 0) { 741 aprint_error_dev(sc->sc_dev, "could not load DMA map\n"); 742 goto fail; 743 } 744 745 ring->paddr = ring->map->dm_segs[0].ds_addr; 746 747 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 748 struct rt2860_rx_data *data = &ring->data[i]; 749 struct rt2860_rxd *rxd = &ring->rxd[i]; 750 const char *msg; 751 752 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 753 0, BUS_DMA_NOWAIT, &data->map); 754 if (error != 0) { 755 aprint_error_dev(sc->sc_dev, 756 "could not create DMA map\n"); 757 goto fail; 758 } 759 760 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 761 if (data->m == NULL) { 762 msg = "allocate Rx mbuf"; 763 goto fail1; 764 } 765 MCLGET(data->m, M_DONTWAIT); 766 if ((data->m->m_flags & M_EXT) == 0) { 767 msg = "allocate Rx mbuf cluster"; 768 goto fail1; 769 } 770 771 772 error = bus_dmamap_load(sc->sc_dmat, data->map, 773 mtod(data->m, void *), MCLBYTES, NULL, 774 BUS_DMA_READ | BUS_DMA_NOWAIT); 775 if (error != 0) { 776 msg = "load DMA map"; 777 fail1: 778 aprint_error_dev(sc->sc_dev, "could not %s\n", msg); 779 m_freem(data->m); 780 data->m = NULL; 781 error = ENOBUFS; 782 goto fail; 783 } 784 785 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 786 rxd->sdl0 = htole16(MCLBYTES); 787 } 788 789 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 790 791 return 0; 792 fail: rt2860_free_rx_ring(sc, ring); 793 return error; 794 } 795 796 static void 797 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 798 { 799 int i; 800 801 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 802 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 803 804 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 805 BUS_DMASYNC_PREWRITE); 806 807 ring->cur = 0; 808 } 809 810 static void 811 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 812 { 813 int i; 814 815 if (ring->rxd != NULL) { 816 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 817 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 818 bus_dmamap_unload(sc->sc_dmat, ring->map); 819 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->rxd, 820 RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd)); 821 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 822 ring->rxd = NULL; 823 } 824 if (ring->map != NULL) { 825 bus_dmamap_destroy(sc->sc_dmat, ring->map); 826 ring->map = NULL; 827 } 828 829 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 830 struct rt2860_rx_data *data = &ring->data[i]; 831 832 if (data->m != NULL) { 833 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 834 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 835 bus_dmamap_unload(sc->sc_dmat, data->map); 836 m_freem(data->m); 837 data->m = NULL; 838 } 839 if (data->map != NULL) { 840 bus_dmamap_destroy(sc->sc_dmat, data->map); 841 data->map = NULL; 842 } 843 } 844 } 845 846 static struct ieee80211_node * 847 rt2860_node_alloc(struct ieee80211_node_table *nt) 848 { 849 struct rt2860_node *rn = malloc(sizeof(*rn), M_80211_NODE, 850 M_NOWAIT | M_ZERO); 851 return rn ? &rn->ni : NULL; 852 } 853 854 static int 855 rt2860_media_change(struct ifnet *ifp) 856 { 857 struct rt2860_softc *sc = ifp->if_softc; 858 struct ieee80211com *ic = &sc->sc_ic; 859 uint8_t rate, ridx; 860 int error; 861 862 error = ieee80211_media_change(ifp); 863 if (error != ENETRESET) 864 return error; 865 866 if (ic->ic_fixed_rate != -1) { 867 rate = ic->ic_sup_rates[ic->ic_curmode]. 868 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 869 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 870 if (rt2860_rates[ridx].rate == rate) 871 break; 872 sc->fixed_ridx = ridx; 873 } 874 875 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 876 (IFF_UP | IFF_RUNNING)) { 877 rt2860_stop(ifp, 0); 878 rt2860_init(ifp); 879 } 880 return 0; 881 } 882 883 static void 884 rt2860_iter_func(void *arg, struct ieee80211_node *ni) 885 { 886 struct rt2860_softc *sc = arg; 887 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 888 889 ieee80211_amrr_choose(&sc->amrr, ni, &sc->amn[wcid]); 890 } 891 892 static void 893 rt2860_updatestats(struct rt2860_softc *sc) 894 { 895 struct ieee80211com *ic = &sc->sc_ic; 896 int s; 897 898 #ifndef IEEE80211_STA_ONLY 899 /* 900 * In IBSS or HostAP modes (when the hardware sends beacons), the 901 * MAC can run into a livelock and start sending CTS-to-self frames 902 * like crazy if protection is enabled. Fortunately, we can detect 903 * when such a situation occurs and reset the MAC. 904 */ 905 if (ic->ic_curmode != IEEE80211_M_STA) { 906 /* check if we're in a livelock situation.. */ 907 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 908 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 909 /* ..and reset MAC/BBP for a while.. */ 910 DPRINTF(("CTS-to-self livelock detected\n")); 911 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 912 RAL_BARRIER_WRITE(sc); 913 DELAY(1); 914 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 915 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 916 } 917 } 918 #endif 919 s = splnet(); 920 if (ic->ic_opmode == IEEE80211_M_STA) 921 rt2860_iter_func(sc, ic->ic_bss); 922 #ifndef IEEE80211_STA_ONLY 923 else 924 ieee80211_iterate_nodes(&ic->ic_sta, rt2860_iter_func, sc); 925 #endif 926 splx(s); 927 } 928 929 static void 930 rt2860_newassoc(struct ieee80211_node *ni, int isnew) 931 { 932 struct rt2860_softc *sc = ni->ni_ic->ic_ifp->if_softc; 933 struct rt2860_node *rn = (void *)ni; 934 struct ieee80211_rateset *rs = &ni->ni_rates; 935 uint8_t rate, wcid = 0; 936 int ridx, i, j; 937 938 if (isnew && ni->ni_associd != 0) { 939 /* only interested in true associations */ 940 wcid = rn->wcid = IEEE80211_AID(ni->ni_associd); 941 942 /* init WCID table entry */ 943 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 944 ni->ni_macaddr, IEEE80211_ADDR_LEN); 945 } 946 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 947 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 948 949 ieee80211_amrr_node_init(&sc->amrr, &sc->amn[wcid]); 950 /* start at lowest available bit-rate, AMRR will raise */ 951 ni->ni_txrate = 0; 952 953 for (i = 0; i < rs->rs_nrates; i++) { 954 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 955 /* convert 802.11 rate to hardware rate index */ 956 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 957 if (rt2860_rates[ridx].rate == rate) 958 break; 959 rn->ridx[i] = ridx; 960 /* determine rate of control response frames */ 961 for (j = i; j >= 0; j--) { 962 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 963 rt2860_rates[rn->ridx[i]].phy == 964 rt2860_rates[rn->ridx[j]].phy) 965 break; 966 } 967 if (j >= 0) { 968 rn->ctl_ridx[i] = rn->ridx[j]; 969 } else { 970 /* no basic rate found, use mandatory one */ 971 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 972 } 973 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 974 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 975 } 976 } 977 978 #ifdef notyet 979 static int 980 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 981 uint8_t tid) 982 { 983 struct rt2860_softc *sc = ic->ic_softc; 984 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 985 uint32_t tmp; 986 987 /* update BA session mask */ 988 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 989 tmp |= (1 << tid) << 16; 990 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 991 return 0; 992 } 993 994 static void 995 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 996 uint8_t tid) 997 { 998 struct rt2860_softc *sc = ic->ic_softc; 999 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 1000 uint32_t tmp; 1001 1002 /* update BA session mask */ 1003 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 1004 tmp &= ~((1 << tid) << 16); 1005 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 1006 } 1007 #endif 1008 1009 static int 1010 rt2860_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1011 { 1012 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 1013 enum ieee80211_state ostate; 1014 uint32_t tmp; 1015 1016 ostate = ic->ic_state; 1017 1018 DPRINTF(("ostate = %d nstate = %d\n", ostate, nstate)); 1019 if (ostate == IEEE80211_S_RUN) { 1020 /* turn link LED off */ 1021 rt2860_set_leds(sc, RT2860_LED_RADIO); 1022 } 1023 1024 switch (nstate) { 1025 case IEEE80211_S_INIT: 1026 if (ostate == IEEE80211_S_RUN) { 1027 /* abort TSF synchronization */ 1028 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 1029 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 1030 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 1031 RT2860_TBTT_TIMER_EN)); 1032 } 1033 rt2860_set_gp_timer(sc, 0); 1034 break; 1035 1036 case IEEE80211_S_SCAN: 1037 rt2860_switch_chan(sc, ic->ic_curchan); 1038 if (ostate != IEEE80211_S_SCAN) 1039 rt2860_set_gp_timer(sc, 150); 1040 break; 1041 1042 case IEEE80211_S_AUTH: 1043 case IEEE80211_S_ASSOC: 1044 rt2860_set_gp_timer(sc, 0); 1045 rt2860_switch_chan(sc, ic->ic_curchan); 1046 break; 1047 1048 case IEEE80211_S_RUN: 1049 rt2860_set_gp_timer(sc, 0); 1050 rt2860_switch_chan(sc, ic->ic_curchan); 1051 1052 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1053 rt2860_updateslot(ic->ic_ifp); 1054 rt2860_enable_mrr(sc); 1055 rt2860_set_txpreamble(sc); 1056 rt2860_set_basicrates(sc); 1057 rt2860_set_bssid(sc, ic->ic_bss->ni_bssid); 1058 } 1059 1060 #ifndef IEEE80211_STA_ONLY 1061 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1062 ic->ic_opmode == IEEE80211_M_IBSS) 1063 (void)rt2860_setup_beacon(sc); 1064 #endif 1065 1066 if (ic->ic_opmode == IEEE80211_M_STA) { 1067 /* fake a join to init the tx rate */ 1068 rt2860_newassoc(ic->ic_bss, 1); 1069 } 1070 1071 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1072 rt2860_enable_tsf_sync(sc); 1073 rt2860_set_gp_timer(sc, 500); 1074 } 1075 1076 /* turn link LED on */ 1077 rt2860_set_leds(sc, RT2860_LED_RADIO | 1078 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan) ? 1079 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1080 break; 1081 } 1082 1083 return sc->sc_newstate(ic, nstate, arg); 1084 } 1085 1086 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 1087 static uint16_t 1088 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 1089 { 1090 uint32_t tmp; 1091 uint16_t reg; 1092 int ntries; 1093 1094 addr *= 2; 1095 /*- 1096 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1097 * DATA0: F E D C 1098 * DATA1: B A 9 8 1099 * DATA2: 7 6 5 4 1100 * DATA3: 3 2 1 0 1101 */ 1102 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1103 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1104 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1105 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 1106 for (ntries = 0; ntries < 500; ntries++) { 1107 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1108 if (!(tmp & RT3070_EFSROM_KICK)) 1109 break; 1110 DELAY(2); 1111 } 1112 if (ntries == 500) 1113 return 0xffff; 1114 1115 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 1116 return 0xffff; /* address not found */ 1117 1118 /* determine to which 32-bit register our 16-bit word belongs */ 1119 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1120 tmp = RAL_READ(sc, reg); 1121 1122 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1123 } 1124 1125 /* 1126 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1127 * 93C66 or 93C86). 1128 */ 1129 static uint16_t 1130 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1131 { 1132 uint32_t tmp; 1133 uint16_t val; 1134 int n; 1135 1136 /* clock C once before the first command */ 1137 RT2860_EEPROM_CTL(sc, 0); 1138 1139 RT2860_EEPROM_CTL(sc, RT2860_S); 1140 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1141 RT2860_EEPROM_CTL(sc, RT2860_S); 1142 1143 /* write start bit (1) */ 1144 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1145 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1146 1147 /* write READ opcode (10) */ 1148 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1149 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1150 RT2860_EEPROM_CTL(sc, RT2860_S); 1151 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1152 1153 /* write address (A5-A0 or A7-A0) */ 1154 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1155 for (; n >= 0; n--) { 1156 RT2860_EEPROM_CTL(sc, RT2860_S | 1157 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1158 RT2860_EEPROM_CTL(sc, RT2860_S | 1159 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1160 } 1161 1162 RT2860_EEPROM_CTL(sc, RT2860_S); 1163 1164 /* read data Q15-Q0 */ 1165 val = 0; 1166 for (n = 15; n >= 0; n--) { 1167 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1168 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1169 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1170 RT2860_EEPROM_CTL(sc, RT2860_S); 1171 } 1172 1173 RT2860_EEPROM_CTL(sc, 0); 1174 1175 /* clear Chip Select and clock C */ 1176 RT2860_EEPROM_CTL(sc, RT2860_S); 1177 RT2860_EEPROM_CTL(sc, 0); 1178 RT2860_EEPROM_CTL(sc, RT2860_C); 1179 1180 return val; 1181 } 1182 1183 static __inline uint16_t 1184 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1185 { 1186 /* either eFUSE ROM or EEPROM */ 1187 return sc->sc_srom_read(sc, addr); 1188 } 1189 1190 static void 1191 rt2860_intr_coherent(struct rt2860_softc *sc) 1192 { 1193 uint32_t tmp; 1194 1195 /* DMA finds data coherent event when checking the DDONE bit */ 1196 1197 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1198 1199 /* restart DMA engine */ 1200 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1201 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1202 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1203 1204 (void)rt2860_txrx_enable(sc); 1205 } 1206 1207 static void 1208 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1209 { 1210 struct ifnet *ifp = &sc->sc_if; 1211 struct ieee80211_amrr_node *amn; 1212 uint32_t stat; 1213 uint8_t wcid, mcs, pid; 1214 1215 /* drain Tx status FIFO (maxsize = 16) */ 1216 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1217 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1218 1219 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1220 1221 /* if no ACK was requested, no feedback is available */ 1222 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff) 1223 continue; 1224 1225 /* update per-STA AMRR stats */ 1226 amn = &sc->amn[wcid]; 1227 amn->amn_txcnt++; 1228 if (stat & RT2860_TXQ_OK) { 1229 /* 1230 * Check if there were retries, ie if the Tx success 1231 * rate is different from the requested rate. Note 1232 * that it works only because we do not allow rate 1233 * fallback from OFDM to CCK. 1234 */ 1235 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1236 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1237 if (mcs + 1 != pid) 1238 amn->amn_retrycnt++; 1239 } else { 1240 amn->amn_retrycnt++; 1241 ifp->if_oerrors++; 1242 } 1243 } 1244 } 1245 1246 static void 1247 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1248 { 1249 struct ifnet *ifp = &sc->sc_if; 1250 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1251 uint32_t hw; 1252 int s; 1253 1254 s = splnet(); 1255 1256 rt2860_drain_stats_fifo(sc); 1257 1258 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1259 DPRINTF(("%s: tx mbuf %#x\n", __func__, hw)); 1260 while (ring->next != hw) { 1261 struct rt2860_tx_data *data = ring->data[ring->next]; 1262 1263 if (data != NULL) { 1264 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1265 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1266 bus_dmamap_unload(sc->sc_dmat, data->map); 1267 m_freem(data->m); 1268 data->m = NULL; 1269 ieee80211_free_node(data->ni); 1270 data->ni = NULL; 1271 1272 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1273 ring->data[ring->next] = NULL; 1274 1275 ifp->if_opackets++; 1276 } 1277 ring->queued--; 1278 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1279 } 1280 1281 sc->sc_tx_timer = 0; 1282 if (ring->queued <= RT2860_TX_RING_ONEMORE) 1283 sc->qfullmsk &= ~(1 << qid); 1284 ifp->if_flags &= ~IFF_OACTIVE; 1285 rt2860_start(ifp); 1286 1287 splx(s); 1288 } 1289 1290 /* 1291 * Return the Rx chain with the highest RSSI for a given frame. 1292 */ 1293 static __inline uint8_t 1294 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1295 { 1296 uint8_t rxchain = 0; 1297 1298 if (sc->nrxchains > 1) { 1299 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1300 rxchain = 1; 1301 if (sc->nrxchains > 2) 1302 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1303 rxchain = 2; 1304 } 1305 return rxchain; 1306 } 1307 1308 static void 1309 rt2860_rx_intr(struct rt2860_softc *sc) 1310 { 1311 struct ieee80211com *ic = &sc->sc_ic; 1312 struct ifnet *ifp = &sc->sc_if; 1313 struct ieee80211_frame *wh; 1314 struct ieee80211_node *ni; 1315 struct mbuf *m, *m1; 1316 uint32_t hw; 1317 uint8_t ant, rssi; 1318 int error, s; 1319 struct rt2860_rx_radiotap_header *tap; 1320 uint16_t phy; 1321 1322 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1323 DPRINTF(("%s: rx mbuf %#x\n", __func__, hw)); 1324 while (sc->rxq.cur != hw) { 1325 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1326 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1327 struct rt2860_rxwi *rxwi; 1328 1329 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1330 sc->rxq.cur * sizeof (struct rt2860_rxd), 1331 sizeof (struct rt2860_rxd), BUS_DMASYNC_POSTREAD); 1332 1333 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1334 DPRINTF(("RXD DDONE bit not set!\n")); 1335 break; /* should not happen */ 1336 } 1337 1338 if (__predict_false(rxd->flags & 1339 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1340 DPRINTF(("error %#x\n", rxd->flags)); 1341 ifp->if_ierrors++; 1342 goto skip; 1343 } 1344 1345 1346 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1347 if (__predict_false(m1 == NULL)) { 1348 DPRINTF(("error2 %#x\n", rxd->flags)); 1349 ifp->if_ierrors++; 1350 goto skip; 1351 } 1352 MCLGET(m1, M_DONTWAIT); 1353 if (__predict_false((m1->m_flags & M_EXT) == 0)) { 1354 DPRINTF(("no mbuf\n")); 1355 m_freem(m1); 1356 ifp->if_ierrors++; 1357 goto skip; 1358 } 1359 1360 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1361 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1362 bus_dmamap_unload(sc->sc_dmat, data->map); 1363 1364 error = bus_dmamap_load(sc->sc_dmat, data->map, 1365 mtod(m1, void *), MCLBYTES, NULL, 1366 BUS_DMA_READ | BUS_DMA_NOWAIT); 1367 if (__predict_false(error != 0)) { 1368 DPRINTF(("dma error %d\n", error)); 1369 m_freem(m1); 1370 1371 /* try to reload the old mbuf */ 1372 error = bus_dmamap_load(sc->sc_dmat, data->map, 1373 mtod(data->m, void *), MCLBYTES, NULL, 1374 BUS_DMA_READ | BUS_DMA_NOWAIT); 1375 if (__predict_false(error != 0)) { 1376 panic("%s: could not load old rx mbuf", 1377 device_xname(sc->sc_dev)); 1378 } 1379 /* physical address may have changed */ 1380 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1381 ifp->if_ierrors++; 1382 goto skip; 1383 } 1384 1385 /* 1386 * New mbuf successfully loaded, update Rx ring and continue 1387 * processing. 1388 */ 1389 m = data->m; 1390 data->m = m1; 1391 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1392 1393 rxwi = mtod(m, struct rt2860_rxwi *); 1394 1395 /* finalize mbuf */ 1396 m->m_data = (void *)(rxwi + 1); 1397 m_set_rcvif(m, ifp); 1398 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1399 1400 wh = mtod(m, struct ieee80211_frame *); 1401 #ifdef HW_CRYPTO 1402 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1403 /* frame is decrypted by hardware */ 1404 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1405 } 1406 #endif 1407 1408 /* HW may insert 2 padding bytes after 802.11 header */ 1409 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1410 u_int hdrlen = ieee80211_hdrsize(wh); 1411 memmove((char *)wh + 2, wh, hdrlen); 1412 m->m_data += 2; 1413 wh = mtod(m, struct ieee80211_frame *); 1414 } 1415 1416 #ifdef HW_CRYPTO 1417 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1418 /* report MIC failures to net80211 for TKIP */ 1419 ieee80211_notify_michael_failure(ic, wh, 0/* XXX */); 1420 DPRINTF(("error2 %#x\n", rxd->flags)); 1421 ifp->if_ierrors++; 1422 goto skip; 1423 } 1424 #endif 1425 ant = rt2860_maxrssi_chain(sc, rxwi); 1426 rssi = rxwi->rssi[ant]; 1427 1428 s = splnet(); 1429 1430 if (__predict_true(sc->sc_drvbpf == NULL)) 1431 goto skipbpf; 1432 1433 tap = &sc->sc_rxtap; 1434 tap->wr_flags = 0; 1435 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1436 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1437 tap->wr_antsignal = rssi; 1438 tap->wr_antenna = ant; 1439 tap->wr_dbm_antsignal = rt2860_rssi2dbm(sc, rssi, ant); 1440 tap->wr_rate = 2; /* in case it can't be found below */ 1441 phy = le16toh(rxwi->phy); 1442 switch (phy & RT2860_PHY_MODE) { 1443 case RT2860_PHY_CCK: 1444 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1445 case 0: tap->wr_rate = 2; break; 1446 case 1: tap->wr_rate = 4; break; 1447 case 2: tap->wr_rate = 11; break; 1448 case 3: tap->wr_rate = 22; break; 1449 } 1450 if (phy & RT2860_PHY_SHPRE) 1451 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1452 break; 1453 case RT2860_PHY_OFDM: 1454 switch (phy & RT2860_PHY_MCS) { 1455 case 0: tap->wr_rate = 12; break; 1456 case 1: tap->wr_rate = 18; break; 1457 case 2: tap->wr_rate = 24; break; 1458 case 3: tap->wr_rate = 36; break; 1459 case 4: tap->wr_rate = 48; break; 1460 case 5: tap->wr_rate = 72; break; 1461 case 6: tap->wr_rate = 96; break; 1462 case 7: tap->wr_rate = 108; break; 1463 } 1464 break; 1465 } 1466 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1467 skipbpf: 1468 /* grab a reference to the source node */ 1469 ni = ieee80211_find_rxnode(ic, 1470 (struct ieee80211_frame_min *)wh); 1471 1472 /* send the frame to the 802.11 layer */ 1473 ieee80211_input(ic, m, ni, rssi, 0); 1474 1475 /* node is no longer needed */ 1476 ieee80211_free_node(ni); 1477 1478 splx(s); 1479 1480 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1481 1482 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1483 sc->rxq.cur * sizeof (struct rt2860_rxd), 1484 sizeof (struct rt2860_rxd), BUS_DMASYNC_PREWRITE); 1485 1486 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1487 } 1488 1489 /* tell HW what we have processed */ 1490 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1491 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1492 } 1493 1494 static void 1495 rt2860_tbtt_intr(struct rt2860_softc *sc) 1496 { 1497 struct ieee80211com *ic = &sc->sc_ic; 1498 1499 #ifndef IEEE80211_STA_ONLY 1500 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1501 /* one less beacon until next DTIM */ 1502 if (ic->ic_dtim_count == 0) 1503 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1504 else 1505 ic->ic_dtim_count--; 1506 1507 /* update dynamic parts of beacon */ 1508 rt2860_setup_beacon(sc); 1509 1510 #if 0 1511 /* flush buffered multicast frames */ 1512 if (ic->ic_dtim_count == 0) 1513 ieee80211_notify_dtim(ic); 1514 #endif 1515 } 1516 #endif 1517 /* check if protection mode has changed */ 1518 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1519 rt2860_updateprot(ic); 1520 sc->sc_ic_flags = ic->ic_flags; 1521 } 1522 } 1523 1524 static void 1525 rt2860_gp_intr(struct rt2860_softc *sc) 1526 { 1527 struct ieee80211com *ic = &sc->sc_ic; 1528 int s; 1529 1530 DPRINTFN(2, ("GP timeout state=%d\n", ic->ic_state)); 1531 1532 s = splnet(); 1533 if (ic->ic_state == IEEE80211_S_SCAN) 1534 ieee80211_next_scan(ic); 1535 else if (ic->ic_state == IEEE80211_S_RUN) 1536 rt2860_updatestats(sc); 1537 splx(s); 1538 } 1539 1540 int 1541 rt2860_intr(void *arg) 1542 { 1543 struct rt2860_softc *sc = arg; 1544 uint32_t r; 1545 1546 r = RAL_READ(sc, RT2860_INT_STATUS); 1547 if (__predict_false(r == 0xffffffff)) 1548 return 0; /* device likely went away */ 1549 if (r == 0) 1550 return 0; /* not for us */ 1551 1552 softint_schedule(sc->sc_soft_ih); 1553 return 1; 1554 } 1555 1556 static void 1557 rt2860_softintr(void *arg) 1558 { 1559 struct rt2860_softc *sc = arg; 1560 uint32_t r; 1561 1562 r = RAL_READ(sc, RT2860_INT_STATUS); 1563 if (__predict_false(r == 0xffffffff)) 1564 goto out; /* device likely went away */ 1565 if (r == 0) 1566 goto out; 1567 1568 /* acknowledge interrupts */ 1569 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1570 1571 if (r & RT2860_TX_RX_COHERENT) 1572 rt2860_intr_coherent(sc); 1573 1574 if (r & RT2860_MAC_INT_2) /* TX status */ 1575 rt2860_drain_stats_fifo(sc); 1576 1577 if (r & RT2860_TX_DONE_INT5) 1578 rt2860_tx_intr(sc, 5); 1579 1580 if (r & RT2860_RX_DONE_INT) 1581 rt2860_rx_intr(sc); 1582 1583 if (r & RT2860_TX_DONE_INT4) 1584 rt2860_tx_intr(sc, 4); 1585 1586 if (r & RT2860_TX_DONE_INT3) 1587 rt2860_tx_intr(sc, 3); 1588 1589 if (r & RT2860_TX_DONE_INT2) 1590 rt2860_tx_intr(sc, 2); 1591 1592 if (r & RT2860_TX_DONE_INT1) 1593 rt2860_tx_intr(sc, 1); 1594 1595 if (r & RT2860_TX_DONE_INT0) 1596 rt2860_tx_intr(sc, 0); 1597 1598 if (r & RT2860_MAC_INT_0) /* TBTT */ 1599 rt2860_tbtt_intr(sc); 1600 1601 if (r & RT2860_MAC_INT_3) { /* Auto wakeup */ 1602 /* TBD wakeup */ 1603 } 1604 1605 if (r & RT2860_MAC_INT_4) /* GP timer */ 1606 rt2860_gp_intr(sc); 1607 1608 out: 1609 /* enable interrupts */ 1610 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 1611 } 1612 1613 static int 1614 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1615 { 1616 struct ieee80211com *ic = &sc->sc_ic; 1617 struct rt2860_node *rn = (void *)ni; 1618 struct rt2860_tx_ring *ring; 1619 struct rt2860_tx_data *data; 1620 struct rt2860_txd *txd; 1621 struct rt2860_txwi *txwi; 1622 struct ieee80211_frame *wh; 1623 bus_dma_segment_t *seg; 1624 u_int hdrlen; 1625 uint16_t qos, dur; 1626 uint8_t type, qsel, mcs, pid, tid, qid; 1627 int nsegs, hasqos, ridx, ctl_ridx; 1628 1629 /* the data pool contains at least one element, pick the first */ 1630 data = SLIST_FIRST(&sc->data_pool); 1631 1632 wh = mtod(m, struct ieee80211_frame *); 1633 #ifndef HW_CRYPTO 1634 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1635 struct ieee80211_key *k = ieee80211_crypto_encap(ic, ni, m); 1636 if (k == NULL) { 1637 m_freem(m); 1638 return ENOBUFS; 1639 } 1640 1641 /* packet header may have moved, reset our local pointer */ 1642 wh = mtod(m, struct ieee80211_frame *); 1643 } 1644 #endif 1645 1646 hdrlen = ieee80211_anyhdrsize(wh); 1647 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1648 1649 if ((hasqos = ieee80211_has_qos(wh))) { 1650 qos = ieee80211_get_qos(wh); 1651 tid = qos & IEEE80211_QOS_TID; 1652 qid = TID_TO_WME_AC(tid); 1653 } else { 1654 qos = 0; 1655 tid = 0; 1656 qid = (type == IEEE80211_FC0_TYPE_MGT) ? 1657 sc->mgtqid : WME_AC_BE; 1658 } 1659 KASSERT(qid < MAXQS); 1660 ring = &sc->txq[qid]; 1661 1662 /* pickup a rate index */ 1663 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1664 type != IEEE80211_FC0_TYPE_DATA) { 1665 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1666 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 1667 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1668 } else if (ic->ic_fixed_rate != -1) { 1669 ridx = sc->fixed_ridx; 1670 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1671 } else { 1672 ridx = rn->ridx[ni->ni_txrate]; 1673 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 1674 } 1675 1676 /* get MCS code from rate index */ 1677 mcs = rt2860_rates[ridx].mcs; 1678 1679 /* setup TX Wireless Information */ 1680 txwi = data->txwi; 1681 txwi->flags = 0; 1682 /* let HW generate seq numbers for non-QoS frames */ 1683 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 1684 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? rn->wcid : 0xff; 1685 txwi->len = htole16(m->m_pkthdr.len); 1686 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1687 txwi->phy = htole16(RT2860_PHY_CCK); 1688 if (ridx != RT2860_RIDX_CCK1 && 1689 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1690 mcs |= RT2860_PHY_SHPRE; 1691 } else 1692 txwi->phy = htole16(RT2860_PHY_OFDM); 1693 txwi->phy |= htole16(mcs); 1694 1695 /* 1696 * We store the MCS code into the driver-private PacketID field. 1697 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1698 * that we know at which initial rate the frame was transmitted. 1699 * We add 1 to the MCS code because setting the PacketID field to 1700 * 0 means that we don't want feedback in TX_STAT_FIFO. 1701 */ 1702 pid = (mcs + 1) & 0xf; 1703 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1704 1705 /* check if RTS/CTS or CTS-to-self protection is required */ 1706 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1707 (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold || 1708 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1709 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1710 txwi->txop = RT2860_TX_TXOP_HT; 1711 else 1712 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1713 1714 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1715 (!hasqos || (qos & IEEE80211_QOS_ACKPOLICY) != 1716 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1717 txwi->xflags |= RT2860_TX_ACK; 1718 1719 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1720 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 1721 else 1722 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 1723 *(uint16_t *)wh->i_dur = htole16(dur); 1724 } 1725 #ifndef IEEE80211_STA_ONLY 1726 /* ask MAC to insert timestamp into probe responses */ 1727 if ((wh->i_fc[0] & 1728 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1729 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1730 /* NOTE: beacons do not pass through tx_data() */ 1731 txwi->flags |= RT2860_TX_TS; 1732 #endif 1733 1734 if (__predict_false(sc->sc_drvbpf != NULL)) { 1735 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1736 1737 tap->wt_flags = 0; 1738 tap->wt_rate = rt2860_rates[ridx].rate; 1739 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1740 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1741 tap->wt_hwqueue = qid; 1742 if (mcs & RT2860_PHY_SHPRE) 1743 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1744 1745 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 1746 } 1747 1748 /* copy and trim 802.11 header */ 1749 memcpy(txwi + 1, wh, hdrlen); 1750 m_adj(m, hdrlen); 1751 1752 KASSERT (ring->queued <= RT2860_TX_RING_ONEMORE); /* <1> */ 1753 if (bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, BUS_DMA_NOWAIT)) { 1754 if (m_defrag(m, M_DONTWAIT)) 1755 return (ENOBUFS); 1756 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1757 data->map, m, BUS_DMA_NOWAIT)) 1758 return (EFBIG); 1759 } 1760 1761 /* The map will fit into the tx ring: (a "full" ring may have a few 1762 * unused descriptors, at most (txds(MAX_SCATTER) - 1)) 1763 * 1764 * ring->queued + txds(data->map->nsegs) 1765 * <= { <0> data->map->nsegs <= MAX_SCATTER } 1766 * ring->queued + txds(MAX_SCATTER) 1767 * <= { <1> ring->queued <= TX_RING_MAX - txds(MAX_SCATTER) } 1768 * TX_RING_MAX - txds(MAX_SCATTER) + txds(MAX_SCATTER) 1769 * <= { arithmetic } 1770 * TX_RING_MAX 1771 */ 1772 1773 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1774 1775 /* first segment is TXWI + 802.11 header */ 1776 txd = &ring->txd[ring->cur]; 1777 txd->sdp0 = htole32(data->paddr); 1778 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + hdrlen); 1779 txd->flags = qsel; 1780 1781 /* setup payload segments */ 1782 seg = data->map->dm_segs; 1783 for (nsegs = data->map->dm_nsegs; nsegs >= 2; nsegs -= 2) { 1784 txd->sdp1 = htole32(seg->ds_addr); 1785 txd->sdl1 = htole16(seg->ds_len); 1786 seg++; 1787 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1788 /* grab a new Tx descriptor */ 1789 txd = &ring->txd[ring->cur]; 1790 txd->sdp0 = htole32(seg->ds_addr); 1791 txd->sdl0 = htole16(seg->ds_len); 1792 txd->flags = qsel; 1793 seg++; 1794 } 1795 /* finalize last segment */ 1796 if (nsegs > 0) { 1797 txd->sdp1 = htole32(seg->ds_addr); 1798 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1799 } else { 1800 txd->sdl0 |= htole16(RT2860_TX_LS0); 1801 txd->sdl1 = 0; 1802 } 1803 1804 /* remove from the free pool and link it into the SW Tx slot */ 1805 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1806 data->m = m; 1807 data->ni = ni; 1808 ring->data[ring->cur] = data; 1809 1810 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 1811 (uintptr_t)txwi - (uintptr_t)sc->txwi_vaddr, RT2860_TXWI_DMASZ, 1812 BUS_DMASYNC_PREWRITE); 1813 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1814 BUS_DMASYNC_PREWRITE); 1815 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1816 BUS_DMASYNC_PREWRITE); 1817 1818 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1819 qid, txwi->wcid, data->map->dm_nsegs, ridx)); 1820 1821 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1822 ring->queued += 1 + (data->map->dm_nsegs / 2); 1823 if (ring->queued > RT2860_TX_RING_ONEMORE) 1824 sc->qfullmsk |= 1 << qid; 1825 1826 /* kick Tx */ 1827 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1828 1829 return 0; 1830 } 1831 1832 static void 1833 rt2860_start(struct ifnet *ifp) 1834 { 1835 struct rt2860_softc *sc = ifp->if_softc; 1836 struct ieee80211com *ic = &sc->sc_ic; 1837 struct ether_header *eh; 1838 struct ieee80211_node *ni; 1839 struct mbuf *m; 1840 1841 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1842 return; 1843 1844 for (;;) { 1845 if (SLIST_EMPTY(&sc->data_pool) || sc->qfullmsk != 0) { 1846 DPRINTF(("%s: stuffup\n", __func__)); 1847 ifp->if_flags |= IFF_OACTIVE; 1848 break; 1849 } 1850 /* send pending management frames first */ 1851 IF_DEQUEUE(&ic->ic_mgtq, m); 1852 if (m != NULL) { 1853 ni = M_GETCTX(m, struct ieee80211_node *); 1854 M_CLEARCTX(m); 1855 DPRINTF(("%s: send management\n", __func__)); 1856 goto sendit; 1857 } 1858 if (ic->ic_state != IEEE80211_S_RUN) { 1859 DPRINTF(("%s: not running %d\n", __func__, 1860 ic->ic_state)); 1861 break; 1862 } 1863 1864 /* encapsulate and send data frames */ 1865 IFQ_DEQUEUE(&ifp->if_snd, m); 1866 if (m == NULL) { 1867 DPRINTF(("%s: nothing to send\n", __func__)); 1868 break; 1869 } 1870 if (m->m_len < (int)sizeof(*eh) && 1871 (m = m_pullup(m, sizeof(*eh))) == NULL) { 1872 DPRINTF(("%s: nothing to send\n", __func__)); 1873 ifp->if_oerrors++; 1874 continue; 1875 } 1876 1877 eh = mtod(m, struct ether_header *); 1878 1879 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1880 if (ni == NULL) { 1881 DPRINTF(("%s: can't find tx node\n", __func__)); 1882 m_freem(m); 1883 ifp->if_oerrors++; 1884 continue; 1885 } 1886 1887 bpf_mtap(ifp, m); 1888 1889 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 1890 DPRINTF(("%s: can't encap\n", __func__)); 1891 ieee80211_free_node(ni); 1892 ifp->if_oerrors++; 1893 continue; 1894 } 1895 sendit: 1896 bpf_mtap3(ic->ic_rawbpf, m); 1897 1898 if (rt2860_tx(sc, m, ni) != 0) { 1899 DPRINTF(("%s: can't tx\n", __func__)); 1900 m_freem(m); 1901 ieee80211_free_node(ni); 1902 ifp->if_oerrors++; 1903 continue; 1904 } 1905 1906 sc->sc_tx_timer = 5; 1907 ifp->if_timer = 1; 1908 } 1909 } 1910 1911 static void 1912 rt2860_watchdog(struct ifnet *ifp) 1913 { 1914 struct rt2860_softc *sc = ifp->if_softc; 1915 struct ieee80211com *ic = &sc->sc_ic; 1916 1917 ifp->if_timer = 0; 1918 1919 if (sc->sc_tx_timer > 0) { 1920 if (--sc->sc_tx_timer == 0) { 1921 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1922 rt2860_stop(ifp, 0); 1923 rt2860_init(ifp); 1924 ifp->if_oerrors++; 1925 return; 1926 } 1927 ifp->if_timer = 1; 1928 } 1929 1930 ieee80211_watchdog(ic); 1931 } 1932 1933 static int 1934 rt2860_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1935 { 1936 struct rt2860_softc *sc = ifp->if_softc; 1937 struct ieee80211com *ic = &sc->sc_ic; 1938 int s, error = 0; 1939 1940 s = splnet(); 1941 1942 switch (cmd) { 1943 case SIOCSIFFLAGS: 1944 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1945 break; 1946 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1947 case IFF_UP|IFF_RUNNING: 1948 rt2860_update_promisc(ifp); 1949 break; 1950 case IFF_UP: 1951 rt2860_init(ifp); 1952 break; 1953 case IFF_RUNNING: 1954 rt2860_stop(ifp, 1); 1955 break; 1956 case 0: 1957 break; 1958 } 1959 break; 1960 1961 case SIOCADDMULTI: 1962 case SIOCDELMULTI: 1963 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1964 /* setup multicast filter, etc */ 1965 error = 0; 1966 } 1967 break; 1968 1969 case SIOCS80211CHANNEL: 1970 /* 1971 * This allows for fast channel switching in monitor mode 1972 * (used by kismet). In IBSS mode, we must explicitly reset 1973 * the interface to generate a new beacon frame. 1974 */ 1975 error = ieee80211_ioctl(ic, cmd, data); 1976 if (error == ENETRESET && 1977 ic->ic_opmode == IEEE80211_M_MONITOR) { 1978 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1979 (IFF_UP | IFF_RUNNING)) 1980 rt2860_switch_chan(sc, ic->ic_ibss_chan); 1981 error = 0; 1982 } 1983 break; 1984 1985 default: 1986 error = ieee80211_ioctl(ic, cmd, data); 1987 } 1988 1989 if (error == ENETRESET) { 1990 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1991 (IFF_UP | IFF_RUNNING)) { 1992 rt2860_stop(ifp, 0); 1993 rt2860_init(ifp); 1994 } 1995 error = 0; 1996 } 1997 1998 splx(s); 1999 2000 return error; 2001 } 2002 2003 /* 2004 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2005 * We access the BBP through the 8051 microcontroller unit which means that 2006 * the microcode must be loaded first. 2007 */ 2008 static void 2009 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2010 { 2011 int ntries; 2012 2013 for (ntries = 0; ntries < 100; ntries++) { 2014 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2015 break; 2016 DELAY(1); 2017 } 2018 if (ntries == 100) { 2019 aprint_error_dev(sc->sc_dev, 2020 "could not write to BBP through MCU\n"); 2021 return; 2022 } 2023 2024 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2025 RT2860_BBP_CSR_KICK | reg << 8 | val); 2026 RAL_BARRIER_WRITE(sc); 2027 2028 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2029 DELAY(1000); 2030 } 2031 2032 static uint8_t 2033 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2034 { 2035 uint32_t val; 2036 int ntries; 2037 2038 for (ntries = 0; ntries < 100; ntries++) { 2039 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2040 break; 2041 DELAY(1); 2042 } 2043 if (ntries == 100) { 2044 aprint_error_dev(sc->sc_dev, 2045 "could not read from BBP through MCU\n"); 2046 return 0; 2047 } 2048 2049 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2050 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2051 RAL_BARRIER_WRITE(sc); 2052 2053 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2054 DELAY(1000); 2055 2056 for (ntries = 0; ntries < 100; ntries++) { 2057 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2058 if (!(val & RT2860_BBP_CSR_KICK)) 2059 return val & 0xff; 2060 DELAY(1); 2061 } 2062 aprint_error_dev(sc->sc_dev, "could not read from BBP through MCU\n"); 2063 2064 return 0; 2065 } 2066 2067 /* 2068 * Write to one of the 4 programmable 24-bit RF registers. 2069 */ 2070 static void 2071 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2072 { 2073 uint32_t tmp; 2074 int ntries; 2075 2076 for (ntries = 0; ntries < 100; ntries++) { 2077 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2078 break; 2079 DELAY(1); 2080 } 2081 if (ntries == 100) { 2082 aprint_error_dev(sc->sc_dev, "could not write to RF\n"); 2083 return; 2084 } 2085 2086 /* RF registers are 24-bit on the RT2860 */ 2087 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2088 (val & 0x3fffff) << 2 | (reg & 3); 2089 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2090 } 2091 2092 static uint8_t 2093 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2094 { 2095 uint32_t tmp; 2096 int ntries; 2097 2098 for (ntries = 0; ntries < 100; ntries++) { 2099 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2100 break; 2101 DELAY(1); 2102 } 2103 if (ntries == 100) { 2104 aprint_error_dev(sc->sc_dev, "could not read RF register\n"); 2105 return 0xff; 2106 } 2107 tmp = RT3070_RF_KICK | reg << 8; 2108 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2109 2110 for (ntries = 0; ntries < 100; ntries++) { 2111 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2112 if (!(tmp & RT3070_RF_KICK)) 2113 break; 2114 DELAY(1); 2115 } 2116 if (ntries == 100) { 2117 aprint_error_dev(sc->sc_dev, "could not read RF register\n"); 2118 return 0xff; 2119 } 2120 return tmp & 0xff; 2121 } 2122 2123 static void 2124 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2125 { 2126 uint32_t tmp; 2127 int ntries; 2128 2129 for (ntries = 0; ntries < 10; ntries++) { 2130 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2131 break; 2132 DELAY(10); 2133 } 2134 if (ntries == 10) { 2135 aprint_error_dev(sc->sc_dev, "could not write to RF\n"); 2136 return; 2137 } 2138 2139 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2140 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2141 } 2142 2143 /* 2144 * Send a command to the 8051 microcontroller unit. 2145 */ 2146 static int 2147 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2148 { 2149 int slot, ntries; 2150 uint32_t tmp; 2151 uint8_t cid; 2152 2153 for (ntries = 0; ntries < 100; ntries++) { 2154 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2155 break; 2156 DELAY(2); 2157 } 2158 if (ntries == 100) 2159 return EIO; 2160 2161 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2162 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2163 RAL_BARRIER_WRITE(sc); 2164 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2165 2166 if (!wait) 2167 return 0; 2168 /* wait for the command to complete */ 2169 for (ntries = 0; ntries < 200; ntries++) { 2170 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2171 /* find the command slot */ 2172 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2173 if ((tmp & 0xff) == cid) 2174 break; 2175 if (slot < 4) 2176 break; 2177 DELAY(100); 2178 } 2179 if (ntries == 200) { 2180 /* clear command and status */ 2181 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2182 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2183 return ETIMEDOUT; 2184 } 2185 /* get command status (1 means success) */ 2186 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2187 tmp = (tmp >> (slot * 8)) & 0xff; 2188 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2189 cmd, slot, tmp)); 2190 /* clear command and status */ 2191 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2192 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2193 return (tmp == 1) ? 0 : EIO; 2194 } 2195 2196 static void 2197 rt2860_enable_mrr(struct rt2860_softc *sc) 2198 { 2199 #define CCK(mcs) (mcs) 2200 #define OFDM(mcs) (1 << 3 | (mcs)) 2201 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2202 OFDM(6) << 28 | /* 54->48 */ 2203 OFDM(5) << 24 | /* 48->36 */ 2204 OFDM(4) << 20 | /* 36->24 */ 2205 OFDM(3) << 16 | /* 24->18 */ 2206 OFDM(2) << 12 | /* 18->12 */ 2207 OFDM(1) << 8 | /* 12-> 9 */ 2208 OFDM(0) << 4 | /* 9-> 6 */ 2209 OFDM(0)); /* 6-> 6 */ 2210 2211 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2212 CCK(2) << 12 | /* 11->5.5 */ 2213 CCK(1) << 8 | /* 5.5-> 2 */ 2214 CCK(0) << 4 | /* 2-> 1 */ 2215 CCK(0)); /* 1-> 1 */ 2216 #undef OFDM 2217 #undef CCK 2218 } 2219 2220 static void 2221 rt2860_set_txpreamble(struct rt2860_softc *sc) 2222 { 2223 uint32_t tmp; 2224 2225 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2226 tmp &= ~RT2860_CCK_SHORT_EN; 2227 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2228 tmp |= RT2860_CCK_SHORT_EN; 2229 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2230 } 2231 2232 static void 2233 rt2860_set_basicrates(struct rt2860_softc *sc) 2234 { 2235 struct ieee80211com *ic = &sc->sc_ic; 2236 2237 /* set basic rates mask */ 2238 if (ic->ic_curmode == IEEE80211_MODE_11B) 2239 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 2240 else if (ic->ic_curmode == IEEE80211_MODE_11A) 2241 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 2242 else /* 11g */ 2243 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 2244 } 2245 2246 static void 2247 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2248 { 2249 uint32_t tmp; 2250 uint8_t agc; 2251 2252 /* Wait for BBP to settle */ 2253 DELAY(1000); 2254 2255 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2256 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2257 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2258 rt2860_mcu_bbp_write(sc, 86, 0x00); 2259 2260 if (group == 0) { 2261 if (sc->ext_2ghz_lna) { 2262 rt2860_mcu_bbp_write(sc, 82, 0x62); 2263 rt2860_mcu_bbp_write(sc, 75, 0x46); 2264 } else { 2265 rt2860_mcu_bbp_write(sc, 82, 0x84); 2266 rt2860_mcu_bbp_write(sc, 75, 0x50); 2267 } 2268 } else { 2269 if (sc->mac_ver == 0x3572) 2270 rt2860_mcu_bbp_write(sc, 82, 0x94); 2271 else 2272 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2273 2274 if (sc->ext_5ghz_lna) 2275 rt2860_mcu_bbp_write(sc, 75, 0x46); 2276 else 2277 rt2860_mcu_bbp_write(sc, 75, 0x50); 2278 } 2279 2280 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2281 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2282 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2283 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2284 2285 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2286 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2287 if (sc->nrxchains > 1) 2288 tmp |= RT2860_LNA_PE1_EN; 2289 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2290 tmp |= RT3593_LNA_PE2_EN; 2291 if (group == 0) { /* 2GHz */ 2292 tmp |= RT2860_PA_PE_G0_EN; 2293 if (sc->ntxchains > 1) 2294 tmp |= RT2860_PA_PE_G1_EN; 2295 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2296 tmp |= RT3593_PA_PE_G2_EN; 2297 } else { /* 5GHz */ 2298 tmp |= RT2860_PA_PE_A0_EN; 2299 if (sc->ntxchains > 1) 2300 tmp |= RT2860_PA_PE_A1_EN; 2301 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2302 tmp |= RT3593_PA_PE_A2_EN; 2303 } 2304 if (sc->mac_ver == 0x3572) { 2305 rt3090_rf_write(sc, 8, 0x00); 2306 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2307 rt3090_rf_write(sc, 8, 0x80); 2308 } else 2309 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2310 2311 if (sc->mac_ver == 0x3593) { 2312 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2313 if (sc->sc_flags & RT2860_PCIE) { 2314 tmp &= ~0x01010000; 2315 if (group == 0) 2316 tmp |= 0x00010000; 2317 } else { 2318 tmp &= ~0x00008080; 2319 if (group == 0) 2320 tmp |= 0x00000080; 2321 } 2322 tmp = (tmp & ~0x00001000) | 0x00000010; 2323 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2324 } 2325 2326 /* set initial AGC value */ 2327 if (group == 0) { /* 2GHz band */ 2328 if (sc->mac_ver >= 0x3071) 2329 agc = 0x1c + sc->lna[0] * 2; 2330 else 2331 agc = 0x2e + sc->lna[0]; 2332 } else { /* 5GHz band */ 2333 if (sc->mac_ver == 0x3572) 2334 agc = 0x22 + (sc->lna[group] * 5) / 3; 2335 else 2336 agc = 0x32 + (sc->lna[group] * 5) / 3; 2337 } 2338 rt2860_mcu_bbp_write(sc, 66, agc); 2339 2340 DELAY(1000); 2341 } 2342 2343 static void 2344 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2345 { 2346 const struct rfprog *rfprog = rt2860_rf2850; 2347 uint32_t r2, r3, r4; 2348 int8_t txpow1, txpow2; 2349 u_int i; 2350 2351 /* find the settings for this channel (we know it exists) */ 2352 for (i = 0; rfprog[i].chan != chan; i++); 2353 2354 r2 = rfprog[i].r2; 2355 if (sc->ntxchains == 1) 2356 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2357 if (sc->nrxchains == 1) 2358 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2359 else if (sc->nrxchains == 2) 2360 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2361 2362 /* use Tx power values from EEPROM */ 2363 txpow1 = sc->txpow1[i]; 2364 txpow2 = sc->txpow2[i]; 2365 if (chan > 14) { 2366 if (txpow1 >= 0) 2367 txpow1 = txpow1 << 1 | 1; 2368 else 2369 txpow1 = (7 + txpow1) << 1; 2370 if (txpow2 >= 0) 2371 txpow2 = txpow2 << 1 | 1; 2372 else 2373 txpow2 = (7 + txpow2) << 1; 2374 } 2375 r3 = rfprog[i].r3 | txpow1 << 7; 2376 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2377 2378 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2379 rt2860_rf_write(sc, RT2860_RF2, r2); 2380 rt2860_rf_write(sc, RT2860_RF3, r3); 2381 rt2860_rf_write(sc, RT2860_RF4, r4); 2382 2383 DELAY(200); 2384 2385 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2386 rt2860_rf_write(sc, RT2860_RF2, r2); 2387 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2388 rt2860_rf_write(sc, RT2860_RF4, r4); 2389 2390 DELAY(200); 2391 2392 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2393 rt2860_rf_write(sc, RT2860_RF2, r2); 2394 rt2860_rf_write(sc, RT2860_RF3, r3); 2395 rt2860_rf_write(sc, RT2860_RF4, r4); 2396 } 2397 2398 static void 2399 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2400 { 2401 int8_t txpow1, txpow2; 2402 uint8_t rf; 2403 int i; 2404 2405 KASSERT(chan >= 1 && chan <= 14); /* RT3090 is 2GHz only */ 2406 2407 /* find the settings for this channel (we know it exists) */ 2408 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2409 2410 /* use Tx power values from EEPROM */ 2411 txpow1 = sc->txpow1[i]; 2412 txpow2 = sc->txpow2[i]; 2413 2414 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2415 rf = rt3090_rf_read(sc, 3); 2416 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2417 rt3090_rf_write(sc, 3, rf); 2418 rf = rt3090_rf_read(sc, 6); 2419 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2420 rt3090_rf_write(sc, 6, rf); 2421 2422 /* set Tx0 power */ 2423 rf = rt3090_rf_read(sc, 12); 2424 rf = (rf & ~0x1f) | txpow1; 2425 rt3090_rf_write(sc, 12, rf); 2426 2427 /* set Tx1 power */ 2428 rf = rt3090_rf_read(sc, 13); 2429 rf = (rf & ~0x1f) | txpow2; 2430 rt3090_rf_write(sc, 13, rf); 2431 2432 rf = rt3090_rf_read(sc, 1); 2433 rf &= ~0xfc; 2434 if (sc->ntxchains == 1) 2435 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2436 else if (sc->ntxchains == 2) 2437 rf |= RT3070_TX2_PD; 2438 if (sc->nrxchains == 1) 2439 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2440 else if (sc->nrxchains == 2) 2441 rf |= RT3070_RX2_PD; 2442 rt3090_rf_write(sc, 1, rf); 2443 2444 /* set RF offset */ 2445 rf = rt3090_rf_read(sc, 23); 2446 rf = (rf & ~0x7f) | sc->freq; 2447 rt3090_rf_write(sc, 23, rf); 2448 2449 /* program RF filter */ 2450 rf = rt3090_rf_read(sc, 24); /* Tx */ 2451 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2452 rt3090_rf_write(sc, 24, rf); 2453 rf = rt3090_rf_read(sc, 31); /* Rx */ 2454 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2455 rt3090_rf_write(sc, 31, rf); 2456 2457 /* enable RF tuning */ 2458 rf = rt3090_rf_read(sc, 7); 2459 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2460 } 2461 2462 static void 2463 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2464 { 2465 uint8_t h20mhz, rf, tmp; 2466 int8_t txpow1, txpow2; 2467 int i; 2468 2469 /* RT5390 is 2GHz only */ 2470 KASSERT(chan >= 1 && chan <= 14); 2471 2472 /* find the settings for this channel (we know it exists) */ 2473 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2474 2475 /* use Tx power values from EEPROM */ 2476 txpow1 = sc->txpow1[i]; 2477 txpow2 = sc->txpow2[i]; 2478 2479 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2480 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2481 rf = rt3090_rf_read(sc, 11); 2482 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2483 rt3090_rf_write(sc, 11, rf); 2484 2485 rf = rt3090_rf_read(sc, 49); 2486 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2487 /* the valid range of the RF R49 is 0x00~0x27 */ 2488 if ((rf & 0x3f) > 0x27) 2489 rf = (rf & ~0x3f) | 0x27; 2490 rt3090_rf_write(sc, 49, rf); 2491 if (sc->mac_ver == 0x5392) { 2492 rf = rt3090_rf_read(sc, 50); 2493 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2494 /* the valid range of the RF R50 is 0x00~0x27 */ 2495 if ((rf & 0x3f) > 0x27) 2496 rf = (rf & ~0x3f) | 0x27; 2497 rt3090_rf_write(sc, 50, rf); 2498 } 2499 2500 rf = rt3090_rf_read(sc, 1); 2501 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2502 if (sc->mac_ver == 0x5392) 2503 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2504 rt3090_rf_write(sc, 1, rf); 2505 2506 rf = rt3090_rf_read(sc, 2); 2507 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2508 DELAY(1000); 2509 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2510 2511 rf = rt3090_rf_read(sc, 17); 2512 tmp = rf; 2513 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2514 rf = MIN(rf, 0x5f); 2515 if (tmp != rf) 2516 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2517 2518 if (sc->mac_ver == 0x5390) { 2519 if (chan <= 4) 2520 rf = 0x73; 2521 else if (chan >= 5 && chan <= 6) 2522 rf = 0x63; 2523 else if (chan >= 7 && chan <= 10) 2524 rf = 0x53; 2525 else 2526 rf = 43; 2527 rt3090_rf_write(sc, 55, rf); 2528 2529 if (chan == 1) 2530 rf = 0x0c; 2531 else if (chan == 2) 2532 rf = 0x0b; 2533 else if (chan == 3) 2534 rf = 0x0a; 2535 else if (chan >= 4 && chan <= 6) 2536 rf = 0x09; 2537 else if (chan >= 7 && chan <= 12) 2538 rf = 0x08; 2539 else if (chan == 13) 2540 rf = 0x07; 2541 else 2542 rf = 0x06; 2543 rt3090_rf_write(sc, 59, rf); 2544 } 2545 2546 /* Tx/Rx h20M */ 2547 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2548 rf = rt3090_rf_read(sc, 30); 2549 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2550 rt3090_rf_write(sc, 30, rf); 2551 2552 /* Rx BB filter VCM */ 2553 rf = rt3090_rf_read(sc, 30); 2554 rf = (rf & ~0x18) | 0x10; 2555 rt3090_rf_write(sc, 30, rf); 2556 2557 /* Initiate VCO calibration. */ 2558 rf = rt3090_rf_read(sc, 3); 2559 rf |= RT3593_VCOCAL; 2560 rt3090_rf_write(sc, 3, rf); 2561 } 2562 2563 static void 2564 rt3090_rf_init(struct rt2860_softc *sc) 2565 { 2566 uint32_t tmp; 2567 uint8_t rf, bbp; 2568 int i; 2569 2570 rf = rt3090_rf_read(sc, 30); 2571 /* toggle RF R30 bit 7 */ 2572 rt3090_rf_write(sc, 30, rf | 0x80); 2573 DELAY(1000); 2574 rt3090_rf_write(sc, 30, rf & ~0x80); 2575 2576 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2577 tmp &= ~0x1f000000; 2578 if (sc->patch_dac && sc->mac_rev < 0x0211) 2579 tmp |= 0x0d000000; /* 1.35V */ 2580 else 2581 tmp |= 0x01000000; /* 1.2V */ 2582 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2583 2584 /* patch LNA_PE_G1 */ 2585 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2586 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2587 2588 /* initialize RF registers to default value */ 2589 if (sc->mac_ver == 0x3572) { 2590 for (i = 0; i < (int)__arraycount(rt3572_def_rf); i++) { 2591 rt3090_rf_write(sc, rt3572_def_rf[i].reg, 2592 rt3572_def_rf[i].val); 2593 } 2594 } else { 2595 for (i = 0; i < (int)__arraycount(rt3090_def_rf); i++) { 2596 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2597 rt3090_def_rf[i].val); 2598 } 2599 } 2600 2601 /* select 20MHz bandwidth */ 2602 rt3090_rf_write(sc, 31, 0x14); 2603 2604 rf = rt3090_rf_read(sc, 6); 2605 rt3090_rf_write(sc, 6, rf | 0x40); 2606 2607 if (sc->mac_ver != 0x3593) { 2608 /* calibrate filter for 20MHz bandwidth */ 2609 sc->rf24_20mhz = 0x1f; /* default value */ 2610 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2611 2612 /* select 40MHz bandwidth */ 2613 bbp = rt2860_mcu_bbp_read(sc, 4); 2614 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2615 rf = rt3090_rf_read(sc, 31); 2616 rt3090_rf_write(sc, 31, rf | 0x20); 2617 2618 /* calibrate filter for 40MHz bandwidth */ 2619 sc->rf24_40mhz = 0x2f; /* default value */ 2620 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2621 2622 /* go back to 20MHz bandwidth */ 2623 bbp = rt2860_mcu_bbp_read(sc, 4); 2624 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2625 } 2626 if (sc->mac_rev < 0x0211) 2627 rt3090_rf_write(sc, 27, 0x03); 2628 2629 tmp = RAL_READ(sc, RT3070_OPT_14); 2630 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2631 2632 if (sc->rf_rev == RT3070_RF_3020) 2633 rt3090_set_rx_antenna(sc, 0); 2634 2635 bbp = rt2860_mcu_bbp_read(sc, 138); 2636 if (sc->mac_ver == 0x3593) { 2637 if (sc->ntxchains == 1) 2638 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2639 else if (sc->ntxchains == 2) 2640 bbp |= 0x40; /* turn off DAC2 */ 2641 if (sc->nrxchains == 1) 2642 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2643 else if (sc->nrxchains == 2) 2644 bbp &= ~0x04; /* turn off ADC2 */ 2645 } else { 2646 if (sc->ntxchains == 1) 2647 bbp |= 0x20; /* turn off DAC1 */ 2648 if (sc->nrxchains == 1) 2649 bbp &= ~0x02; /* turn off ADC1 */ 2650 } 2651 rt2860_mcu_bbp_write(sc, 138, bbp); 2652 2653 rf = rt3090_rf_read(sc, 1); 2654 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2655 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2656 rt3090_rf_write(sc, 1, rf); 2657 2658 rf = rt3090_rf_read(sc, 15); 2659 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2660 2661 rf = rt3090_rf_read(sc, 17); 2662 rf &= ~RT3070_TX_LO1; 2663 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2664 rf |= 0x20; /* fix for long range Rx issue */ 2665 if (sc->txmixgain_2ghz >= 2) 2666 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2667 rt3090_rf_write(sc, 17, rf); 2668 2669 rf = rt3090_rf_read(sc, 20); 2670 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2671 2672 rf = rt3090_rf_read(sc, 21); 2673 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2674 } 2675 2676 static void 2677 rt5390_rf_init(struct rt2860_softc *sc) 2678 { 2679 uint8_t rf, bbp; 2680 int i; 2681 2682 rf = rt3090_rf_read(sc, 2); 2683 /* Toggle RF R2 bit 7. */ 2684 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2685 DELAY(1000); 2686 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2687 2688 /* Initialize RF registers to default value. */ 2689 if (sc->mac_ver == 0x5392) { 2690 for (i = 0; i < __arraycount(rt5392_def_rf); i++) { 2691 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2692 rt5392_def_rf[i].val); 2693 } 2694 } else { 2695 for (i = 0; i < __arraycount(rt5390_def_rf); i++) { 2696 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2697 rt5390_def_rf[i].val); 2698 } 2699 } 2700 2701 sc->rf24_20mhz = 0x1f; 2702 sc->rf24_40mhz = 0x2f; 2703 2704 if (sc->mac_rev < 0x0211) 2705 rt3090_rf_write(sc, 27, 0x03); 2706 2707 /* Set led open drain enable. */ 2708 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2709 2710 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2711 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2712 2713 if (sc->mac_ver == 0x5390) 2714 rt3090_set_rx_antenna(sc, 0); 2715 2716 /* Patch RSSI inaccurate issue. */ 2717 rt2860_mcu_bbp_write(sc, 79, 0x13); 2718 rt2860_mcu_bbp_write(sc, 80, 0x05); 2719 rt2860_mcu_bbp_write(sc, 81, 0x33); 2720 2721 /* Enable DC filter. */ 2722 if (sc->mac_rev >= 0x0211) 2723 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2724 2725 bbp = rt2860_mcu_bbp_read(sc, 138); 2726 if (sc->ntxchains == 1) 2727 bbp |= 0x20; /* Turn off DAC1. */ 2728 if (sc->nrxchains == 1) 2729 bbp &= ~0x02; /* Turn off ADC1. */ 2730 rt2860_mcu_bbp_write(sc, 138, bbp); 2731 2732 /* Enable RX LO1 and LO2. */ 2733 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2734 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2735 2736 /* Avoid data lost and CRC error. */ 2737 rt2860_mcu_bbp_write(sc, 4, 2738 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2739 2740 rf = rt3090_rf_read(sc, 30); 2741 rf = (rf & ~0x18) | 0x10; 2742 rt3090_rf_write(sc, 30, rf); 2743 } 2744 2745 static void 2746 rt3090_rf_wakeup(struct rt2860_softc *sc) 2747 { 2748 uint32_t tmp; 2749 uint8_t rf; 2750 2751 if (sc->mac_ver == 0x3593) { 2752 /* enable VCO */ 2753 rf = rt3090_rf_read(sc, 1); 2754 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2755 2756 /* initiate VCO calibration */ 2757 rf = rt3090_rf_read(sc, 3); 2758 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2759 2760 /* enable VCO bias current control */ 2761 rf = rt3090_rf_read(sc, 6); 2762 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2763 2764 /* initiate res calibration */ 2765 rf = rt3090_rf_read(sc, 2); 2766 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2767 2768 /* set reference current control to 0.33 mA */ 2769 rf = rt3090_rf_read(sc, 22); 2770 rf &= ~RT3593_CP_IC_MASK; 2771 rf |= 1 << RT3593_CP_IC_SHIFT; 2772 rt3090_rf_write(sc, 22, rf); 2773 2774 /* enable RX CTB */ 2775 rf = rt3090_rf_read(sc, 46); 2776 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2777 2778 rf = rt3090_rf_read(sc, 20); 2779 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2780 rt3090_rf_write(sc, 20, rf); 2781 } else { 2782 /* enable RF block */ 2783 rf = rt3090_rf_read(sc, 1); 2784 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2785 2786 /* enable VCO bias current control */ 2787 rf = rt3090_rf_read(sc, 7); 2788 rt3090_rf_write(sc, 7, rf | 0x30); 2789 2790 rf = rt3090_rf_read(sc, 9); 2791 rt3090_rf_write(sc, 9, rf | 0x0e); 2792 2793 /* enable RX CTB */ 2794 rf = rt3090_rf_read(sc, 21); 2795 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2796 2797 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2798 rf = rt3090_rf_read(sc, 27); 2799 rf &= ~0x77; 2800 if (sc->mac_rev < 0x0211) 2801 rf |= 0x03; 2802 rt3090_rf_write(sc, 27, rf); 2803 } 2804 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2805 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2806 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2807 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2808 } 2809 } 2810 2811 static void 2812 rt5390_rf_wakeup(struct rt2860_softc *sc) 2813 { 2814 uint32_t tmp; 2815 uint8_t rf; 2816 2817 rf = rt3090_rf_read(sc, 1); 2818 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2819 RT3070_TX0_PD; 2820 if (sc->mac_ver == 0x5392) 2821 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2822 rt3090_rf_write(sc, 1, rf); 2823 2824 rf = rt3090_rf_read(sc, 6); 2825 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2826 if (sc->mac_ver == 0x5390) 2827 rf &= ~RT3593_VCO_IC; 2828 rt3090_rf_write(sc, 6, rf); 2829 2830 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2831 2832 rf = rt3090_rf_read(sc, 22); 2833 rf = (rf & ~0xe0) | 0x20; 2834 rt3090_rf_write(sc, 22, rf); 2835 2836 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2837 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2838 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2839 2840 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2841 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2842 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2843 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2844 } 2845 } 2846 2847 static int 2848 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2849 uint8_t *val) 2850 { 2851 uint8_t rf22, rf24; 2852 uint8_t bbp55_pb, bbp55_sb, delta; 2853 int ntries; 2854 2855 /* program filter */ 2856 rf24 = rt3090_rf_read(sc, 24); 2857 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2858 rt3090_rf_write(sc, 24, rf24); 2859 2860 /* enable baseband loopback mode */ 2861 rf22 = rt3090_rf_read(sc, 22); 2862 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2863 2864 /* set power and frequency of passband test tone */ 2865 rt2860_mcu_bbp_write(sc, 24, 0x00); 2866 for (ntries = 0; ntries < 100; ntries++) { 2867 /* transmit test tone */ 2868 rt2860_mcu_bbp_write(sc, 25, 0x90); 2869 DELAY(1000); 2870 /* read received power */ 2871 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2872 if (bbp55_pb != 0) 2873 break; 2874 } 2875 if (ntries == 100) 2876 return ETIMEDOUT; 2877 2878 /* set power and frequency of stopband test tone */ 2879 rt2860_mcu_bbp_write(sc, 24, 0x06); 2880 for (ntries = 0; ntries < 100; ntries++) { 2881 /* transmit test tone */ 2882 rt2860_mcu_bbp_write(sc, 25, 0x90); 2883 DELAY(1000); 2884 /* read received power */ 2885 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2886 2887 delta = bbp55_pb - bbp55_sb; 2888 if (delta > target) 2889 break; 2890 2891 /* reprogram filter */ 2892 rf24++; 2893 rt3090_rf_write(sc, 24, rf24); 2894 } 2895 if (ntries < 100) { 2896 if (rf24 != init) 2897 rf24--; /* backtrack */ 2898 *val = rf24; 2899 rt3090_rf_write(sc, 24, rf24); 2900 } 2901 2902 /* restore initial state */ 2903 rt2860_mcu_bbp_write(sc, 24, 0x00); 2904 2905 /* disable baseband loopback mode */ 2906 rf22 = rt3090_rf_read(sc, 22); 2907 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2908 2909 return 0; 2910 } 2911 2912 static void 2913 rt3090_rf_setup(struct rt2860_softc *sc) 2914 { 2915 uint8_t bbp; 2916 int i; 2917 2918 if (sc->mac_rev >= 0x0211) { 2919 /* enable DC filter */ 2920 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2921 2922 /* improve power consumption */ 2923 bbp = rt2860_mcu_bbp_read(sc, 31); 2924 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2925 } 2926 2927 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2928 if (sc->mac_rev < 0x0211) { 2929 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2930 sc->patch_dac ? 0x2c : 0x0f); 2931 } else 2932 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2933 2934 /* initialize RF registers from ROM */ 2935 if (sc->mac_ver < 0x5390) { 2936 for (i = 0; i < 10; i++) { 2937 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 2938 continue; 2939 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 2940 } 2941 } 2942 } 2943 2944 static void 2945 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 2946 { 2947 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 2948 which | (sc->leds & 0x7f), 0); 2949 } 2950 2951 /* 2952 * Hardware has a general-purpose programmable timer interrupt that can 2953 * periodically raise MAC_INT_4. 2954 */ 2955 static void 2956 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 2957 { 2958 uint32_t tmp; 2959 2960 /* disable GP timer before reprogramming it */ 2961 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2962 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 2963 2964 if (ms == 0) 2965 return; 2966 2967 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 2968 ms *= 16; /* Unit: 64us */ 2969 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 2970 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 2971 2972 /* enable GP timer */ 2973 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2974 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 2975 } 2976 2977 static void 2978 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 2979 { 2980 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 2981 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 2982 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 2983 bssid[4] | bssid[5] << 8); 2984 } 2985 2986 static void 2987 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 2988 { 2989 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 2990 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2991 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 2992 addr[4] | addr[5] << 8 | 0xff << 16); 2993 } 2994 2995 static void 2996 rt2860_updateslot(struct ifnet *ifp) 2997 { 2998 struct rt2860_softc *sc = ifp->if_softc; 2999 struct ieee80211com *ic = &sc->sc_ic; 3000 uint32_t tmp; 3001 3002 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 3003 tmp &= ~0xff; 3004 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 3005 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3006 } 3007 3008 static void 3009 rt2860_updateprot(struct ieee80211com *ic) 3010 { 3011 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 3012 uint32_t tmp; 3013 3014 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3015 /* setup protection frame rate (MCS code) */ 3016 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 3017 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 3018 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3019 3020 /* CCK frames don't require protection */ 3021 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 3022 3023 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3024 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3025 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3026 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3027 tmp |= RT2860_PROT_CTRL_CTS; 3028 } 3029 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 3030 } 3031 3032 static void 3033 rt2860_update_promisc(struct ifnet *ifp) 3034 { 3035 struct rt2860_softc *sc = ifp->if_softc; 3036 uint32_t tmp; 3037 3038 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 3039 tmp &= ~RT2860_DROP_NOT_MYBSS; 3040 if (!(ifp->if_flags & IFF_PROMISC)) 3041 tmp |= RT2860_DROP_NOT_MYBSS; 3042 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3043 } 3044 3045 static int 3046 rt2860_updateedca(struct ieee80211com *ic) 3047 { 3048 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 3049 int aci; 3050 3051 /* update MAC TX configuration registers */ 3052 for (aci = 0; aci < WME_NUM_AC; aci++) { 3053 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 3054 ic->ic_wme.wme_params[aci].wmep_logcwmax << 16 | 3055 ic->ic_wme.wme_params[aci].wmep_logcwmin << 12 | 3056 ic->ic_wme.wme_params[aci].wmep_aifsn << 8 | 3057 ic->ic_wme.wme_params[aci].wmep_txopLimit); 3058 } 3059 3060 /* update SCH/DMA registers too */ 3061 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 3062 ic->ic_wme.wme_params[WME_AC_VO].wmep_aifsn << 12 | 3063 ic->ic_wme.wme_params[WME_AC_VI].wmep_aifsn << 8 | 3064 ic->ic_wme.wme_params[WME_AC_BK].wmep_aifsn << 4 | 3065 ic->ic_wme.wme_params[WME_AC_BE].wmep_aifsn); 3066 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 3067 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmin << 12 | 3068 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmin << 8 | 3069 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmin << 4 | 3070 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmin); 3071 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 3072 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmax << 12 | 3073 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmax << 8 | 3074 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmax << 4 | 3075 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmax); 3076 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 3077 ic->ic_wme.wme_params[WME_AC_BK].wmep_txopLimit << 16 | 3078 ic->ic_wme.wme_params[WME_AC_BE].wmep_txopLimit); 3079 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 3080 ic->ic_wme.wme_params[WME_AC_VO].wmep_txopLimit << 16 | 3081 ic->ic_wme.wme_params[WME_AC_VI].wmep_txopLimit); 3082 return 0; 3083 } 3084 3085 #ifdef HW_CRYPTO 3086 static int 3087 rt2860_set_key(struct ieee80211com *ic, const struct ieee80211_key *ck, 3088 const uint8_t *mac) 3089 { 3090 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 3091 struct ieee80211_node *ni = ic->ic_bss; 3092 bus_size_t base; 3093 uint32_t attr; 3094 uint8_t mode, wcid, iv[8]; 3095 struct ieee80211_key *k = __UNCONST(ck); /* XXX */ 3096 3097 DPRINTF(("%s: cipher %d\n", __func__, k->wk_cipher->ic_cipher)); 3098 /* defer setting of WEP keys until interface is brought up */ 3099 if ((ic->ic_ifp->if_flags & (IFF_UP | IFF_RUNNING)) != 3100 (IFF_UP | IFF_RUNNING)) { 3101 DPRINTF(("%s: not running %d\n", __func__, 3102 k->wk_cipher->ic_cipher)); 3103 return 1; 3104 } 3105 /* map net80211 cipher to RT2860 security mode */ 3106 switch (k->wk_cipher->ic_cipher) { 3107 case IEEE80211_CIPHER_WEP: 3108 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 3109 if (k->wk_keylen == 5) 3110 mode = RT2860_MODE_WEP40; 3111 else 3112 mode = RT2860_MODE_WEP104; 3113 break; 3114 case IEEE80211_CIPHER_TKIP: 3115 mode = RT2860_MODE_TKIP; 3116 break; 3117 case IEEE80211_CIPHER_AES_CCM: 3118 mode = RT2860_MODE_AES_CCMP; 3119 break; 3120 default: 3121 DPRINTF(("%s: bad\n", __func__)); 3122 return 0; 3123 } 3124 3125 if (k->wk_flags & IEEE80211_KEY_GROUP) { 3126 wcid = 0; /* NB: update WCID0 for group keys */ 3127 base = RT2860_SKEY(0, k->wk_keyix); 3128 } else { 3129 wcid = ((struct rt2860_node *)ni)->wcid; 3130 base = RT2860_PKEY(wcid); 3131 } 3132 3133 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 3134 RAL_WRITE_REGION_1(sc, base, k->wk_key, 16); 3135 #ifndef IEEE80211_STA_ONLY 3136 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3137 RAL_WRITE_REGION_1(sc, base + 16, &k->wk_key[16], 8); 3138 RAL_WRITE_REGION_1(sc, base + 24, &k->wk_key[24], 8); 3139 } else 3140 #endif 3141 { 3142 RAL_WRITE_REGION_1(sc, base + 16, &k->wk_key[24], 8); 3143 RAL_WRITE_REGION_1(sc, base + 24, &k->wk_key[16], 8); 3144 } 3145 } else 3146 RAL_WRITE_REGION_1(sc, base, k->wk_key, k->wk_keylen); 3147 3148 if (!(k->wk_flags & IEEE80211_KEY_GROUP) || 3149 (k->wk_flags & IEEE80211_KEY_XMIT)) { 3150 /* set initial packet number in IV+EIV */ 3151 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) { 3152 uint32_t val = cprng_fast32(); 3153 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3154 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3155 val += 0x000100; 3156 iv[0] = val; 3157 iv[1] = val >> 8; 3158 iv[2] = val >> 16; 3159 iv[3] = k->wk_keyix << 6; 3160 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3161 } else { 3162 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 3163 iv[0] = k->wk_keytsc >> 8; 3164 iv[1] = (iv[0] | 0x20) & 0x7f; 3165 iv[2] = k->wk_keytsc; 3166 } else /* CCMP */ { 3167 iv[0] = k->wk_keytsc; 3168 iv[1] = k->wk_keytsc >> 8; 3169 iv[2] = 0; 3170 } 3171 iv[3] = k->wk_keyix << 6 | IEEE80211_WEP_EXTIV; 3172 iv[4] = k->wk_keytsc >> 16; 3173 iv[5] = k->wk_keytsc >> 24; 3174 iv[6] = k->wk_keytsc >> 32; 3175 iv[7] = k->wk_keytsc >> 40; 3176 } 3177 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3178 } 3179 3180 if (k->wk_flags & IEEE80211_KEY_GROUP) { 3181 /* install group key */ 3182 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3183 attr &= ~(0xf << (k->wk_keyix * 4)); 3184 attr |= mode << (k->wk_keyix * 4); 3185 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3186 } else { 3187 /* install pairwise key */ 3188 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3189 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3190 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3191 } 3192 DPRINTF(("%s: ok\n", __func__)); 3193 return 1; 3194 } 3195 3196 static int 3197 rt2860_delete_key(struct ieee80211com *ic, const struct ieee80211_key *k) 3198 { 3199 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 3200 struct ieee80211_node *ni = ic->ic_bss; 3201 uint32_t attr; 3202 uint8_t wcid; 3203 3204 if (k->wk_flags & IEEE80211_KEY_GROUP) { 3205 /* remove group key */ 3206 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3207 attr &= ~(0xf << (k->wk_keyix * 4)); 3208 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3209 3210 } else { 3211 /* remove pairwise key */ 3212 wcid = ((struct rt2860_node *)ni)->wcid; 3213 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3214 attr &= ~0xf; 3215 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3216 } 3217 return 1; 3218 } 3219 #endif 3220 3221 static int8_t 3222 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3223 { 3224 struct ieee80211com *ic = &sc->sc_ic; 3225 struct ieee80211_channel *c = ic->ic_curchan; 3226 int delta; 3227 3228 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3229 u_int chan = ieee80211_chan2ieee(ic, c); 3230 delta = sc->rssi_5ghz[rxchain]; 3231 3232 /* determine channel group */ 3233 if (chan <= 64) 3234 delta -= sc->lna[1]; 3235 else if (chan <= 128) 3236 delta -= sc->lna[2]; 3237 else 3238 delta -= sc->lna[3]; 3239 } else 3240 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3241 3242 return -12 - delta - rssi; 3243 } 3244 3245 /* 3246 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3247 * Used to adjust per-rate Tx power registers. 3248 */ 3249 static __inline uint32_t 3250 b4inc(uint32_t b32, int8_t delta) 3251 { 3252 int8_t i, b4; 3253 3254 for (i = 0; i < 8; i++) { 3255 b4 = b32 & 0xf; 3256 b4 += delta; 3257 if (b4 < 0) 3258 b4 = 0; 3259 else if (b4 > 0xf) 3260 b4 = 0xf; 3261 b32 = b32 >> 4 | b4 << 28; 3262 } 3263 return b32; 3264 } 3265 3266 static const char * 3267 rt2860_get_rf(uint32_t rev) 3268 { 3269 switch (rev) { 3270 case RT2860_RF_2820: return "RT2820"; 3271 case RT2860_RF_2850: return "RT2850"; 3272 case RT2860_RF_2720: return "RT2720"; 3273 case RT2860_RF_2750: return "RT2750"; 3274 case RT3070_RF_3020: return "RT3020"; 3275 case RT3070_RF_2020: return "RT2020"; 3276 case RT3070_RF_3021: return "RT3021"; 3277 case RT3070_RF_3022: return "RT3022"; 3278 case RT3070_RF_3052: return "RT3052"; 3279 case RT3070_RF_3320: return "RT3320"; 3280 case RT3070_RF_3053: return "RT3053"; 3281 case RT5390_RF_5360: return "RT5360"; 3282 case RT5390_RF_5390: return "RT5390"; 3283 case RT5390_RF_5392: return "RT5392"; 3284 default: return "unknown"; 3285 } 3286 } 3287 3288 static int 3289 rt2860_read_eeprom(struct rt2860_softc *sc) 3290 { 3291 struct ieee80211com *ic = &sc->sc_ic; 3292 int8_t delta_2ghz, delta_5ghz; 3293 uint32_t tmp; 3294 uint16_t val; 3295 int ridx, ant, i; 3296 3297 /* check whether the ROM is eFUSE ROM or EEPROM */ 3298 sc->sc_srom_read = rt2860_eeprom_read_2; 3299 if (sc->mac_ver >= 0x3071) { 3300 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3301 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3302 if (tmp & RT3070_SEL_EFUSE) 3303 sc->sc_srom_read = rt3090_efuse_read_2; 3304 } 3305 3306 #ifdef RAL_DEBUG 3307 /* read EEPROM version */ 3308 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3309 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 3310 #endif 3311 3312 /* read MAC address */ 3313 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3314 ic->ic_myaddr[0] = val & 0xff; 3315 ic->ic_myaddr[1] = val >> 8; 3316 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3317 ic->ic_myaddr[2] = val & 0xff; 3318 ic->ic_myaddr[3] = val >> 8; 3319 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3320 ic->ic_myaddr[4] = val & 0xff; 3321 ic->ic_myaddr[5] = val >> 8; 3322 3323 #ifdef RAL_DEBUG 3324 /* read country code */ 3325 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3326 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3327 #endif 3328 3329 /* read vendor BBP settings */ 3330 for (i = 0; i < 8; i++) { 3331 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3332 sc->bbp[i].val = val & 0xff; 3333 sc->bbp[i].reg = val >> 8; 3334 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3335 } 3336 if (sc->mac_ver >= 0x3071) { 3337 /* read vendor RF settings */ 3338 for (i = 0; i < 10; i++) { 3339 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3340 sc->rf[i].val = val & 0xff; 3341 sc->rf[i].reg = val >> 8; 3342 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3343 sc->rf[i].val)); 3344 } 3345 } 3346 3347 /* read RF frequency offset from EEPROM */ 3348 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3349 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3350 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3351 if ((val >> 8) != 0xff) { 3352 /* read LEDs operating mode */ 3353 sc->leds = val >> 8; 3354 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3355 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3356 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3357 } else { 3358 /* broken EEPROM, use default settings */ 3359 sc->leds = 0x01; 3360 sc->led[0] = 0x5555; 3361 sc->led[1] = 0x2221; 3362 sc->led[2] = 0xa9f8; 3363 } 3364 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3365 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3366 3367 /* read RF information */ 3368 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3369 if (sc->mac_ver >= 0x5390) 3370 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); 3371 else 3372 sc->rf_rev = (val >> 8) & 0xf; 3373 sc->ntxchains = (val >> 4) & 0xf; 3374 sc->nrxchains = val & 0xf; 3375 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3376 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3377 3378 /* check if RF supports automatic Tx access gain control */ 3379 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3380 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3381 /* check if driver should patch the DAC issue */ 3382 if ((val >> 8) != 0xff) 3383 sc->patch_dac = (val >> 15) & 1; 3384 if ((val & 0xff) != 0xff) { 3385 sc->ext_5ghz_lna = (val >> 3) & 1; 3386 sc->ext_2ghz_lna = (val >> 2) & 1; 3387 /* check if RF supports automatic Tx access gain control */ 3388 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */ 3389 /* check if we have a hardware radio switch */ 3390 sc->rfswitch = val & 1; 3391 } 3392 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3393 /* read PCIe power save level */ 3394 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3395 if ((val & 0xff) != 0xff) { 3396 sc->pslevel = val & 0x3; 3397 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3398 if ((val & 0xff80) != 0x9280) 3399 sc->pslevel = MIN(sc->pslevel, 1); 3400 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3401 } 3402 } 3403 3404 /* read power settings for 2GHz channels */ 3405 for (i = 0; i < 14; i += 2) { 3406 val = rt2860_srom_read(sc, 3407 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3408 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3409 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3410 3411 if (sc->mac_ver != 0x5390) { 3412 val = rt2860_srom_read(sc, 3413 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3414 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3415 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3416 } 3417 } 3418 /* fix broken Tx power entries */ 3419 for (i = 0; i < 14; i++) { 3420 if (sc->txpow1[i] < 0 || 3421 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3422 sc->txpow1[i] = 5; 3423 if (sc->mac_ver != 0x5390) { 3424 if (sc->txpow2[i] < 0 || 3425 sc->txpow2[i] > ((sc->mac_ver >= 0x5392) ? 39 : 31)) 3426 sc->txpow2[i] = 5; 3427 } 3428 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3429 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3430 } 3431 /* read power settings for 5GHz channels */ 3432 for (i = 0; i < 40; i += 2) { 3433 val = rt2860_srom_read(sc, 3434 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3435 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3436 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3437 3438 val = rt2860_srom_read(sc, 3439 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3440 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3441 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3442 } 3443 /* fix broken Tx power entries */ 3444 for (i = 0; i < 40; i++) { 3445 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3446 sc->txpow1[14 + i] = 5; 3447 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3448 sc->txpow2[14 + i] = 5; 3449 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3450 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3451 sc->txpow2[14 + i])); 3452 } 3453 3454 /* read Tx power compensation for each Tx rate */ 3455 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3456 delta_2ghz = delta_5ghz = 0; 3457 if ((val & 0xff) != 0xff && (val & 0x80)) { 3458 delta_2ghz = val & 0xf; 3459 if (!(val & 0x40)) /* negative number */ 3460 delta_2ghz = -delta_2ghz; 3461 } 3462 val >>= 8; 3463 if ((val & 0xff) != 0xff && (val & 0x80)) { 3464 delta_5ghz = val & 0xf; 3465 if (!(val & 0x40)) /* negative number */ 3466 delta_5ghz = -delta_5ghz; 3467 } 3468 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3469 delta_2ghz, delta_5ghz)); 3470 3471 for (ridx = 0; ridx < 5; ridx++) { 3472 uint32_t reg; 3473 3474 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3475 reg = val; 3476 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3477 reg |= (uint32_t)val << 16; 3478 3479 sc->txpow20mhz[ridx] = reg; 3480 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3481 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3482 3483 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3484 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3485 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3486 } 3487 3488 /* read factory-calibrated samples for temperature compensation */ 3489 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3490 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3491 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3492 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3493 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3494 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3495 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3496 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3497 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3498 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3499 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3500 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3501 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3502 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3503 sc->step_2ghz = val >> 8; 3504 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3505 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3506 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3507 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3508 sc->tssi_2ghz[8], sc->step_2ghz)); 3509 /* check that ref value is correct, otherwise disable calibration */ 3510 if (sc->tssi_2ghz[4] == 0xff) 3511 sc->calib_2ghz = 0; 3512 3513 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3514 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3515 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3516 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3517 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3518 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3519 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3520 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3521 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3522 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3523 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3524 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3525 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3526 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3527 sc->step_5ghz = val >> 8; 3528 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3529 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3530 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3531 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3532 sc->tssi_5ghz[8], sc->step_5ghz)); 3533 /* check that ref value is correct, otherwise disable calibration */ 3534 if (sc->tssi_5ghz[4] == 0xff) 3535 sc->calib_5ghz = 0; 3536 3537 /* read RSSI offsets and LNA gains from EEPROM */ 3538 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3539 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3540 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3541 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3542 if (sc->mac_ver >= 0x3071) { 3543 /* 3544 * On RT3090 chips (limited to 2 Rx chains), this ROM 3545 * field contains the Tx mixer gain for the 2GHz band. 3546 */ 3547 if ((val & 0xff) != 0xff) 3548 sc->txmixgain_2ghz = val & 0x7; 3549 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3550 } else 3551 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3552 sc->lna[2] = val >> 8; /* channel group 2 */ 3553 3554 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3555 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3556 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3557 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3558 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3559 sc->lna[3] = val >> 8; /* channel group 3 */ 3560 3561 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3562 if (sc->mac_ver >= 0x3071) 3563 sc->lna[0] = RT3090_DEF_LNA; 3564 else /* channel group 0 */ 3565 sc->lna[0] = val & 0xff; 3566 sc->lna[1] = val >> 8; /* channel group 1 */ 3567 3568 /* fix broken 5GHz LNA entries */ 3569 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3570 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3571 sc->lna[2] = sc->lna[1]; 3572 } 3573 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3574 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3575 sc->lna[3] = sc->lna[1]; 3576 } 3577 3578 /* fix broken RSSI offset entries */ 3579 for (ant = 0; ant < 3; ant++) { 3580 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3581 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3582 ant + 1, sc->rssi_2ghz[ant])); 3583 sc->rssi_2ghz[ant] = 0; 3584 } 3585 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3586 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3587 ant + 1, sc->rssi_5ghz[ant])); 3588 sc->rssi_5ghz[ant] = 0; 3589 } 3590 } 3591 3592 return 0; 3593 } 3594 3595 static int 3596 rt2860_bbp_init(struct rt2860_softc *sc) 3597 { 3598 int i, ntries; 3599 3600 /* wait for BBP to wake up */ 3601 for (ntries = 0; ntries < 20; ntries++) { 3602 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3603 if (bbp0 != 0 && bbp0 != 0xff) 3604 break; 3605 } 3606 if (ntries == 20) { 3607 aprint_error_dev(sc->sc_dev, 3608 "timeout waiting for BBP to wake up\n"); 3609 return ETIMEDOUT; 3610 } 3611 3612 /* initialize BBP registers to default values */ 3613 if (sc->mac_ver >= 0x5390) 3614 rt5390_bbp_init(sc); 3615 else { 3616 for (i = 0; i < (int)__arraycount(rt2860_def_bbp); i++) { 3617 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3618 rt2860_def_bbp[i].val); 3619 } 3620 } 3621 3622 /* fix BBP84 for RT2860E */ 3623 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3624 rt2860_mcu_bbp_write(sc, 84, 0x19); 3625 3626 if (sc->mac_ver >= 0x3071) { 3627 rt2860_mcu_bbp_write(sc, 79, 0x13); 3628 rt2860_mcu_bbp_write(sc, 80, 0x05); 3629 rt2860_mcu_bbp_write(sc, 81, 0x33); 3630 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3631 rt2860_mcu_bbp_write(sc, 69, 0x16); 3632 rt2860_mcu_bbp_write(sc, 73, 0x12); 3633 } 3634 3635 return 0; 3636 } 3637 3638 static int 3639 rt5390_bbp_init(struct rt2860_softc *sc) 3640 { 3641 uint8_t bbp; 3642 int i; 3643 3644 /* Apply maximum likelihood detection for 2 stream case. */ 3645 if (sc->nrxchains > 1) { 3646 bbp = rt2860_mcu_bbp_read(sc, 105); 3647 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3648 } 3649 3650 /* Avoid data lost and CRC error. */ 3651 bbp = rt2860_mcu_bbp_read(sc, 4); 3652 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3653 3654 for (i = 0; i < __arraycount(rt5390_def_bbp); i++) { 3655 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3656 rt5390_def_bbp[i].val); 3657 } 3658 3659 if (sc->mac_ver == 0x5392) { 3660 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3661 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3662 rt2860_mcu_bbp_write(sc, 98, 0x12); 3663 rt2860_mcu_bbp_write(sc, 106, 0x05); 3664 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3665 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3666 } 3667 3668 bbp = rt2860_mcu_bbp_read(sc, 152); 3669 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3670 3671 /* Disable hardware antenna diversity. */ 3672 if (sc->mac_ver == 0x5390) 3673 rt2860_mcu_bbp_write(sc, 154, 0); 3674 3675 return 0; 3676 } 3677 3678 static int 3679 rt2860_txrx_enable(struct rt2860_softc *sc) 3680 { 3681 uint32_t tmp; 3682 int ntries; 3683 3684 /* enable Tx/Rx DMA engine */ 3685 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3686 RAL_BARRIER_READ_WRITE(sc); 3687 for (ntries = 0; ntries < 200; ntries++) { 3688 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3689 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3690 break; 3691 DELAY(1000); 3692 } 3693 if (ntries == 200) { 3694 aprint_error_dev(sc->sc_dev, 3695 "timeout waiting for DMA engine\n"); 3696 return ETIMEDOUT; 3697 } 3698 3699 DELAY(50); 3700 3701 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3702 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3703 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3704 3705 /* set Rx filter */ 3706 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3707 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 3708 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3709 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3710 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3711 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3712 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 3713 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3714 } 3715 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3716 3717 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3718 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3719 3720 return 0; 3721 } 3722 3723 static int 3724 rt2860_init(struct ifnet *ifp) 3725 { 3726 struct rt2860_softc *sc = ifp->if_softc; 3727 struct ieee80211com *ic = &sc->sc_ic; 3728 uint32_t tmp; 3729 uint8_t bbp1, bbp3; 3730 int i, qid, ridx, ntries, error; 3731 3732 /* for CardBus, power on the socket */ 3733 if (!(sc->sc_flags & RT2860_ENABLED)) { 3734 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 3735 aprint_error_dev(sc->sc_dev, 3736 "could not enable device\n"); 3737 return EIO; 3738 } 3739 sc->sc_flags |= RT2860_ENABLED; 3740 } 3741 3742 if (sc->rfswitch) { 3743 /* hardware has a radio switch on GPIO pin 2 */ 3744 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3745 aprint_normal_dev(sc->sc_dev, 3746 "radio is disabled by hardware switch\n"); 3747 #ifdef notyet 3748 rt2860_stop(ifp, 1); 3749 return EPERM; 3750 #endif 3751 } 3752 } 3753 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3754 3755 /* disable DMA */ 3756 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3757 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3758 RT2860_TX_DMA_EN); 3759 tmp |= RT2860_TX_WB_DDONE; 3760 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3761 3762 /* reset DMA indexes */ 3763 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, RT2860_RST_DRX_IDX0 | 3764 RT2860_RST_DTX_IDX5 | RT2860_RST_DTX_IDX4 | RT2860_RST_DTX_IDX3 | 3765 RT2860_RST_DTX_IDX2 | RT2860_RST_DTX_IDX1 | RT2860_RST_DTX_IDX0); 3766 3767 /* PBF hardware reset */ 3768 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3769 RAL_BARRIER_WRITE(sc); 3770 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3771 3772 if ((error = rt2860_load_microcode(sc)) != 0) { 3773 aprint_error_dev(sc->sc_dev, 3774 "could not load 8051 microcode\n"); 3775 rt2860_stop(ifp, 1); 3776 return error; 3777 } 3778 3779 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3780 rt2860_set_macaddr(sc, ic->ic_myaddr); 3781 3782 /* init Tx power for all Tx rates (from EEPROM) */ 3783 for (ridx = 0; ridx < 5; ridx++) { 3784 if (sc->txpow20mhz[ridx] == 0xffffffff) 3785 continue; 3786 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3787 } 3788 3789 for (ntries = 0; ntries < 100; ntries++) { 3790 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3791 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3792 break; 3793 DELAY(1000); 3794 } 3795 if (ntries == 100) { 3796 aprint_error_dev(sc->sc_dev, 3797 "timeout waiting for DMA engine\n"); 3798 rt2860_stop(ifp, 1); 3799 return ETIMEDOUT; 3800 } 3801 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3802 RT2860_TX_DMA_EN); 3803 tmp |= RT2860_TX_WB_DDONE; 3804 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3805 3806 /* reset Rx ring and all 6 Tx rings */ 3807 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3808 3809 /* PBF hardware reset */ 3810 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3811 RAL_BARRIER_WRITE(sc); 3812 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3813 3814 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3815 3816 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3817 RAL_BARRIER_WRITE(sc); 3818 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3819 3820 for (i = 0; i < (int)__arraycount(rt2860_def_mac); i++) 3821 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3822 if (sc->mac_ver >= 0x5390) 3823 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3824 else if (sc->mac_ver >= 0x3071) { 3825 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3826 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3827 4 << RT2860_DLY_PAPE_EN_SHIFT); 3828 } 3829 3830 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3831 sc->sc_flags |= RT2860_PCIE; 3832 /* PCIe has different clock cycle count than PCI */ 3833 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3834 tmp = (tmp & ~0xff) | 0x7d; 3835 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3836 } 3837 3838 /* wait while MAC is busy */ 3839 for (ntries = 0; ntries < 100; ntries++) { 3840 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3841 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3842 break; 3843 DELAY(1000); 3844 } 3845 if (ntries == 100) { 3846 aprint_error_dev(sc->sc_dev, "timeout waiting for MAC\n"); 3847 rt2860_stop(ifp, 1); 3848 return ETIMEDOUT; 3849 } 3850 3851 /* clear Host to MCU mailbox */ 3852 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3853 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3854 3855 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3856 DELAY(1000); 3857 3858 if ((error = rt2860_bbp_init(sc)) != 0) { 3859 rt2860_stop(ifp, 1); 3860 return error; 3861 } 3862 3863 /* clear RX WCID search table */ 3864 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3865 /* clear pairwise key table */ 3866 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3867 /* clear IV/EIV table */ 3868 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3869 /* clear WCID attribute table */ 3870 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3871 /* clear shared key table */ 3872 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3873 /* clear shared key mode */ 3874 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3875 3876 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3877 for (qid = 0; qid < MAXQS; qid++) { 3878 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3879 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3880 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3881 } 3882 3883 /* init Rx ring */ 3884 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3885 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3886 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3887 3888 /* setup maximum buffer sizes */ 3889 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3890 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3891 3892 for (ntries = 0; ntries < 100; ntries++) { 3893 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3894 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3895 break; 3896 DELAY(1000); 3897 } 3898 if (ntries == 100) { 3899 aprint_error_dev(sc->sc_dev, 3900 "timeout waiting for DMA engine\n"); 3901 rt2860_stop(ifp, 1); 3902 return ETIMEDOUT; 3903 } 3904 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3905 RT2860_TX_DMA_EN); 3906 tmp |= RT2860_TX_WB_DDONE; 3907 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3908 3909 /* disable interrupts mitigation */ 3910 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3911 3912 /* write vendor-specific BBP values (from EEPROM) */ 3913 for (i = 0; i < 8; i++) { 3914 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3915 continue; 3916 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3917 } 3918 3919 /* select Main antenna for 1T1R devices */ 3920 if (sc->rf_rev == RT3070_RF_2020 || 3921 sc->rf_rev == RT3070_RF_3020 || 3922 sc->rf_rev == RT3070_RF_3320 || 3923 sc->rf_rev == RT5390_RF_5390) 3924 rt3090_set_rx_antenna(sc, 0); 3925 3926 /* send LEDs operating mode to microcontroller */ 3927 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3928 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3929 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3930 3931 if (sc->mac_ver >= 0x5390) 3932 rt5390_rf_init(sc); 3933 else if (sc->mac_ver >= 0x3071) 3934 rt3090_rf_init(sc); 3935 3936 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 3937 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 3938 3939 if (sc->mac_ver >= 0x5390) 3940 rt5390_rf_wakeup(sc); 3941 else if (sc->mac_ver >= 0x3071) 3942 rt3090_rf_wakeup(sc); 3943 3944 /* disable non-existing Rx chains */ 3945 bbp3 = rt2860_mcu_bbp_read(sc, 3); 3946 bbp3 &= ~(1 << 3 | 1 << 4); 3947 if (sc->nrxchains == 2) 3948 bbp3 |= 1 << 3; 3949 else if (sc->nrxchains == 3) 3950 bbp3 |= 1 << 4; 3951 rt2860_mcu_bbp_write(sc, 3, bbp3); 3952 3953 /* disable non-existing Tx chains */ 3954 bbp1 = rt2860_mcu_bbp_read(sc, 1); 3955 if (sc->ntxchains == 1) 3956 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 3957 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 3958 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 3959 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 3960 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 3961 rt2860_mcu_bbp_write(sc, 1, bbp1); 3962 3963 if (sc->mac_ver >= 0x3071) 3964 rt3090_rf_setup(sc); 3965 3966 /* select default channel */ 3967 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 3968 rt2860_switch_chan(sc, ic->ic_ibss_chan); 3969 3970 /* reset RF from MCU */ 3971 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3972 3973 /* set RTS threshold */ 3974 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 3975 tmp &= ~0xffff00; 3976 tmp |= ic->ic_rtsthreshold << 8; 3977 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 3978 3979 /* setup initial protection mode */ 3980 sc->sc_ic_flags = ic->ic_flags; 3981 rt2860_updateprot(ic); 3982 3983 /* turn radio LED on */ 3984 rt2860_set_leds(sc, RT2860_LED_RADIO); 3985 3986 /* enable Tx/Rx DMA engine */ 3987 if ((error = rt2860_txrx_enable(sc)) != 0) { 3988 rt2860_stop(ifp, 1); 3989 return error; 3990 } 3991 3992 /* clear pending interrupts */ 3993 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 3994 /* enable interrupts */ 3995 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 3996 3997 if (sc->sc_flags & RT2860_ADVANCED_PS) 3998 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 3999 4000 ifp->if_flags |= IFF_RUNNING; 4001 ifp->if_flags &= ~IFF_OACTIVE; 4002 4003 if (ic->ic_opmode != IEEE80211_M_MONITOR) 4004 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4005 else 4006 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4007 4008 return 0; 4009 } 4010 4011 static void 4012 rt2860_stop(struct ifnet *ifp, int disable) 4013 { 4014 struct rt2860_softc *sc = ifp->if_softc; 4015 struct ieee80211com *ic = &sc->sc_ic; 4016 uint32_t tmp; 4017 int qid; 4018 4019 if (ifp->if_flags & IFF_RUNNING) 4020 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 4021 4022 sc->sc_tx_timer = 0; 4023 ifp->if_timer = 0; 4024 ifp->if_flags &= ~IFF_RUNNING; 4025 ifp->if_flags &= ~IFF_OACTIVE; 4026 4027 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 4028 4029 /* disable interrupts */ 4030 RAL_WRITE(sc, RT2860_INT_MASK, 0); 4031 4032 /* disable GP timer */ 4033 rt2860_set_gp_timer(sc, 0); 4034 4035 /* disable Rx */ 4036 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 4037 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4038 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 4039 4040 /* reset adapter */ 4041 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4042 RAL_BARRIER_WRITE(sc); 4043 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 4044 4045 /* reset Tx and Rx rings (and reclaim TXWIs) */ 4046 sc->qfullmsk = 0; 4047 for (qid = 0; qid < MAXQS; qid++) 4048 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 4049 rt2860_reset_rx_ring(sc, &sc->rxq); 4050 4051 /* for CardBus, power down the socket */ 4052 if (disable && sc->sc_disable != NULL) { 4053 if (sc->sc_flags & RT2860_ENABLED) { 4054 (*sc->sc_disable)(sc); 4055 sc->sc_flags &= ~RT2860_ENABLED; 4056 } 4057 } 4058 } 4059 4060 static int 4061 rt2860_load_microcode(struct rt2860_softc *sc) 4062 { 4063 int ntries; 4064 4065 /* set "host program ram write selection" bit */ 4066 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4067 /* write microcode image */ 4068 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, sc->ucode, sc->ucsize); 4069 /* kick microcontroller unit */ 4070 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4071 RAL_BARRIER_WRITE(sc); 4072 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4073 4074 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4075 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4076 4077 /* wait until microcontroller is ready */ 4078 RAL_BARRIER_READ_WRITE(sc); 4079 for (ntries = 0; ntries < 1000; ntries++) { 4080 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4081 break; 4082 DELAY(1000); 4083 } 4084 if (ntries == 1000) { 4085 aprint_error_dev(sc->sc_dev, 4086 "timeout waiting for MCU to initialize\n"); 4087 return ETIMEDOUT; 4088 } 4089 return 0; 4090 } 4091 4092 #if 0 4093 /* 4094 * This function is called periodically to adjust Tx power based on 4095 * temperature variation. 4096 */ 4097 static void 4098 rt2860_calib(struct rt2860_softc *sc) 4099 { 4100 struct ieee80211com *ic = &sc->sc_ic; 4101 const uint8_t *tssi; 4102 uint8_t step, bbp49; 4103 int8_t ridx, d; 4104 4105 /* read current temperature */ 4106 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4107 4108 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4109 tssi = &sc->tssi_2ghz[4]; 4110 step = sc->step_2ghz; 4111 } else { 4112 tssi = &sc->tssi_5ghz[4]; 4113 step = sc->step_5ghz; 4114 } 4115 4116 if (bbp49 < tssi[0]) { /* lower than reference */ 4117 /* use higher Tx power than default */ 4118 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4119 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4120 /* use lower Tx power than default */ 4121 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4122 } else { 4123 /* use default Tx power */ 4124 d = 0; 4125 } 4126 d *= step; 4127 4128 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4129 4130 /* write adjusted Tx power values for each Tx rate */ 4131 for (ridx = 0; ridx < 5; ridx++) { 4132 if (sc->txpow20mhz[ridx] == 0xffffffff) 4133 continue; 4134 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4135 b4inc(sc->txpow20mhz[ridx], d)); 4136 } 4137 } 4138 #endif /* 0 */ 4139 4140 static void 4141 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4142 { 4143 uint32_t tmp; 4144 4145 if (aux) { 4146 if (sc->mac_ver == 0x5390) { 4147 rt2860_mcu_bbp_write(sc, 152, 4148 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4149 } else { 4150 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4151 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 4152 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4153 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 4154 } 4155 } else { 4156 if (sc->mac_ver == 0x5390) { 4157 rt2860_mcu_bbp_write(sc, 152, 4158 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4159 } else { 4160 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4161 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4162 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4163 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4164 } 4165 } 4166 } 4167 4168 static void 4169 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4170 { 4171 struct ieee80211com *ic = &sc->sc_ic; 4172 u_int chan, group; 4173 4174 chan = ieee80211_chan2ieee(ic, c); 4175 DPRINTF(("switch channel %u\n", chan)); 4176 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4177 return; 4178 4179 if (sc->mac_ver >= 0x5390) 4180 rt5390_set_chan(sc, chan); 4181 else if (sc->mac_ver >= 0x3071) 4182 rt3090_set_chan(sc, chan); 4183 else 4184 rt2860_set_chan(sc, chan); 4185 4186 /* determine channel group */ 4187 if (chan <= 14) 4188 group = 0; 4189 else if (chan <= 64) 4190 group = 1; 4191 else if (chan <= 128) 4192 group = 2; 4193 else 4194 group = 3; 4195 4196 /* XXX necessary only when group has changed! */ 4197 if (sc->mac_ver < 0x5390) 4198 rt2860_select_chan_group(sc, group); 4199 4200 DELAY(1000); 4201 } 4202 4203 #ifndef IEEE80211_STA_ONLY 4204 static int 4205 rt2860_setup_beacon(struct rt2860_softc *sc) 4206 { 4207 struct ieee80211com *ic = &sc->sc_ic; 4208 struct rt2860_txwi txwi; 4209 struct mbuf *m; 4210 int ridx; 4211 4212 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss, &sc->sc_bo)) == NULL) 4213 return ENOBUFS; 4214 4215 memset(&txwi, 0, sizeof txwi); 4216 txwi.wcid = 0xff; 4217 txwi.len = htole16(m->m_pkthdr.len); 4218 /* send beacons at the lowest available rate */ 4219 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 4220 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4221 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4222 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4223 txwi.phy |= htole16(RT2860_PHY_OFDM); 4224 txwi.txop = RT2860_TX_TXOP_HT; 4225 txwi.flags = RT2860_TX_TS; 4226 txwi.xflags = RT2860_TX_NSEQ; 4227 4228 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4229 (uint8_t *)&txwi, sizeof txwi); 4230 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4231 mtod(m, uint8_t *), m->m_pkthdr.len); 4232 4233 m_freem(m); 4234 4235 return 0; 4236 } 4237 #endif 4238 4239 static void 4240 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4241 { 4242 struct ieee80211com *ic = &sc->sc_ic; 4243 uint32_t tmp; 4244 4245 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4246 4247 tmp &= ~0x1fffff; 4248 tmp |= ic->ic_bss->ni_intval * 16; 4249 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4250 if (ic->ic_opmode == IEEE80211_M_STA) { 4251 /* 4252 * Local TSF is always updated with remote TSF on beacon 4253 * reception. 4254 */ 4255 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4256 } 4257 #ifndef IEEE80211_STA_ONLY 4258 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 4259 tmp |= RT2860_BCN_TX_EN; 4260 /* 4261 * Local TSF is updated with remote TSF on beacon reception 4262 * only if the remote TSF is greater than local TSF. 4263 */ 4264 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4265 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4266 tmp |= RT2860_BCN_TX_EN; 4267 /* SYNC with nobody */ 4268 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4269 } 4270 #endif 4271 4272 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4273 } 4274