1 /* $NetBSD: rt2860.c,v 1.35 2020/01/29 15:06:12 thorpej Exp $ */ 2 /* $OpenBSD: rt2860.c,v 1.90 2016/04/13 10:49:26 mpi Exp $ */ 3 /* $FreeBSD: head/sys/dev/ral/rt2860.c 306591 2016-10-02 20:35:55Z avos $ */ 4 5 /*- 6 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 7 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 24 * http://www.ralinktech.com/ 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: rt2860.c,v 1.35 2020/01/29 15:06:12 thorpej Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/sockio.h> 32 #include <sys/sysctl.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/queue.h> 39 #include <sys/callout.h> 40 #include <sys/module.h> 41 #include <sys/conf.h> 42 #include <sys/device.h> 43 #include <sys/endian.h> 44 #include <sys/cprng.h> 45 46 #include <sys/bus.h> 47 #include <sys/intr.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_ether.h> 53 #include <net/if_media.h> 54 55 #include <net80211/ieee80211_var.h> 56 #include <net80211/ieee80211_amrr.h> 57 #include <net80211/ieee80211_radiotap.h> 58 59 #include <dev/firmload.h> 60 61 #include <dev/ic/rt2860var.h> 62 #include <dev/ic/rt2860reg.h> 63 64 #include <dev/pci/pcidevs.h> 65 66 #ifdef RAL_DEBUG 67 #define DPRINTF(x) do { if (rt2860_debug > 0) printf x; } while (0) 68 #define DPRINTFN(n, x) do { if (rt2860_debug >= (n)) printf x; } while (0) 69 int rt2860_debug = 0; 70 #else 71 #define DPRINTF(x) 72 #define DPRINTFN(n, x) 73 #endif 74 #define MAXQS 6 /* Tx (4 EDCAs + HCCA + Mgt) and Rx rings */ 75 76 static void rt2860_attachhook(device_t); 77 static bool rt2860_suspend(device_t self, const pmf_qual_t *qual); 78 static bool rt2860_wakeup(device_t self, const pmf_qual_t *qual); 79 static int rt2860_alloc_tx_ring(struct rt2860_softc *, 80 struct rt2860_tx_ring *); 81 static void rt2860_reset_tx_ring(struct rt2860_softc *, 82 struct rt2860_tx_ring *); 83 static void rt2860_free_tx_ring(struct rt2860_softc *, 84 struct rt2860_tx_ring *); 85 static int rt2860_alloc_tx_pool(struct rt2860_softc *); 86 static void rt2860_free_tx_pool(struct rt2860_softc *); 87 static int rt2860_alloc_rx_ring(struct rt2860_softc *, 88 struct rt2860_rx_ring *); 89 static void rt2860_reset_rx_ring(struct rt2860_softc *, 90 struct rt2860_rx_ring *); 91 static void rt2860_free_rx_ring(struct rt2860_softc *, 92 struct rt2860_rx_ring *); 93 static struct ieee80211_node *rt2860_node_alloc(struct ieee80211_node_table *); 94 static int rt2860_media_change(struct ifnet *); 95 static void rt2860_iter_func(void *, struct ieee80211_node *); 96 static void rt2860_updatestats(struct rt2860_softc *); 97 static void rt2860_update_promisc(struct ifnet *); 98 static void rt2860_newassoc(struct ieee80211_node *, 99 int); 100 #ifdef notyet 101 static int rt2860_ampdu_rx_start(struct ieee80211com *, 102 struct ieee80211_node *, uint8_t); 103 static void rt2860_ampdu_rx_stop(struct ieee80211com *, 104 struct ieee80211_node *, uint8_t); 105 #endif 106 static int rt2860_newstate(struct ieee80211com *, enum ieee80211_state, 107 int); 108 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 109 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 110 static void rt2860_intr_coherent(struct rt2860_softc *); 111 static void rt2860_drain_stats_fifo(struct rt2860_softc *); 112 static void rt2860_tx_intr(struct rt2860_softc *, int); 113 static void rt2860_rx_intr(struct rt2860_softc *); 114 static void rt2860_tbtt_intr(struct rt2860_softc *); 115 static void rt2860_gp_intr(struct rt2860_softc *); 116 static int rt2860_tx(struct rt2860_softc *, struct mbuf **, 117 struct ieee80211_node *); 118 static void rt2860_start(struct ifnet *); 119 static void rt2860_watchdog(struct ifnet *); 120 static int rt2860_ioctl(struct ifnet *, u_long, void *); 121 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 122 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 123 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 124 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 125 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 126 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 127 static void rt2860_enable_mrr(struct rt2860_softc *); 128 static void rt2860_set_txpreamble(struct rt2860_softc *); 129 static void rt2860_set_basicrates(struct rt2860_softc *); 130 static void rt2860_select_chan_group(struct rt2860_softc *, int); 131 static void rt2860_set_chan(struct rt2860_softc *, u_int); 132 static void rt3090_set_chan(struct rt2860_softc *, u_int); 133 static void rt5390_set_chan(struct rt2860_softc *, u_int); 134 static void rt3090_rf_init(struct rt2860_softc *); 135 static void rt5390_rf_init(struct rt2860_softc *); 136 static void rt3090_rf_wakeup(struct rt2860_softc *); 137 static void rt5390_rf_wakeup(struct rt2860_softc *); 138 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 139 uint8_t *); 140 static void rt3090_rf_setup(struct rt2860_softc *); 141 static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 142 static void rt2860_set_gp_timer(struct rt2860_softc *, int); 143 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 144 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 145 static void rt2860_updateslot(struct ifnet *); 146 static void rt2860_updateprot(struct ieee80211com *); 147 static int rt2860_updateedca(struct ieee80211com *); 148 149 #ifdef HW_CRYPTO 150 static int rt2860_set_key(struct ieee80211com *, 151 const struct ieee80211_key *, const uint8_t *); 152 static int rt2860_delete_key(struct ieee80211com *, 153 const struct ieee80211_key *); 154 #endif 155 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 156 static const char * rt2860_get_rf(uint32_t); 157 static int rt2860_read_eeprom(struct rt2860_softc *); 158 static int rt2860_bbp_init(struct rt2860_softc *); 159 static int rt5390_bbp_init(struct rt2860_softc *); 160 static int rt2860_txrx_enable(struct rt2860_softc *); 161 static int rt2860_init(struct ifnet *); 162 static void rt2860_stop(struct ifnet *, int); 163 static int rt2860_load_microcode(struct rt2860_softc *); 164 #if 0 165 static void rt2860_calib(struct rt2860_softc *); 166 #endif 167 static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 168 static void rt2860_switch_chan(struct rt2860_softc *, 169 struct ieee80211_channel *); 170 #ifndef IEEE80211_STA_ONLY 171 static int rt2860_setup_beacon(struct rt2860_softc *); 172 #endif 173 static void rt2860_enable_tsf_sync(struct rt2860_softc *); 174 static void rt2860_softintr(void *); 175 176 static const struct { 177 uint32_t reg; 178 uint32_t val; 179 } rt2860_def_mac[] = { 180 RT2860_DEF_MAC 181 }; 182 183 static const struct { 184 uint8_t reg; 185 uint8_t val; 186 } rt2860_def_bbp[] = { 187 RT2860_DEF_BBP 188 }, rt5390_def_bbp[] = { 189 RT5390_DEF_BBP 190 }; 191 192 static const struct rfprog { 193 uint8_t chan; 194 uint32_t r1, r2, r3, r4; 195 } rt2860_rf2850[] = { 196 RT2860_RF2850 197 }; 198 199 static const struct { 200 uint8_t n, r, k; 201 } rt3090_freqs[] = { 202 RT3070_RF3052 203 }; 204 205 static const struct { 206 uint8_t reg; 207 uint8_t val; 208 } rt3090_def_rf[] = { 209 RT3070_DEF_RF 210 }, rt3572_def_rf[] = { 211 RT3572_DEF_RF 212 }, rt5390_def_rf[] = { 213 RT5390_DEF_RF 214 }, rt5392_def_rf[] = { 215 RT5392_DEF_RF 216 }; 217 218 int 219 rt2860_attach(void *xsc, int id) 220 { 221 struct rt2860_softc *sc = xsc; 222 struct ieee80211com *ic = &sc->sc_ic; 223 int qid, ntries, error; 224 uint32_t tmp; 225 226 sc->amrr.amrr_min_success_threshold = 1; 227 sc->amrr.amrr_max_success_threshold = 15; 228 229 /* wait for NIC to initialize */ 230 for (ntries = 0; ntries < 100; ntries++) { 231 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 232 if (tmp != 0 && tmp != 0xffffffff) 233 break; 234 DELAY(10); 235 } 236 if (ntries == 100) { 237 aprint_error_dev(sc->sc_dev, 238 "timeout waiting for NIC to initialize\n"); 239 return ETIMEDOUT; 240 } 241 sc->mac_ver = tmp >> 16; 242 sc->mac_rev = tmp & 0xffff; 243 244 if (sc->mac_ver != 0x2860 && 245 (id == PCI_PRODUCT_RALINK_RT2890 || 246 id == PCI_PRODUCT_RALINK_RT2790 || 247 id == PCI_PRODUCT_AWT_RT2890)) 248 sc->sc_flags |= RT2860_ADVANCED_PS; 249 250 /* retrieve RF rev. no and various other things from EEPROM */ 251 rt2860_read_eeprom(sc); 252 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 253 ether_sprintf(ic->ic_myaddr)); 254 aprint_normal_dev(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 255 "RF %s (MIMO %dT%dR)\n", 256 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 257 sc->ntxchains, sc->nrxchains); 258 259 sc->sc_soft_ih = softint_establish(SOFTINT_NET, rt2860_softintr, sc); 260 if (sc->sc_soft_ih == NULL) { 261 aprint_error_dev(sc->sc_dev, "could not establish softint\n"); 262 error = EINVAL; 263 goto fail0; 264 } 265 266 /* 267 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 268 */ 269 for (qid = 0; qid < MAXQS; qid++) { 270 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 271 aprint_error_dev(sc->sc_dev, 272 "could not allocate Tx ring %d\n", qid); 273 goto fail1; 274 } 275 } 276 277 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 278 aprint_error_dev(sc->sc_dev, "could not allocate Rx ring\n"); 279 goto fail1; 280 } 281 282 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 283 aprint_error_dev(sc->sc_dev, "could not allocate Tx pool\n"); 284 goto fail2; 285 } 286 287 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 288 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 289 WME_AC_VO : 5; 290 291 config_mountroot(sc->sc_dev, rt2860_attachhook); 292 293 return 0; 294 295 fail2: rt2860_free_rx_ring(sc, &sc->rxq); 296 fail1: while (--qid >= 0) 297 rt2860_free_tx_ring(sc, &sc->txq[qid]); 298 fail0: softint_disestablish(sc->sc_soft_ih); 299 sc->sc_soft_ih = NULL; 300 return error; 301 } 302 303 static int 304 firmware_load(const char *dname, const char *iname, uint8_t **ucodep, 305 size_t *sizep) 306 { 307 firmware_handle_t fh; 308 int error; 309 310 if ((error = firmware_open(dname, iname, &fh)) != 0) 311 return (error); 312 *sizep = firmware_get_size(fh); 313 if ((*ucodep = firmware_malloc(*sizep)) == NULL) { 314 firmware_close(fh); 315 return (ENOMEM); 316 } 317 if ((error = firmware_read(fh, 0, *ucodep, *sizep)) != 0) 318 firmware_free(*ucodep, *sizep); 319 firmware_close(fh); 320 321 return (error); 322 } 323 324 static void 325 rt2860_attachhook(device_t self) 326 { 327 struct rt2860_softc *sc = device_private(self); 328 struct ieee80211com *ic = &sc->sc_ic; 329 struct ifnet *ifp = &sc->sc_if; 330 int i, error; 331 332 error = firmware_load("ral", "ral-rt2860", &sc->ucode, &sc->ucsize); 333 if (error != 0) { 334 aprint_error_dev(sc->sc_dev, 335 "error %d, could not read firmware file %s\n", 336 error, "ral-rt2860"); 337 return; 338 } 339 340 ic->ic_ifp = ifp; 341 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 342 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 343 ic->ic_state = IEEE80211_S_INIT; 344 345 /* set device capabilities */ 346 ic->ic_caps = 347 IEEE80211_C_MONITOR | /* monitor mode supported */ 348 #ifndef IEEE80211_STA_ONLY 349 IEEE80211_C_IBSS | /* IBSS mode supported */ 350 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 351 #ifdef IEEE80211_C_APPMGT 352 IEEE80211_C_APPMGT | /* HostAP power management */ 353 #endif 354 #endif 355 IEEE80211_C_WDS | /* 4-address traffic works */ 356 IEEE80211_C_WME | /* 802.11e */ 357 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 358 IEEE80211_C_SHSLOT | /* short slot time supported */ 359 #ifdef HW_CRYPTO 360 IEEE80211_C_WEP | /* WEP */ 361 #endif 362 IEEE80211_C_WPA; /* 802.11i */ 363 364 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 365 /* set supported .11a rates */ 366 ic->ic_sup_rates[IEEE80211_MODE_11A] = 367 ieee80211_std_rateset_11a; 368 369 /* set supported .11a channels */ 370 for (i = 14; i < (int)__arraycount(rt2860_rf2850); i++) { 371 uint8_t chan = rt2860_rf2850[i].chan; 372 ic->ic_channels[chan].ic_freq = 373 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 374 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 375 } 376 } 377 378 /* set supported .11b and .11g rates */ 379 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 380 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 381 382 /* set supported .11b and .11g channels (1 through 14) */ 383 for (i = 1; i <= 14; i++) { 384 ic->ic_channels[i].ic_freq = 385 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 386 ic->ic_channels[i].ic_flags = 387 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 388 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 389 } 390 391 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 392 ic->ic_max_aid = uimin(IEEE80211_AID_MAX, RT2860_WCID_MAX); 393 394 ifp->if_softc = sc; 395 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 396 ifp->if_init = rt2860_init; 397 ifp->if_ioctl = rt2860_ioctl; 398 ifp->if_start = rt2860_start; 399 ifp->if_stop = rt2860_stop; 400 ifp->if_watchdog = rt2860_watchdog; 401 IFQ_SET_READY(&ifp->if_snd); 402 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 403 404 error = if_initialize(ifp); 405 if (error != 0) { 406 int qid; 407 408 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 409 error); 410 for (qid = 0; qid < MAXQS; qid++) 411 rt2860_free_tx_ring(sc, &sc->txq[qid]); 412 rt2860_free_rx_ring(sc, &sc->rxq); 413 rt2860_free_tx_pool(sc); 414 415 if (sc->sc_soft_ih != NULL) { 416 softint_disestablish(sc->sc_soft_ih); 417 sc->sc_soft_ih = NULL; 418 } 419 if (sc->ucode != NULL) 420 firmware_free(sc->ucode, sc->ucsize); 421 return; 422 } 423 ieee80211_ifattach(ic); 424 /* Use common softint-based if_input */ 425 ifp->if_percpuq = if_percpuq_create(ifp); 426 if_register(ifp); 427 428 ic->ic_node_alloc = rt2860_node_alloc; 429 ic->ic_newassoc = rt2860_newassoc; 430 #ifdef notyet 431 ic->ic_ampdu_rx_start = rt2860_ampdu_rx_start; 432 ic->ic_ampdu_rx_stop = rt2860_ampdu_rx_stop; 433 #endif 434 ic->ic_updateslot = rt2860_updateslot; 435 ic->ic_wme.wme_update = rt2860_updateedca; 436 #ifdef HW_CRYPTO 437 ic->ic_crypto.cs_key_set = rt2860_set_key; 438 ic->ic_crypto.cs_key_delete = rt2860_delete_key; 439 #endif 440 /* override state transition machine */ 441 sc->sc_newstate = ic->ic_newstate; 442 ic->ic_newstate = rt2860_newstate; 443 ieee80211_media_init(ic, rt2860_media_change, ieee80211_media_status); 444 445 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 446 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 447 448 sc->sc_rxtap_len = roundup(sizeof(sc->sc_rxtap), sizeof(u_int32_t)); 449 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 450 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2860_RX_RADIOTAP_PRESENT); 451 452 sc->sc_txtap_len = roundup(sizeof(sc->sc_txtap), sizeof(u_int32_t)); 453 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 454 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2860_TX_RADIOTAP_PRESENT); 455 456 ieee80211_announce(ic); 457 458 if (pmf_device_register(sc->sc_dev, rt2860_wakeup, rt2860_suspend)) 459 pmf_class_network_register(sc->sc_dev, ifp); 460 else 461 aprint_error_dev(sc->sc_dev, 462 "couldn't establish power handler\n"); 463 } 464 465 int 466 rt2860_detach(void *xsc) 467 { 468 struct rt2860_softc *sc = xsc; 469 struct ifnet *ifp = &sc->sc_if; 470 int qid; 471 472 pmf_device_deregister(sc->sc_dev); 473 474 rt2860_stop(ifp, 1); 475 476 ieee80211_ifdetach(&sc->sc_ic); /* free all nodes */ 477 if_detach(ifp); 478 479 for (qid = 0; qid < MAXQS; qid++) 480 rt2860_free_tx_ring(sc, &sc->txq[qid]); 481 rt2860_free_rx_ring(sc, &sc->rxq); 482 rt2860_free_tx_pool(sc); 483 484 if (sc->sc_soft_ih != NULL) { 485 softint_disestablish(sc->sc_soft_ih); 486 sc->sc_soft_ih = NULL; 487 } 488 489 if (sc->ucode != NULL) 490 firmware_free(sc->ucode, sc->ucsize); 491 492 return 0; 493 } 494 495 static bool 496 rt2860_suspend(device_t self, const pmf_qual_t *qual) 497 { 498 struct rt2860_softc *sc = device_private(self); 499 struct ifnet *ifp = &sc->sc_if; 500 501 if (ifp->if_flags & IFF_RUNNING) 502 rt2860_stop(ifp, 1); 503 504 return true; 505 } 506 507 static bool 508 rt2860_wakeup(device_t self, const pmf_qual_t *qual) 509 { 510 struct rt2860_softc *sc = device_private(self); 511 struct ifnet *ifp = &sc->sc_if; 512 int s; 513 514 s = splnet(); 515 if (ifp->if_flags & IFF_UP) 516 rt2860_init(ifp); 517 splx(s); 518 519 return true; 520 } 521 522 static int 523 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 524 { 525 int nsegs, size, error; 526 527 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 528 529 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 530 BUS_DMA_NOWAIT, &ring->map); 531 if (error != 0) { 532 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 533 goto fail; 534 } 535 536 /* Tx rings must be 4-DWORD aligned */ 537 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 538 &nsegs, BUS_DMA_NOWAIT); 539 if (error != 0) { 540 aprint_error_dev(sc->sc_dev, 541 "could not allocate DMA memory\n"); 542 goto fail; 543 } 544 545 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 546 (void **)&ring->txd, BUS_DMA_NOWAIT); 547 if (error != 0) { 548 aprint_error_dev(sc->sc_dev, "can't map DMA memory\n"); 549 goto fail; 550 } 551 552 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->txd, size, NULL, 553 BUS_DMA_NOWAIT); 554 if (error != 0) { 555 aprint_error_dev(sc->sc_dev, "could not load DMA map\n"); 556 goto fail; 557 } 558 559 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 560 561 ring->paddr = ring->map->dm_segs[0].ds_addr; 562 563 return 0; 564 565 fail: rt2860_free_tx_ring(sc, ring); 566 return error; 567 } 568 569 static void 570 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 571 { 572 struct rt2860_tx_data *data; 573 int i; 574 575 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 576 if ((data = ring->data[i]) == NULL) 577 continue; /* nothing mapped in this slot */ 578 579 if (data->ni != NULL) { 580 ieee80211_free_node(data->ni); 581 data->ni = NULL; 582 } 583 584 if (data->m != NULL) { 585 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 586 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 587 bus_dmamap_unload(sc->sc_dmat, data->map); 588 m_freem(data->m); 589 data->m = NULL; 590 } 591 592 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 593 ring->data[i] = NULL; 594 } 595 596 ring->queued = 0; 597 ring->cur = ring->next = 0; 598 } 599 600 static void 601 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 602 { 603 struct rt2860_tx_data *data; 604 int i; 605 606 if (ring->txd != NULL) { 607 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 608 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 609 bus_dmamap_unload(sc->sc_dmat, ring->map); 610 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->txd, 611 RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd)); 612 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 613 } 614 if (ring->map != NULL) 615 bus_dmamap_destroy(sc->sc_dmat, ring->map); 616 617 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 618 if ((data = ring->data[i]) == NULL) 619 continue; /* nothing mapped in this slot */ 620 621 if (data->ni != NULL) { 622 ieee80211_free_node(data->ni); 623 data->ni = NULL; 624 } 625 if (data->m != NULL) { 626 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 627 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 628 bus_dmamap_unload(sc->sc_dmat, data->map); 629 m_freem(data->m); 630 data->m = NULL; 631 } 632 633 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 634 ring->data[i] = NULL; 635 } 636 ring->queued = 0; 637 ring->cur = ring->next = 0; 638 } 639 640 /* 641 * Allocate a pool of TX Wireless Information blocks. 642 */ 643 static int 644 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 645 { 646 char *vaddr; 647 bus_addr_t paddr; 648 int i, nsegs, size, error; 649 650 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 651 652 /* init data_pool early in case of failure.. */ 653 SLIST_INIT(&sc->data_pool); 654 655 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 656 BUS_DMA_NOWAIT, &sc->txwi_map); 657 if (error != 0) { 658 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 659 goto fail; 660 } 661 662 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 663 &sc->txwi_seg, 1, &nsegs, BUS_DMA_NOWAIT); 664 if (error != 0) { 665 aprint_error_dev(sc->sc_dev, 666 "could not allocate DMA memory\n"); 667 goto fail; 668 } 669 670 error = bus_dmamem_map(sc->sc_dmat, &sc->txwi_seg, nsegs, size, 671 &sc->txwi_vaddr, BUS_DMA_NOWAIT); 672 if (error != 0) { 673 aprint_error_dev(sc->sc_dev, "can't map DMA memory\n"); 674 goto fail; 675 } 676 677 error = bus_dmamap_load(sc->sc_dmat, sc->txwi_map, sc->txwi_vaddr, 678 size, NULL, BUS_DMA_NOWAIT); 679 if (error != 0) { 680 aprint_error_dev(sc->sc_dev, "could not load DMA map\n"); 681 goto fail; 682 } 683 684 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, size, 685 BUS_DMASYNC_PREWRITE); 686 687 vaddr = sc->txwi_vaddr; 688 paddr = sc->txwi_map->dm_segs[0].ds_addr; 689 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 690 struct rt2860_tx_data *data = &sc->data[i]; 691 692 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 693 RT2860_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 694 &data->map); /* <0> */ 695 if (error != 0) { 696 aprint_error_dev(sc->sc_dev, 697 "could not create DMA map\n"); 698 goto fail; 699 } 700 data->txwi = (struct rt2860_txwi *)vaddr; 701 data->paddr = paddr; 702 vaddr += RT2860_TXWI_DMASZ; 703 paddr += RT2860_TXWI_DMASZ; 704 705 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 706 } 707 708 return 0; 709 710 fail: rt2860_free_tx_pool(sc); 711 return error; 712 } 713 714 static void 715 rt2860_free_tx_pool(struct rt2860_softc *sc) 716 { 717 if (sc->txwi_vaddr != NULL) { 718 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, 719 sc->txwi_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 720 bus_dmamap_unload(sc->sc_dmat, sc->txwi_map); 721 bus_dmamem_unmap(sc->sc_dmat, sc->txwi_vaddr, 722 RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ); 723 bus_dmamem_free(sc->sc_dmat, &sc->txwi_seg, 1); 724 } 725 if (sc->txwi_map != NULL) 726 bus_dmamap_destroy(sc->sc_dmat, sc->txwi_map); 727 728 while (!SLIST_EMPTY(&sc->data_pool)) { 729 struct rt2860_tx_data *data; 730 data = SLIST_FIRST(&sc->data_pool); 731 bus_dmamap_destroy(sc->sc_dmat, data->map); 732 SLIST_REMOVE_HEAD(&sc->data_pool, next); 733 } 734 } 735 736 static int 737 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 738 { 739 int i, nsegs, size, error; 740 741 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 742 743 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 744 BUS_DMA_NOWAIT, &ring->map); 745 if (error != 0) { 746 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 747 goto fail; 748 } 749 750 /* Rx ring must be 4-DWORD aligned */ 751 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 752 &nsegs, BUS_DMA_NOWAIT); 753 if (error != 0) { 754 aprint_error_dev(sc->sc_dev, 755 "could not allocate DMA memory\n"); 756 goto fail; 757 } 758 759 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 760 (void **)&ring->rxd, BUS_DMA_NOWAIT); 761 if (error != 0) { 762 aprint_error_dev(sc->sc_dev, "can't map DMA memory\n"); 763 goto fail; 764 } 765 766 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->rxd, size, NULL, 767 BUS_DMA_NOWAIT); 768 if (error != 0) { 769 aprint_error_dev(sc->sc_dev, "could not load DMA map\n"); 770 goto fail; 771 } 772 773 ring->paddr = ring->map->dm_segs[0].ds_addr; 774 775 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 776 struct rt2860_rx_data *data = &ring->data[i]; 777 struct rt2860_rxd *rxd = &ring->rxd[i]; 778 const char *msg; 779 780 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 781 0, BUS_DMA_NOWAIT, &data->map); 782 if (error != 0) { 783 aprint_error_dev(sc->sc_dev, 784 "could not create DMA map\n"); 785 goto fail; 786 } 787 788 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 789 if (data->m == NULL) { 790 msg = "allocate Rx mbuf"; 791 goto fail1; 792 } 793 MCLGET(data->m, M_DONTWAIT); 794 if ((data->m->m_flags & M_EXT) == 0) { 795 msg = "allocate Rx mbuf cluster"; 796 goto fail1; 797 } 798 799 800 error = bus_dmamap_load(sc->sc_dmat, data->map, 801 mtod(data->m, void *), MCLBYTES, NULL, 802 BUS_DMA_READ | BUS_DMA_NOWAIT); 803 if (error != 0) { 804 msg = "load DMA map"; 805 fail1: 806 aprint_error_dev(sc->sc_dev, "could not %s\n", msg); 807 m_freem(data->m); 808 data->m = NULL; 809 error = ENOBUFS; 810 goto fail; 811 } 812 813 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 814 rxd->sdl0 = htole16(MCLBYTES); 815 } 816 817 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 818 819 return 0; 820 fail: rt2860_free_rx_ring(sc, ring); 821 return error; 822 } 823 824 static void 825 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 826 { 827 int i; 828 829 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 830 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 831 832 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 833 BUS_DMASYNC_PREWRITE); 834 835 ring->cur = 0; 836 } 837 838 static void 839 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 840 { 841 int i; 842 843 if (ring->rxd != NULL) { 844 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 845 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 846 bus_dmamap_unload(sc->sc_dmat, ring->map); 847 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->rxd, 848 RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd)); 849 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 850 ring->rxd = NULL; 851 } 852 if (ring->map != NULL) { 853 bus_dmamap_destroy(sc->sc_dmat, ring->map); 854 ring->map = NULL; 855 } 856 857 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 858 struct rt2860_rx_data *data = &ring->data[i]; 859 860 if (data->m != NULL) { 861 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 862 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 863 bus_dmamap_unload(sc->sc_dmat, data->map); 864 m_freem(data->m); 865 data->m = NULL; 866 } 867 if (data->map != NULL) { 868 bus_dmamap_destroy(sc->sc_dmat, data->map); 869 data->map = NULL; 870 } 871 } 872 } 873 874 static struct ieee80211_node * 875 rt2860_node_alloc(struct ieee80211_node_table *nt) 876 { 877 struct rt2860_node *rn = malloc(sizeof(*rn), M_80211_NODE, 878 M_NOWAIT | M_ZERO); 879 return rn ? &rn->ni : NULL; 880 } 881 882 static int 883 rt2860_media_change(struct ifnet *ifp) 884 { 885 struct rt2860_softc *sc = ifp->if_softc; 886 struct ieee80211com *ic = &sc->sc_ic; 887 uint8_t rate, ridx; 888 int error; 889 890 error = ieee80211_media_change(ifp); 891 if (error != ENETRESET) 892 return error; 893 894 if (ic->ic_fixed_rate != -1) { 895 rate = ic->ic_sup_rates[ic->ic_curmode]. 896 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 897 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 898 if (rt2860_rates[ridx].rate == rate) 899 break; 900 sc->fixed_ridx = ridx; 901 } 902 903 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 904 (IFF_UP | IFF_RUNNING)) { 905 rt2860_stop(ifp, 0); 906 rt2860_init(ifp); 907 } 908 return 0; 909 } 910 911 static void 912 rt2860_iter_func(void *arg, struct ieee80211_node *ni) 913 { 914 struct rt2860_softc *sc = arg; 915 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 916 917 ieee80211_amrr_choose(&sc->amrr, ni, &sc->amn[wcid]); 918 } 919 920 static void 921 rt2860_updatestats(struct rt2860_softc *sc) 922 { 923 struct ieee80211com *ic = &sc->sc_ic; 924 int s; 925 926 #ifndef IEEE80211_STA_ONLY 927 /* 928 * In IBSS or HostAP modes (when the hardware sends beacons), the 929 * MAC can run into a livelock and start sending CTS-to-self frames 930 * like crazy if protection is enabled. Fortunately, we can detect 931 * when such a situation occurs and reset the MAC. 932 */ 933 if (ic->ic_curmode != IEEE80211_M_STA) { 934 /* check if we're in a livelock situation.. */ 935 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 936 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 937 /* ..and reset MAC/BBP for a while.. */ 938 DPRINTF(("CTS-to-self livelock detected\n")); 939 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 940 RAL_BARRIER_WRITE(sc); 941 DELAY(1); 942 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 943 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 944 } 945 } 946 #endif 947 s = splnet(); 948 if (ic->ic_opmode == IEEE80211_M_STA) 949 rt2860_iter_func(sc, ic->ic_bss); 950 #ifndef IEEE80211_STA_ONLY 951 else 952 ieee80211_iterate_nodes(&ic->ic_sta, rt2860_iter_func, sc); 953 #endif 954 splx(s); 955 } 956 957 static void 958 rt2860_newassoc(struct ieee80211_node *ni, int isnew) 959 { 960 struct rt2860_softc *sc = ni->ni_ic->ic_ifp->if_softc; 961 struct rt2860_node *rn = (void *)ni; 962 struct ieee80211_rateset *rs = &ni->ni_rates; 963 uint8_t rate, wcid = 0; 964 int ridx, i, j; 965 966 if (isnew && ni->ni_associd != 0) { 967 /* only interested in true associations */ 968 wcid = rn->wcid = IEEE80211_AID(ni->ni_associd); 969 970 /* init WCID table entry */ 971 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 972 ni->ni_macaddr, IEEE80211_ADDR_LEN); 973 } 974 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 975 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 976 977 ieee80211_amrr_node_init(&sc->amrr, &sc->amn[wcid]); 978 /* start at lowest available bit-rate, AMRR will raise */ 979 ni->ni_txrate = 0; 980 981 for (i = 0; i < rs->rs_nrates; i++) { 982 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 983 /* convert 802.11 rate to hardware rate index */ 984 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 985 if (rt2860_rates[ridx].rate == rate) 986 break; 987 rn->ridx[i] = ridx; 988 /* determine rate of control response frames */ 989 for (j = i; j >= 0; j--) { 990 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 991 rt2860_rates[rn->ridx[i]].phy == 992 rt2860_rates[rn->ridx[j]].phy) 993 break; 994 } 995 if (j >= 0) { 996 rn->ctl_ridx[i] = rn->ridx[j]; 997 } else { 998 /* no basic rate found, use mandatory one */ 999 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 1000 } 1001 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 1002 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 1003 } 1004 } 1005 1006 #ifdef notyet 1007 static int 1008 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 1009 uint8_t tid) 1010 { 1011 struct rt2860_softc *sc = ic->ic_softc; 1012 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 1013 uint32_t tmp; 1014 1015 /* update BA session mask */ 1016 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 1017 tmp |= (1 << tid) << 16; 1018 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 1019 return 0; 1020 } 1021 1022 static void 1023 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 1024 uint8_t tid) 1025 { 1026 struct rt2860_softc *sc = ic->ic_softc; 1027 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 1028 uint32_t tmp; 1029 1030 /* update BA session mask */ 1031 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 1032 tmp &= ~((1 << tid) << 16); 1033 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 1034 } 1035 #endif 1036 1037 static int 1038 rt2860_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1039 { 1040 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 1041 enum ieee80211_state ostate; 1042 uint32_t tmp; 1043 1044 ostate = ic->ic_state; 1045 1046 DPRINTF(("ostate = %d nstate = %d\n", ostate, nstate)); 1047 if (ostate == IEEE80211_S_RUN) { 1048 /* turn link LED off */ 1049 rt2860_set_leds(sc, RT2860_LED_RADIO); 1050 } 1051 1052 switch (nstate) { 1053 case IEEE80211_S_INIT: 1054 if (ostate == IEEE80211_S_RUN) { 1055 /* abort TSF synchronization */ 1056 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 1057 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 1058 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 1059 RT2860_TBTT_TIMER_EN)); 1060 } 1061 rt2860_set_gp_timer(sc, 0); 1062 break; 1063 1064 case IEEE80211_S_SCAN: 1065 rt2860_switch_chan(sc, ic->ic_curchan); 1066 if (ostate != IEEE80211_S_SCAN) 1067 rt2860_set_gp_timer(sc, 150); 1068 break; 1069 1070 case IEEE80211_S_AUTH: 1071 case IEEE80211_S_ASSOC: 1072 rt2860_set_gp_timer(sc, 0); 1073 rt2860_switch_chan(sc, ic->ic_curchan); 1074 break; 1075 1076 case IEEE80211_S_RUN: 1077 rt2860_set_gp_timer(sc, 0); 1078 rt2860_switch_chan(sc, ic->ic_curchan); 1079 1080 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1081 rt2860_updateslot(ic->ic_ifp); 1082 rt2860_enable_mrr(sc); 1083 rt2860_set_txpreamble(sc); 1084 rt2860_set_basicrates(sc); 1085 rt2860_set_bssid(sc, ic->ic_bss->ni_bssid); 1086 } 1087 1088 #ifndef IEEE80211_STA_ONLY 1089 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1090 ic->ic_opmode == IEEE80211_M_IBSS) 1091 (void)rt2860_setup_beacon(sc); 1092 #endif 1093 1094 if (ic->ic_opmode == IEEE80211_M_STA) { 1095 /* fake a join to init the tx rate */ 1096 rt2860_newassoc(ic->ic_bss, 1); 1097 } 1098 1099 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1100 rt2860_enable_tsf_sync(sc); 1101 rt2860_set_gp_timer(sc, 500); 1102 } 1103 1104 /* turn link LED on */ 1105 rt2860_set_leds(sc, RT2860_LED_RADIO | 1106 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan) ? 1107 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1108 break; 1109 } 1110 1111 return sc->sc_newstate(ic, nstate, arg); 1112 } 1113 1114 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 1115 static uint16_t 1116 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 1117 { 1118 uint32_t tmp; 1119 uint16_t reg; 1120 int ntries; 1121 1122 addr *= 2; 1123 /*- 1124 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1125 * DATA0: F E D C 1126 * DATA1: B A 9 8 1127 * DATA2: 7 6 5 4 1128 * DATA3: 3 2 1 0 1129 */ 1130 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1131 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1132 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1133 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 1134 for (ntries = 0; ntries < 500; ntries++) { 1135 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1136 if (!(tmp & RT3070_EFSROM_KICK)) 1137 break; 1138 DELAY(2); 1139 } 1140 if (ntries == 500) 1141 return 0xffff; 1142 1143 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 1144 return 0xffff; /* address not found */ 1145 1146 /* determine to which 32-bit register our 16-bit word belongs */ 1147 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1148 tmp = RAL_READ(sc, reg); 1149 1150 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1151 } 1152 1153 /* 1154 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1155 * 93C66 or 93C86). 1156 */ 1157 static uint16_t 1158 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1159 { 1160 uint32_t tmp; 1161 uint16_t val; 1162 int n; 1163 1164 /* clock C once before the first command */ 1165 RT2860_EEPROM_CTL(sc, 0); 1166 1167 RT2860_EEPROM_CTL(sc, RT2860_S); 1168 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1169 RT2860_EEPROM_CTL(sc, RT2860_S); 1170 1171 /* write start bit (1) */ 1172 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1173 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1174 1175 /* write READ opcode (10) */ 1176 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1177 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1178 RT2860_EEPROM_CTL(sc, RT2860_S); 1179 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1180 1181 /* write address (A5-A0 or A7-A0) */ 1182 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1183 for (; n >= 0; n--) { 1184 RT2860_EEPROM_CTL(sc, RT2860_S | 1185 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1186 RT2860_EEPROM_CTL(sc, RT2860_S | 1187 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1188 } 1189 1190 RT2860_EEPROM_CTL(sc, RT2860_S); 1191 1192 /* read data Q15-Q0 */ 1193 val = 0; 1194 for (n = 15; n >= 0; n--) { 1195 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1196 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1197 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1198 RT2860_EEPROM_CTL(sc, RT2860_S); 1199 } 1200 1201 RT2860_EEPROM_CTL(sc, 0); 1202 1203 /* clear Chip Select and clock C */ 1204 RT2860_EEPROM_CTL(sc, RT2860_S); 1205 RT2860_EEPROM_CTL(sc, 0); 1206 RT2860_EEPROM_CTL(sc, RT2860_C); 1207 1208 return val; 1209 } 1210 1211 static __inline uint16_t 1212 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1213 { 1214 /* either eFUSE ROM or EEPROM */ 1215 return sc->sc_srom_read(sc, addr); 1216 } 1217 1218 static void 1219 rt2860_intr_coherent(struct rt2860_softc *sc) 1220 { 1221 uint32_t tmp; 1222 1223 /* DMA finds data coherent event when checking the DDONE bit */ 1224 1225 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1226 1227 /* restart DMA engine */ 1228 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1229 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1230 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1231 1232 (void)rt2860_txrx_enable(sc); 1233 } 1234 1235 static void 1236 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1237 { 1238 struct ifnet *ifp = &sc->sc_if; 1239 struct ieee80211_amrr_node *amn; 1240 uint32_t stat; 1241 uint8_t wcid, mcs, pid; 1242 1243 /* drain Tx status FIFO (maxsize = 16) */ 1244 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1245 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1246 1247 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1248 1249 /* if no ACK was requested, no feedback is available */ 1250 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff) 1251 continue; 1252 1253 /* update per-STA AMRR stats */ 1254 amn = &sc->amn[wcid]; 1255 amn->amn_txcnt++; 1256 if (stat & RT2860_TXQ_OK) { 1257 /* 1258 * Check if there were retries, ie if the Tx success 1259 * rate is different from the requested rate. Note 1260 * that it works only because we do not allow rate 1261 * fallback from OFDM to CCK. 1262 */ 1263 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1264 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1265 if (mcs + 1 != pid) 1266 amn->amn_retrycnt++; 1267 } else { 1268 amn->amn_retrycnt++; 1269 if_statinc(ifp, if_oerrors); 1270 } 1271 } 1272 } 1273 1274 static void 1275 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1276 { 1277 struct ifnet *ifp = &sc->sc_if; 1278 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1279 uint32_t hw; 1280 int s; 1281 1282 s = splnet(); 1283 1284 rt2860_drain_stats_fifo(sc); 1285 1286 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1287 DPRINTF(("%s: tx mbuf %#x\n", __func__, hw)); 1288 while (ring->next != hw) { 1289 struct rt2860_tx_data *data = ring->data[ring->next]; 1290 1291 if (data != NULL) { 1292 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1293 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1294 bus_dmamap_unload(sc->sc_dmat, data->map); 1295 m_freem(data->m); 1296 data->m = NULL; 1297 ieee80211_free_node(data->ni); 1298 data->ni = NULL; 1299 1300 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1301 ring->data[ring->next] = NULL; 1302 1303 if_statinc(ifp, if_opackets); 1304 } 1305 ring->queued--; 1306 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1307 } 1308 1309 sc->sc_tx_timer = 0; 1310 if (ring->queued <= RT2860_TX_RING_ONEMORE) 1311 sc->qfullmsk &= ~(1 << qid); 1312 ifp->if_flags &= ~IFF_OACTIVE; 1313 rt2860_start(ifp); /* in softint */ 1314 1315 splx(s); 1316 } 1317 1318 /* 1319 * Return the Rx chain with the highest RSSI for a given frame. 1320 */ 1321 static __inline uint8_t 1322 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1323 { 1324 uint8_t rxchain = 0; 1325 1326 if (sc->nrxchains > 1) { 1327 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1328 rxchain = 1; 1329 if (sc->nrxchains > 2) 1330 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1331 rxchain = 2; 1332 } 1333 return rxchain; 1334 } 1335 1336 static void 1337 rt2860_rx_intr(struct rt2860_softc *sc) 1338 { 1339 struct ieee80211com *ic = &sc->sc_ic; 1340 struct ifnet *ifp = &sc->sc_if; 1341 struct ieee80211_frame *wh; 1342 struct ieee80211_node *ni; 1343 struct mbuf *m, *m1; 1344 uint32_t hw; 1345 uint8_t ant, rssi; 1346 int error, s; 1347 struct rt2860_rx_radiotap_header *tap; 1348 uint16_t phy; 1349 1350 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1351 DPRINTF(("%s: rx mbuf %#x\n", __func__, hw)); 1352 while (sc->rxq.cur != hw) { 1353 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1354 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1355 struct rt2860_rxwi *rxwi; 1356 1357 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1358 sc->rxq.cur * sizeof (struct rt2860_rxd), 1359 sizeof (struct rt2860_rxd), BUS_DMASYNC_POSTREAD); 1360 1361 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1362 DPRINTF(("RXD DDONE bit not set!\n")); 1363 break; /* should not happen */ 1364 } 1365 1366 if (__predict_false(rxd->flags & 1367 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1368 DPRINTF(("error %#x\n", rxd->flags)); 1369 if_statinc(ifp, if_ierrors); 1370 goto skip; 1371 } 1372 1373 1374 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1375 if (__predict_false(m1 == NULL)) { 1376 DPRINTF(("error2 %#x\n", rxd->flags)); 1377 if_statinc(ifp, if_ierrors); 1378 goto skip; 1379 } 1380 MCLGET(m1, M_DONTWAIT); 1381 if (__predict_false((m1->m_flags & M_EXT) == 0)) { 1382 DPRINTF(("no mbuf\n")); 1383 m_freem(m1); 1384 if_statinc(ifp, if_ierrors); 1385 goto skip; 1386 } 1387 1388 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1389 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1390 bus_dmamap_unload(sc->sc_dmat, data->map); 1391 1392 error = bus_dmamap_load(sc->sc_dmat, data->map, 1393 mtod(m1, void *), MCLBYTES, NULL, 1394 BUS_DMA_READ | BUS_DMA_NOWAIT); 1395 if (__predict_false(error != 0)) { 1396 DPRINTF(("dma error %d\n", error)); 1397 m_freem(m1); 1398 1399 /* try to reload the old mbuf */ 1400 error = bus_dmamap_load(sc->sc_dmat, data->map, 1401 mtod(data->m, void *), MCLBYTES, NULL, 1402 BUS_DMA_READ | BUS_DMA_NOWAIT); 1403 if (__predict_false(error != 0)) { 1404 panic("%s: could not load old rx mbuf", 1405 device_xname(sc->sc_dev)); 1406 } 1407 /* physical address may have changed */ 1408 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1409 if_statinc(ifp, if_ierrors); 1410 goto skip; 1411 } 1412 1413 /* 1414 * New mbuf successfully loaded, update Rx ring and continue 1415 * processing. 1416 */ 1417 m = data->m; 1418 data->m = m1; 1419 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1420 1421 rxwi = mtod(m, struct rt2860_rxwi *); 1422 1423 /* finalize mbuf */ 1424 m->m_data = (void *)(rxwi + 1); 1425 m_set_rcvif(m, ifp); 1426 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1427 1428 wh = mtod(m, struct ieee80211_frame *); 1429 #ifdef HW_CRYPTO 1430 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1431 /* frame is decrypted by hardware */ 1432 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1433 } 1434 #endif 1435 1436 /* HW may insert 2 padding bytes after 802.11 header */ 1437 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1438 u_int hdrlen = ieee80211_hdrsize(wh); 1439 memmove((char *)wh + 2, wh, hdrlen); 1440 m->m_data += 2; 1441 wh = mtod(m, struct ieee80211_frame *); 1442 } 1443 1444 #ifdef HW_CRYPTO 1445 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1446 /* report MIC failures to net80211 for TKIP */ 1447 ieee80211_notify_michael_failure(ic, wh, 0/* XXX */); 1448 DPRINTF(("error2 %#x\n", rxd->flags)); 1449 if_statinc(ifp, if_ierrors); 1450 goto skip; 1451 } 1452 #endif 1453 ant = rt2860_maxrssi_chain(sc, rxwi); 1454 rssi = rxwi->rssi[ant]; 1455 1456 s = splnet(); 1457 1458 if (__predict_true(sc->sc_drvbpf == NULL)) 1459 goto skipbpf; 1460 1461 tap = &sc->sc_rxtap; 1462 tap->wr_flags = 0; 1463 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1464 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1465 tap->wr_antsignal = rssi; 1466 tap->wr_antenna = ant; 1467 tap->wr_dbm_antsignal = rt2860_rssi2dbm(sc, rssi, ant); 1468 tap->wr_rate = 2; /* in case it can't be found below */ 1469 phy = le16toh(rxwi->phy); 1470 switch (phy & RT2860_PHY_MODE) { 1471 case RT2860_PHY_CCK: 1472 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1473 case 0: tap->wr_rate = 2; break; 1474 case 1: tap->wr_rate = 4; break; 1475 case 2: tap->wr_rate = 11; break; 1476 case 3: tap->wr_rate = 22; break; 1477 } 1478 if (phy & RT2860_PHY_SHPRE) 1479 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1480 break; 1481 case RT2860_PHY_OFDM: 1482 switch (phy & RT2860_PHY_MCS) { 1483 case 0: tap->wr_rate = 12; break; 1484 case 1: tap->wr_rate = 18; break; 1485 case 2: tap->wr_rate = 24; break; 1486 case 3: tap->wr_rate = 36; break; 1487 case 4: tap->wr_rate = 48; break; 1488 case 5: tap->wr_rate = 72; break; 1489 case 6: tap->wr_rate = 96; break; 1490 case 7: tap->wr_rate = 108; break; 1491 } 1492 break; 1493 } 1494 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 1495 skipbpf: 1496 /* grab a reference to the source node */ 1497 ni = ieee80211_find_rxnode(ic, 1498 (struct ieee80211_frame_min *)wh); 1499 1500 /* send the frame to the 802.11 layer */ 1501 ieee80211_input(ic, m, ni, rssi, 0); 1502 1503 /* node is no longer needed */ 1504 ieee80211_free_node(ni); 1505 1506 splx(s); 1507 1508 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1509 1510 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1511 sc->rxq.cur * sizeof (struct rt2860_rxd), 1512 sizeof (struct rt2860_rxd), BUS_DMASYNC_PREWRITE); 1513 1514 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1515 } 1516 1517 /* tell HW what we have processed */ 1518 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1519 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1520 } 1521 1522 static void 1523 rt2860_tbtt_intr(struct rt2860_softc *sc) 1524 { 1525 struct ieee80211com *ic = &sc->sc_ic; 1526 1527 #ifndef IEEE80211_STA_ONLY 1528 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1529 /* one less beacon until next DTIM */ 1530 if (ic->ic_dtim_count == 0) 1531 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1532 else 1533 ic->ic_dtim_count--; 1534 1535 /* update dynamic parts of beacon */ 1536 rt2860_setup_beacon(sc); 1537 1538 #if 0 1539 /* flush buffered multicast frames */ 1540 if (ic->ic_dtim_count == 0) 1541 ieee80211_notify_dtim(ic); 1542 #endif 1543 } 1544 #endif 1545 /* check if protection mode has changed */ 1546 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1547 rt2860_updateprot(ic); 1548 sc->sc_ic_flags = ic->ic_flags; 1549 } 1550 } 1551 1552 static void 1553 rt2860_gp_intr(struct rt2860_softc *sc) 1554 { 1555 struct ieee80211com *ic = &sc->sc_ic; 1556 int s; 1557 1558 DPRINTFN(2, ("GP timeout state=%d\n", ic->ic_state)); 1559 1560 s = splnet(); 1561 if (ic->ic_state == IEEE80211_S_SCAN) 1562 ieee80211_next_scan(ic); 1563 else if (ic->ic_state == IEEE80211_S_RUN) 1564 rt2860_updatestats(sc); 1565 splx(s); 1566 } 1567 1568 int 1569 rt2860_intr(void *arg) 1570 { 1571 struct rt2860_softc *sc = arg; 1572 uint32_t r; 1573 1574 r = RAL_READ(sc, RT2860_INT_STATUS); 1575 if (__predict_false(r == 0xffffffff)) 1576 return 0; /* device likely went away */ 1577 if (r == 0) 1578 return 0; /* not for us */ 1579 1580 softint_schedule(sc->sc_soft_ih); 1581 return 1; 1582 } 1583 1584 static void 1585 rt2860_softintr(void *arg) 1586 { 1587 struct rt2860_softc *sc = arg; 1588 uint32_t r; 1589 1590 r = RAL_READ(sc, RT2860_INT_STATUS); 1591 if (__predict_false(r == 0xffffffff)) 1592 goto out; /* device likely went away */ 1593 if (r == 0) 1594 goto out; 1595 1596 /* acknowledge interrupts */ 1597 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1598 1599 if (r & RT2860_TX_RX_COHERENT) 1600 rt2860_intr_coherent(sc); 1601 1602 if (r & RT2860_MAC_INT_2) /* TX status */ 1603 rt2860_drain_stats_fifo(sc); 1604 1605 if (r & RT2860_TX_DONE_INT5) 1606 rt2860_tx_intr(sc, 5); 1607 1608 if (r & RT2860_RX_DONE_INT) 1609 rt2860_rx_intr(sc); 1610 1611 if (r & RT2860_TX_DONE_INT4) 1612 rt2860_tx_intr(sc, 4); 1613 1614 if (r & RT2860_TX_DONE_INT3) 1615 rt2860_tx_intr(sc, 3); 1616 1617 if (r & RT2860_TX_DONE_INT2) 1618 rt2860_tx_intr(sc, 2); 1619 1620 if (r & RT2860_TX_DONE_INT1) 1621 rt2860_tx_intr(sc, 1); 1622 1623 if (r & RT2860_TX_DONE_INT0) 1624 rt2860_tx_intr(sc, 0); 1625 1626 if (r & RT2860_MAC_INT_0) /* TBTT */ 1627 rt2860_tbtt_intr(sc); 1628 1629 if (r & RT2860_MAC_INT_3) { /* Auto wakeup */ 1630 /* TBD wakeup */ 1631 } 1632 1633 if (r & RT2860_MAC_INT_4) /* GP timer */ 1634 rt2860_gp_intr(sc); 1635 1636 out: 1637 /* enable interrupts */ 1638 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 1639 } 1640 1641 static int 1642 rt2860_tx(struct rt2860_softc *sc, struct mbuf **m0, struct ieee80211_node *ni) 1643 { 1644 struct ieee80211com *ic = &sc->sc_ic; 1645 struct rt2860_node *rn = (void *)ni; 1646 struct rt2860_tx_ring *ring; 1647 struct rt2860_tx_data *data; 1648 struct rt2860_txd *txd; 1649 struct rt2860_txwi *txwi; 1650 struct ieee80211_frame *wh; 1651 struct mbuf *m = *m0; 1652 bus_dma_segment_t *seg; 1653 u_int hdrlen; 1654 uint16_t qos, dur; 1655 uint8_t type, qsel, mcs, pid, tid, qid; 1656 int nsegs, hasqos, ridx, ctl_ridx; 1657 1658 /* the data pool contains at least one element, pick the first */ 1659 data = SLIST_FIRST(&sc->data_pool); 1660 1661 wh = mtod(m, struct ieee80211_frame *); 1662 #ifndef HW_CRYPTO 1663 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1664 struct ieee80211_key *k = ieee80211_crypto_encap(ic, ni, m); 1665 if (k == NULL) { 1666 m_freem(m); 1667 *m0 = NULL; 1668 return ENOBUFS; 1669 } 1670 1671 /* packet header may have moved, reset our local pointer */ 1672 wh = mtod(m, struct ieee80211_frame *); 1673 } 1674 #endif 1675 1676 hdrlen = ieee80211_anyhdrsize(wh); 1677 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1678 1679 if ((hasqos = ieee80211_has_qos(wh))) { 1680 qos = ieee80211_get_qos(wh); 1681 tid = qos & IEEE80211_QOS_TID; 1682 qid = TID_TO_WME_AC(tid); 1683 } else { 1684 qos = 0; 1685 tid = 0; 1686 qid = (type == IEEE80211_FC0_TYPE_MGT) ? 1687 sc->mgtqid : WME_AC_BE; 1688 } 1689 KASSERT(qid < MAXQS); 1690 ring = &sc->txq[qid]; 1691 1692 /* pickup a rate index */ 1693 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1694 type != IEEE80211_FC0_TYPE_DATA) { 1695 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1696 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 1697 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1698 } else if (ic->ic_fixed_rate != -1) { 1699 ridx = sc->fixed_ridx; 1700 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1701 } else { 1702 ridx = rn->ridx[ni->ni_txrate]; 1703 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 1704 } 1705 1706 /* get MCS code from rate index */ 1707 mcs = rt2860_rates[ridx].mcs; 1708 1709 /* setup TX Wireless Information */ 1710 txwi = data->txwi; 1711 txwi->flags = 0; 1712 /* let HW generate seq numbers for non-QoS frames */ 1713 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 1714 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? rn->wcid : 0xff; 1715 txwi->len = htole16(m->m_pkthdr.len); 1716 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1717 txwi->phy = htole16(RT2860_PHY_CCK); 1718 if (ridx != RT2860_RIDX_CCK1 && 1719 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1720 mcs |= RT2860_PHY_SHPRE; 1721 } else 1722 txwi->phy = htole16(RT2860_PHY_OFDM); 1723 txwi->phy |= htole16(mcs); 1724 1725 /* 1726 * We store the MCS code into the driver-private PacketID field. 1727 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1728 * that we know at which initial rate the frame was transmitted. 1729 * We add 1 to the MCS code because setting the PacketID field to 1730 * 0 means that we don't want feedback in TX_STAT_FIFO. 1731 */ 1732 pid = (mcs + 1) & 0xf; 1733 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1734 1735 /* check if RTS/CTS or CTS-to-self protection is required */ 1736 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1737 (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold || 1738 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1739 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1740 txwi->txop = RT2860_TX_TXOP_HT; 1741 else 1742 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1743 1744 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1745 (!hasqos || (qos & IEEE80211_QOS_ACKPOLICY) != 1746 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1747 txwi->xflags |= RT2860_TX_ACK; 1748 1749 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1750 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 1751 else 1752 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 1753 *(uint16_t *)wh->i_dur = htole16(dur); 1754 } 1755 #ifndef IEEE80211_STA_ONLY 1756 /* ask MAC to insert timestamp into probe responses */ 1757 if ((wh->i_fc[0] & 1758 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1759 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1760 /* NOTE: beacons do not pass through tx_data() */ 1761 txwi->flags |= RT2860_TX_TS; 1762 #endif 1763 1764 if (__predict_false(sc->sc_drvbpf != NULL)) { 1765 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1766 1767 tap->wt_flags = 0; 1768 tap->wt_rate = rt2860_rates[ridx].rate; 1769 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1770 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1771 tap->wt_hwqueue = qid; 1772 if (mcs & RT2860_PHY_SHPRE) 1773 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1774 1775 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 1776 } 1777 1778 /* copy and trim 802.11 header */ 1779 memcpy(txwi + 1, wh, hdrlen); 1780 m_adj(m, hdrlen); 1781 1782 KASSERT (ring->queued <= RT2860_TX_RING_ONEMORE); /* <1> */ 1783 if (bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, BUS_DMA_NOWAIT)) { 1784 struct mbuf *m_new = m_defrag(m, M_DONTWAIT); 1785 if (m_new != NULL) { 1786 /* m got freed */ 1787 m = m_new; 1788 *m0 = m_new; 1789 } else { 1790 return (ENOBUFS); 1791 } 1792 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1793 data->map, m, BUS_DMA_NOWAIT)) 1794 return (EFBIG); 1795 } 1796 1797 /* The map will fit into the tx ring: (a "full" ring may have a few 1798 * unused descriptors, at most (txds(MAX_SCATTER) - 1)) 1799 * 1800 * ring->queued + txds(data->map->nsegs) 1801 * <= { <0> data->map->nsegs <= MAX_SCATTER } 1802 * ring->queued + txds(MAX_SCATTER) 1803 * <= { <1> ring->queued <= TX_RING_MAX - txds(MAX_SCATTER) } 1804 * TX_RING_MAX - txds(MAX_SCATTER) + txds(MAX_SCATTER) 1805 * <= { arithmetic } 1806 * TX_RING_MAX 1807 */ 1808 1809 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1810 1811 /* first segment is TXWI + 802.11 header */ 1812 txd = &ring->txd[ring->cur]; 1813 txd->sdp0 = htole32(data->paddr); 1814 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + hdrlen); 1815 txd->flags = qsel; 1816 1817 /* setup payload segments */ 1818 seg = data->map->dm_segs; 1819 for (nsegs = data->map->dm_nsegs; nsegs >= 2; nsegs -= 2) { 1820 txd->sdp1 = htole32(seg->ds_addr); 1821 txd->sdl1 = htole16(seg->ds_len); 1822 seg++; 1823 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1824 /* grab a new Tx descriptor */ 1825 txd = &ring->txd[ring->cur]; 1826 txd->sdp0 = htole32(seg->ds_addr); 1827 txd->sdl0 = htole16(seg->ds_len); 1828 txd->flags = qsel; 1829 seg++; 1830 } 1831 /* finalize last segment */ 1832 if (nsegs > 0) { 1833 txd->sdp1 = htole32(seg->ds_addr); 1834 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1835 } else { 1836 txd->sdl0 |= htole16(RT2860_TX_LS0); 1837 txd->sdl1 = 0; 1838 } 1839 1840 /* remove from the free pool and link it into the SW Tx slot */ 1841 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1842 data->m = m; 1843 data->ni = ni; 1844 ring->data[ring->cur] = data; 1845 1846 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 1847 (uintptr_t)txwi - (uintptr_t)sc->txwi_vaddr, RT2860_TXWI_DMASZ, 1848 BUS_DMASYNC_PREWRITE); 1849 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1850 BUS_DMASYNC_PREWRITE); 1851 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1852 BUS_DMASYNC_PREWRITE); 1853 1854 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1855 qid, txwi->wcid, data->map->dm_nsegs, ridx)); 1856 1857 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1858 ring->queued += 1 + (data->map->dm_nsegs / 2); 1859 if (ring->queued > RT2860_TX_RING_ONEMORE) 1860 sc->qfullmsk |= 1 << qid; 1861 1862 /* kick Tx */ 1863 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1864 1865 return 0; 1866 } 1867 1868 static void 1869 rt2860_start(struct ifnet *ifp) 1870 { 1871 struct rt2860_softc *sc = ifp->if_softc; 1872 struct ieee80211com *ic = &sc->sc_ic; 1873 struct ether_header *eh; 1874 struct ieee80211_node *ni; 1875 struct mbuf *m; 1876 1877 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1878 return; 1879 1880 for (;;) { 1881 if (SLIST_EMPTY(&sc->data_pool) || sc->qfullmsk != 0) { 1882 DPRINTF(("%s: stuffup\n", __func__)); 1883 ifp->if_flags |= IFF_OACTIVE; 1884 break; 1885 } 1886 /* send pending management frames first */ 1887 IF_DEQUEUE(&ic->ic_mgtq, m); 1888 if (m != NULL) { 1889 ni = M_GETCTX(m, struct ieee80211_node *); 1890 M_CLEARCTX(m); 1891 DPRINTF(("%s: send management\n", __func__)); 1892 goto sendit; 1893 } 1894 if (ic->ic_state != IEEE80211_S_RUN) { 1895 DPRINTF(("%s: not running %d\n", __func__, 1896 ic->ic_state)); 1897 break; 1898 } 1899 1900 /* encapsulate and send data frames */ 1901 IFQ_DEQUEUE(&ifp->if_snd, m); 1902 if (m == NULL) { 1903 DPRINTF(("%s: nothing to send\n", __func__)); 1904 break; 1905 } 1906 if (m->m_len < (int)sizeof(*eh) && 1907 (m = m_pullup(m, sizeof(*eh))) == NULL) { 1908 DPRINTF(("%s: nothing to send\n", __func__)); 1909 if_statinc(ifp, if_oerrors); 1910 continue; 1911 } 1912 1913 eh = mtod(m, struct ether_header *); 1914 1915 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1916 if (ni == NULL) { 1917 DPRINTF(("%s: can't find tx node\n", __func__)); 1918 m_freem(m); 1919 if_statinc(ifp, if_oerrors); 1920 continue; 1921 } 1922 1923 bpf_mtap(ifp, m, BPF_D_OUT); 1924 1925 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 1926 DPRINTF(("%s: can't encap\n", __func__)); 1927 ieee80211_free_node(ni); 1928 if_statinc(ifp, if_oerrors); 1929 continue; 1930 } 1931 sendit: 1932 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 1933 1934 if (rt2860_tx(sc, &m, ni) != 0) { 1935 DPRINTF(("%s: can't tx\n", __func__)); 1936 m_freem(m); 1937 ieee80211_free_node(ni); 1938 if_statinc(ifp, if_oerrors); 1939 continue; 1940 } 1941 1942 sc->sc_tx_timer = 5; 1943 ifp->if_timer = 1; 1944 } 1945 } 1946 1947 static void 1948 rt2860_watchdog(struct ifnet *ifp) 1949 { 1950 struct rt2860_softc *sc = ifp->if_softc; 1951 struct ieee80211com *ic = &sc->sc_ic; 1952 1953 ifp->if_timer = 0; 1954 1955 if (sc->sc_tx_timer > 0) { 1956 if (--sc->sc_tx_timer == 0) { 1957 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1958 rt2860_stop(ifp, 0); 1959 rt2860_init(ifp); 1960 if_statinc(ifp, if_oerrors); 1961 return; 1962 } 1963 ifp->if_timer = 1; 1964 } 1965 1966 ieee80211_watchdog(ic); 1967 } 1968 1969 static int 1970 rt2860_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1971 { 1972 struct rt2860_softc *sc = ifp->if_softc; 1973 struct ieee80211com *ic = &sc->sc_ic; 1974 int s, error = 0; 1975 1976 s = splnet(); 1977 1978 switch (cmd) { 1979 case SIOCSIFFLAGS: 1980 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1981 break; 1982 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1983 case IFF_UP|IFF_RUNNING: 1984 rt2860_update_promisc(ifp); 1985 break; 1986 case IFF_UP: 1987 rt2860_init(ifp); 1988 break; 1989 case IFF_RUNNING: 1990 rt2860_stop(ifp, 1); 1991 break; 1992 case 0: 1993 break; 1994 } 1995 break; 1996 1997 case SIOCADDMULTI: 1998 case SIOCDELMULTI: 1999 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2000 /* setup multicast filter, etc */ 2001 error = 0; 2002 } 2003 break; 2004 2005 case SIOCS80211CHANNEL: 2006 /* 2007 * This allows for fast channel switching in monitor mode 2008 * (used by kismet). In IBSS mode, we must explicitly reset 2009 * the interface to generate a new beacon frame. 2010 */ 2011 error = ieee80211_ioctl(ic, cmd, data); 2012 if (error == ENETRESET && 2013 ic->ic_opmode == IEEE80211_M_MONITOR) { 2014 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2015 (IFF_UP | IFF_RUNNING)) 2016 rt2860_switch_chan(sc, ic->ic_ibss_chan); 2017 error = 0; 2018 } 2019 break; 2020 2021 default: 2022 error = ieee80211_ioctl(ic, cmd, data); 2023 } 2024 2025 if (error == ENETRESET) { 2026 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2027 (IFF_UP | IFF_RUNNING)) { 2028 rt2860_stop(ifp, 0); 2029 rt2860_init(ifp); 2030 } 2031 error = 0; 2032 } 2033 2034 splx(s); 2035 2036 return error; 2037 } 2038 2039 /* 2040 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2041 * We access the BBP through the 8051 microcontroller unit which means that 2042 * the microcode must be loaded first. 2043 */ 2044 static void 2045 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2046 { 2047 int ntries; 2048 2049 for (ntries = 0; ntries < 100; ntries++) { 2050 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2051 break; 2052 DELAY(1); 2053 } 2054 if (ntries == 100) { 2055 aprint_error_dev(sc->sc_dev, 2056 "could not write to BBP through MCU\n"); 2057 return; 2058 } 2059 2060 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2061 RT2860_BBP_CSR_KICK | reg << 8 | val); 2062 RAL_BARRIER_WRITE(sc); 2063 2064 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2065 DELAY(1000); 2066 } 2067 2068 static uint8_t 2069 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2070 { 2071 uint32_t val; 2072 int ntries; 2073 2074 for (ntries = 0; ntries < 100; ntries++) { 2075 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2076 break; 2077 DELAY(1); 2078 } 2079 if (ntries == 100) { 2080 aprint_error_dev(sc->sc_dev, 2081 "could not read from BBP through MCU\n"); 2082 return 0; 2083 } 2084 2085 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2086 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2087 RAL_BARRIER_WRITE(sc); 2088 2089 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2090 DELAY(1000); 2091 2092 for (ntries = 0; ntries < 100; ntries++) { 2093 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2094 if (!(val & RT2860_BBP_CSR_KICK)) 2095 return val & 0xff; 2096 DELAY(1); 2097 } 2098 aprint_error_dev(sc->sc_dev, "could not read from BBP through MCU\n"); 2099 2100 return 0; 2101 } 2102 2103 /* 2104 * Write to one of the 4 programmable 24-bit RF registers. 2105 */ 2106 static void 2107 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2108 { 2109 uint32_t tmp; 2110 int ntries; 2111 2112 for (ntries = 0; ntries < 100; ntries++) { 2113 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2114 break; 2115 DELAY(1); 2116 } 2117 if (ntries == 100) { 2118 aprint_error_dev(sc->sc_dev, "could not write to RF\n"); 2119 return; 2120 } 2121 2122 /* RF registers are 24-bit on the RT2860 */ 2123 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2124 (val & 0x3fffff) << 2 | (reg & 3); 2125 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2126 } 2127 2128 static uint8_t 2129 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2130 { 2131 uint32_t tmp; 2132 int ntries; 2133 2134 for (ntries = 0; ntries < 100; ntries++) { 2135 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2136 break; 2137 DELAY(1); 2138 } 2139 if (ntries == 100) { 2140 aprint_error_dev(sc->sc_dev, "could not read RF register\n"); 2141 return 0xff; 2142 } 2143 tmp = RT3070_RF_KICK | reg << 8; 2144 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2145 2146 for (ntries = 0; ntries < 100; ntries++) { 2147 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2148 if (!(tmp & RT3070_RF_KICK)) 2149 break; 2150 DELAY(1); 2151 } 2152 if (ntries == 100) { 2153 aprint_error_dev(sc->sc_dev, "could not read RF register\n"); 2154 return 0xff; 2155 } 2156 return tmp & 0xff; 2157 } 2158 2159 static void 2160 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2161 { 2162 uint32_t tmp; 2163 int ntries; 2164 2165 for (ntries = 0; ntries < 10; ntries++) { 2166 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2167 break; 2168 DELAY(10); 2169 } 2170 if (ntries == 10) { 2171 aprint_error_dev(sc->sc_dev, "could not write to RF\n"); 2172 return; 2173 } 2174 2175 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2176 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2177 } 2178 2179 /* 2180 * Send a command to the 8051 microcontroller unit. 2181 */ 2182 static int 2183 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2184 { 2185 int slot, ntries; 2186 uint32_t tmp; 2187 uint8_t cid; 2188 2189 for (ntries = 0; ntries < 100; ntries++) { 2190 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2191 break; 2192 DELAY(2); 2193 } 2194 if (ntries == 100) 2195 return EIO; 2196 2197 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2198 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2199 RAL_BARRIER_WRITE(sc); 2200 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2201 2202 if (!wait) 2203 return 0; 2204 /* wait for the command to complete */ 2205 for (ntries = 0; ntries < 200; ntries++) { 2206 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2207 /* find the command slot */ 2208 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2209 if ((tmp & 0xff) == cid) 2210 break; 2211 if (slot < 4) 2212 break; 2213 DELAY(100); 2214 } 2215 if (ntries == 200) { 2216 /* clear command and status */ 2217 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2218 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2219 return ETIMEDOUT; 2220 } 2221 /* get command status (1 means success) */ 2222 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2223 tmp = (tmp >> (slot * 8)) & 0xff; 2224 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2225 cmd, slot, tmp)); 2226 /* clear command and status */ 2227 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2228 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2229 return (tmp == 1) ? 0 : EIO; 2230 } 2231 2232 static void 2233 rt2860_enable_mrr(struct rt2860_softc *sc) 2234 { 2235 #define CCK(mcs) (mcs) 2236 #define OFDM(mcs) (1U << 3 | (mcs)) 2237 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2238 OFDM(6) << 28 | /* 54->48 */ 2239 OFDM(5) << 24 | /* 48->36 */ 2240 OFDM(4) << 20 | /* 36->24 */ 2241 OFDM(3) << 16 | /* 24->18 */ 2242 OFDM(2) << 12 | /* 18->12 */ 2243 OFDM(1) << 8 | /* 12-> 9 */ 2244 OFDM(0) << 4 | /* 9-> 6 */ 2245 OFDM(0)); /* 6-> 6 */ 2246 2247 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2248 CCK(2) << 12 | /* 11->5.5 */ 2249 CCK(1) << 8 | /* 5.5-> 2 */ 2250 CCK(0) << 4 | /* 2-> 1 */ 2251 CCK(0)); /* 1-> 1 */ 2252 #undef OFDM 2253 #undef CCK 2254 } 2255 2256 static void 2257 rt2860_set_txpreamble(struct rt2860_softc *sc) 2258 { 2259 uint32_t tmp; 2260 2261 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2262 tmp &= ~RT2860_CCK_SHORT_EN; 2263 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2264 tmp |= RT2860_CCK_SHORT_EN; 2265 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2266 } 2267 2268 static void 2269 rt2860_set_basicrates(struct rt2860_softc *sc) 2270 { 2271 struct ieee80211com *ic = &sc->sc_ic; 2272 2273 /* set basic rates mask */ 2274 if (ic->ic_curmode == IEEE80211_MODE_11B) 2275 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 2276 else if (ic->ic_curmode == IEEE80211_MODE_11A) 2277 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 2278 else /* 11g */ 2279 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 2280 } 2281 2282 static void 2283 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2284 { 2285 uint32_t tmp; 2286 uint8_t agc; 2287 2288 /* Wait for BBP to settle */ 2289 DELAY(1000); 2290 2291 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2292 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2293 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2294 rt2860_mcu_bbp_write(sc, 86, 0x00); 2295 2296 if (group == 0) { 2297 if (sc->ext_2ghz_lna) { 2298 rt2860_mcu_bbp_write(sc, 82, 0x62); 2299 rt2860_mcu_bbp_write(sc, 75, 0x46); 2300 } else { 2301 rt2860_mcu_bbp_write(sc, 82, 0x84); 2302 rt2860_mcu_bbp_write(sc, 75, 0x50); 2303 } 2304 } else { 2305 if (sc->mac_ver == 0x3572) 2306 rt2860_mcu_bbp_write(sc, 82, 0x94); 2307 else 2308 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2309 2310 if (sc->ext_5ghz_lna) 2311 rt2860_mcu_bbp_write(sc, 75, 0x46); 2312 else 2313 rt2860_mcu_bbp_write(sc, 75, 0x50); 2314 } 2315 2316 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2317 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2318 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2319 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2320 2321 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2322 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2323 if (sc->nrxchains > 1) 2324 tmp |= RT2860_LNA_PE1_EN; 2325 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2326 tmp |= RT3593_LNA_PE2_EN; 2327 if (group == 0) { /* 2GHz */ 2328 tmp |= RT2860_PA_PE_G0_EN; 2329 if (sc->ntxchains > 1) 2330 tmp |= RT2860_PA_PE_G1_EN; 2331 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2332 tmp |= RT3593_PA_PE_G2_EN; 2333 } else { /* 5GHz */ 2334 tmp |= RT2860_PA_PE_A0_EN; 2335 if (sc->ntxchains > 1) 2336 tmp |= RT2860_PA_PE_A1_EN; 2337 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2338 tmp |= RT3593_PA_PE_A2_EN; 2339 } 2340 if (sc->mac_ver == 0x3572) { 2341 rt3090_rf_write(sc, 8, 0x00); 2342 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2343 rt3090_rf_write(sc, 8, 0x80); 2344 } else 2345 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2346 2347 if (sc->mac_ver == 0x3593) { 2348 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2349 if (sc->sc_flags & RT2860_PCIE) { 2350 tmp &= ~0x01010000; 2351 if (group == 0) 2352 tmp |= 0x00010000; 2353 } else { 2354 tmp &= ~0x00008080; 2355 if (group == 0) 2356 tmp |= 0x00000080; 2357 } 2358 tmp = (tmp & ~0x00001000) | 0x00000010; 2359 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2360 } 2361 2362 /* set initial AGC value */ 2363 if (group == 0) { /* 2GHz band */ 2364 if (sc->mac_ver >= 0x3071) 2365 agc = 0x1c + sc->lna[0] * 2; 2366 else 2367 agc = 0x2e + sc->lna[0]; 2368 } else { /* 5GHz band */ 2369 if (sc->mac_ver == 0x3572) 2370 agc = 0x22 + (sc->lna[group] * 5) / 3; 2371 else 2372 agc = 0x32 + (sc->lna[group] * 5) / 3; 2373 } 2374 rt2860_mcu_bbp_write(sc, 66, agc); 2375 2376 DELAY(1000); 2377 } 2378 2379 static void 2380 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2381 { 2382 const struct rfprog *rfprog = rt2860_rf2850; 2383 uint32_t r2, r3, r4; 2384 int8_t txpow1, txpow2; 2385 u_int i; 2386 2387 /* find the settings for this channel (we know it exists) */ 2388 for (i = 0; rfprog[i].chan != chan; i++); 2389 2390 r2 = rfprog[i].r2; 2391 if (sc->ntxchains == 1) 2392 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2393 if (sc->nrxchains == 1) 2394 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2395 else if (sc->nrxchains == 2) 2396 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2397 2398 /* use Tx power values from EEPROM */ 2399 txpow1 = sc->txpow1[i]; 2400 txpow2 = sc->txpow2[i]; 2401 if (chan > 14) { 2402 if (txpow1 >= 0) 2403 txpow1 = txpow1 << 1 | 1; 2404 else 2405 txpow1 = (7 + txpow1) << 1; 2406 if (txpow2 >= 0) 2407 txpow2 = txpow2 << 1 | 1; 2408 else 2409 txpow2 = (7 + txpow2) << 1; 2410 } 2411 r3 = rfprog[i].r3 | txpow1 << 7; 2412 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2413 2414 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2415 rt2860_rf_write(sc, RT2860_RF2, r2); 2416 rt2860_rf_write(sc, RT2860_RF3, r3); 2417 rt2860_rf_write(sc, RT2860_RF4, r4); 2418 2419 DELAY(200); 2420 2421 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2422 rt2860_rf_write(sc, RT2860_RF2, r2); 2423 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2424 rt2860_rf_write(sc, RT2860_RF4, r4); 2425 2426 DELAY(200); 2427 2428 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2429 rt2860_rf_write(sc, RT2860_RF2, r2); 2430 rt2860_rf_write(sc, RT2860_RF3, r3); 2431 rt2860_rf_write(sc, RT2860_RF4, r4); 2432 } 2433 2434 static void 2435 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2436 { 2437 int8_t txpow1, txpow2; 2438 uint8_t rf; 2439 int i; 2440 2441 KASSERT(chan >= 1 && chan <= 14); /* RT3090 is 2GHz only */ 2442 2443 /* find the settings for this channel (we know it exists) */ 2444 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2445 2446 /* use Tx power values from EEPROM */ 2447 txpow1 = sc->txpow1[i]; 2448 txpow2 = sc->txpow2[i]; 2449 2450 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2451 rf = rt3090_rf_read(sc, 3); 2452 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2453 rt3090_rf_write(sc, 3, rf); 2454 rf = rt3090_rf_read(sc, 6); 2455 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2456 rt3090_rf_write(sc, 6, rf); 2457 2458 /* set Tx0 power */ 2459 rf = rt3090_rf_read(sc, 12); 2460 rf = (rf & ~0x1f) | txpow1; 2461 rt3090_rf_write(sc, 12, rf); 2462 2463 /* set Tx1 power */ 2464 rf = rt3090_rf_read(sc, 13); 2465 rf = (rf & ~0x1f) | txpow2; 2466 rt3090_rf_write(sc, 13, rf); 2467 2468 rf = rt3090_rf_read(sc, 1); 2469 rf &= ~0xfc; 2470 if (sc->ntxchains == 1) 2471 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2472 else if (sc->ntxchains == 2) 2473 rf |= RT3070_TX2_PD; 2474 if (sc->nrxchains == 1) 2475 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2476 else if (sc->nrxchains == 2) 2477 rf |= RT3070_RX2_PD; 2478 rt3090_rf_write(sc, 1, rf); 2479 2480 /* set RF offset */ 2481 rf = rt3090_rf_read(sc, 23); 2482 rf = (rf & ~0x7f) | sc->freq; 2483 rt3090_rf_write(sc, 23, rf); 2484 2485 /* program RF filter */ 2486 rf = rt3090_rf_read(sc, 24); /* Tx */ 2487 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2488 rt3090_rf_write(sc, 24, rf); 2489 rf = rt3090_rf_read(sc, 31); /* Rx */ 2490 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2491 rt3090_rf_write(sc, 31, rf); 2492 2493 /* enable RF tuning */ 2494 rf = rt3090_rf_read(sc, 7); 2495 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2496 } 2497 2498 static void 2499 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2500 { 2501 uint8_t h20mhz, rf, tmp; 2502 int8_t txpow1, txpow2; 2503 int i; 2504 2505 /* RT5390 is 2GHz only */ 2506 KASSERT(chan >= 1 && chan <= 14); 2507 2508 /* find the settings for this channel (we know it exists) */ 2509 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2510 2511 /* use Tx power values from EEPROM */ 2512 txpow1 = sc->txpow1[i]; 2513 txpow2 = sc->txpow2[i]; 2514 2515 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2516 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2517 rf = rt3090_rf_read(sc, 11); 2518 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2519 rt3090_rf_write(sc, 11, rf); 2520 2521 rf = rt3090_rf_read(sc, 49); 2522 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2523 /* the valid range of the RF R49 is 0x00~0x27 */ 2524 if ((rf & 0x3f) > 0x27) 2525 rf = (rf & ~0x3f) | 0x27; 2526 rt3090_rf_write(sc, 49, rf); 2527 if (sc->mac_ver == 0x5392) { 2528 rf = rt3090_rf_read(sc, 50); 2529 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2530 /* the valid range of the RF R50 is 0x00~0x27 */ 2531 if ((rf & 0x3f) > 0x27) 2532 rf = (rf & ~0x3f) | 0x27; 2533 rt3090_rf_write(sc, 50, rf); 2534 } 2535 2536 rf = rt3090_rf_read(sc, 1); 2537 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2538 if (sc->mac_ver == 0x5392) 2539 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2540 rt3090_rf_write(sc, 1, rf); 2541 2542 rf = rt3090_rf_read(sc, 2); 2543 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2544 DELAY(1000); 2545 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2546 2547 rf = rt3090_rf_read(sc, 17); 2548 tmp = rf; 2549 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2550 rf = MIN(rf, 0x5f); 2551 if (tmp != rf) 2552 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2553 2554 if (sc->mac_ver == 0x5390) { 2555 if (chan <= 4) 2556 rf = 0x73; 2557 else if (chan >= 5 && chan <= 6) 2558 rf = 0x63; 2559 else if (chan >= 7 && chan <= 10) 2560 rf = 0x53; 2561 else 2562 rf = 43; 2563 rt3090_rf_write(sc, 55, rf); 2564 2565 if (chan == 1) 2566 rf = 0x0c; 2567 else if (chan == 2) 2568 rf = 0x0b; 2569 else if (chan == 3) 2570 rf = 0x0a; 2571 else if (chan >= 4 && chan <= 6) 2572 rf = 0x09; 2573 else if (chan >= 7 && chan <= 12) 2574 rf = 0x08; 2575 else if (chan == 13) 2576 rf = 0x07; 2577 else 2578 rf = 0x06; 2579 rt3090_rf_write(sc, 59, rf); 2580 } 2581 2582 /* Tx/Rx h20M */ 2583 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2584 rf = rt3090_rf_read(sc, 30); 2585 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2586 rt3090_rf_write(sc, 30, rf); 2587 2588 /* Rx BB filter VCM */ 2589 rf = rt3090_rf_read(sc, 30); 2590 rf = (rf & ~0x18) | 0x10; 2591 rt3090_rf_write(sc, 30, rf); 2592 2593 /* Initiate VCO calibration. */ 2594 rf = rt3090_rf_read(sc, 3); 2595 rf |= RT3593_VCOCAL; 2596 rt3090_rf_write(sc, 3, rf); 2597 } 2598 2599 static void 2600 rt3090_rf_init(struct rt2860_softc *sc) 2601 { 2602 uint32_t tmp; 2603 uint8_t rf, bbp; 2604 int i; 2605 2606 rf = rt3090_rf_read(sc, 30); 2607 /* toggle RF R30 bit 7 */ 2608 rt3090_rf_write(sc, 30, rf | 0x80); 2609 DELAY(1000); 2610 rt3090_rf_write(sc, 30, rf & ~0x80); 2611 2612 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2613 tmp &= ~0x1f000000; 2614 if (sc->patch_dac && sc->mac_rev < 0x0211) 2615 tmp |= 0x0d000000; /* 1.35V */ 2616 else 2617 tmp |= 0x01000000; /* 1.2V */ 2618 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2619 2620 /* patch LNA_PE_G1 */ 2621 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2622 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2623 2624 /* initialize RF registers to default value */ 2625 if (sc->mac_ver == 0x3572) { 2626 for (i = 0; i < (int)__arraycount(rt3572_def_rf); i++) { 2627 rt3090_rf_write(sc, rt3572_def_rf[i].reg, 2628 rt3572_def_rf[i].val); 2629 } 2630 } else { 2631 for (i = 0; i < (int)__arraycount(rt3090_def_rf); i++) { 2632 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2633 rt3090_def_rf[i].val); 2634 } 2635 } 2636 2637 /* select 20MHz bandwidth */ 2638 rt3090_rf_write(sc, 31, 0x14); 2639 2640 rf = rt3090_rf_read(sc, 6); 2641 rt3090_rf_write(sc, 6, rf | 0x40); 2642 2643 if (sc->mac_ver != 0x3593) { 2644 /* calibrate filter for 20MHz bandwidth */ 2645 sc->rf24_20mhz = 0x1f; /* default value */ 2646 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2647 2648 /* select 40MHz bandwidth */ 2649 bbp = rt2860_mcu_bbp_read(sc, 4); 2650 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2651 rf = rt3090_rf_read(sc, 31); 2652 rt3090_rf_write(sc, 31, rf | 0x20); 2653 2654 /* calibrate filter for 40MHz bandwidth */ 2655 sc->rf24_40mhz = 0x2f; /* default value */ 2656 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2657 2658 /* go back to 20MHz bandwidth */ 2659 bbp = rt2860_mcu_bbp_read(sc, 4); 2660 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2661 } 2662 if (sc->mac_rev < 0x0211) 2663 rt3090_rf_write(sc, 27, 0x03); 2664 2665 tmp = RAL_READ(sc, RT3070_OPT_14); 2666 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2667 2668 if (sc->rf_rev == RT3070_RF_3020) 2669 rt3090_set_rx_antenna(sc, 0); 2670 2671 bbp = rt2860_mcu_bbp_read(sc, 138); 2672 if (sc->mac_ver == 0x3593) { 2673 if (sc->ntxchains == 1) 2674 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2675 else if (sc->ntxchains == 2) 2676 bbp |= 0x40; /* turn off DAC2 */ 2677 if (sc->nrxchains == 1) 2678 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2679 else if (sc->nrxchains == 2) 2680 bbp &= ~0x04; /* turn off ADC2 */ 2681 } else { 2682 if (sc->ntxchains == 1) 2683 bbp |= 0x20; /* turn off DAC1 */ 2684 if (sc->nrxchains == 1) 2685 bbp &= ~0x02; /* turn off ADC1 */ 2686 } 2687 rt2860_mcu_bbp_write(sc, 138, bbp); 2688 2689 rf = rt3090_rf_read(sc, 1); 2690 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2691 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2692 rt3090_rf_write(sc, 1, rf); 2693 2694 rf = rt3090_rf_read(sc, 15); 2695 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2696 2697 rf = rt3090_rf_read(sc, 17); 2698 rf &= ~RT3070_TX_LO1; 2699 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2700 rf |= 0x20; /* fix for long range Rx issue */ 2701 if (sc->txmixgain_2ghz >= 2) 2702 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2703 rt3090_rf_write(sc, 17, rf); 2704 2705 rf = rt3090_rf_read(sc, 20); 2706 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2707 2708 rf = rt3090_rf_read(sc, 21); 2709 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2710 } 2711 2712 static void 2713 rt5390_rf_init(struct rt2860_softc *sc) 2714 { 2715 uint8_t rf, bbp; 2716 int i; 2717 2718 rf = rt3090_rf_read(sc, 2); 2719 /* Toggle RF R2 bit 7. */ 2720 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2721 DELAY(1000); 2722 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2723 2724 /* Initialize RF registers to default value. */ 2725 if (sc->mac_ver == 0x5392) { 2726 for (i = 0; i < __arraycount(rt5392_def_rf); i++) { 2727 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2728 rt5392_def_rf[i].val); 2729 } 2730 } else { 2731 for (i = 0; i < __arraycount(rt5390_def_rf); i++) { 2732 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2733 rt5390_def_rf[i].val); 2734 } 2735 } 2736 2737 sc->rf24_20mhz = 0x1f; 2738 sc->rf24_40mhz = 0x2f; 2739 2740 if (sc->mac_rev < 0x0211) 2741 rt3090_rf_write(sc, 27, 0x03); 2742 2743 /* Set led open drain enable. */ 2744 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2745 2746 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2747 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2748 2749 if (sc->mac_ver == 0x5390) 2750 rt3090_set_rx_antenna(sc, 0); 2751 2752 /* Patch RSSI inaccurate issue. */ 2753 rt2860_mcu_bbp_write(sc, 79, 0x13); 2754 rt2860_mcu_bbp_write(sc, 80, 0x05); 2755 rt2860_mcu_bbp_write(sc, 81, 0x33); 2756 2757 /* Enable DC filter. */ 2758 if (sc->mac_rev >= 0x0211) 2759 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2760 2761 bbp = rt2860_mcu_bbp_read(sc, 138); 2762 if (sc->ntxchains == 1) 2763 bbp |= 0x20; /* Turn off DAC1. */ 2764 if (sc->nrxchains == 1) 2765 bbp &= ~0x02; /* Turn off ADC1. */ 2766 rt2860_mcu_bbp_write(sc, 138, bbp); 2767 2768 /* Enable RX LO1 and LO2. */ 2769 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2770 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2771 2772 /* Avoid data lost and CRC error. */ 2773 rt2860_mcu_bbp_write(sc, 4, 2774 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2775 2776 rf = rt3090_rf_read(sc, 30); 2777 rf = (rf & ~0x18) | 0x10; 2778 rt3090_rf_write(sc, 30, rf); 2779 } 2780 2781 static void 2782 rt3090_rf_wakeup(struct rt2860_softc *sc) 2783 { 2784 uint32_t tmp; 2785 uint8_t rf; 2786 2787 if (sc->mac_ver == 0x3593) { 2788 /* enable VCO */ 2789 rf = rt3090_rf_read(sc, 1); 2790 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2791 2792 /* initiate VCO calibration */ 2793 rf = rt3090_rf_read(sc, 3); 2794 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2795 2796 /* enable VCO bias current control */ 2797 rf = rt3090_rf_read(sc, 6); 2798 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2799 2800 /* initiate res calibration */ 2801 rf = rt3090_rf_read(sc, 2); 2802 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2803 2804 /* set reference current control to 0.33 mA */ 2805 rf = rt3090_rf_read(sc, 22); 2806 rf &= ~RT3593_CP_IC_MASK; 2807 rf |= 1 << RT3593_CP_IC_SHIFT; 2808 rt3090_rf_write(sc, 22, rf); 2809 2810 /* enable RX CTB */ 2811 rf = rt3090_rf_read(sc, 46); 2812 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2813 2814 rf = rt3090_rf_read(sc, 20); 2815 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2816 rt3090_rf_write(sc, 20, rf); 2817 } else { 2818 /* enable RF block */ 2819 rf = rt3090_rf_read(sc, 1); 2820 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2821 2822 /* enable VCO bias current control */ 2823 rf = rt3090_rf_read(sc, 7); 2824 rt3090_rf_write(sc, 7, rf | 0x30); 2825 2826 rf = rt3090_rf_read(sc, 9); 2827 rt3090_rf_write(sc, 9, rf | 0x0e); 2828 2829 /* enable RX CTB */ 2830 rf = rt3090_rf_read(sc, 21); 2831 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2832 2833 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2834 rf = rt3090_rf_read(sc, 27); 2835 rf &= ~0x77; 2836 if (sc->mac_rev < 0x0211) 2837 rf |= 0x03; 2838 rt3090_rf_write(sc, 27, rf); 2839 } 2840 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2841 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2842 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2843 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2844 } 2845 } 2846 2847 static void 2848 rt5390_rf_wakeup(struct rt2860_softc *sc) 2849 { 2850 uint32_t tmp; 2851 uint8_t rf; 2852 2853 rf = rt3090_rf_read(sc, 1); 2854 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2855 RT3070_TX0_PD; 2856 if (sc->mac_ver == 0x5392) 2857 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2858 rt3090_rf_write(sc, 1, rf); 2859 2860 rf = rt3090_rf_read(sc, 6); 2861 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2862 if (sc->mac_ver == 0x5390) 2863 rf &= ~RT3593_VCO_IC; 2864 rt3090_rf_write(sc, 6, rf); 2865 2866 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2867 2868 rf = rt3090_rf_read(sc, 22); 2869 rf = (rf & ~0xe0) | 0x20; 2870 rt3090_rf_write(sc, 22, rf); 2871 2872 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2873 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2874 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2875 2876 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2877 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2878 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2879 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2880 } 2881 } 2882 2883 static int 2884 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2885 uint8_t *val) 2886 { 2887 uint8_t rf22, rf24; 2888 uint8_t bbp55_pb, bbp55_sb, delta; 2889 int ntries; 2890 2891 /* program filter */ 2892 rf24 = rt3090_rf_read(sc, 24); 2893 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2894 rt3090_rf_write(sc, 24, rf24); 2895 2896 /* enable baseband loopback mode */ 2897 rf22 = rt3090_rf_read(sc, 22); 2898 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2899 2900 /* set power and frequency of passband test tone */ 2901 rt2860_mcu_bbp_write(sc, 24, 0x00); 2902 for (ntries = 0; ntries < 100; ntries++) { 2903 /* transmit test tone */ 2904 rt2860_mcu_bbp_write(sc, 25, 0x90); 2905 DELAY(1000); 2906 /* read received power */ 2907 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2908 if (bbp55_pb != 0) 2909 break; 2910 } 2911 if (ntries == 100) 2912 return ETIMEDOUT; 2913 2914 /* set power and frequency of stopband test tone */ 2915 rt2860_mcu_bbp_write(sc, 24, 0x06); 2916 for (ntries = 0; ntries < 100; ntries++) { 2917 /* transmit test tone */ 2918 rt2860_mcu_bbp_write(sc, 25, 0x90); 2919 DELAY(1000); 2920 /* read received power */ 2921 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2922 2923 delta = bbp55_pb - bbp55_sb; 2924 if (delta > target) 2925 break; 2926 2927 /* reprogram filter */ 2928 rf24++; 2929 rt3090_rf_write(sc, 24, rf24); 2930 } 2931 if (ntries < 100) { 2932 if (rf24 != init) 2933 rf24--; /* backtrack */ 2934 *val = rf24; 2935 rt3090_rf_write(sc, 24, rf24); 2936 } 2937 2938 /* restore initial state */ 2939 rt2860_mcu_bbp_write(sc, 24, 0x00); 2940 2941 /* disable baseband loopback mode */ 2942 rf22 = rt3090_rf_read(sc, 22); 2943 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2944 2945 return 0; 2946 } 2947 2948 static void 2949 rt3090_rf_setup(struct rt2860_softc *sc) 2950 { 2951 uint8_t bbp; 2952 int i; 2953 2954 if (sc->mac_rev >= 0x0211) { 2955 /* enable DC filter */ 2956 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2957 2958 /* improve power consumption */ 2959 bbp = rt2860_mcu_bbp_read(sc, 31); 2960 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2961 } 2962 2963 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2964 if (sc->mac_rev < 0x0211) { 2965 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2966 sc->patch_dac ? 0x2c : 0x0f); 2967 } else 2968 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2969 2970 /* initialize RF registers from ROM */ 2971 if (sc->mac_ver < 0x5390) { 2972 for (i = 0; i < 10; i++) { 2973 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 2974 continue; 2975 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 2976 } 2977 } 2978 } 2979 2980 static void 2981 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 2982 { 2983 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 2984 which | (sc->leds & 0x7f), 0); 2985 } 2986 2987 /* 2988 * Hardware has a general-purpose programmable timer interrupt that can 2989 * periodically raise MAC_INT_4. 2990 */ 2991 static void 2992 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 2993 { 2994 uint32_t tmp; 2995 2996 /* disable GP timer before reprogramming it */ 2997 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2998 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 2999 3000 if (ms == 0) 3001 return; 3002 3003 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 3004 ms *= 16; /* Unit: 64us */ 3005 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 3006 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 3007 3008 /* enable GP timer */ 3009 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3010 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 3011 } 3012 3013 static void 3014 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 3015 { 3016 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 3017 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3018 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 3019 bssid[4] | bssid[5] << 8); 3020 } 3021 3022 static void 3023 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 3024 { 3025 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 3026 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3027 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 3028 addr[4] | addr[5] << 8 | 0xff << 16); 3029 } 3030 3031 static void 3032 rt2860_updateslot(struct ifnet *ifp) 3033 { 3034 struct rt2860_softc *sc = ifp->if_softc; 3035 struct ieee80211com *ic = &sc->sc_ic; 3036 uint32_t tmp; 3037 3038 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 3039 tmp &= ~0xff; 3040 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 3041 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3042 } 3043 3044 static void 3045 rt2860_updateprot(struct ieee80211com *ic) 3046 { 3047 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 3048 uint32_t tmp; 3049 3050 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3051 /* setup protection frame rate (MCS code) */ 3052 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 3053 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 3054 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3055 3056 /* CCK frames don't require protection */ 3057 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 3058 3059 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3060 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3061 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3062 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3063 tmp |= RT2860_PROT_CTRL_CTS; 3064 } 3065 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 3066 } 3067 3068 static void 3069 rt2860_update_promisc(struct ifnet *ifp) 3070 { 3071 struct rt2860_softc *sc = ifp->if_softc; 3072 uint32_t tmp; 3073 3074 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 3075 tmp &= ~RT2860_DROP_NOT_MYBSS; 3076 if (!(ifp->if_flags & IFF_PROMISC)) 3077 tmp |= RT2860_DROP_NOT_MYBSS; 3078 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3079 } 3080 3081 static int 3082 rt2860_updateedca(struct ieee80211com *ic) 3083 { 3084 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 3085 int aci; 3086 3087 /* update MAC TX configuration registers */ 3088 for (aci = 0; aci < WME_NUM_AC; aci++) { 3089 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 3090 ic->ic_wme.wme_params[aci].wmep_logcwmax << 16 | 3091 ic->ic_wme.wme_params[aci].wmep_logcwmin << 12 | 3092 ic->ic_wme.wme_params[aci].wmep_aifsn << 8 | 3093 ic->ic_wme.wme_params[aci].wmep_txopLimit); 3094 } 3095 3096 /* update SCH/DMA registers too */ 3097 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 3098 ic->ic_wme.wme_params[WME_AC_VO].wmep_aifsn << 12 | 3099 ic->ic_wme.wme_params[WME_AC_VI].wmep_aifsn << 8 | 3100 ic->ic_wme.wme_params[WME_AC_BK].wmep_aifsn << 4 | 3101 ic->ic_wme.wme_params[WME_AC_BE].wmep_aifsn); 3102 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 3103 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmin << 12 | 3104 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmin << 8 | 3105 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmin << 4 | 3106 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmin); 3107 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 3108 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmax << 12 | 3109 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmax << 8 | 3110 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmax << 4 | 3111 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmax); 3112 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 3113 ic->ic_wme.wme_params[WME_AC_BK].wmep_txopLimit << 16 | 3114 ic->ic_wme.wme_params[WME_AC_BE].wmep_txopLimit); 3115 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 3116 ic->ic_wme.wme_params[WME_AC_VO].wmep_txopLimit << 16 | 3117 ic->ic_wme.wme_params[WME_AC_VI].wmep_txopLimit); 3118 return 0; 3119 } 3120 3121 #ifdef HW_CRYPTO 3122 static int 3123 rt2860_set_key(struct ieee80211com *ic, const struct ieee80211_key *ck, 3124 const uint8_t *mac) 3125 { 3126 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 3127 struct ieee80211_node *ni = ic->ic_bss; 3128 bus_size_t base; 3129 uint32_t attr; 3130 uint8_t mode, wcid, iv[8]; 3131 struct ieee80211_key *k = __UNCONST(ck); /* XXX */ 3132 3133 DPRINTF(("%s: cipher %d\n", __func__, k->wk_cipher->ic_cipher)); 3134 /* defer setting of WEP keys until interface is brought up */ 3135 if ((ic->ic_ifp->if_flags & (IFF_UP | IFF_RUNNING)) != 3136 (IFF_UP | IFF_RUNNING)) { 3137 DPRINTF(("%s: not running %d\n", __func__, 3138 k->wk_cipher->ic_cipher)); 3139 return 1; 3140 } 3141 /* map net80211 cipher to RT2860 security mode */ 3142 switch (k->wk_cipher->ic_cipher) { 3143 case IEEE80211_CIPHER_WEP: 3144 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 3145 if (k->wk_keylen == 5) 3146 mode = RT2860_MODE_WEP40; 3147 else 3148 mode = RT2860_MODE_WEP104; 3149 break; 3150 case IEEE80211_CIPHER_TKIP: 3151 mode = RT2860_MODE_TKIP; 3152 break; 3153 case IEEE80211_CIPHER_AES_CCM: 3154 mode = RT2860_MODE_AES_CCMP; 3155 break; 3156 default: 3157 DPRINTF(("%s: bad\n", __func__)); 3158 return 0; 3159 } 3160 3161 if (k->wk_flags & IEEE80211_KEY_GROUP) { 3162 wcid = 0; /* NB: update WCID0 for group keys */ 3163 base = RT2860_SKEY(0, k->wk_keyix); 3164 } else { 3165 wcid = ((struct rt2860_node *)ni)->wcid; 3166 base = RT2860_PKEY(wcid); 3167 } 3168 3169 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 3170 RAL_WRITE_REGION_1(sc, base, k->wk_key, 16); 3171 #ifndef IEEE80211_STA_ONLY 3172 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3173 RAL_WRITE_REGION_1(sc, base + 16, &k->wk_key[16], 8); 3174 RAL_WRITE_REGION_1(sc, base + 24, &k->wk_key[24], 8); 3175 } else 3176 #endif 3177 { 3178 RAL_WRITE_REGION_1(sc, base + 16, &k->wk_key[24], 8); 3179 RAL_WRITE_REGION_1(sc, base + 24, &k->wk_key[16], 8); 3180 } 3181 } else 3182 RAL_WRITE_REGION_1(sc, base, k->wk_key, k->wk_keylen); 3183 3184 if (!(k->wk_flags & IEEE80211_KEY_GROUP) || 3185 (k->wk_flags & IEEE80211_KEY_XMIT)) { 3186 /* set initial packet number in IV+EIV */ 3187 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) { 3188 uint32_t val = cprng_fast32(); 3189 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3190 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3191 val += 0x000100; 3192 iv[0] = val; 3193 iv[1] = val >> 8; 3194 iv[2] = val >> 16; 3195 iv[3] = k->wk_keyix << 6; 3196 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3197 } else { 3198 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 3199 iv[0] = k->wk_keytsc >> 8; 3200 iv[1] = (iv[0] | 0x20) & 0x7f; 3201 iv[2] = k->wk_keytsc; 3202 } else /* CCMP */ { 3203 iv[0] = k->wk_keytsc; 3204 iv[1] = k->wk_keytsc >> 8; 3205 iv[2] = 0; 3206 } 3207 iv[3] = k->wk_keyix << 6 | IEEE80211_WEP_EXTIV; 3208 iv[4] = k->wk_keytsc >> 16; 3209 iv[5] = k->wk_keytsc >> 24; 3210 iv[6] = k->wk_keytsc >> 32; 3211 iv[7] = k->wk_keytsc >> 40; 3212 } 3213 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3214 } 3215 3216 if (k->wk_flags & IEEE80211_KEY_GROUP) { 3217 /* install group key */ 3218 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3219 attr &= ~(0xf << (k->wk_keyix * 4)); 3220 attr |= mode << (k->wk_keyix * 4); 3221 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3222 } else { 3223 /* install pairwise key */ 3224 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3225 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3226 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3227 } 3228 DPRINTF(("%s: ok\n", __func__)); 3229 return 1; 3230 } 3231 3232 static int 3233 rt2860_delete_key(struct ieee80211com *ic, const struct ieee80211_key *k) 3234 { 3235 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 3236 struct ieee80211_node *ni = ic->ic_bss; 3237 uint32_t attr; 3238 uint8_t wcid; 3239 3240 if (k->wk_flags & IEEE80211_KEY_GROUP) { 3241 /* remove group key */ 3242 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3243 attr &= ~(0xf << (k->wk_keyix * 4)); 3244 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3245 3246 } else { 3247 /* remove pairwise key */ 3248 wcid = ((struct rt2860_node *)ni)->wcid; 3249 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3250 attr &= ~0xf; 3251 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3252 } 3253 return 1; 3254 } 3255 #endif 3256 3257 static int8_t 3258 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3259 { 3260 struct ieee80211com *ic = &sc->sc_ic; 3261 struct ieee80211_channel *c = ic->ic_curchan; 3262 int delta; 3263 3264 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3265 u_int chan = ieee80211_chan2ieee(ic, c); 3266 delta = sc->rssi_5ghz[rxchain]; 3267 3268 /* determine channel group */ 3269 if (chan <= 64) 3270 delta -= sc->lna[1]; 3271 else if (chan <= 128) 3272 delta -= sc->lna[2]; 3273 else 3274 delta -= sc->lna[3]; 3275 } else 3276 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3277 3278 return -12 - delta - rssi; 3279 } 3280 3281 /* 3282 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3283 * Used to adjust per-rate Tx power registers. 3284 */ 3285 static __inline uint32_t 3286 b4inc(uint32_t b32, int8_t delta) 3287 { 3288 int8_t i, b4; 3289 3290 for (i = 0; i < 8; i++) { 3291 b4 = b32 & 0xf; 3292 b4 += delta; 3293 if (b4 < 0) 3294 b4 = 0; 3295 else if (b4 > 0xf) 3296 b4 = 0xf; 3297 b32 = b32 >> 4 | (uint32_t)b4 << 28; 3298 } 3299 return b32; 3300 } 3301 3302 static const char * 3303 rt2860_get_rf(uint32_t rev) 3304 { 3305 switch (rev) { 3306 case RT2860_RF_2820: return "RT2820"; 3307 case RT2860_RF_2850: return "RT2850"; 3308 case RT2860_RF_2720: return "RT2720"; 3309 case RT2860_RF_2750: return "RT2750"; 3310 case RT3070_RF_3020: return "RT3020"; 3311 case RT3070_RF_2020: return "RT2020"; 3312 case RT3070_RF_3021: return "RT3021"; 3313 case RT3070_RF_3022: return "RT3022"; 3314 case RT3070_RF_3052: return "RT3052"; 3315 case RT3070_RF_3320: return "RT3320"; 3316 case RT3070_RF_3053: return "RT3053"; 3317 case RT5390_RF_5360: return "RT5360"; 3318 case RT5390_RF_5390: return "RT5390"; 3319 case RT5390_RF_5392: return "RT5392"; 3320 default: return "unknown"; 3321 } 3322 } 3323 3324 static int 3325 rt2860_read_eeprom(struct rt2860_softc *sc) 3326 { 3327 struct ieee80211com *ic = &sc->sc_ic; 3328 int8_t delta_2ghz, delta_5ghz; 3329 uint32_t tmp; 3330 uint16_t val; 3331 int ridx, ant, i; 3332 3333 /* check whether the ROM is eFUSE ROM or EEPROM */ 3334 sc->sc_srom_read = rt2860_eeprom_read_2; 3335 if (sc->mac_ver >= 0x3071) { 3336 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3337 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3338 if (tmp & RT3070_SEL_EFUSE) 3339 sc->sc_srom_read = rt3090_efuse_read_2; 3340 } 3341 3342 #ifdef RAL_DEBUG 3343 /* read EEPROM version */ 3344 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3345 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 3346 #endif 3347 3348 /* read MAC address */ 3349 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3350 ic->ic_myaddr[0] = val & 0xff; 3351 ic->ic_myaddr[1] = val >> 8; 3352 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3353 ic->ic_myaddr[2] = val & 0xff; 3354 ic->ic_myaddr[3] = val >> 8; 3355 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3356 ic->ic_myaddr[4] = val & 0xff; 3357 ic->ic_myaddr[5] = val >> 8; 3358 3359 #ifdef RAL_DEBUG 3360 /* read country code */ 3361 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3362 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3363 #endif 3364 3365 /* read vendor BBP settings */ 3366 for (i = 0; i < 8; i++) { 3367 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3368 sc->bbp[i].val = val & 0xff; 3369 sc->bbp[i].reg = val >> 8; 3370 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3371 } 3372 if (sc->mac_ver >= 0x3071) { 3373 /* read vendor RF settings */ 3374 for (i = 0; i < 10; i++) { 3375 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3376 sc->rf[i].val = val & 0xff; 3377 sc->rf[i].reg = val >> 8; 3378 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3379 sc->rf[i].val)); 3380 } 3381 } 3382 3383 /* read RF frequency offset from EEPROM */ 3384 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3385 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3386 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3387 if ((val >> 8) != 0xff) { 3388 /* read LEDs operating mode */ 3389 sc->leds = val >> 8; 3390 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3391 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3392 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3393 } else { 3394 /* broken EEPROM, use default settings */ 3395 sc->leds = 0x01; 3396 sc->led[0] = 0x5555; 3397 sc->led[1] = 0x2221; 3398 sc->led[2] = 0xa9f8; 3399 } 3400 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3401 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3402 3403 /* read RF information */ 3404 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3405 if (sc->mac_ver >= 0x5390) 3406 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); 3407 else 3408 sc->rf_rev = (val >> 8) & 0xf; 3409 sc->ntxchains = (val >> 4) & 0xf; 3410 sc->nrxchains = val & 0xf; 3411 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3412 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3413 3414 /* check if RF supports automatic Tx access gain control */ 3415 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3416 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3417 /* check if driver should patch the DAC issue */ 3418 if ((val >> 8) != 0xff) 3419 sc->patch_dac = (val >> 15) & 1; 3420 if ((val & 0xff) != 0xff) { 3421 sc->ext_5ghz_lna = (val >> 3) & 1; 3422 sc->ext_2ghz_lna = (val >> 2) & 1; 3423 /* check if RF supports automatic Tx access gain control */ 3424 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */ 3425 /* check if we have a hardware radio switch */ 3426 sc->rfswitch = val & 1; 3427 } 3428 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3429 /* read PCIe power save level */ 3430 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3431 if ((val & 0xff) != 0xff) { 3432 sc->pslevel = val & 0x3; 3433 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3434 if ((val & 0xff80) != 0x9280) 3435 sc->pslevel = MIN(sc->pslevel, 1); 3436 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3437 } 3438 } 3439 3440 /* read power settings for 2GHz channels */ 3441 for (i = 0; i < 14; i += 2) { 3442 val = rt2860_srom_read(sc, 3443 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3444 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3445 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3446 3447 if (sc->mac_ver != 0x5390) { 3448 val = rt2860_srom_read(sc, 3449 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3450 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3451 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3452 } 3453 } 3454 /* fix broken Tx power entries */ 3455 for (i = 0; i < 14; i++) { 3456 if (sc->txpow1[i] < 0 || 3457 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3458 sc->txpow1[i] = 5; 3459 if (sc->mac_ver != 0x5390) { 3460 if (sc->txpow2[i] < 0 || 3461 sc->txpow2[i] > ((sc->mac_ver >= 0x5392) ? 39 : 31)) 3462 sc->txpow2[i] = 5; 3463 } 3464 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3465 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3466 } 3467 /* read power settings for 5GHz channels */ 3468 for (i = 0; i < 40; i += 2) { 3469 val = rt2860_srom_read(sc, 3470 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3471 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3472 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3473 3474 val = rt2860_srom_read(sc, 3475 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3476 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3477 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3478 } 3479 /* fix broken Tx power entries */ 3480 for (i = 0; i < 40; i++) { 3481 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3482 sc->txpow1[14 + i] = 5; 3483 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3484 sc->txpow2[14 + i] = 5; 3485 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3486 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3487 sc->txpow2[14 + i])); 3488 } 3489 3490 /* read Tx power compensation for each Tx rate */ 3491 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3492 delta_2ghz = delta_5ghz = 0; 3493 if ((val & 0xff) != 0xff && (val & 0x80)) { 3494 delta_2ghz = val & 0xf; 3495 if (!(val & 0x40)) /* negative number */ 3496 delta_2ghz = -delta_2ghz; 3497 } 3498 val >>= 8; 3499 if ((val & 0xff) != 0xff && (val & 0x80)) { 3500 delta_5ghz = val & 0xf; 3501 if (!(val & 0x40)) /* negative number */ 3502 delta_5ghz = -delta_5ghz; 3503 } 3504 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3505 delta_2ghz, delta_5ghz)); 3506 3507 for (ridx = 0; ridx < 5; ridx++) { 3508 uint32_t reg; 3509 3510 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3511 reg = val; 3512 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3513 reg |= (uint32_t)val << 16; 3514 3515 sc->txpow20mhz[ridx] = reg; 3516 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3517 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3518 3519 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3520 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3521 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3522 } 3523 3524 /* read factory-calibrated samples for temperature compensation */ 3525 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3526 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3527 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3528 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3529 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3530 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3531 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3532 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3533 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3534 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3535 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3536 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3537 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3538 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3539 sc->step_2ghz = val >> 8; 3540 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3541 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3542 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3543 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3544 sc->tssi_2ghz[8], sc->step_2ghz)); 3545 /* check that ref value is correct, otherwise disable calibration */ 3546 if (sc->tssi_2ghz[4] == 0xff) 3547 sc->calib_2ghz = 0; 3548 3549 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3550 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3551 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3552 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3553 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3554 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3555 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3556 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3557 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3558 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3559 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3560 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3561 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3562 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3563 sc->step_5ghz = val >> 8; 3564 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3565 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3566 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3567 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3568 sc->tssi_5ghz[8], sc->step_5ghz)); 3569 /* check that ref value is correct, otherwise disable calibration */ 3570 if (sc->tssi_5ghz[4] == 0xff) 3571 sc->calib_5ghz = 0; 3572 3573 /* read RSSI offsets and LNA gains from EEPROM */ 3574 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3575 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3576 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3577 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3578 if (sc->mac_ver >= 0x3071) { 3579 /* 3580 * On RT3090 chips (limited to 2 Rx chains), this ROM 3581 * field contains the Tx mixer gain for the 2GHz band. 3582 */ 3583 if ((val & 0xff) != 0xff) 3584 sc->txmixgain_2ghz = val & 0x7; 3585 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3586 } else 3587 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3588 sc->lna[2] = val >> 8; /* channel group 2 */ 3589 3590 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3591 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3592 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3593 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3594 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3595 sc->lna[3] = val >> 8; /* channel group 3 */ 3596 3597 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3598 if (sc->mac_ver >= 0x3071) 3599 sc->lna[0] = RT3090_DEF_LNA; 3600 else /* channel group 0 */ 3601 sc->lna[0] = val & 0xff; 3602 sc->lna[1] = val >> 8; /* channel group 1 */ 3603 3604 /* fix broken 5GHz LNA entries */ 3605 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3606 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3607 sc->lna[2] = sc->lna[1]; 3608 } 3609 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3610 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3611 sc->lna[3] = sc->lna[1]; 3612 } 3613 3614 /* fix broken RSSI offset entries */ 3615 for (ant = 0; ant < 3; ant++) { 3616 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3617 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3618 ant + 1, sc->rssi_2ghz[ant])); 3619 sc->rssi_2ghz[ant] = 0; 3620 } 3621 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3622 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3623 ant + 1, sc->rssi_5ghz[ant])); 3624 sc->rssi_5ghz[ant] = 0; 3625 } 3626 } 3627 3628 return 0; 3629 } 3630 3631 static int 3632 rt2860_bbp_init(struct rt2860_softc *sc) 3633 { 3634 int i, ntries; 3635 3636 /* wait for BBP to wake up */ 3637 for (ntries = 0; ntries < 20; ntries++) { 3638 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3639 if (bbp0 != 0 && bbp0 != 0xff) 3640 break; 3641 } 3642 if (ntries == 20) { 3643 aprint_error_dev(sc->sc_dev, 3644 "timeout waiting for BBP to wake up\n"); 3645 return ETIMEDOUT; 3646 } 3647 3648 /* initialize BBP registers to default values */ 3649 if (sc->mac_ver >= 0x5390) 3650 rt5390_bbp_init(sc); 3651 else { 3652 for (i = 0; i < (int)__arraycount(rt2860_def_bbp); i++) { 3653 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3654 rt2860_def_bbp[i].val); 3655 } 3656 } 3657 3658 /* fix BBP84 for RT2860E */ 3659 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3660 rt2860_mcu_bbp_write(sc, 84, 0x19); 3661 3662 if (sc->mac_ver >= 0x3071) { 3663 rt2860_mcu_bbp_write(sc, 79, 0x13); 3664 rt2860_mcu_bbp_write(sc, 80, 0x05); 3665 rt2860_mcu_bbp_write(sc, 81, 0x33); 3666 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3667 rt2860_mcu_bbp_write(sc, 69, 0x16); 3668 rt2860_mcu_bbp_write(sc, 73, 0x12); 3669 } 3670 3671 return 0; 3672 } 3673 3674 static int 3675 rt5390_bbp_init(struct rt2860_softc *sc) 3676 { 3677 uint8_t bbp; 3678 int i; 3679 3680 /* Apply maximum likelihood detection for 2 stream case. */ 3681 if (sc->nrxchains > 1) { 3682 bbp = rt2860_mcu_bbp_read(sc, 105); 3683 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3684 } 3685 3686 /* Avoid data lost and CRC error. */ 3687 bbp = rt2860_mcu_bbp_read(sc, 4); 3688 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3689 3690 for (i = 0; i < __arraycount(rt5390_def_bbp); i++) { 3691 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3692 rt5390_def_bbp[i].val); 3693 } 3694 3695 if (sc->mac_ver == 0x5392) { 3696 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3697 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3698 rt2860_mcu_bbp_write(sc, 98, 0x12); 3699 rt2860_mcu_bbp_write(sc, 106, 0x05); 3700 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3701 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3702 } 3703 3704 bbp = rt2860_mcu_bbp_read(sc, 152); 3705 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3706 3707 /* Disable hardware antenna diversity. */ 3708 if (sc->mac_ver == 0x5390) 3709 rt2860_mcu_bbp_write(sc, 154, 0); 3710 3711 return 0; 3712 } 3713 3714 static int 3715 rt2860_txrx_enable(struct rt2860_softc *sc) 3716 { 3717 uint32_t tmp; 3718 int ntries; 3719 3720 /* enable Tx/Rx DMA engine */ 3721 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3722 RAL_BARRIER_READ_WRITE(sc); 3723 for (ntries = 0; ntries < 200; ntries++) { 3724 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3725 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3726 break; 3727 DELAY(1000); 3728 } 3729 if (ntries == 200) { 3730 aprint_error_dev(sc->sc_dev, 3731 "timeout waiting for DMA engine\n"); 3732 return ETIMEDOUT; 3733 } 3734 3735 DELAY(50); 3736 3737 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3738 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3739 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3740 3741 /* set Rx filter */ 3742 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3743 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 3744 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3745 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3746 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3747 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3748 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 3749 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3750 } 3751 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3752 3753 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3754 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3755 3756 return 0; 3757 } 3758 3759 static int 3760 rt2860_init(struct ifnet *ifp) 3761 { 3762 struct rt2860_softc *sc = ifp->if_softc; 3763 struct ieee80211com *ic = &sc->sc_ic; 3764 uint32_t tmp; 3765 uint8_t bbp1, bbp3; 3766 int i, qid, ridx, ntries, error; 3767 3768 /* for CardBus, power on the socket */ 3769 if (!(sc->sc_flags & RT2860_ENABLED)) { 3770 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 3771 aprint_error_dev(sc->sc_dev, 3772 "could not enable device\n"); 3773 return EIO; 3774 } 3775 sc->sc_flags |= RT2860_ENABLED; 3776 } 3777 3778 if (sc->rfswitch) { 3779 /* hardware has a radio switch on GPIO pin 2 */ 3780 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3781 aprint_normal_dev(sc->sc_dev, 3782 "radio is disabled by hardware switch\n"); 3783 #ifdef notyet 3784 rt2860_stop(ifp, 1); 3785 return EPERM; 3786 #endif 3787 } 3788 } 3789 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3790 3791 /* disable DMA */ 3792 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3793 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3794 RT2860_TX_DMA_EN); 3795 tmp |= RT2860_TX_WB_DDONE; 3796 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3797 3798 /* reset DMA indexes */ 3799 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, RT2860_RST_DRX_IDX0 | 3800 RT2860_RST_DTX_IDX5 | RT2860_RST_DTX_IDX4 | RT2860_RST_DTX_IDX3 | 3801 RT2860_RST_DTX_IDX2 | RT2860_RST_DTX_IDX1 | RT2860_RST_DTX_IDX0); 3802 3803 /* PBF hardware reset */ 3804 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3805 RAL_BARRIER_WRITE(sc); 3806 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3807 3808 if ((error = rt2860_load_microcode(sc)) != 0) { 3809 aprint_error_dev(sc->sc_dev, 3810 "could not load 8051 microcode\n"); 3811 rt2860_stop(ifp, 1); 3812 return error; 3813 } 3814 3815 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3816 rt2860_set_macaddr(sc, ic->ic_myaddr); 3817 3818 /* init Tx power for all Tx rates (from EEPROM) */ 3819 for (ridx = 0; ridx < 5; ridx++) { 3820 if (sc->txpow20mhz[ridx] == 0xffffffff) 3821 continue; 3822 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3823 } 3824 3825 for (ntries = 0; ntries < 100; ntries++) { 3826 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3827 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3828 break; 3829 DELAY(1000); 3830 } 3831 if (ntries == 100) { 3832 aprint_error_dev(sc->sc_dev, 3833 "timeout waiting for DMA engine\n"); 3834 rt2860_stop(ifp, 1); 3835 return ETIMEDOUT; 3836 } 3837 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3838 RT2860_TX_DMA_EN); 3839 tmp |= RT2860_TX_WB_DDONE; 3840 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3841 3842 /* reset Rx ring and all 6 Tx rings */ 3843 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3844 3845 /* PBF hardware reset */ 3846 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3847 RAL_BARRIER_WRITE(sc); 3848 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3849 3850 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3851 3852 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3853 RAL_BARRIER_WRITE(sc); 3854 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3855 3856 for (i = 0; i < (int)__arraycount(rt2860_def_mac); i++) 3857 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3858 if (sc->mac_ver >= 0x5390) 3859 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3860 else if (sc->mac_ver >= 0x3071) { 3861 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3862 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3863 4 << RT2860_DLY_PAPE_EN_SHIFT); 3864 } 3865 3866 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3867 sc->sc_flags |= RT2860_PCIE; 3868 /* PCIe has different clock cycle count than PCI */ 3869 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3870 tmp = (tmp & ~0xff) | 0x7d; 3871 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3872 } 3873 3874 /* wait while MAC is busy */ 3875 for (ntries = 0; ntries < 100; ntries++) { 3876 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3877 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3878 break; 3879 DELAY(1000); 3880 } 3881 if (ntries == 100) { 3882 aprint_error_dev(sc->sc_dev, "timeout waiting for MAC\n"); 3883 rt2860_stop(ifp, 1); 3884 return ETIMEDOUT; 3885 } 3886 3887 /* clear Host to MCU mailbox */ 3888 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3889 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3890 3891 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3892 DELAY(1000); 3893 3894 if ((error = rt2860_bbp_init(sc)) != 0) { 3895 rt2860_stop(ifp, 1); 3896 return error; 3897 } 3898 3899 /* clear RX WCID search table */ 3900 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3901 /* clear pairwise key table */ 3902 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3903 /* clear IV/EIV table */ 3904 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3905 /* clear WCID attribute table */ 3906 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3907 /* clear shared key table */ 3908 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3909 /* clear shared key mode */ 3910 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3911 3912 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3913 for (qid = 0; qid < MAXQS; qid++) { 3914 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3915 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3916 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3917 } 3918 3919 /* init Rx ring */ 3920 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3921 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3922 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3923 3924 /* setup maximum buffer sizes */ 3925 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3926 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3927 3928 for (ntries = 0; ntries < 100; ntries++) { 3929 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3930 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3931 break; 3932 DELAY(1000); 3933 } 3934 if (ntries == 100) { 3935 aprint_error_dev(sc->sc_dev, 3936 "timeout waiting for DMA engine\n"); 3937 rt2860_stop(ifp, 1); 3938 return ETIMEDOUT; 3939 } 3940 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3941 RT2860_TX_DMA_EN); 3942 tmp |= RT2860_TX_WB_DDONE; 3943 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3944 3945 /* disable interrupts mitigation */ 3946 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3947 3948 /* write vendor-specific BBP values (from EEPROM) */ 3949 for (i = 0; i < 8; i++) { 3950 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3951 continue; 3952 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3953 } 3954 3955 /* select Main antenna for 1T1R devices */ 3956 if (sc->rf_rev == RT3070_RF_2020 || 3957 sc->rf_rev == RT3070_RF_3020 || 3958 sc->rf_rev == RT3070_RF_3320 || 3959 sc->rf_rev == RT5390_RF_5390) 3960 rt3090_set_rx_antenna(sc, 0); 3961 3962 /* send LEDs operating mode to microcontroller */ 3963 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3964 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3965 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3966 3967 if (sc->mac_ver >= 0x5390) 3968 rt5390_rf_init(sc); 3969 else if (sc->mac_ver >= 0x3071) 3970 rt3090_rf_init(sc); 3971 3972 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 3973 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 3974 3975 if (sc->mac_ver >= 0x5390) 3976 rt5390_rf_wakeup(sc); 3977 else if (sc->mac_ver >= 0x3071) 3978 rt3090_rf_wakeup(sc); 3979 3980 /* disable non-existing Rx chains */ 3981 bbp3 = rt2860_mcu_bbp_read(sc, 3); 3982 bbp3 &= ~(1 << 3 | 1 << 4); 3983 if (sc->nrxchains == 2) 3984 bbp3 |= 1 << 3; 3985 else if (sc->nrxchains == 3) 3986 bbp3 |= 1 << 4; 3987 rt2860_mcu_bbp_write(sc, 3, bbp3); 3988 3989 /* disable non-existing Tx chains */ 3990 bbp1 = rt2860_mcu_bbp_read(sc, 1); 3991 if (sc->ntxchains == 1) 3992 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 3993 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 3994 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 3995 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 3996 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 3997 rt2860_mcu_bbp_write(sc, 1, bbp1); 3998 3999 if (sc->mac_ver >= 0x3071) 4000 rt3090_rf_setup(sc); 4001 4002 /* select default channel */ 4003 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 4004 rt2860_switch_chan(sc, ic->ic_ibss_chan); 4005 4006 /* reset RF from MCU */ 4007 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 4008 4009 /* set RTS threshold */ 4010 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 4011 tmp &= ~0xffff00; 4012 tmp |= ic->ic_rtsthreshold << 8; 4013 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 4014 4015 /* setup initial protection mode */ 4016 sc->sc_ic_flags = ic->ic_flags; 4017 rt2860_updateprot(ic); 4018 4019 /* turn radio LED on */ 4020 rt2860_set_leds(sc, RT2860_LED_RADIO); 4021 4022 /* enable Tx/Rx DMA engine */ 4023 if ((error = rt2860_txrx_enable(sc)) != 0) { 4024 rt2860_stop(ifp, 1); 4025 return error; 4026 } 4027 4028 /* clear pending interrupts */ 4029 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 4030 /* enable interrupts */ 4031 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 4032 4033 if (sc->sc_flags & RT2860_ADVANCED_PS) 4034 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 4035 4036 ifp->if_flags |= IFF_RUNNING; 4037 ifp->if_flags &= ~IFF_OACTIVE; 4038 4039 if (ic->ic_opmode != IEEE80211_M_MONITOR) 4040 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4041 else 4042 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4043 4044 return 0; 4045 } 4046 4047 static void 4048 rt2860_stop(struct ifnet *ifp, int disable) 4049 { 4050 struct rt2860_softc *sc = ifp->if_softc; 4051 struct ieee80211com *ic = &sc->sc_ic; 4052 uint32_t tmp; 4053 int qid; 4054 4055 if (ifp->if_flags & IFF_RUNNING) 4056 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 4057 4058 sc->sc_tx_timer = 0; 4059 ifp->if_timer = 0; 4060 ifp->if_flags &= ~IFF_RUNNING; 4061 ifp->if_flags &= ~IFF_OACTIVE; 4062 4063 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 4064 4065 /* disable interrupts */ 4066 RAL_WRITE(sc, RT2860_INT_MASK, 0); 4067 4068 /* disable GP timer */ 4069 rt2860_set_gp_timer(sc, 0); 4070 4071 /* disable Rx */ 4072 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 4073 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4074 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 4075 4076 /* reset adapter */ 4077 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4078 RAL_BARRIER_WRITE(sc); 4079 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 4080 4081 /* reset Tx and Rx rings (and reclaim TXWIs) */ 4082 sc->qfullmsk = 0; 4083 for (qid = 0; qid < MAXQS; qid++) 4084 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 4085 rt2860_reset_rx_ring(sc, &sc->rxq); 4086 4087 /* for CardBus, power down the socket */ 4088 if (disable && sc->sc_disable != NULL) { 4089 if (sc->sc_flags & RT2860_ENABLED) { 4090 (*sc->sc_disable)(sc); 4091 sc->sc_flags &= ~RT2860_ENABLED; 4092 } 4093 } 4094 } 4095 4096 static int 4097 rt2860_load_microcode(struct rt2860_softc *sc) 4098 { 4099 int ntries; 4100 4101 /* set "host program ram write selection" bit */ 4102 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4103 /* write microcode image */ 4104 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, sc->ucode, sc->ucsize); 4105 /* kick microcontroller unit */ 4106 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4107 RAL_BARRIER_WRITE(sc); 4108 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4109 4110 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4111 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4112 4113 /* wait until microcontroller is ready */ 4114 RAL_BARRIER_READ_WRITE(sc); 4115 for (ntries = 0; ntries < 1000; ntries++) { 4116 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4117 break; 4118 DELAY(1000); 4119 } 4120 if (ntries == 1000) { 4121 aprint_error_dev(sc->sc_dev, 4122 "timeout waiting for MCU to initialize\n"); 4123 return ETIMEDOUT; 4124 } 4125 return 0; 4126 } 4127 4128 #if 0 4129 /* 4130 * This function is called periodically to adjust Tx power based on 4131 * temperature variation. 4132 */ 4133 static void 4134 rt2860_calib(struct rt2860_softc *sc) 4135 { 4136 struct ieee80211com *ic = &sc->sc_ic; 4137 const uint8_t *tssi; 4138 uint8_t step, bbp49; 4139 int8_t ridx, d; 4140 4141 /* read current temperature */ 4142 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4143 4144 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4145 tssi = &sc->tssi_2ghz[4]; 4146 step = sc->step_2ghz; 4147 } else { 4148 tssi = &sc->tssi_5ghz[4]; 4149 step = sc->step_5ghz; 4150 } 4151 4152 if (bbp49 < tssi[0]) { /* lower than reference */ 4153 /* use higher Tx power than default */ 4154 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4155 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4156 /* use lower Tx power than default */ 4157 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4158 } else { 4159 /* use default Tx power */ 4160 d = 0; 4161 } 4162 d *= step; 4163 4164 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4165 4166 /* write adjusted Tx power values for each Tx rate */ 4167 for (ridx = 0; ridx < 5; ridx++) { 4168 if (sc->txpow20mhz[ridx] == 0xffffffff) 4169 continue; 4170 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4171 b4inc(sc->txpow20mhz[ridx], d)); 4172 } 4173 } 4174 #endif /* 0 */ 4175 4176 static void 4177 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4178 { 4179 uint32_t tmp; 4180 4181 if (aux) { 4182 if (sc->mac_ver == 0x5390) { 4183 rt2860_mcu_bbp_write(sc, 152, 4184 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4185 } else { 4186 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4187 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 4188 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4189 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 4190 } 4191 } else { 4192 if (sc->mac_ver == 0x5390) { 4193 rt2860_mcu_bbp_write(sc, 152, 4194 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4195 } else { 4196 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4197 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4198 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4199 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4200 } 4201 } 4202 } 4203 4204 static void 4205 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4206 { 4207 struct ieee80211com *ic = &sc->sc_ic; 4208 u_int chan, group; 4209 4210 chan = ieee80211_chan2ieee(ic, c); 4211 DPRINTF(("switch channel %u\n", chan)); 4212 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4213 return; 4214 4215 if (sc->mac_ver >= 0x5390) 4216 rt5390_set_chan(sc, chan); 4217 else if (sc->mac_ver >= 0x3071) 4218 rt3090_set_chan(sc, chan); 4219 else 4220 rt2860_set_chan(sc, chan); 4221 4222 /* determine channel group */ 4223 if (chan <= 14) 4224 group = 0; 4225 else if (chan <= 64) 4226 group = 1; 4227 else if (chan <= 128) 4228 group = 2; 4229 else 4230 group = 3; 4231 4232 /* XXX necessary only when group has changed! */ 4233 if (sc->mac_ver < 0x5390) 4234 rt2860_select_chan_group(sc, group); 4235 4236 DELAY(1000); 4237 } 4238 4239 #ifndef IEEE80211_STA_ONLY 4240 static int 4241 rt2860_setup_beacon(struct rt2860_softc *sc) 4242 { 4243 struct ieee80211com *ic = &sc->sc_ic; 4244 struct rt2860_txwi txwi; 4245 struct mbuf *m; 4246 int ridx; 4247 4248 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss, &sc->sc_bo)) == NULL) 4249 return ENOBUFS; 4250 4251 memset(&txwi, 0, sizeof txwi); 4252 txwi.wcid = 0xff; 4253 txwi.len = htole16(m->m_pkthdr.len); 4254 /* send beacons at the lowest available rate */ 4255 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 4256 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4257 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4258 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4259 txwi.phy |= htole16(RT2860_PHY_OFDM); 4260 txwi.txop = RT2860_TX_TXOP_HT; 4261 txwi.flags = RT2860_TX_TS; 4262 txwi.xflags = RT2860_TX_NSEQ; 4263 4264 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4265 (uint8_t *)&txwi, sizeof txwi); 4266 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4267 mtod(m, uint8_t *), m->m_pkthdr.len); 4268 4269 m_freem(m); 4270 4271 return 0; 4272 } 4273 #endif 4274 4275 static void 4276 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4277 { 4278 struct ieee80211com *ic = &sc->sc_ic; 4279 uint32_t tmp; 4280 4281 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4282 4283 tmp &= ~0x1fffff; 4284 tmp |= ic->ic_bss->ni_intval * 16; 4285 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4286 if (ic->ic_opmode == IEEE80211_M_STA) { 4287 /* 4288 * Local TSF is always updated with remote TSF on beacon 4289 * reception. 4290 */ 4291 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4292 } 4293 #ifndef IEEE80211_STA_ONLY 4294 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 4295 tmp |= RT2860_BCN_TX_EN; 4296 /* 4297 * Local TSF is updated with remote TSF on beacon reception 4298 * only if the remote TSF is greater than local TSF. 4299 */ 4300 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4301 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4302 tmp |= RT2860_BCN_TX_EN; 4303 /* SYNC with nobody */ 4304 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4305 } 4306 #endif 4307 4308 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4309 } 4310