1 /* $NetBSD: nvmereg.h,v 1.11 2018/04/18 10:10:26 nonaka Exp $ */ 2 /* $OpenBSD: nvmereg.h,v 1.10 2016/04/14 11:18:32 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2014 David Gwynne <dlg@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef __NVMEREG_H__ 21 #define __NVMEREG_H__ 22 23 #ifndef NVME_CTASSERT 24 #define NVME_CTASSERT(x, s) __CTASSERT(x) 25 #endif 26 27 #define NVME_CAP 0x0000 /* Controller Capabilities */ 28 #define NVME_CAP_MPSMAX(_r) (12 + (((_r) >> 52) & 0xf)) /* shift */ 29 #define NVME_CAP_MPSMIN(_r) (12 + (((_r) >> 48) & 0xf)) /* shift */ 30 #define NVME_CAP_CSS(_r) (((_r) >> 37) & 0x7f) 31 #define NVME_CAP_CSS_NVM __BIT(0) 32 #define NVME_CAP_NSSRS(_r) ISSET((_r), __BIT(36)) 33 #define NVME_CAP_DSTRD(_r) __BIT(2 + (((_r) >> 32) & 0xf)) /* bytes */ 34 #define NVME_CAP_TO(_r) (500 * (((_r) >> 24) & 0xff)) /* ms */ 35 #define NVME_CAP_AMS(_r) (((_r) >> 17) & 0x3) 36 #define NVME_CAP_AMS_WRR __BIT(0) 37 #define NVME_CAP_AMS_VENDOR __BIT(1) 38 #define NVME_CAP_CQR(_r) ISSET((_r), __BIT(16)) 39 #define NVME_CAP_MQES(_r) (((_r) & 0xffff) + 1) 40 #define NVME_CAP_LO 0x0000 41 #define NVME_CAP_HI 0x0004 42 #define NVME_VS 0x0008 /* Version */ 43 #define NVME_VS_MJR(_r) (((_r) >> 16) & 0xffff) 44 #define NVME_VS_MNR(_r) (((_r) >> 8) & 0xff) 45 #define NVME_VS_TER(_r) ((_r) & 0xff) 46 #define NVME_INTMS 0x000c /* Interrupt Mask Set */ 47 #define NVME_INTMC 0x0010 /* Interrupt Mask Clear */ 48 #define NVME_CC 0x0014 /* Controller Configuration */ 49 #define NVME_CC_IOCQES(_v) (((_v) & 0xf) << 20) 50 #define NVME_CC_IOCQES_MASK NVME_CC_IOCQES(0xf) 51 #define NVME_CC_IOCQES_R(_v) (((_v) >> 20) & 0xf) 52 #define NVME_CC_IOSQES(_v) (((_v) & 0xf) << 16) 53 #define NVME_CC_IOSQES_MASK NVME_CC_IOSQES(0xf) 54 #define NVME_CC_IOSQES_R(_v) (((_v) >> 16) & 0xf) 55 #define NVME_CC_SHN(_v) (((_v) & 0x3) << 14) 56 #define NVME_CC_SHN_MASK NVME_CC_SHN(0x3) 57 #define NVME_CC_SHN_R(_v) (((_v) >> 15) & 0x3) 58 #define NVME_CC_SHN_NONE 0 59 #define NVME_CC_SHN_NORMAL 1 60 #define NVME_CC_SHN_ABRUPT 2 61 #define NVME_CC_AMS(_v) (((_v) & 0x7) << 11) 62 #define NVME_CC_AMS_MASK NVME_CC_AMS(0x7) 63 #define NVME_CC_AMS_R(_v) (((_v) >> 11) & 0xf) 64 #define NVME_CC_AMS_RR 0 /* round-robin */ 65 #define NVME_CC_AMS_WRR_U 1 /* weighted round-robin w/ urgent */ 66 #define NVME_CC_AMS_VENDOR 7 /* vendor */ 67 #define NVME_CC_MPS(_v) ((((_v) - 12) & 0xf) << 7) 68 #define NVME_CC_MPS_MASK (0xf << 7) 69 #define NVME_CC_MPS_R(_v) (12 + (((_v) >> 7) & 0xf)) 70 #define NVME_CC_CSS(_v) (((_v) & 0x7) << 4) 71 #define NVME_CC_CSS_MASK NVME_CC_CSS(0x7) 72 #define NVME_CC_CSS_R(_v) (((_v) >> 4) & 0x7) 73 #define NVME_CC_CSS_NVM 0 74 #define NVME_CC_EN __BIT(0) 75 #define NVME_CSTS 0x001c /* Controller Status */ 76 #define NVME_CSTS_SHST_MASK (0x3 << 2) 77 #define NVME_CSTS_SHST_NONE (0x0 << 2) /* normal operation */ 78 #define NVME_CSTS_SHST_WAIT (0x1 << 2) /* shutdown processing occurring */ 79 #define NVME_CSTS_SHST_DONE (0x2 << 2) /* shutdown processing complete */ 80 #define NVME_CSTS_CFS (1 << 1) 81 #define NVME_CSTS_RDY (1 << 0) 82 #define NVME_NSSR 0x0020 /* NVM Subsystem Reset (Optional) */ 83 #define NVME_AQA 0x0024 /* Admin Queue Attributes */ 84 /* Admin Completion Queue Size */ 85 #define NVME_AQA_ACQS(_v) (((_v) - 1) << 16) 86 #define NVME_AQA_ACQS_R(_v) ((_v >> 16) & ((1 << 12) - 1)) 87 /* Admin Submission Queue Size */ 88 #define NVME_AQA_ASQS(_v) (((_v) - 1) << 0) 89 #define NVME_AQA_ASQS_R(_v) (_v & ((1 << 12) - 1)) 90 #define NVME_ASQ 0x0028 /* Admin Submission Queue Base Address */ 91 #define NVME_ACQ 0x0030 /* Admin Completion Queue Base Address */ 92 93 #define NVME_ADMIN_Q 0 94 /* Submission Queue Tail Doorbell */ 95 #define NVME_SQTDBL(_q, _s) (0x1000 + (2 * (_q) + 0) * (_s)) 96 /* Completion Queue Head Doorbell */ 97 #define NVME_CQHDBL(_q, _s) (0x1000 + (2 * (_q) + 1) * (_s)) 98 99 struct nvme_sge { 100 uint8_t id; 101 uint8_t _reserved[15]; 102 } __packed __aligned(8); 103 NVME_CTASSERT(sizeof(struct nvme_sge) == 16, "bad size for nvme_sge"); 104 105 struct nvme_sge_data { 106 uint8_t id; 107 uint8_t _reserved[3]; 108 109 uint32_t length; 110 111 uint64_t address; 112 } __packed __aligned(8); 113 NVME_CTASSERT(sizeof(struct nvme_sge_data) == 16, "bad size for nvme_sge_data"); 114 115 struct nvme_sge_bit_bucket { 116 uint8_t id; 117 uint8_t _reserved[3]; 118 119 uint32_t length; 120 121 uint64_t address; 122 } __packed __aligned(8); 123 NVME_CTASSERT(sizeof(struct nvme_sge_bit_bucket) == 16, "bad size for nvme_sge_bit_bucket"); 124 125 struct nvme_sqe { 126 uint8_t opcode; 127 uint8_t flags; 128 uint16_t cid; 129 130 uint32_t nsid; 131 132 uint8_t _reserved[8]; 133 134 uint64_t mptr; 135 136 union { 137 uint64_t prp[2]; 138 struct nvme_sge sge; 139 } __packed entry; 140 141 uint32_t cdw10; 142 uint32_t cdw11; 143 uint32_t cdw12; 144 uint32_t cdw13; 145 uint32_t cdw14; 146 uint32_t cdw15; 147 } __packed __aligned(8); 148 NVME_CTASSERT(sizeof(struct nvme_sqe) == 64, "bad size for nvme_sqe"); 149 150 struct nvme_sqe_q { 151 uint8_t opcode; 152 uint8_t flags; 153 uint16_t cid; 154 155 uint8_t _reserved1[20]; 156 157 uint64_t prp1; 158 159 uint8_t _reserved2[8]; 160 161 uint16_t qid; 162 uint16_t qsize; 163 164 uint8_t qflags; 165 #define NVM_SQE_SQ_QPRIO_URG (0x0 << 1) 166 #define NVM_SQE_SQ_QPRIO_HI (0x1 << 1) 167 #define NVM_SQE_SQ_QPRIO_MED (0x2 << 1) 168 #define NVM_SQE_SQ_QPRIO_LOW (0x3 << 1) 169 #define NVM_SQE_CQ_IEN (1 << 1) 170 #define NVM_SQE_Q_PC (1 << 0) 171 uint8_t _reserved3; 172 uint16_t cqid; /* XXX interrupt vector for cq */ 173 174 uint8_t _reserved4[16]; 175 } __packed __aligned(8); 176 NVME_CTASSERT(sizeof(struct nvme_sqe_q) == 64, "bad size for nvme_sqe_q"); 177 178 struct nvme_sqe_io { 179 uint8_t opcode; 180 uint8_t flags; 181 uint16_t cid; 182 183 uint32_t nsid; 184 185 uint8_t _reserved[8]; 186 187 uint64_t mptr; 188 189 union { 190 uint64_t prp[2]; 191 struct nvme_sge sge; 192 } __packed entry; 193 194 uint64_t slba; /* Starting LBA */ 195 196 uint16_t nlb; /* Number of Logical Blocks */ 197 uint16_t ioflags; 198 #define NVM_SQE_IO_LR __BIT(15) /* Limited Retry */ 199 #define NVM_SQE_IO_FUA __BIT(14) /* Force Unit Access (bypass cache) */ 200 201 uint8_t dsm; /* Dataset Management */ 202 #define NVM_SQE_IO_INCOMP __BIT(7) /* Incompressible */ 203 #define NVM_SQE_IO_SEQ __BIT(6) /* Sequential request */ 204 #define NVM_SQE_IO_LAT_MASK __BITS(4, 5) /* Access Latency */ 205 #define NVM_SQE_IO_LAT_NONE 0 /* Latency: none */ 206 #define NVM_SQE_IO_LAT_IDLE __BIT(4) /* Latency: idle */ 207 #define NVM_SQE_IO_LAT_NORMAL __BIT(5) /* Latency: normal */ 208 #define NVM_SQE_IO_LAT_LOW __BITS(4, 5) /* Latency: low */ 209 #define NVM_SQE_IO_FREQ_MASK __BITS(0, 3) /* Access Frequency */ 210 #define NVM_SQE_IO_FREQ_TYPICAL 0x1 /* Typical */ 211 #define NVM_SQE_IO_FREQ_INFR_INFW 0x2 /* Infrequent read and writes */ 212 #define NVM_SQE_IO_FREQ_FRR_INFW 0x3 /* Frequent read, inf. writes */ 213 #define NVM_SQE_IO_FREQ_INFR_FRW 0x4 /* Inf. read, freq. writes */ 214 #define NVM_SQE_IO_FREQ_FRR_FRW 0x5 /* Freq. read and writes */ 215 #define NVM_SQE_IO_FREQ_ONCE 0x6 /* One time i/o operation */ 216 /* Extra Access Frequency bits for read operations */ 217 #define NVM_SQE_IO_FREQ_SPEC 0x7 /* Speculative read - prefech */ 218 #define NVM_SQE_IO_FREQ_OVERWRITE 0x8 /* Will be overwritten soon */ 219 uint8_t _reserved2[3]; 220 221 uint32_t eilbrt; /* Expected Initial Logical Block 222 Reference Tag */ 223 224 uint16_t elbat; /* Expected Logical Block 225 Application Tag */ 226 uint16_t elbatm; /* Expected Logical Block 227 Application Tag Mask */ 228 } __packed __aligned(8); 229 NVME_CTASSERT(sizeof(struct nvme_sqe_io) == 64, "bad size for nvme_sqe_io"); 230 231 struct nvme_cqe { 232 uint32_t cdw0; 233 #define NVME_CQE_CDW0_VWC_WCE __BIT(1) /* Volatile Write Cache Enable */ 234 235 uint32_t _reserved; 236 237 uint16_t sqhd; /* SQ Head Pointer */ 238 uint16_t sqid; /* SQ Identifier */ 239 240 uint16_t cid; /* Command Identifier */ 241 uint16_t flags; 242 #define NVME_CQE_DNR __BIT(15) 243 #define NVME_CQE_M __BIT(14) 244 #define NVME_CQE_SCT_MASK __BITS(8, 10) 245 #define NVME_CQE_SCT(_f) ((_f) & (0x07 << 8)) 246 #define NVME_CQE_SCT_GENERIC (0x00 << 8) 247 #define NVME_CQE_SCT_COMMAND (0x01 << 8) 248 #define NVME_CQE_SCT_MEDIAERR (0x02 << 8) 249 #define NVME_CQE_SCT_VENDOR (0x07 << 8) 250 #define NVME_CQE_SC_MASK __BITS(1, 7) 251 #define NVME_CQE_SC(_f) ((_f) & (0x7f << 1)) 252 /* generic command status codes */ 253 #define NVME_CQE_SC_SUCCESS (0x00 << 1) 254 #define NVME_CQE_SC_INVALID_OPCODE (0x01 << 1) 255 #define NVME_CQE_SC_INVALID_FIELD (0x02 << 1) 256 #define NVME_CQE_SC_CID_CONFLICT (0x03 << 1) 257 #define NVME_CQE_SC_DATA_XFER_ERR (0x04 << 1) 258 #define NVME_CQE_SC_ABRT_BY_NO_PWR (0x05 << 1) 259 #define NVME_CQE_SC_INTERNAL_DEV_ERR (0x06 << 1) 260 #define NVME_CQE_SC_CMD_ABRT_REQD (0x07 << 1) 261 #define NVME_CQE_SC_CMD_ABDR_SQ_DEL (0x08 << 1) 262 #define NVME_CQE_SC_CMD_ABDR_FUSE_ERR (0x09 << 1) 263 #define NVME_CQE_SC_CMD_ABDR_FUSE_MISS (0x0a << 1) 264 #define NVME_CQE_SC_INVALID_NS (0x0b << 1) 265 #define NVME_CQE_SC_CMD_SEQ_ERR (0x0c << 1) 266 #define NVME_CQE_SC_INVALID_LAST_SGL (0x0d << 1) 267 #define NVME_CQE_SC_INVALID_NUM_SGL (0x0e << 1) 268 #define NVME_CQE_SC_DATA_SGL_LEN (0x0f << 1) 269 #define NVME_CQE_SC_MDATA_SGL_LEN (0x10 << 1) 270 #define NVME_CQE_SC_SGL_TYPE_INVALID (0x11 << 1) 271 #define NVME_CQE_SC_LBA_RANGE (0x80 << 1) 272 #define NVME_CQE_SC_CAP_EXCEEDED (0x81 << 1) 273 #define NVME_CQE_SC_NS_NOT_RDY (0x82 << 1) 274 #define NVME_CQE_SC_RSV_CONFLICT (0x83 << 1) 275 /* command specific status codes */ 276 #define NVME_CQE_SC_CQE_INVALID (0x00 << 1) 277 #define NVME_CQE_SC_INVALID_QID (0x01 << 1) 278 #define NVME_CQE_SC_MAX_Q_SIZE (0x02 << 1) 279 #define NVME_CQE_SC_ABORT_LIMIT (0x03 << 1) 280 #define NVME_CQE_SC_ASYNC_EV_REQ_LIMIT (0x05 << 1) 281 #define NVME_CQE_SC_INVALID_FW_SLOT (0x06 << 1) 282 #define NVME_CQE_SC_INVALID_FW_IMAGE (0x07 << 1) 283 #define NVME_CQE_SC_INVALID_INT_VEC (0x08 << 1) 284 #define NVME_CQE_SC_INVALID_LOG_PAGE (0x09 << 1) 285 #define NVME_CQE_SC_INVALID_FORMAT (0x0a << 1) 286 #define NVME_CQE_SC_FW_REQ_CNV_RESET (0x0b << 1) 287 #define NVME_CQE_SC_FW_REQ_NVM_RESET (0x10 << 1) 288 #define NVME_CQE_SC_FW_REQ_RESET (0x11 << 1) 289 #define NVME_CQE_SC_FW_MAX_TIME_VIO (0x12 << 1) 290 #define NVME_CQE_SC_FW_PROHIBIT (0x13 << 1) 291 #define NVME_CQE_SC_OVERLAP_RANGE (0x14 << 1) 292 #define NVME_CQE_SC_CONFLICT_ATTRS (0x80 << 1) 293 #define NVME_CQE_SC_INVALID_PROT_INFO (0x81 << 1) 294 #define NVME_CQE_SC_ATT_WR_TO_RO_PAGE (0x82 << 1) 295 /* media error status codes */ 296 #define NVME_CQE_SC_WRITE_FAULTS (0x80 << 1) 297 #define NVME_CQE_SC_UNRECV_READ_ERR (0x81 << 1) 298 #define NVME_CQE_SC_GUARD_CHECK_ERR (0x82 << 1) 299 #define NVME_CQE_SC_APPL_TAG_CHECK_ERR (0x83 << 1) 300 #define NVME_CQE_SC_REF_TAG_CHECK_ERR (0x84 << 1) 301 #define NVME_CQE_SC_CMP_FAIL (0x85 << 1) 302 #define NVME_CQE_SC_ACCESS_DENIED (0x86 << 1) 303 #define NVME_CQE_PHASE __BIT(0) 304 } __packed __aligned(8); 305 NVME_CTASSERT(sizeof(struct nvme_cqe) == 16, "bad size for nvme_cqe"); 306 307 #define NVM_ADMIN_DEL_IOSQ 0x00 /* Delete I/O Submission Queue */ 308 #define NVM_ADMIN_ADD_IOSQ 0x01 /* Create I/O Submission Queue */ 309 #define NVM_ADMIN_GET_LOG_PG 0x02 /* Get Log Page */ 310 #define NVM_ADMIN_DEL_IOCQ 0x04 /* Delete I/O Completion Queue */ 311 #define NVM_ADMIN_ADD_IOCQ 0x05 /* Create I/O Completion Queue */ 312 #define NVM_ADMIN_IDENTIFY 0x06 /* Identify */ 313 #define NVM_ADMIN_ABORT 0x08 /* Abort */ 314 #define NVM_ADMIN_SET_FEATURES 0x09 /* Set Features */ 315 #define NVM_ADMIN_GET_FEATURES 0x0a /* Get Features */ 316 #define NVM_ADMIN_ASYNC_EV_REQ 0x0c /* Asynchronous Event Request */ 317 #define NVM_ADMIN_NS_MANAGEMENT 0x0d /* Namespace Management */ 318 /* 0x0e-0x0f - reserved */ 319 #define NVM_ADMIN_FW_COMMIT 0x10 /* Firmware Commit */ 320 #define NVM_ADMIN_FW_DOWNLOAD 0x11 /* Firmware Image Download */ 321 #define NVM_ADMIN_DEV_SELFTEST 0x14 /* Device Self Test */ 322 #define NVM_ADMIN_NS_ATTACHMENT 0x15 /* Namespace Attachment */ 323 #define NVM_ADMIN_KEEP_ALIVE 0x18 /* Keep Alive */ 324 #define NVM_ADMIN_DIRECTIVE_SND 0x19 /* Derective Send */ 325 #define NVM_ADMIN_DIRECTIVE_RCV 0x1a /* Derective Receive */ 326 #define NVM_ADMIN_VIRT_MGMT 0x1c /* Virtualization Management */ 327 #define NVM_ADMIN_NVME_MI_SEND 0x1d /* NVMe-MI Send */ 328 #define NVM_ADMIN_NVME_MI_RECV 0x1e /* NVMe-MI Receive */ 329 #define NVM_ADMIN_DOORBELL_BC 0x7c /* Doorbell Buffer Config */ 330 #define NVM_ADMIN_FORMAT_NVM 0x80 /* Format NVM */ 331 #define NVM_ADMIN_SECURITY_SND 0x81 /* Security Send */ 332 #define NVM_ADMIN_SECURITY_RCV 0x82 /* Security Receive */ 333 #define NVM_ADMIN_SANITIZE 0x84 /* Sanitize */ 334 335 #define NVM_CMD_FLUSH 0x00 /* Flush */ 336 #define NVM_CMD_WRITE 0x01 /* Write */ 337 #define NVM_CMD_READ 0x02 /* Read */ 338 #define NVM_CMD_WR_UNCOR 0x04 /* Write Uncorrectable */ 339 #define NVM_CMD_COMPARE 0x05 /* Compare */ 340 /* 0x06-0x07 - reserved */ 341 #define NVM_CMD_WRITE_ZEROES 0x08 /* Write Zeroes */ 342 #define NVM_CMD_DSM 0x09 /* Dataset Management */ 343 344 /* Features for GET/SET FEATURES */ 345 /* 0x00 - reserved */ 346 #define NVM_FEAT_ARBITRATION 0x01 347 #define NVM_FEAT_POWER_MANAGEMENT 0x02 348 #define NVM_FEAT_LBA_RANGE_TYPE 0x03 349 #define NVM_FEAT_TEMPERATURE_THRESHOLD 0x04 350 #define NVM_FEAT_ERROR_RECOVERY 0x05 351 #define NVM_FEATURE_VOLATILE_WRITE_CACHE 0x06 /* optional */ 352 #define NVM_FEATURE_NUMBER_OF_QUEUES 0x07 /* mandatory */ 353 #define NVM_FEAT_INTERRUPT_COALESCING 0x08 354 #define NVM_FEAT_INTERRUPT_VECTOR_CONFIGURATION 0x09 355 #define NVM_FEAT_WRITE_ATOMICITY 0x0a 356 #define NVM_FEAT_ASYNC_EVENT_CONFIGURATION 0x0b 357 #define NVM_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION 0x0c 358 #define NVM_FEAT_HOST_MEMORY_BUFFER 0x0d 359 #define NVM_FEAT_TIMESTAMP 0x0e 360 #define NVM_FEAT_KEEP_ALIVE_TIMER 0x0f 361 #define NVM_FEAT_HOST_CONTROLLED_THERMAL_MGMT 0x10 362 #define NVM_FEAT_NON_OP_POWER_STATE_CONFIG 0x11 363 /* 0x12-0x77 - reserved */ 364 /* 0x78-0x7f - NVMe Management Interface */ 365 #define NVM_FEAT_SOFTWARE_PROGRESS_MARKER 0x80 366 #define NVM_FEAT_HOST_IDENTIFIER 0x81 367 #define NVM_FEAT_RESERVATION_NOTIFICATION_MASK 0x82 368 #define NVM_FEAT_RESERVATION_PERSISTANCE 0x83 369 /* 0x84-0xBF - command set specific (reserved) */ 370 /* 0xC0-0xFF - vendor specific */ 371 372 /* Power State Descriptor Data */ 373 struct nvm_identify_psd { 374 uint16_t mp; /* Max Power */ 375 uint8_t _reserved1; 376 uint8_t flags; 377 #define NVME_PSD_NOPS __BIT(1) 378 #define NVME_PSD_MPS __BIT(0) 379 380 uint32_t enlat; /* Entry Latency */ 381 382 uint32_t exlat; /* Exit Latency */ 383 384 uint8_t rrt; /* Relative Read Throughput */ 385 #define NVME_PSD_RRT_MASK __BITS(0, 4) 386 uint8_t rrl; /* Relative Read Latency */ 387 #define NVME_PSD_RRL_MASK __BITS(0, 4) 388 uint8_t rwt; /* Relative Write Throughput */ 389 #define NVME_PSD_RWT_MASK __BITS(0, 4) 390 uint8_t rwl; /* Relative Write Latency */ 391 #define NVME_PSD_RWL_MASK __BITS(0, 4) 392 393 uint16_t idlp; /* Idle Power */ 394 uint8_t ips; /* Idle Power Scale */ 395 #define NVME_PSD_IPS_MASK __BITS(0, 1) 396 uint8_t _reserved2; 397 uint16_t actp; /* Active Power */ 398 uint16_t ap; /* Active Power Workload/Scale */ 399 #define NVME_PSD_APW_MASK __BITS(0, 2) 400 #define NVME_PSD_APS_MASK __BITS(6, 7) 401 402 uint8_t _reserved[8]; 403 } __packed __aligned(8); 404 NVME_CTASSERT(sizeof(struct nvm_identify_psd) == 32, "bad size for nvm_identify_psd"); 405 406 struct nvm_identify_controller { 407 /* Controller Capabilities and Features */ 408 409 uint16_t vid; /* PCI Vendor ID */ 410 uint16_t ssvid; /* PCI Subsystem Vendor ID */ 411 412 uint8_t sn[20]; /* Serial Number */ 413 uint8_t mn[40]; /* Model Number */ 414 uint8_t fr[8]; /* Firmware Revision */ 415 416 uint8_t rab; /* Recommended Arbitration Burst */ 417 uint8_t ieee[3]; /* IEEE OUI Identifier */ 418 419 uint8_t cmic; /* Controller Multi-Path I/O and 420 Namespace Sharing Capabilities */ 421 uint8_t mdts; /* Maximum Data Transfer Size */ 422 423 uint16_t cntlid; /* Controller ID */ 424 uint32_t ver; /* Version */ 425 426 uint32_t rtd3r; /* RTD3 Resume Latency */ 427 uint32_t rtd3e; /* RTD3 Enter Latency */ 428 429 uint32_t oaes; /* Optional Asynchronous Events Supported */ 430 uint32_t ctrattr; /* Controller Attributes */ 431 432 uint8_t _reserved1[12]; 433 434 uint8_t fguid[16]; /* FRU Globally Unique Identifier */ 435 436 uint8_t _reserved2[128]; 437 438 /* Admin Command Set Attributes & Optional Controller Capabilities */ 439 440 uint16_t oacs; /* Optional Admin Command Support */ 441 #define NVME_ID_CTRLR_OACS_DOORBELL_BC __BIT(8) 442 #define NVME_ID_CTRLR_OACS_VIRT_MGMT __BIT(7) 443 #define NVME_ID_CTRLR_OACS_NVME_MI __BIT(6) 444 #define NVME_ID_CTRLR_OACS_DIRECTIVES __BIT(5) 445 #define NVME_ID_CTRLR_OACS_DEV_SELFTEST __BIT(4) 446 #define NVME_ID_CTRLR_OACS_NS __BIT(3) 447 #define NVME_ID_CTRLR_OACS_FW __BIT(2) 448 #define NVME_ID_CTRLR_OACS_FORMAT __BIT(1) 449 #define NVME_ID_CTRLR_OACS_SECURITY __BIT(0) 450 uint8_t acl; /* Abort Command Limit */ 451 uint8_t aerl; /* Asynchronous Event Request Limit */ 452 453 uint8_t frmw; /* Firmware Updates */ 454 #define NVME_ID_CTRLR_FRMW_NOREQ_RESET __BIT(4) 455 #define NVME_ID_CTRLR_FRMW_NSLOT __BITS(1, 3) 456 #define NVME_ID_CTRLR_FRMW_SLOT1_RO __BIT(0) 457 uint8_t lpa; /* Log Page Attributes */ 458 #define NVME_ID_CTRLR_LPA_CMD_EFFECT __BIT(1) 459 #define NVME_ID_CTRLR_LPA_NS_SMART __BIT(0) 460 uint8_t elpe; /* Error Log Page Entries */ 461 uint8_t npss; /* Number of Power States Support */ 462 463 uint8_t avscc; /* Admin Vendor Specific Command 464 Configuration */ 465 uint8_t apsta; /* Autonomous Power State Transition 466 Attributes */ 467 468 uint16_t wctemp; /* Warning Composite Temperature 469 Threshold */ 470 uint16_t cctemp; /* Critical Composite Temperature 471 Threshold */ 472 473 uint16_t mtfa; /* Maximum Time for Firmware Activation */ 474 475 uint32_t hmpre; /* Host Memory Buffer Preferred Size */ 476 uint32_t hmmin; /* Host Memory Buffer Minimum Size */ 477 478 struct { 479 uint64_t tnvmcap[2]; 480 uint64_t unvmcap[2]; 481 } __packed untncap; /* Name space capabilities: 482 if NVME_ID_CTRLR_OACS_NS, 483 report tnvmcap and unvmcap */ 484 485 uint32_t rpmbs; /* Replay Protected Memory Block Support */ 486 487 uint16_t edstt; /* Extended Device Self-test Time */ 488 uint8_t dsto; /* Device Self-test Options */ 489 490 uint8_t fwug; /* Firmware Update Granularity */ 491 492 uint16_t kas; /* Keep Alive Support */ 493 494 uint16_t hctma; /* Host Controlled Thermal Management 495 Attributes */ 496 uint16_t mntmt; /* Minimum Thermal Management Temperature */ 497 uint16_t mxtmt; /* Maximum Thermal Management Temperature */ 498 499 uint32_t sanicap; /* Sanitize Capabilities */ 500 501 uint8_t _reserved3[180]; 502 503 /* NVM Command Set Attributes */ 504 505 uint8_t sqes; /* Submission Queue Entry Size */ 506 #define NVME_ID_CTRLR_SQES_MAX __BITS(4, 7) 507 #define NVME_ID_CTRLR_SQES_MIN __BITS(0, 3) 508 uint8_t cqes; /* Completion Queue Entry Size */ 509 #define NVME_ID_CTRLR_CQES_MAX __BITS(4, 7) 510 #define NVME_ID_CTRLR_CQES_MIN __BITS(0, 3) 511 512 uint16_t maxcmd; /* Maximum Outstanding Commands */ 513 514 uint32_t nn; /* Number of Namespaces */ 515 516 uint16_t oncs; /* Optional NVM Command Support */ 517 #define NVME_ID_CTRLR_ONCS_RESERVATION __BIT(5) 518 #define NVME_ID_CTRLR_ONCS_SET_FEATURES __BIT(4) 519 #define NVME_ID_CTRLR_ONCS_WRITE_ZERO __BIT(3) 520 #define NVME_ID_CTRLR_ONCS_DSM __BIT(2) 521 #define NVME_ID_CTRLR_ONCS_WRITE_UNC __BIT(1) 522 #define NVME_ID_CTRLR_ONCS_COMPARE __BIT(0) 523 uint16_t fuses; /* Fused Operation Support */ 524 525 uint8_t fna; /* Format NVM Attributes */ 526 #define NVME_ID_CTRLR_FNA_CRYPTO_ERASE __BIT(2) 527 #define NVME_ID_CTRLR_FNA_ERASE_ALL __BIT(1) 528 #define NVME_ID_CTRLR_FNA_FORMAT_ALL __BIT(0) 529 uint8_t vwc; /* Volatile Write Cache */ 530 #define NVME_ID_CTRLR_VWC_PRESENT __BIT(0) 531 uint16_t awun; /* Atomic Write Unit Normal */ 532 uint16_t awupf; /* Atomic Write Unit Power Fail */ 533 534 uint8_t nvscc; /* NVM Vendor Specific Command */ 535 uint8_t _reserved4[1]; 536 537 uint16_t acwu; /* Atomic Compare & Write Unit */ 538 uint8_t _reserved5[2]; 539 540 uint32_t sgls; /* SGL Support */ 541 542 uint8_t _reserved6[228]; 543 544 uint8_t subnqn[256]; /* NVM Subsystem NVMe Qualified Name */ 545 546 uint8_t _reserved7[768]; 547 548 uint8_t _reserved8[256]; /* NVMe over Fabrics specification */ 549 550 struct nvm_identify_psd psd[32]; /* Power State Descriptors */ 551 552 uint8_t vs[1024]; /* Vendor Specific */ 553 } __packed __aligned(8); 554 NVME_CTASSERT(sizeof(struct nvm_identify_controller) == 4096, "bad size for nvm_identify_controller"); 555 556 struct nvm_namespace_format { 557 uint16_t ms; /* Metadata Size */ 558 uint8_t lbads; /* LBA Data Size */ 559 uint8_t rp; /* Relative Performance */ 560 } __packed __aligned(4); 561 NVME_CTASSERT(sizeof(struct nvm_namespace_format) == 4, "bad size for nvm_namespace_format"); 562 563 struct nvm_identify_namespace { 564 uint64_t nsze; /* Namespace Size */ 565 566 uint64_t ncap; /* Namespace Capacity */ 567 568 uint64_t nuse; /* Namespace Utilization */ 569 570 uint8_t nsfeat; /* Namespace Features */ 571 #define NVME_ID_NS_NSFEAT_LOGICAL_BLK_ERR __BIT(2) 572 #define NVME_ID_NS_NSFEAT_NS __BIT(1) 573 #define NVME_ID_NS_NSFEAT_THIN_PROV __BIT(0) 574 uint8_t nlbaf; /* Number of LBA Formats */ 575 uint8_t flbas; /* Formatted LBA Size */ 576 #define NVME_ID_NS_FLBAS(_f) ((_f) & 0x0f) 577 #define NVME_ID_NS_FLBAS_MD 0x10 578 uint8_t mc; /* Metadata Capabilities */ 579 uint8_t dpc; /* End-to-end Data Protection 580 Capabilities */ 581 uint8_t dps; /* End-to-end Data Protection Type 582 Settings */ 583 #define NVME_ID_NS_DPS_MD_START __BIT(3) 584 #define NVME_ID_NS_DPS_PIT(_f) ((_f) & 0x7) 585 586 uint8_t nmic; /* Namespace Multi-path I/O and Namespace 587 Sharing Capabilities */ 588 589 uint8_t rescap; /* Reservation Capabilities */ 590 591 uint8_t fpi; /* Format Progress Indicator */ 592 593 uint8_t dlfeat; /* Deallocate Logical Block Features */ 594 595 uint16_t nawun; /* Namespace Atomic Write Unit Normal */ 596 uint16_t nawupf; /* Namespace Atomic Write Unit Power Fail */ 597 uint16_t nacwu; /* Namespace Atomic Compare & Write Unit */ 598 uint16_t nabsn; /* Namespace Atomic Boundary Size Normal */ 599 uint16_t nabo; /* Namespace Atomic Boundary Offset */ 600 uint16_t nabspf; /* Namespace Atomic Boundary Size Power 601 Fail */ 602 uint16_t noiob; /* Namespace Optimal IO Boundary */ 603 604 uint8_t nvmcap[16]; /* NVM Capacity */ 605 606 uint8_t _reserved1[40]; /* bytes 64-103: Reserved */ 607 608 uint8_t nguid[16]; /* Namespace Globally Unique Identifier */ 609 uint8_t eui64[8]; /* IEEE Extended Unique Identifier */ 610 611 struct nvm_namespace_format 612 lbaf[16]; /* LBA Format Support */ 613 614 uint8_t _reserved2[192]; 615 616 uint8_t vs[3712]; 617 } __packed __aligned(8); 618 NVME_CTASSERT(sizeof(struct nvm_identify_namespace) == 4096, "bad size for nvm_identify_namespace"); 619 620 #endif /* __NVMEREG_H__ */ 621