1 /* $NetBSD: ncr53c9xreg.h,v 1.4 1997/05/17 20:56:55 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Peter Galbavy. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Register addresses, relative to some base address 34 */ 35 36 #define NCR_TCL 0x00 /* RW - Transfer Count Low */ 37 #define NCR_TCM 0x01 /* RW - Transfer Count Mid */ 38 #define NCR_TCH 0x0e /* RW - Transfer Count High */ 39 /* NOT on 53C90 */ 40 41 #define NCR_FIFO 0x02 /* RW - FIFO data */ 42 43 #define NCR_CMD 0x03 /* RW - Command (2 deep) */ 44 #define NCRCMD_DMA 0x80 /* DMA Bit */ 45 #define NCRCMD_NOP 0x00 /* No Operation */ 46 #define NCRCMD_FLUSH 0x01 /* Flush FIFO */ 47 #define NCRCMD_RSTCHIP 0x02 /* Reset Chip */ 48 #define NCRCMD_RSTSCSI 0x03 /* Reset SCSI Bus */ 49 #define NCRCMD_RESEL 0x40 /* Reselect Sequence */ 50 #define NCRCMD_SELNATN 0x41 /* Select without ATN */ 51 #define NCRCMD_SELATN 0x42 /* Select with ATN */ 52 #define NCRCMD_SELATNS 0x43 /* Select with ATN & Stop */ 53 #define NCRCMD_ENSEL 0x44 /* Enable (Re)Selection */ 54 #define NCRCMD_DISSEL 0x45 /* Disable (Re)Selection */ 55 #define NCRCMD_SELATN3 0x46 /* Select with ATN3 */ 56 #define NCRCMD_RESEL3 0x47 /* Reselect3 Sequence */ 57 #define NCRCMD_SNDMSG 0x20 /* Send Message */ 58 #define NCRCMD_SNDSTAT 0x21 /* Send Status */ 59 #define NCRCMD_SNDDATA 0x22 /* Send Data */ 60 #define NCRCMD_DISCSEQ 0x23 /* Disconnect Sequence */ 61 #define NCRCMD_TERMSEQ 0x24 /* Terminate Sequence */ 62 #define NCRCMD_TCCS 0x25 /* Target Command Comp Seq */ 63 #define NCRCMD_DISC 0x27 /* Disconnect */ 64 #define NCRCMD_RECMSG 0x28 /* Receive Message */ 65 #define NCRCMD_RECCMD 0x29 /* Receive Command */ 66 #define NCRCMD_RECDATA 0x2a /* Receive Data */ 67 #define NCRCMD_RECCSEQ 0x2b /* Receive Command Sequence*/ 68 #define NCRCMD_ABORT 0x04 /* Target Abort DMA */ 69 #define NCRCMD_TRANS 0x10 /* Transfer Information */ 70 #define NCRCMD_ICCS 0x11 /* Initiator Cmd Comp Seq */ 71 #define NCRCMD_MSGOK 0x12 /* Message Accepted */ 72 #define NCRCMD_TRPAD 0x18 /* Transfer Pad */ 73 #define NCRCMD_SETATN 0x1a /* Set ATN */ 74 #define NCRCMD_RSTATN 0x1b /* Reset ATN */ 75 76 #define NCR_STAT 0x04 /* RO - Status */ 77 #define NCRSTAT_INT 0x80 /* Interrupt */ 78 #define NCRSTAT_GE 0x40 /* Gross Error */ 79 #define NCRSTAT_PE 0x20 /* Parity Error */ 80 #define NCRSTAT_TC 0x10 /* Terminal Count */ 81 #define NCRSTAT_VGC 0x08 /* Valid Group Code */ 82 #define NCRSTAT_PHASE 0x07 /* Phase bits */ 83 84 #define NCR_SELID 0x04 /* WO - Select/Reselect Bus ID */ 85 86 #define NCR_INTR 0x05 /* RO - Interrupt */ 87 #define NCRINTR_SBR 0x80 /* SCSI Bus Reset */ 88 #define NCRINTR_ILL 0x40 /* Illegal Command */ 89 #define NCRINTR_DIS 0x20 /* Disconnect */ 90 #define NCRINTR_BS 0x10 /* Bus Service */ 91 #define NCRINTR_FC 0x08 /* Function Complete */ 92 #define NCRINTR_RESEL 0x04 /* Reselected */ 93 #define NCRINTR_SELATN 0x02 /* Select with ATN */ 94 #define NCRINTR_SEL 0x01 /* Selected */ 95 96 #define NCR_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */ 97 98 #define NCR_STEP 0x06 /* RO - Sequence Step */ 99 #define NCRSTEP_MASK 0x07 /* the last 3 bits */ 100 #define NCRSTEP_DONE 0x04 /* command went out */ 101 102 #define NCR_SYNCTP 0x06 /* WO - Synch Transfer Period */ 103 /* Default 5 (53C9X) */ 104 105 #define NCR_FFLAG 0x07 /* RO - FIFO Flags */ 106 #define NCRFIFO_SS 0xe0 /* Sequence Step (Dup) */ 107 #define NCRFIFO_FF 0x1f /* Bytes in FIFO */ 108 109 #define NCR_SYNCOFF 0x07 /* WO - Synch Offset */ 110 /* 0 = ASYNC */ 111 /* 1 - 15 = SYNC bytes */ 112 113 #define NCR_CFG1 0x08 /* RW - Configuration #1 */ 114 #define NCRCFG1_SLOW 0x80 /* Slow Cable Mode */ 115 #define NCRCFG1_SRR 0x40 /* SCSI Reset Rep Int Dis */ 116 #define NCRCFG1_PTEST 0x20 /* Parity Test Mod */ 117 #define NCRCFG1_PARENB 0x10 /* Enable Parity Check */ 118 #define NCRCFG1_CTEST 0x08 /* Enable Chip Test */ 119 #define NCRCFG1_BUSID 0x07 /* Bus ID */ 120 121 #define NCR_CCF 0x09 /* WO - Clock Conversion Factor */ 122 /* 0 = 35.01 - 40Mhz */ 123 /* NEVER SET TO 1 */ 124 /* 2 = 10Mhz */ 125 /* 3 = 10.01 - 15Mhz */ 126 /* 4 = 15.01 - 20Mhz */ 127 /* 5 = 20.01 - 25Mhz */ 128 /* 6 = 25.01 - 30Mhz */ 129 /* 7 = 30.01 - 35Mhz */ 130 131 #define NCR_TEST 0x0a /* WO - Test (Chip Test Only) */ 132 133 #define NCR_CFG2 0x0b /* RW - Configuration #2 */ 134 #define NCRCFG2_RSVD 0xa0 /* reserved */ 135 #define NCRCFG2_FE 0x40 /* Features Enable */ 136 #define NCRCFG2_DREQ 0x10 /* DREQ High Impedance */ 137 #define NCRCFG2_SCSI2 0x08 /* SCSI-2 Enable */ 138 #define NCRCFG2_BPA 0x04 /* Target Bad Parity Abort */ 139 #define NCRCFG2_RPE 0x02 /* Register Parity Error */ 140 #define NCRCFG2_DPE 0x01 /* DMA Parity Error */ 141 142 /* Config #3 only on 53C9X */ 143 #define NCR_CFG3 0x0c /* RW - Configuration #3 */ 144 #define NCRCFG3_RSVD 0xe0 /* reserved */ 145 #define NCRCFG3_IDM 0x10 /* ID Message Res Check */ 146 #define NCRCFG3_QTE 0x08 /* Queue Tag Enable */ 147 #define NCRCFG3_CDB 0x04 /* CDB 10-bytes OK */ 148 #define NCRCFG3_FSCSI 0x02 /* Fast SCSI */ 149 #define NCRCFG3_FCLK 0x01 /* Fast Clock (>25Mhz) */ 150 151 /* 152 * For some unknown reason, the ESP406/FAS408 looks like every 153 * other ncr53c9x, except for configuration #3 register. At any 154 * rate, if you're dealing with these chips, you need to use these 155 * defines instead. 156 */ 157 158 /* Config #3 different on ESP406/FAS408 */ 159 #define NCR_ESPCFG3 0x0c /* RW - Configuration #3 */ 160 #define NCRESPCFG3_IDM 0x80 /* ID Message Res Check */ 161 #define NCRESPCFG3_QTE 0x40 /* Queue Tag Enable */ 162 #define NCRESPCFG3_CDB 0x20 /* CDB 10-bytes OK */ 163 #define NCRESPCFG3_FSCSI 0x10 /* Fast SCSI */ 164 #define NCRESPCFG3_SRESB 0x08 /* Save Residual Byte */ 165 #define NCRESPCFG3_FCLK 0x04 /* Fast Clock (>25Mhz) */ 166 #define NCRESPCFG3_ADMA 0x02 /* Alternate DMA Mode */ 167 #define NCRESPCFG3_T8M 0x01 /* Threshold 8 Mode */ 168 169 /* Config #4 only on ESP406/FAS408 */ 170 #define NCR_CFG4 0x0d /* RW - Configuration #4 */ 171 #define NCRCFG4_CRS1 0x80 /* Select register set #1 */ 172 #define NCRCFG4_RSVD 0x7b /* reserved */ 173 #define NCRCFG4_ACTNEG 0x04 /* Active negation */ 174 175 #define NCR_SCSIREGS(sc) do { NCR_WRITE_REG(sc, NCR_CFG4, \ 176 ~NCRCFG4_CRS1 & NCR_READ_REG(sc, NCR_CFG4)); } while(0) 177 #define NCR_PIOREGS(sc) do { NCR_WRITE_REG(sc, NCR_CFG4, \ 178 NCRCFG4_CRS1 | NCR_READ_REG(sc, NCR_CFG4)); } while(0) 179 180 /* 181 The following registers are only on the ESP406/FAS408. The 182 documentation refers to them as "Control Register Set #1". 183 These are the registers that are visible when bit 7 of 184 register 0x0d is set. This bit is common to both register sets. 185 */ 186 187 #define NCR_JMP 0x00 /* RO - Jumper Sense Register */ 188 #define NCRJMP_RSVD 0xc0 /* reserved */ 189 #define NCRJMP_ROMSZ 0x20 /* ROM Size 1=16K, 0=32K */ 190 #define NCRJMP_J4 0x10 /* Jumper #4 */ 191 #define NCRJMP_J3 0x08 /* Jumper #3 */ 192 #define NCRJMP_J2 0x04 /* Jumper #2 */ 193 #define NCRJMP_J1 0x02 /* Jumper #1 */ 194 #define NCRJMP_J0 0x01 /* Jumper #0 */ 195 196 #define NCR_PIOFIFO 0x04 /* WO - PIO FIFO, 4 bytes deep */ 197 198 #define NCR_PSTAT 0x08 /* RW - PIO Status Register */ 199 #define NCRPSTAT_PERR 0x80 /* PIO Error */ 200 #define NCRPSTAT_SIRQ 0x40 /* Active High of SCSI IRQ */ 201 #define NCRPSTAT_ATAI 0x20 /* ATA IRQ */ 202 #define NCRPSTAT_FEMPT 0x10 /* PIO FIFO Empty */ 203 #define NCRPSTAT_F13 0x08 /* PIO FIFO 1/3 */ 204 #define NCRPSTAT_F23 0x04 /* PIO FIFO 2/3 */ 205 #define NCRPSTAT_FFULL 0x02 /* PIO FIFO Full */ 206 #define NCRPSTAT_PIOM 0x01 /* PIO/DMA Mode */ 207 208 #define NCR_PIOI 0x0b /* RW - PIO Interrupt Enable */ 209 #define NCRPIOI_RSVD 0xe0 /* reserved */ 210 #define NCRPIOI_EMPTY 0x10 /* IRQ When Empty */ 211 #define NCRPIOI_13 0x08 /* IRQ When 1/3 */ 212 #define NCRPIOI_23 0x04 /* IRQ When 2/3 */ 213 #define NCRPIOI_FULL 0x02 /* IRQ When Full */ 214 #define NCRPIOI_FINV 0x01 /* Flag Invert */ 215 216 #define NCR_CFG5 0x0d /* RW - Configuration #5 */ 217 #define NCRCFG5_CRS1 0x80 /* Select Register Set #1 */ 218 #define NCRCFG5_SRAM 0x40 /* SRAM Memory Map */ 219 #define NCRCFG5_AADDR 0x20 /* Auto Address */ 220 #define NCRCFG5_PTRINC 0x10 /* Pointer Increment */ 221 #define NCRCFG5_LOWPWR 0x08 /* Low Power Mode */ 222 #define NCRCFG5_SINT 0x04 /* SCSI Interupt Enable */ 223 #define NCRCFG5_INTP 0x02 /* INT Polarity */ 224 #define NCRCFG5_AINT 0x01 /* ATA Interupt Enable */ 225 226 #define NCR_SIGNTR 0x0e /* RO - Signature */ 227