1 /* $NetBSD: ncr53c9x.c,v 1.21 1997/10/26 16:45:24 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1994 Peter Galbavy 34 * Copyright (c) 1995 Paul Kranenburg 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Peter Galbavy 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 53 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 54 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 59 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 60 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Based on aic6360 by Jarle Greipsland 66 * 67 * Acknowledgements: Many of the algorithms used in this driver are 68 * inspired by the work of Julian Elischer (julian@tfs.com) and 69 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! 70 */ 71 72 #include <sys/types.h> 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/kernel.h> 76 #include <sys/errno.h> 77 #include <sys/ioctl.h> 78 #include <sys/device.h> 79 #include <sys/buf.h> 80 #include <sys/proc.h> 81 #include <sys/user.h> 82 #include <sys/queue.h> 83 84 #include <dev/scsipi/scsi_all.h> 85 #include <dev/scsipi/scsipi_all.h> 86 #include <dev/scsipi/scsiconf.h> 87 #include <dev/scsipi/scsi_message.h> 88 89 #include <machine/cpu.h> 90 91 #include <dev/ic/ncr53c9xreg.h> 92 #include <dev/ic/ncr53c9xvar.h> 93 94 int ncr53c9x_debug = 0; /*NCR_SHOWPHASE|NCR_SHOWMISC|NCR_SHOWTRAC|NCR_SHOWCMDS;*/ 95 96 /*static*/ void ncr53c9x_readregs __P((struct ncr53c9x_softc *)); 97 /*static*/ void ncr53c9x_select __P((struct ncr53c9x_softc *, 98 struct ncr53c9x_ecb *)); 99 /*static*/ int ncr53c9x_reselect __P((struct ncr53c9x_softc *, int)); 100 /*static*/ void ncr53c9x_scsi_reset __P((struct ncr53c9x_softc *)); 101 /*static*/ void ncr53c9x_init __P((struct ncr53c9x_softc *, int)); 102 /*static*/ int ncr53c9x_poll __P((struct ncr53c9x_softc *, 103 struct scsipi_xfer *, int)); 104 /*static*/ void ncr53c9x_sched __P((struct ncr53c9x_softc *)); 105 /*static*/ void ncr53c9x_done __P((struct ncr53c9x_softc *, 106 struct ncr53c9x_ecb *)); 107 /*static*/ void ncr53c9x_msgin __P((struct ncr53c9x_softc *)); 108 /*static*/ void ncr53c9x_msgout __P((struct ncr53c9x_softc *)); 109 /*static*/ void ncr53c9x_timeout __P((void *arg)); 110 /*static*/ void ncr53c9x_abort __P((struct ncr53c9x_softc *, 111 struct ncr53c9x_ecb *)); 112 /*static*/ void ncr53c9x_dequeue __P((struct ncr53c9x_softc *, 113 struct ncr53c9x_ecb *)); 114 115 void ncr53c9x_sense __P((struct ncr53c9x_softc *, 116 struct ncr53c9x_ecb *)); 117 void ncr53c9x_free_ecb __P((struct ncr53c9x_softc *, 118 struct ncr53c9x_ecb *, int)); 119 struct ncr53c9x_ecb *ncr53c9x_get_ecb __P((struct ncr53c9x_softc *, int)); 120 121 static inline int ncr53c9x_stp2cpb __P((struct ncr53c9x_softc *, int)); 122 static inline void ncr53c9x_setsync __P((struct ncr53c9x_softc *, 123 struct ncr53c9x_tinfo *)); 124 125 /* 126 * Names for the NCR53c9x variants, correspnding to the variant tags 127 * in ncr53c9xvar.h. 128 */ 129 const char *ncr53c9x_variant_names[] = { 130 "ESP100", 131 "ESP100A", 132 "ESP200", 133 "NCR53C94", 134 "NCR53C96", 135 "ESP406", 136 "FAS408", 137 "FAS216", 138 }; 139 140 /* 141 * Attach this instance, and then all the sub-devices 142 */ 143 void 144 ncr53c9x_attach(sc, adapter, dev) 145 struct ncr53c9x_softc *sc; 146 struct scsipi_adapter *adapter; 147 struct scsipi_device *dev; 148 { 149 150 /* 151 * Note, the front-end has set us up to print the chip variation. 152 */ 153 154 if (sc->sc_rev >= NCR_VARIANT_MAX) { 155 printf("\n%s: unknown variant %d, devices not attached\n", 156 sc->sc_dev.dv_xname, sc->sc_rev); 157 return; 158 } 159 160 printf(": %s, %dMHz, SCSI ID %d\n", 161 ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id); 162 163 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 164 165 /* The value *must not* be == 1. Make it 2 */ 166 if (sc->sc_ccf == 1) 167 sc->sc_ccf = 2; 168 169 /* 170 * The recommended timeout is 250ms. This register is loaded 171 * with a value calculated as follows, from the docs: 172 * 173 * (timout period) x (CLK frequency) 174 * reg = ------------------------------------- 175 * 8192 x (Clock Conversion Factor) 176 * 177 * Since CCF has a linear relation to CLK, this generally computes 178 * to the constant of 153. 179 */ 180 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 181 182 /* CCF register only has 3 bits; 0 is actually 8 */ 183 sc->sc_ccf &= 7; 184 185 /* Reset state & bus */ 186 sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags; 187 sc->sc_state = 0; 188 ncr53c9x_init(sc, 1); 189 190 /* 191 * fill in the prototype scsipi_link. 192 */ 193 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 194 sc->sc_link.adapter_softc = sc; 195 sc->sc_link.scsipi_scsi.adapter_target = sc->sc_id; 196 sc->sc_link.adapter = adapter; 197 sc->sc_link.device = dev; 198 sc->sc_link.openings = 2; 199 sc->sc_link.scsipi_scsi.max_target = 7; 200 sc->sc_link.type = BUS_SCSI; 201 202 /* 203 * Now try to attach all the sub-devices 204 */ 205 config_found(&sc->sc_dev, &sc->sc_link, scsiprint); 206 207 /* 208 * Enable interupts from the SCSI core 209 */ 210 if ((sc->sc_rev == NCR_VARIANT_ESP406) || 211 (sc->sc_rev == NCR_VARIANT_FAS408)) { 212 NCR_PIOREGS(sc); 213 NCR_WRITE_REG(sc, NCR_CFG5, NCRCFG5_SINT | 214 NCR_READ_REG(sc, NCR_CFG5)); 215 NCR_SCSIREGS(sc); 216 } 217 } 218 219 /* 220 * This is the generic esp reset function. It does not reset the SCSI bus, 221 * only this controllers, but kills any on-going commands, and also stops 222 * and resets the DMA. 223 * 224 * After reset, registers are loaded with the defaults from the attach 225 * routine above. 226 */ 227 void 228 ncr53c9x_reset(sc) 229 struct ncr53c9x_softc *sc; 230 { 231 232 /* reset DMA first */ 233 NCRDMA_RESET(sc); 234 235 /* reset SCSI chip */ 236 NCRCMD(sc, NCRCMD_RSTCHIP); 237 NCRCMD(sc, NCRCMD_NOP); 238 DELAY(500); 239 240 /* do these backwards, and fall through */ 241 switch (sc->sc_rev) { 242 case NCR_VARIANT_ESP406: 243 case NCR_VARIANT_FAS408: 244 NCR_SCSIREGS(sc); 245 case NCR_VARIANT_FAS216: 246 case NCR_VARIANT_NCR53C94: 247 case NCR_VARIANT_NCR53C96: 248 case NCR_VARIANT_ESP200: 249 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 250 case NCR_VARIANT_ESP100A: 251 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 252 case NCR_VARIANT_ESP100: 253 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 254 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 255 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 256 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 257 break; 258 default: 259 printf("%s: unknown revision code, assuming ESP100\n", 260 sc->sc_dev.dv_xname); 261 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 262 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 263 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 264 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 265 } 266 } 267 268 /* 269 * Reset the SCSI bus, but not the chip 270 */ 271 void 272 ncr53c9x_scsi_reset(sc) 273 struct ncr53c9x_softc *sc; 274 { 275 276 (*sc->sc_glue->gl_dma_stop)(sc); 277 278 printf("%s: resetting SCSI bus\n", sc->sc_dev.dv_xname); 279 NCRCMD(sc, NCRCMD_RSTSCSI); 280 } 281 282 /* 283 * Initialize esp state machine 284 */ 285 void 286 ncr53c9x_init(sc, doreset) 287 struct ncr53c9x_softc *sc; 288 int doreset; 289 { 290 struct ncr53c9x_ecb *ecb; 291 int r; 292 293 NCR_TRACE(("[NCR_INIT(%d)] ", doreset)); 294 295 if (sc->sc_state == 0) { 296 /* First time through; initialize. */ 297 TAILQ_INIT(&sc->ready_list); 298 TAILQ_INIT(&sc->nexus_list); 299 TAILQ_INIT(&sc->free_list); 300 sc->sc_nexus = NULL; 301 ecb = sc->sc_ecb; 302 bzero(ecb, sizeof(sc->sc_ecb)); 303 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) { 304 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain); 305 ecb++; 306 } 307 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo)); 308 } else { 309 /* Cancel any active commands. */ 310 sc->sc_state = NCR_CLEANING; 311 if ((ecb = sc->sc_nexus) != NULL) { 312 ecb->xs->error = XS_TIMEOUT; 313 ncr53c9x_done(sc, ecb); 314 } 315 while ((ecb = sc->nexus_list.tqh_first) != NULL) { 316 ecb->xs->error = XS_TIMEOUT; 317 ncr53c9x_done(sc, ecb); 318 } 319 } 320 321 /* 322 * reset the chip to a known state 323 */ 324 ncr53c9x_reset(sc); 325 326 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 327 for (r = 0; r < 8; r++) { 328 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[r]; 329 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 330 331 ti->flags = ((sc->sc_minsync && !(sc->sc_cfflags & (1<<(r+8)))) 332 ? T_NEGOTIATE : 0) | 333 ((sc->sc_cfflags & (1<<r)) ? T_RSELECTOFF : 0) | 334 T_NEED_TO_RESET; 335 ti->period = sc->sc_minsync; 336 ti->offset = 0; 337 } 338 339 if (doreset) { 340 sc->sc_state = NCR_SBR; 341 NCRCMD(sc, NCRCMD_RSTSCSI); 342 } else { 343 sc->sc_state = NCR_IDLE; 344 ncr53c9x_sched(sc); 345 } 346 } 347 348 /* 349 * Read the NCR registers, and save their contents for later use. 350 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading 351 * NCR_INTR - so make sure it is the last read. 352 * 353 * I think that (from reading the docs) most bits in these registers 354 * only make sense when he DMA CSR has an interrupt showing. Call only 355 * if an interrupt is pending. 356 */ 357 void 358 ncr53c9x_readregs(sc) 359 struct ncr53c9x_softc *sc; 360 { 361 362 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT); 363 /* Only the stepo bits are of interest */ 364 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK; 365 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR); 366 367 if (sc->sc_glue->gl_clear_latched_intr != NULL) 368 (*sc->sc_glue->gl_clear_latched_intr)(sc); 369 370 /* 371 * Determine the SCSI bus phase, return either a real SCSI bus phase 372 * or some pseudo phase we use to detect certain exceptions. 373 */ 374 375 sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS) 376 ? /* Disconnected */ BUSFREE_PHASE 377 : sc->sc_espstat & NCRSTAT_PHASE; 378 379 NCR_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ", 380 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep)); 381 } 382 383 /* 384 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 385 */ 386 static inline int 387 ncr53c9x_stp2cpb(sc, period) 388 struct ncr53c9x_softc *sc; 389 int period; 390 { 391 int v; 392 v = (sc->sc_freq * period) / 250; 393 if (ncr53c9x_cpb2stp(sc, v) < period) 394 /* Correct round-down error */ 395 v++; 396 return v; 397 } 398 399 static inline void 400 ncr53c9x_setsync(sc, ti) 401 struct ncr53c9x_softc *sc; 402 struct ncr53c9x_tinfo *ti; 403 { 404 405 if (ti->flags & T_SYNCMODE) { 406 NCR_WRITE_REG(sc, NCR_SYNCOFF, ti->offset); 407 NCR_WRITE_REG(sc, NCR_SYNCTP, 408 ncr53c9x_stp2cpb(sc, ti->period)); 409 } else { 410 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 411 NCR_WRITE_REG(sc, NCR_SYNCTP, 0); 412 } 413 } 414 415 int ncr53c9x_dmaselect = 0; 416 /* 417 * Send a command to a target, set the driver state to NCR_SELECTING 418 * and let the caller take care of the rest. 419 * 420 * Keeping this as a function allows me to say that this may be done 421 * by DMA instead of programmed I/O soon. 422 */ 423 void 424 ncr53c9x_select(sc, ecb) 425 struct ncr53c9x_softc *sc; 426 struct ncr53c9x_ecb *ecb; 427 { 428 struct scsipi_link *sc_link = ecb->xs->sc_link; 429 int target = sc_link->scsipi_scsi.target; 430 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[target]; 431 u_char *cmd; 432 int clen; 433 434 NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x)] ", 435 sc_link->scsipi_scsi.target, sc_link->scsipi_scsi.lun, ecb->cmd.cmd.opcode)); 436 437 /* new state NCR_SELECTING */ 438 sc->sc_state = NCR_SELECTING; 439 440 /* 441 * Schedule the timeout now, the first time we will go away 442 * expecting to come back due to an interrupt, because it is 443 * always possible that the interrupt may never happen. 444 */ 445 if ((ecb->xs->flags & SCSI_POLL) == 0) 446 timeout(ncr53c9x_timeout, ecb, 447 (ecb->timeout * hz) / 1000); 448 449 /* 450 * The docs say the target register is never reset, and I 451 * can't think of a better place to set it 452 */ 453 NCR_WRITE_REG(sc, NCR_SELID, target); 454 ncr53c9x_setsync(sc, ti); 455 456 if (ncr53c9x_dmaselect && (ti->flags & T_NEGOTIATE) == 0) { 457 size_t dmacl; 458 ecb->cmd.id = 459 MSG_IDENTIFY(sc_link->scsipi_scsi.lun, 460 (ti->flags & T_RSELECTOFF)?0:1); 461 462 /* setup DMA transfer for command */ 463 clen = ecb->clen + 1; 464 sc->sc_cmdlen = clen; 465 sc->sc_cmdp = (caddr_t)&ecb->cmd; 466 dmacl = clen; 467 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmacl); 468 /* Program the SCSI counter */ 469 NCR_WRITE_REG(sc, NCR_TCL, clen); 470 NCR_WRITE_REG(sc, NCR_TCM, clen >> 8); 471 if (sc->sc_cfg2 & NCRCFG2_FE) { 472 NCR_WRITE_REG(sc, NCR_TCH, clen >> 16); 473 } 474 475 /* And get the targets attention */ 476 NCRCMD(sc, NCRCMD_SELATN | NCRCMD_DMA); 477 NCRDMA_GO(sc); 478 return; 479 } 480 /* 481 * Who am I. This is where we tell the target that we are 482 * happy for it to disconnect etc. 483 */ 484 NCR_WRITE_REG(sc, NCR_FIFO, 485 MSG_IDENTIFY(sc_link->scsipi_scsi.lun, (ti->flags & T_RSELECTOFF)?0:1)); 486 487 if (ti->flags & T_NEGOTIATE) { 488 /* Arbitrate, select and stop after IDENTIFY message */ 489 NCRCMD(sc, NCRCMD_SELATNS); 490 return; 491 } 492 493 /* Now the command into the FIFO */ 494 cmd = (u_char *)&ecb->cmd.cmd; 495 clen = ecb->clen; 496 while (clen--) 497 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 498 499 /* And get the targets attention */ 500 NCRCMD(sc, NCRCMD_SELATN); 501 } 502 503 void 504 ncr53c9x_free_ecb(sc, ecb, flags) 505 struct ncr53c9x_softc *sc; 506 struct ncr53c9x_ecb *ecb; 507 int flags; 508 { 509 int s; 510 511 s = splbio(); 512 513 ecb->flags = 0; 514 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain); 515 516 /* 517 * If there were none, wake anybody waiting for one to come free, 518 * starting with queued entries. 519 */ 520 if (ecb->chain.tqe_next == 0) 521 wakeup(&sc->free_list); 522 523 splx(s); 524 } 525 526 struct ncr53c9x_ecb * 527 ncr53c9x_get_ecb(sc, flags) 528 struct ncr53c9x_softc *sc; 529 int flags; 530 { 531 struct ncr53c9x_ecb *ecb; 532 int s; 533 534 s = splbio(); 535 536 while ((ecb = sc->free_list.tqh_first) == NULL && 537 (flags & SCSI_NOSLEEP) == 0) 538 tsleep(&sc->free_list, PRIBIO, "especb", 0); 539 if (ecb) { 540 TAILQ_REMOVE(&sc->free_list, ecb, chain); 541 ecb->flags |= ECB_ALLOC; 542 } 543 544 splx(s); 545 return ecb; 546 } 547 548 /* 549 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 550 */ 551 552 /* 553 * Start a SCSI-command 554 * This function is called by the higher level SCSI-driver to queue/run 555 * SCSI-commands. 556 */ 557 int 558 ncr53c9x_scsi_cmd(xs) 559 struct scsipi_xfer *xs; 560 { 561 struct scsipi_link *sc_link = xs->sc_link; 562 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 563 struct ncr53c9x_ecb *ecb; 564 int s, flags; 565 566 NCR_TRACE(("[ncr53c9x_scsi_cmd] ")); 567 NCR_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 568 sc_link->scsipi_scsi.target)); 569 570 flags = xs->flags; 571 if ((ecb = ncr53c9x_get_ecb(sc, flags)) == NULL) 572 return TRY_AGAIN_LATER; 573 574 /* Initialize ecb */ 575 ecb->xs = xs; 576 ecb->timeout = xs->timeout; 577 578 if (flags & SCSI_RESET) { 579 ecb->flags |= ECB_RESET; 580 ecb->clen = 0; 581 ecb->dleft = 0; 582 } else { 583 bcopy(xs->cmd, &ecb->cmd.cmd, xs->cmdlen); 584 ecb->clen = xs->cmdlen; 585 ecb->daddr = xs->data; 586 ecb->dleft = xs->datalen; 587 } 588 ecb->stat = 0; 589 590 s = splbio(); 591 592 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 593 if (sc->sc_state == NCR_IDLE) 594 ncr53c9x_sched(sc); 595 596 splx(s); 597 598 if ((flags & SCSI_POLL) == 0) 599 return SUCCESSFULLY_QUEUED; 600 601 /* Not allowed to use interrupts, use polling instead */ 602 if (ncr53c9x_poll(sc, xs, ecb->timeout)) { 603 ncr53c9x_timeout(ecb); 604 if (ncr53c9x_poll(sc, xs, ecb->timeout)) 605 ncr53c9x_timeout(ecb); 606 } 607 return COMPLETE; 608 } 609 610 /* 611 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 612 */ 613 int 614 ncr53c9x_poll(sc, xs, count) 615 struct ncr53c9x_softc *sc; 616 struct scsipi_xfer *xs; 617 int count; 618 { 619 620 NCR_TRACE(("[ncr53c9x_poll] ")); 621 while (count) { 622 if (NCRDMA_ISINTR(sc)) { 623 ncr53c9x_intr(sc); 624 } 625 #if alternatively 626 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) 627 ncr53c9x_intr(sc); 628 #endif 629 if ((xs->flags & ITSDONE) != 0) 630 return 0; 631 if (sc->sc_state == NCR_IDLE) { 632 NCR_TRACE(("[ncr53c9x_poll: rescheduling] ")); 633 ncr53c9x_sched(sc); 634 } 635 DELAY(1000); 636 count--; 637 } 638 return 1; 639 } 640 641 642 /* 643 * LOW LEVEL SCSI UTILITIES 644 */ 645 646 /* 647 * Schedule a scsi operation. This has now been pulled out of the interrupt 648 * handler so that we may call it from ncr53c9x_scsi_cmd and ncr53c9x_done. 649 * This may save us an unecessary interrupt just to get things going. 650 * Should only be called when state == NCR_IDLE and at bio pl. 651 */ 652 void 653 ncr53c9x_sched(sc) 654 struct ncr53c9x_softc *sc; 655 { 656 struct ncr53c9x_ecb *ecb; 657 struct scsipi_link *sc_link; 658 struct ncr53c9x_tinfo *ti; 659 660 NCR_TRACE(("[ncr53c9x_sched] ")); 661 if (sc->sc_state != NCR_IDLE) 662 panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state); 663 664 /* 665 * Find first ecb in ready queue that is for a target/lunit 666 * combinations that is not busy. 667 */ 668 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 669 sc_link = ecb->xs->sc_link; 670 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 671 if ((ti->lubusy & (1 << sc_link->scsipi_scsi.lun)) == 0) { 672 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 673 sc->sc_nexus = ecb; 674 ncr53c9x_select(sc, ecb); 675 break; 676 } else 677 NCR_MISC(("%d:%d busy\n", 678 sc_link->scsipi_scsi.target, sc_link->scsipi_scsi.lun)); 679 } 680 } 681 682 void 683 ncr53c9x_sense(sc, ecb) 684 struct ncr53c9x_softc *sc; 685 struct ncr53c9x_ecb *ecb; 686 { 687 struct scsipi_xfer *xs = ecb->xs; 688 struct scsipi_link *sc_link = xs->sc_link; 689 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 690 struct scsipi_sense *ss = (void *)&ecb->cmd.cmd; 691 692 NCR_MISC(("requesting sense ")); 693 /* Next, setup a request sense command block */ 694 bzero(ss, sizeof(*ss)); 695 ss->opcode = REQUEST_SENSE; 696 ss->byte2 = sc_link->scsipi_scsi.lun << 5; 697 ss->length = sizeof(struct scsipi_sense_data); 698 ecb->clen = sizeof(*ss); 699 ecb->daddr = (char *)&xs->sense.scsi_sense; 700 ecb->dleft = sizeof(struct scsipi_sense_data); 701 ecb->flags |= ECB_SENSE; 702 ecb->timeout = NCR_SENSE_TIMEOUT; 703 ti->senses++; 704 if (ecb->flags & ECB_NEXUS) 705 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 706 if (ecb == sc->sc_nexus) { 707 ncr53c9x_select(sc, ecb); 708 } else { 709 ncr53c9x_dequeue(sc, ecb); 710 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 711 if (sc->sc_state == NCR_IDLE) 712 ncr53c9x_sched(sc); 713 } 714 } 715 716 /* 717 * POST PROCESSING OF SCSI_CMD (usually current) 718 */ 719 void 720 ncr53c9x_done(sc, ecb) 721 struct ncr53c9x_softc *sc; 722 struct ncr53c9x_ecb *ecb; 723 { 724 struct scsipi_xfer *xs = ecb->xs; 725 struct scsipi_link *sc_link = xs->sc_link; 726 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 727 728 NCR_TRACE(("[ncr53c9x_done(error:%x)] ", xs->error)); 729 730 untimeout(ncr53c9x_timeout, ecb); 731 732 /* 733 * Now, if we've come here with no error code, i.e. we've kept the 734 * initial XS_NOERROR, and the status code signals that we should 735 * check sense, we'll need to set up a request sense cmd block and 736 * push the command back into the ready queue *before* any other 737 * commands for this target/lunit, else we lose the sense info. 738 * We don't support chk sense conditions for the request sense cmd. 739 */ 740 if (xs->error == XS_NOERROR) { 741 xs->status = ecb->stat; 742 if ((ecb->flags & ECB_ABORT) != 0) { 743 xs->error = XS_TIMEOUT; 744 } else if ((ecb->flags & ECB_SENSE) != 0) { 745 xs->error = XS_SENSE; 746 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) { 747 /* First, save the return values */ 748 xs->resid = ecb->dleft; 749 ncr53c9x_sense(sc, ecb); 750 return; 751 } else { 752 xs->resid = ecb->dleft; 753 } 754 } 755 756 xs->flags |= ITSDONE; 757 758 #ifdef NCR53C9X_DEBUG 759 if (ncr53c9x_debug & NCR_SHOWMISC) { 760 if (xs->resid != 0) 761 printf("resid=%d ", xs->resid); 762 if (xs->error == XS_SENSE) 763 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 764 else 765 printf("error=%d\n", xs->error); 766 } 767 #endif 768 769 /* 770 * Remove the ECB from whatever queue it's on. 771 */ 772 if (ecb->flags & ECB_NEXUS) 773 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 774 if (ecb == sc->sc_nexus) { 775 sc->sc_nexus = NULL; 776 if (sc->sc_state != NCR_CLEANING) { 777 sc->sc_state = NCR_IDLE; 778 ncr53c9x_sched(sc); 779 } 780 } else 781 ncr53c9x_dequeue(sc, ecb); 782 783 ncr53c9x_free_ecb(sc, ecb, xs->flags); 784 ti->cmds++; 785 scsipi_done(xs); 786 } 787 788 void 789 ncr53c9x_dequeue(sc, ecb) 790 struct ncr53c9x_softc *sc; 791 struct ncr53c9x_ecb *ecb; 792 { 793 794 if (ecb->flags & ECB_NEXUS) { 795 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 796 } else { 797 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 798 } 799 } 800 801 /* 802 * INTERRUPT/PROTOCOL ENGINE 803 */ 804 805 /* 806 * Schedule an outgoing message by prioritizing it, and asserting 807 * attention on the bus. We can only do this when we are the initiator 808 * else there will be an illegal command interrupt. 809 */ 810 #define ncr53c9x_sched_msgout(m) \ 811 do { \ 812 NCR_MISC(("ncr53c9x_sched_msgout %d ", m)); \ 813 NCRCMD(sc, NCRCMD_SETATN); \ 814 sc->sc_flags |= NCR_ATN; \ 815 sc->sc_msgpriq |= (m); \ 816 } while (0) 817 818 int 819 ncr53c9x_reselect(sc, message) 820 struct ncr53c9x_softc *sc; 821 int message; 822 { 823 u_char selid, target, lun; 824 struct ncr53c9x_ecb *ecb; 825 struct scsipi_link *sc_link; 826 struct ncr53c9x_tinfo *ti; 827 828 /* 829 * The SCSI chip made a snapshot of the data bus while the reselection 830 * was being negotiated. This enables us to determine which target did 831 * the reselect. 832 */ 833 selid = sc->sc_selid & ~(1 << sc->sc_id); 834 if (selid & (selid - 1)) { 835 printf("%s: reselect with invalid selid %02x;" 836 " sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 837 goto reset; 838 } 839 840 /* 841 * Search wait queue for disconnected cmd 842 * The list should be short, so I haven't bothered with 843 * any more sophisticated structures than a simple 844 * singly linked list. 845 */ 846 target = ffs(selid) - 1; 847 lun = message & 0x07; 848 for (ecb = sc->nexus_list.tqh_first; ecb != NULL; 849 ecb = ecb->chain.tqe_next) { 850 sc_link = ecb->xs->sc_link; 851 if (sc_link->scsipi_scsi.target == target && sc_link->scsipi_scsi.lun == lun) 852 break; 853 } 854 if (ecb == NULL) { 855 printf("%s: reselect from target %d lun %d with no nexus;" 856 " sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 857 goto abort; 858 } 859 860 /* Make this nexus active again. */ 861 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 862 sc->sc_state = NCR_CONNECTED; 863 sc->sc_nexus = ecb; 864 ti = &sc->sc_tinfo[target]; 865 ti->lubusy |= (1 << lun); 866 ncr53c9x_setsync(sc, ti); 867 868 if (ecb->flags & ECB_RESET) 869 ncr53c9x_sched_msgout(SEND_DEV_RESET); 870 else if (ecb->flags & ECB_ABORT) 871 ncr53c9x_sched_msgout(SEND_ABORT); 872 873 /* Do an implicit RESTORE POINTERS. */ 874 sc->sc_dp = ecb->daddr; 875 sc->sc_dleft = ecb->dleft; 876 877 return (0); 878 879 reset: 880 ncr53c9x_sched_msgout(SEND_DEV_RESET); 881 return (1); 882 883 abort: 884 ncr53c9x_sched_msgout(SEND_ABORT); 885 return (1); 886 } 887 888 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80) 889 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 890 #define ISEXTMSG(m) ((m) == 1) 891 892 /* 893 * Get an incoming message as initiator. 894 * 895 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 896 * byte in the FIFO 897 */ 898 void 899 ncr53c9x_msgin(sc) 900 register struct ncr53c9x_softc *sc; 901 { 902 register int v; 903 904 NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen)); 905 906 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) == 0) { 907 printf("%s: msgin: no msg byte available\n", 908 sc->sc_dev.dv_xname); 909 return; 910 } 911 912 /* 913 * Prepare for a new message. A message should (according 914 * to the SCSI standard) be transmitted in one single 915 * MESSAGE_IN_PHASE. If we have been in some other phase, 916 * then this is a new message. 917 */ 918 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 919 sc->sc_flags &= ~NCR_DROP_MSGI; 920 sc->sc_imlen = 0; 921 } 922 923 v = NCR_READ_REG(sc, NCR_FIFO); 924 NCR_MISC(("<msgbyte:0x%02x>", v)); 925 926 #if 0 927 if (sc->sc_state == NCR_RESELECTED && sc->sc_imlen == 0) { 928 /* 929 * Which target is reselecting us? (The ID bit really) 930 */ 931 sc->sc_selid = v; 932 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 933 return; 934 } 935 #endif 936 937 sc->sc_imess[sc->sc_imlen] = v; 938 939 /* 940 * If we're going to reject the message, don't bother storing 941 * the incoming bytes. But still, we need to ACK them. 942 */ 943 944 if ((sc->sc_flags & NCR_DROP_MSGI)) { 945 NCRCMD(sc, NCRCMD_MSGOK); 946 printf("<dropping msg byte %x>", 947 sc->sc_imess[sc->sc_imlen]); 948 return; 949 } 950 951 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) { 952 ncr53c9x_sched_msgout(SEND_REJECT); 953 sc->sc_flags |= NCR_DROP_MSGI; 954 } else { 955 sc->sc_imlen++; 956 /* 957 * This testing is suboptimal, but most 958 * messages will be of the one byte variety, so 959 * it should not effect performance 960 * significantly. 961 */ 962 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 963 goto gotit; 964 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 965 goto gotit; 966 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 967 sc->sc_imlen == sc->sc_imess[1] + 2) 968 goto gotit; 969 } 970 /* Ack what we have so far */ 971 NCRCMD(sc, NCRCMD_MSGOK); 972 return; 973 974 gotit: 975 NCR_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 976 /* 977 * Now we should have a complete message (1 byte, 2 byte 978 * and moderately long extended messages). We only handle 979 * extended messages which total length is shorter than 980 * NCR_MAX_MSG_LEN. Longer messages will be amputated. 981 */ 982 switch (sc->sc_state) { 983 struct ncr53c9x_ecb *ecb; 984 struct ncr53c9x_tinfo *ti; 985 986 case NCR_CONNECTED: 987 ecb = sc->sc_nexus; 988 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 989 990 switch (sc->sc_imess[0]) { 991 case MSG_CMDCOMPLETE: 992 NCR_MSGS(("cmdcomplete ")); 993 if (sc->sc_dleft < 0) { 994 struct scsipi_link *sc_link = ecb->xs->sc_link; 995 printf("%s: %ld extra bytes from %d:%d\n", 996 sc->sc_dev.dv_xname, -(long)sc->sc_dleft, 997 sc_link->scsipi_scsi.target, sc_link->scsipi_scsi.lun); 998 sc->sc_dleft = 0; 999 } 1000 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) 1001 ? 0 1002 : sc->sc_dleft; 1003 if ((ecb->flags & ECB_SENSE) == 0) 1004 ecb->xs->resid = ecb->dleft; 1005 sc->sc_state = NCR_CMDCOMPLETE; 1006 break; 1007 1008 case MSG_MESSAGE_REJECT: 1009 if (ncr53c9x_debug & NCR_SHOWMSGS) 1010 printf("%s: our msg rejected by target\n", 1011 sc->sc_dev.dv_xname); 1012 switch (sc->sc_msgout) { 1013 case SEND_SDTR: 1014 sc->sc_flags &= ~NCR_SYNCHNEGO; 1015 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1016 ncr53c9x_setsync(sc, ti); 1017 break; 1018 case SEND_INIT_DET_ERR: 1019 goto abort; 1020 } 1021 break; 1022 1023 case MSG_NOOP: 1024 NCR_MSGS(("noop ")); 1025 break; 1026 1027 case MSG_DISCONNECT: 1028 NCR_MSGS(("disconnect ")); 1029 ti->dconns++; 1030 sc->sc_state = NCR_DISCONNECT; 1031 1032 /* 1033 * Mark the fact that all bytes have moved. The 1034 * target may not bother to do a SAVE POINTERS 1035 * at this stage. This flag will set the residual 1036 * count to zero on MSG COMPLETE. 1037 */ 1038 if (sc->sc_dleft == 0) 1039 ecb->flags |= ECB_TENTATIVE_DONE; 1040 1041 break; 1042 1043 case MSG_SAVEDATAPOINTER: 1044 NCR_MSGS(("save datapointer ")); 1045 ecb->daddr = sc->sc_dp; 1046 ecb->dleft = sc->sc_dleft; 1047 break; 1048 1049 case MSG_RESTOREPOINTERS: 1050 NCR_MSGS(("restore datapointer ")); 1051 sc->sc_dp = ecb->daddr; 1052 sc->sc_dleft = ecb->dleft; 1053 break; 1054 1055 case MSG_EXTENDED: 1056 NCR_MSGS(("extended(%x) ", sc->sc_imess[2])); 1057 switch (sc->sc_imess[2]) { 1058 case MSG_EXT_SDTR: 1059 NCR_MSGS(("SDTR period %d, offset %d ", 1060 sc->sc_imess[3], sc->sc_imess[4])); 1061 if (sc->sc_imess[1] != 3) 1062 goto reject; 1063 ti->period = sc->sc_imess[3]; 1064 ti->offset = sc->sc_imess[4]; 1065 ti->flags &= ~T_NEGOTIATE; 1066 if (sc->sc_minsync == 0 || 1067 ti->offset == 0 || 1068 ti->period > 124) { 1069 printf("%s:%d: async\n", "esp", 1070 ecb->xs->sc_link->scsipi_scsi.target); 1071 if ((sc->sc_flags&NCR_SYNCHNEGO) 1072 == 0) { 1073 /* 1074 * target initiated negotiation 1075 */ 1076 ti->offset = 0; 1077 ti->flags &= ~T_SYNCMODE; 1078 ncr53c9x_sched_msgout( 1079 SEND_SDTR); 1080 } else { 1081 /* we are async */ 1082 ti->flags &= ~T_SYNCMODE; 1083 } 1084 } else { 1085 int r = 250/ti->period; 1086 int s = (100*250)/ti->period - 100*r; 1087 int p; 1088 1089 p = ncr53c9x_stp2cpb(sc, ti->period); 1090 ti->period = ncr53c9x_cpb2stp(sc, p); 1091 #ifdef NCR53C9X_DEBUG 1092 scsi_print_addr(ecb->xs->sc_link); 1093 printf("max sync rate %d.%02dMb/s\n", 1094 r, s); 1095 #endif 1096 if ((sc->sc_flags&NCR_SYNCHNEGO) 1097 == 0) { 1098 /* 1099 * target initiated negotiation 1100 */ 1101 if (ti->period < 1102 sc->sc_minsync) 1103 ti->period = 1104 sc->sc_minsync; 1105 if (ti->offset > 15) 1106 ti->offset = 15; 1107 ti->flags &= ~T_SYNCMODE; 1108 ncr53c9x_sched_msgout( 1109 SEND_SDTR); 1110 } else { 1111 /* we are sync */ 1112 ti->flags |= T_SYNCMODE; 1113 } 1114 } 1115 sc->sc_flags &= ~NCR_SYNCHNEGO; 1116 ncr53c9x_setsync(sc, ti); 1117 break; 1118 1119 default: 1120 printf("%s: unrecognized MESSAGE EXTENDED;" 1121 " sending REJECT\n", sc->sc_dev.dv_xname); 1122 goto reject; 1123 } 1124 break; 1125 1126 default: 1127 NCR_MSGS(("ident ")); 1128 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1129 sc->sc_dev.dv_xname); 1130 reject: 1131 ncr53c9x_sched_msgout(SEND_REJECT); 1132 break; 1133 } 1134 break; 1135 1136 case NCR_RESELECTED: 1137 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1138 printf("%s: reselect without IDENTIFY;" 1139 " sending DEVICE RESET\n", sc->sc_dev.dv_xname); 1140 goto reset; 1141 } 1142 1143 (void) ncr53c9x_reselect(sc, sc->sc_imess[0]); 1144 break; 1145 1146 default: 1147 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1148 sc->sc_dev.dv_xname); 1149 reset: 1150 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1151 break; 1152 1153 abort: 1154 ncr53c9x_sched_msgout(SEND_ABORT); 1155 break; 1156 } 1157 1158 /* Ack last message byte */ 1159 NCRCMD(sc, NCRCMD_MSGOK); 1160 1161 /* Done, reset message pointer. */ 1162 sc->sc_flags &= ~NCR_DROP_MSGI; 1163 sc->sc_imlen = 0; 1164 } 1165 1166 1167 /* 1168 * Send the highest priority, scheduled message 1169 */ 1170 void 1171 ncr53c9x_msgout(sc) 1172 register struct ncr53c9x_softc *sc; 1173 { 1174 struct ncr53c9x_tinfo *ti; 1175 struct ncr53c9x_ecb *ecb; 1176 size_t size; 1177 1178 NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]", 1179 sc->sc_msgpriq, sc->sc_prevphase)); 1180 1181 if (sc->sc_flags & NCR_ATN) { 1182 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1183 new: 1184 NCRCMD(sc, NCRCMD_FLUSH); 1185 DELAY(1); 1186 sc->sc_msgoutq = 0; 1187 sc->sc_omlen = 0; 1188 } 1189 } else { 1190 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1191 ncr53c9x_sched_msgout(sc->sc_msgoutq); 1192 goto new; 1193 } else { 1194 printf("%s at line %d: unexpected MESSAGE OUT phase\n", 1195 sc->sc_dev.dv_xname, __LINE__); 1196 } 1197 } 1198 1199 if (sc->sc_omlen == 0) { 1200 /* Pick up highest priority message */ 1201 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1202 sc->sc_msgoutq |= sc->sc_msgout; 1203 sc->sc_msgpriq &= ~sc->sc_msgout; 1204 sc->sc_omlen = 1; /* "Default" message len */ 1205 switch (sc->sc_msgout) { 1206 case SEND_SDTR: 1207 ecb = sc->sc_nexus; 1208 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1209 sc->sc_omess[0] = MSG_EXTENDED; 1210 sc->sc_omess[1] = 3; 1211 sc->sc_omess[2] = MSG_EXT_SDTR; 1212 sc->sc_omess[3] = ti->period; 1213 sc->sc_omess[4] = ti->offset; 1214 sc->sc_omlen = 5; 1215 if ((sc->sc_flags & NCR_SYNCHNEGO) == 0) { 1216 ti->flags |= T_SYNCMODE; 1217 ncr53c9x_setsync(sc, ti); 1218 } 1219 break; 1220 case SEND_IDENTIFY: 1221 if (sc->sc_state != NCR_CONNECTED) { 1222 printf("%s at line %d: no nexus\n", 1223 sc->sc_dev.dv_xname, __LINE__); 1224 } 1225 ecb = sc->sc_nexus; 1226 sc->sc_omess[0] = 1227 MSG_IDENTIFY(ecb->xs->sc_link->scsipi_scsi.lun, 0); 1228 break; 1229 case SEND_DEV_RESET: 1230 sc->sc_flags |= NCR_ABORTING; 1231 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1232 ecb = sc->sc_nexus; 1233 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1234 ti->flags &= ~T_SYNCMODE; 1235 ti->flags |= T_NEGOTIATE; 1236 break; 1237 case SEND_PARITY_ERROR: 1238 sc->sc_omess[0] = MSG_PARITY_ERROR; 1239 break; 1240 case SEND_ABORT: 1241 sc->sc_flags |= NCR_ABORTING; 1242 sc->sc_omess[0] = MSG_ABORT; 1243 break; 1244 case SEND_INIT_DET_ERR: 1245 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1246 break; 1247 case SEND_REJECT: 1248 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1249 break; 1250 default: 1251 NCRCMD(sc, NCRCMD_RSTATN); 1252 sc->sc_flags &= ~NCR_ATN; 1253 sc->sc_omess[0] = MSG_NOOP; 1254 break; 1255 } 1256 sc->sc_omp = sc->sc_omess; 1257 } 1258 1259 #if 1 1260 /* (re)send the message */ 1261 size = min(sc->sc_omlen, sc->sc_maxxfer); 1262 NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size); 1263 /* Program the SCSI counter */ 1264 NCR_WRITE_REG(sc, NCR_TCL, size); 1265 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1266 if (sc->sc_cfg2 & NCRCFG2_FE) { 1267 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1268 } 1269 /* load the count in */ 1270 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 1271 NCRCMD(sc, NCRCMD_TRANS|NCRCMD_DMA); 1272 NCRDMA_GO(sc); 1273 #else 1274 { int i; 1275 for (i = 0; i < sc->sc_omlen; i++) 1276 NCR_WRITE_REG(sc, FIFO, sc->sc_omess[i]); 1277 NCRCMD(sc, NCRCMD_TRANS); 1278 sc->sc_omlen = 0; 1279 } 1280 #endif 1281 } 1282 1283 /* 1284 * This is the most critical part of the driver, and has to know 1285 * how to deal with *all* error conditions and phases from the SCSI 1286 * bus. If there are no errors and the DMA was active, then call the 1287 * DMA pseudo-interrupt handler. If this returns 1, then that was it 1288 * and we can return from here without further processing. 1289 * 1290 * Most of this needs verifying. 1291 */ 1292 int 1293 ncr53c9x_intr(sc) 1294 register struct ncr53c9x_softc *sc; 1295 { 1296 register struct ncr53c9x_ecb *ecb; 1297 register struct scsipi_link *sc_link; 1298 struct ncr53c9x_tinfo *ti; 1299 int loop; 1300 size_t size; 1301 int nfifo; 1302 1303 NCR_TRACE(("[ncr53c9x_intr] ")); 1304 1305 /* 1306 * I have made some (maybe seriously flawed) assumptions here, 1307 * but basic testing (uncomment the printf() below), show that 1308 * certainly something happens when this loop is here. 1309 * 1310 * The idea is that many of the SCSI operations take very little 1311 * time, and going away and getting interrupted is too high an 1312 * overhead to pay. For example, selecting, sending a message 1313 * and command and then doing some work can be done in one "pass". 1314 * 1315 * The DELAY is not variable because I do not understand that the 1316 * DELAY loop should be fixed-time regardless of CPU speed, but 1317 * I am *assuming* that the faster SCSI processors get things done 1318 * quicker (sending a command byte etc), and so there is no 1319 * need to be too slow. 1320 * 1321 * This is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1 1322 * at 40Mhz. This needs testing. 1323 */ 1324 for (loop = 0; 1;loop++, DELAY(50/sc->sc_freq)) { 1325 /* a feeling of deja-vu */ 1326 if (!NCRDMA_ISINTR(sc)) 1327 return (loop != 0); 1328 #if 0 1329 if (loop) 1330 printf("*"); 1331 #endif 1332 1333 /* and what do the registers say... */ 1334 ncr53c9x_readregs(sc); 1335 1336 sc->sc_intrcnt.ev_count++; 1337 1338 /* 1339 * At the moment, only a SCSI Bus Reset or Illegal 1340 * Command are classed as errors. A disconnect is a 1341 * valid condition, and we let the code check is the 1342 * "NCR_BUSFREE_OK" flag was set before declaring it 1343 * and error. 1344 * 1345 * Also, the status register tells us about "Gross 1346 * Errors" and "Parity errors". Only the Gross Error 1347 * is really bad, and the parity errors are dealt 1348 * with later 1349 * 1350 * TODO 1351 * If there are too many parity error, go to slow 1352 * cable mode ? 1353 */ 1354 1355 /* SCSI Reset */ 1356 if (sc->sc_espintr & NCRINTR_SBR) { 1357 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1358 NCRCMD(sc, NCRCMD_FLUSH); 1359 DELAY(1); 1360 } 1361 if (sc->sc_state != NCR_SBR) { 1362 printf("%s: SCSI bus reset\n", 1363 sc->sc_dev.dv_xname); 1364 ncr53c9x_init(sc, 0); /* Restart everything */ 1365 return 1; 1366 } 1367 #if 0 1368 /*XXX*/ printf("<expected bus reset: " 1369 "[intr %x, stat %x, step %d]>\n", 1370 sc->sc_espintr, sc->sc_espstat, 1371 sc->sc_espstep); 1372 #endif 1373 if (sc->sc_nexus) 1374 panic("%s: nexus in reset state", 1375 sc->sc_dev.dv_xname); 1376 goto sched; 1377 } 1378 1379 ecb = sc->sc_nexus; 1380 1381 #define NCRINTR_ERR (NCRINTR_SBR|NCRINTR_ILL) 1382 if (sc->sc_espintr & NCRINTR_ERR || 1383 sc->sc_espstat & NCRSTAT_GE) { 1384 1385 if (sc->sc_espstat & NCRSTAT_GE) { 1386 /* no target ? */ 1387 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1388 NCRCMD(sc, NCRCMD_FLUSH); 1389 DELAY(1); 1390 } 1391 if (sc->sc_state == NCR_CONNECTED || 1392 sc->sc_state == NCR_SELECTING) { 1393 ecb->xs->error = XS_TIMEOUT; 1394 ncr53c9x_done(sc, ecb); 1395 } 1396 return 1; 1397 } 1398 1399 if (sc->sc_espintr & NCRINTR_ILL) { 1400 if (sc->sc_flags & NCR_EXPECT_ILLCMD) { 1401 /* 1402 * Eat away "Illegal command" interrupt 1403 * on a ESP100 caused by a re-selection 1404 * while we were trying to select 1405 * another target. 1406 */ 1407 #ifdef DEBUG 1408 printf("%s: ESP100 work-around activated\n", 1409 sc->sc_dev.dv_xname); 1410 #endif 1411 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 1412 continue; 1413 } 1414 /* illegal command, out of sync ? */ 1415 printf("%s: illegal command: 0x%x " 1416 "(state %d, phase %x, prevphase %x)\n", 1417 sc->sc_dev.dv_xname, sc->sc_lastcmd, 1418 sc->sc_state, sc->sc_phase, 1419 sc->sc_prevphase); 1420 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1421 NCRCMD(sc, NCRCMD_FLUSH); 1422 DELAY(1); 1423 } 1424 ncr53c9x_init(sc, 1); /* Restart everything */ 1425 return 1; 1426 } 1427 } 1428 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 1429 1430 /* 1431 * Call if DMA is active. 1432 * 1433 * If DMA_INTR returns true, then maybe go 'round the loop 1434 * again in case there is no more DMA queued, but a phase 1435 * change is expected. 1436 */ 1437 if (NCRDMA_ISACTIVE(sc)) { 1438 int r = NCRDMA_INTR(sc); 1439 if (r == -1) { 1440 printf("%s: DMA error; resetting\n", 1441 sc->sc_dev.dv_xname); 1442 ncr53c9x_init(sc, 1); 1443 } 1444 /* If DMA active here, then go back to work... */ 1445 if (NCRDMA_ISACTIVE(sc)) 1446 return 1; 1447 1448 /* 1449 * Note that this can happen during normal operation 1450 * if we are reselected while using DMA to select 1451 * a target. If this is the case, don't issue the 1452 * warning. 1453 */ 1454 if (sc->sc_dleft == 0 && 1455 (sc->sc_espstat & NCRSTAT_TC) == 0 && 1456 sc->sc_state != NCR_SELECTING) 1457 printf("%s: !TC [intr %x, stat %x, step %d]" 1458 " prevphase %x, resid %x\n", 1459 sc->sc_dev.dv_xname, 1460 sc->sc_espintr, 1461 sc->sc_espstat, 1462 sc->sc_espstep, 1463 sc->sc_prevphase, 1464 ecb?ecb->dleft:-1); 1465 } 1466 1467 #if 0 /* Unreliable on some NCR revisions? */ 1468 if ((sc->sc_espstat & NCRSTAT_INT) == 0) { 1469 printf("%s: spurious interrupt\n", 1470 sc->sc_dev.dv_xname); 1471 return 1; 1472 } 1473 #endif 1474 1475 /* 1476 * check for less serious errors 1477 */ 1478 if (sc->sc_espstat & NCRSTAT_PE) { 1479 printf("%s: SCSI bus parity error\n", 1480 sc->sc_dev.dv_xname); 1481 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 1482 ncr53c9x_sched_msgout(SEND_PARITY_ERROR); 1483 else 1484 ncr53c9x_sched_msgout(SEND_INIT_DET_ERR); 1485 } 1486 1487 if (sc->sc_espintr & NCRINTR_DIS) { 1488 NCR_MISC(("<DISC [intr %x, stat %x, step %d]>", 1489 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 1490 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1491 NCRCMD(sc, NCRCMD_FLUSH); 1492 DELAY(1); 1493 } 1494 /* 1495 * This command must (apparently) be issued within 1496 * 250mS of a disconnect. So here you are... 1497 */ 1498 NCRCMD(sc, NCRCMD_ENSEL); 1499 switch (sc->sc_state) { 1500 case NCR_RESELECTED: 1501 goto sched; 1502 1503 case NCR_SELECTING: 1504 ecb->xs->error = XS_SELTIMEOUT; 1505 goto finish; 1506 1507 case NCR_CONNECTED: 1508 if ((sc->sc_flags & NCR_SYNCHNEGO)) { 1509 #ifdef NCR53C9X_DEBUG 1510 if (ecb) 1511 scsi_print_addr(ecb->xs->sc_link); 1512 printf("sync nego not completed!\n"); 1513 #endif 1514 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1515 sc->sc_flags &= ~NCR_SYNCHNEGO; 1516 ti->flags &= 1517 ~(T_NEGOTIATE | T_SYNCMODE); 1518 } 1519 1520 /* it may be OK to disconnect */ 1521 if ((sc->sc_flags & NCR_ABORTING) == 0) { 1522 /* 1523 * Section 5.1.1 of the SCSI 2 spec 1524 * suggests issuing a REQUEST SENSE 1525 * following an unexpected disconnect. 1526 * Some devices go into a contingent 1527 * allegiance condition when 1528 * disconnecting, and this is necessary 1529 * to clean up their state. 1530 */ 1531 printf("%s: unexpected disconnect; ", 1532 sc->sc_dev.dv_xname); 1533 if (ecb->flags & ECB_SENSE) { 1534 printf("resetting\n"); 1535 goto reset; 1536 } 1537 printf("sending REQUEST SENSE\n"); 1538 untimeout(ncr53c9x_timeout, ecb); 1539 ncr53c9x_sense(sc, ecb); 1540 goto out; 1541 } 1542 1543 ecb->xs->error = XS_TIMEOUT; 1544 goto finish; 1545 1546 case NCR_DISCONNECT: 1547 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain); 1548 sc->sc_nexus = NULL; 1549 goto sched; 1550 1551 case NCR_CMDCOMPLETE: 1552 goto finish; 1553 } 1554 } 1555 1556 switch (sc->sc_state) { 1557 1558 case NCR_SBR: 1559 printf("%s: waiting for SCSI Bus Reset to happen\n", 1560 sc->sc_dev.dv_xname); 1561 return 1; 1562 1563 case NCR_RESELECTED: 1564 /* 1565 * we must be continuing a message ? 1566 */ 1567 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1568 printf("%s: target didn't identify\n", 1569 sc->sc_dev.dv_xname); 1570 ncr53c9x_init(sc, 1); 1571 return 1; 1572 } 1573 printf("<<RESELECT CONT'd>>"); 1574 #if XXXX 1575 ncr53c9x_msgin(sc); 1576 if (sc->sc_state != NCR_CONNECTED) { 1577 /* IDENTIFY fail?! */ 1578 printf("%s: identify failed\n", 1579 sc->sc_dev.dv_xname); 1580 ncr53c9x_init(sc, 1); 1581 return 1; 1582 } 1583 #endif 1584 break; 1585 1586 case NCR_IDLE: 1587 if (sc->sc_flags & NCR_ICCS) printf("[[esp: BUMMER]]"); 1588 case NCR_SELECTING: 1589 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1590 sc->sc_flags = 0; 1591 ecb = sc->sc_nexus; 1592 1593 if (sc->sc_espintr & NCRINTR_RESEL) { 1594 /* 1595 * If we're trying to select a 1596 * target ourselves, push our command 1597 * back into the ready list. 1598 */ 1599 if (sc->sc_state == NCR_SELECTING) { 1600 NCR_MISC(("backoff selector ")); 1601 untimeout(ncr53c9x_timeout, ecb); 1602 sc_link = ecb->xs->sc_link; 1603 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1604 TAILQ_INSERT_HEAD(&sc->ready_list, 1605 ecb, chain); 1606 ecb = sc->sc_nexus = NULL; 1607 } 1608 sc->sc_state = NCR_RESELECTED; 1609 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1610 /* 1611 * Things are seriously fucked up. 1612 * Pull the brakes, i.e. reset 1613 */ 1614 printf("%s: target didn't identify\n", 1615 sc->sc_dev.dv_xname); 1616 ncr53c9x_init(sc, 1); 1617 return 1; 1618 } 1619 /* 1620 * The C90 only inhibits FIFO writes until 1621 * reselection is complete, instead of 1622 * waiting until the interrupt status register 1623 * has been read. So, if the reselect happens 1624 * while we were entering a command bytes (for 1625 * another target) some of those bytes can 1626 * appear in the FIFO here, after the 1627 * interrupt is taken. 1628 */ 1629 nfifo = NCR_READ_REG(sc,NCR_FFLAG) & NCRFIFO_FF; 1630 if (nfifo < 2 || 1631 (nfifo > 2 && 1632 sc->sc_rev != NCR_VARIANT_ESP100)) { 1633 printf("%s: RESELECT: " 1634 "%d bytes in FIFO! " 1635 "[intr %x, stat %x, step %d, prevphase %x]\n", 1636 sc->sc_dev.dv_xname, 1637 nfifo, 1638 sc->sc_espintr, 1639 sc->sc_espstat, 1640 sc->sc_espstep, 1641 sc->sc_prevphase); 1642 ncr53c9x_init(sc, 1); 1643 return 1; 1644 } 1645 sc->sc_selid = NCR_READ_REG(sc, NCR_FIFO); 1646 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 1647 1648 /* Handle identify message */ 1649 ncr53c9x_msgin(sc); 1650 if (nfifo != 2) { 1651 /* 1652 * Note: this should not happen 1653 * with `dmaselect' on. 1654 */ 1655 sc->sc_flags |= NCR_EXPECT_ILLCMD; 1656 NCRCMD(sc, NCRCMD_FLUSH); 1657 } else if (ncr53c9x_dmaselect && 1658 sc->sc_rev == NCR_VARIANT_ESP100) { 1659 sc->sc_flags |= NCR_EXPECT_ILLCMD; 1660 } 1661 1662 if (sc->sc_state != NCR_CONNECTED) { 1663 /* IDENTIFY fail?! */ 1664 printf("%s: identify failed\n", 1665 sc->sc_dev.dv_xname); 1666 ncr53c9x_init(sc, 1); 1667 return 1; 1668 } 1669 continue; /* ie. next phase expected soon */ 1670 } 1671 1672 #define NCRINTR_DONE (NCRINTR_FC|NCRINTR_BS) 1673 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) { 1674 ecb = sc->sc_nexus; 1675 if (!ecb) 1676 panic("esp: not nexus at sc->sc_nexus"); 1677 1678 sc_link = ecb->xs->sc_link; 1679 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1680 1681 switch (sc->sc_espstep) { 1682 case 0: 1683 /* 1684 * The target did not respond with a 1685 * message out phase - probably an old 1686 * device that doesn't recognize ATN. 1687 * Clear ATN and just continue, the 1688 * target should be in the command 1689 * phase. 1690 * XXXX check for command phase? 1691 */ 1692 NCRCMD(sc, NCRCMD_RSTATN); 1693 break; 1694 case 1: 1695 if ((ti->flags & T_NEGOTIATE) == 0) { 1696 printf("%s: step 1 & !NEG\n", 1697 sc->sc_dev.dv_xname); 1698 goto reset; 1699 } 1700 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 1701 printf("%s: !MSGOUT\n", 1702 sc->sc_dev.dv_xname); 1703 goto reset; 1704 } 1705 /* Start negotiating */ 1706 ti->period = sc->sc_minsync; 1707 ti->offset = 15; 1708 sc->sc_flags |= NCR_SYNCHNEGO; 1709 ncr53c9x_sched_msgout(SEND_SDTR); 1710 break; 1711 case 3: 1712 /* 1713 * Grr, this is supposed to mean 1714 * "target left command phase 1715 * prematurely". It seems to happen 1716 * regularly when sync mode is on. 1717 * Look at FIFO to see if command 1718 * went out. 1719 * (Timing problems?) 1720 */ 1721 if (ncr53c9x_dmaselect) { 1722 if (sc->sc_cmdlen == 0) 1723 /* Hope for the best.. */ 1724 break; 1725 } else if ((NCR_READ_REG(sc, NCR_FFLAG) 1726 & NCRFIFO_FF) == 0) { 1727 /* Hope for the best.. */ 1728 break; 1729 } 1730 printf("(%s:%d:%d): selection failed;" 1731 " %d left in FIFO " 1732 "[intr %x, stat %x, step %d]\n", 1733 sc->sc_dev.dv_xname, 1734 sc_link->scsipi_scsi.target, 1735 sc_link->scsipi_scsi.lun, 1736 NCR_READ_REG(sc, NCR_FFLAG) 1737 & NCRFIFO_FF, 1738 sc->sc_espintr, sc->sc_espstat, 1739 sc->sc_espstep); 1740 NCRCMD(sc, NCRCMD_FLUSH); 1741 ncr53c9x_sched_msgout(SEND_ABORT); 1742 return 1; 1743 case 2: 1744 /* Select stuck at Command Phase */ 1745 NCRCMD(sc, NCRCMD_FLUSH); 1746 case 4: 1747 if (ncr53c9x_dmaselect && 1748 sc->sc_cmdlen != 0) 1749 printf("(%s:%d:%d): select; " 1750 "%d left in DMA buffer\n", 1751 sc->sc_dev.dv_xname, 1752 sc_link->scsipi_scsi.target, 1753 sc_link->scsipi_scsi.lun, 1754 sc->sc_cmdlen); 1755 /* So far, everything went fine */ 1756 break; 1757 } 1758 #if 0 1759 if (ecb->xs->flags & SCSI_RESET) 1760 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1761 else if (ti->flags & T_NEGOTIATE) 1762 ncr53c9x_sched_msgout( 1763 SEND_IDENTIFY | SEND_SDTR); 1764 else 1765 ncr53c9x_sched_msgout(SEND_IDENTIFY); 1766 #endif 1767 1768 ecb->flags |= ECB_NEXUS; 1769 ti->lubusy |= (1 << sc_link->scsipi_scsi.lun); 1770 1771 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 1772 /* Do an implicit RESTORE POINTERS. */ 1773 sc->sc_dp = ecb->daddr; 1774 sc->sc_dleft = ecb->dleft; 1775 sc->sc_state = NCR_CONNECTED; 1776 break; 1777 } else { 1778 printf("%s: unexpected status after select" 1779 ": [intr %x, stat %x, step %x]\n", 1780 sc->sc_dev.dv_xname, 1781 sc->sc_espintr, sc->sc_espstat, 1782 sc->sc_espstep); 1783 NCRCMD(sc, NCRCMD_FLUSH); 1784 DELAY(1); 1785 goto reset; 1786 } 1787 if (sc->sc_state == NCR_IDLE) { 1788 printf("%s: stray interrupt\n", 1789 sc->sc_dev.dv_xname); 1790 return 0; 1791 } 1792 break; 1793 1794 case NCR_CONNECTED: 1795 if (sc->sc_flags & NCR_ICCS) { 1796 u_char msg; 1797 1798 sc->sc_flags &= ~NCR_ICCS; 1799 1800 if (!(sc->sc_espintr & NCRINTR_DONE)) { 1801 printf("%s: ICCS: " 1802 ": [intr %x, stat %x, step %x]\n", 1803 sc->sc_dev.dv_xname, 1804 sc->sc_espintr, sc->sc_espstat, 1805 sc->sc_espstep); 1806 } 1807 if ((NCR_READ_REG(sc, NCR_FFLAG) 1808 & NCRFIFO_FF) != 2) { 1809 int i = (NCR_READ_REG(sc, NCR_FFLAG) 1810 & NCRFIFO_FF) - 2; 1811 while (i--) 1812 (void) NCR_READ_REG(sc, 1813 NCR_FIFO); 1814 } 1815 ecb->stat = NCR_READ_REG(sc, NCR_FIFO); 1816 msg = NCR_READ_REG(sc, NCR_FIFO); 1817 NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 1818 if (msg == MSG_CMDCOMPLETE) { 1819 ecb->dleft = 1820 (ecb->flags & ECB_TENTATIVE_DONE) 1821 ? 0 1822 : sc->sc_dleft; 1823 if ((ecb->flags & ECB_SENSE) == 0) 1824 ecb->xs->resid = ecb->dleft; 1825 sc->sc_state = NCR_CMDCOMPLETE; 1826 } else 1827 printf("%s: STATUS_PHASE: msg %d\n", 1828 sc->sc_dev.dv_xname, msg); 1829 NCRCMD(sc, NCRCMD_MSGOK); 1830 continue; /* ie. wait for disconnect */ 1831 } 1832 break; 1833 default: 1834 panic("%s: invalid state: %d", 1835 sc->sc_dev.dv_xname, 1836 sc->sc_state); 1837 } 1838 1839 /* 1840 * Driver is now in state NCR_CONNECTED, i.e. we 1841 * have a current command working the SCSI bus. 1842 */ 1843 if (sc->sc_state != NCR_CONNECTED || ecb == NULL) { 1844 panic("esp no nexus"); 1845 } 1846 1847 switch (sc->sc_phase) { 1848 case MESSAGE_OUT_PHASE: 1849 NCR_PHASE(("MESSAGE_OUT_PHASE ")); 1850 ncr53c9x_msgout(sc); 1851 sc->sc_prevphase = MESSAGE_OUT_PHASE; 1852 break; 1853 case MESSAGE_IN_PHASE: 1854 NCR_PHASE(("MESSAGE_IN_PHASE ")); 1855 if (sc->sc_espintr & NCRINTR_BS) { 1856 NCRCMD(sc, NCRCMD_FLUSH); 1857 sc->sc_flags |= NCR_WAITI; 1858 NCRCMD(sc, NCRCMD_TRANS); 1859 } else if (sc->sc_espintr & NCRINTR_FC) { 1860 if ((sc->sc_flags & NCR_WAITI) == 0) { 1861 printf("%s: MSGIN: unexpected FC bit: " 1862 "[intr %x, stat %x, step %x]\n", 1863 sc->sc_dev.dv_xname, 1864 sc->sc_espintr, sc->sc_espstat, 1865 sc->sc_espstep); 1866 } 1867 sc->sc_flags &= ~NCR_WAITI; 1868 ncr53c9x_msgin(sc); 1869 } else { 1870 printf("%s: MSGIN: weird bits: " 1871 "[intr %x, stat %x, step %x]\n", 1872 sc->sc_dev.dv_xname, 1873 sc->sc_espintr, sc->sc_espstat, 1874 sc->sc_espstep); 1875 } 1876 sc->sc_prevphase = MESSAGE_IN_PHASE; 1877 break; 1878 case COMMAND_PHASE: 1879 /* 1880 * Send the command block. Normally we don't see this 1881 * phase because the SEL_ATN command takes care of 1882 * all this. However, we end up here if either the 1883 * target or we wanted exchange some more messages 1884 * first (e.g. to start negotiations). 1885 */ 1886 1887 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 1888 ecb->cmd.cmd.opcode, ecb->clen)); 1889 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1890 NCRCMD(sc, NCRCMD_FLUSH); 1891 DELAY(1); 1892 } 1893 if (ncr53c9x_dmaselect) { 1894 size_t size; 1895 /* setup DMA transfer for command */ 1896 size = ecb->clen; 1897 sc->sc_cmdlen = size; 1898 sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd; 1899 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 1900 0, &size); 1901 /* Program the SCSI counter */ 1902 NCR_WRITE_REG(sc, NCR_TCL, size); 1903 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1904 if (sc->sc_cfg2 & NCRCFG2_FE) { 1905 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1906 } 1907 1908 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA); 1909 NCRDMA_GO(sc); 1910 } else { 1911 u_char *cmd = (u_char *)&ecb->cmd.cmd; 1912 int i; 1913 /* Now the command into the FIFO */ 1914 for (i = 0; i < ecb->clen; i++) 1915 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 1916 NCRCMD(sc, NCRCMD_TRANS); 1917 } 1918 sc->sc_prevphase = COMMAND_PHASE; 1919 break; 1920 case DATA_OUT_PHASE: 1921 NCR_PHASE(("DATA_OUT_PHASE [%ld] ",(long)sc->sc_dleft)); 1922 NCRCMD(sc, NCRCMD_FLUSH); 1923 size = min(sc->sc_dleft, sc->sc_maxxfer); 1924 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1925 0, &size); 1926 sc->sc_prevphase = DATA_OUT_PHASE; 1927 goto setup_xfer; 1928 case DATA_IN_PHASE: 1929 NCR_PHASE(("DATA_IN_PHASE ")); 1930 if (sc->sc_rev == NCR_VARIANT_ESP100) 1931 NCRCMD(sc, NCRCMD_FLUSH); 1932 size = min(sc->sc_dleft, sc->sc_maxxfer); 1933 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1934 1, &size); 1935 sc->sc_prevphase = DATA_IN_PHASE; 1936 setup_xfer: 1937 /* Target returned to data phase: wipe "done" memory */ 1938 ecb->flags &= ~ECB_TENTATIVE_DONE; 1939 1940 /* Program the SCSI counter */ 1941 NCR_WRITE_REG(sc, NCR_TCL, size); 1942 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1943 if (sc->sc_cfg2 & NCRCFG2_FE) { 1944 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1945 } 1946 /* load the count in */ 1947 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 1948 1949 /* 1950 * Note that if `size' is 0, we've already transceived 1951 * all the bytes we want but we're still in DATA PHASE. 1952 * Apparently, the device needs padding. Also, a 1953 * transfer size of 0 means "maximum" to the chip 1954 * DMA logic. 1955 */ 1956 NCRCMD(sc, 1957 (size==0?NCRCMD_TRPAD:NCRCMD_TRANS)|NCRCMD_DMA); 1958 NCRDMA_GO(sc); 1959 return 1; 1960 case STATUS_PHASE: 1961 NCR_PHASE(("STATUS_PHASE ")); 1962 sc->sc_flags |= NCR_ICCS; 1963 NCRCMD(sc, NCRCMD_ICCS); 1964 sc->sc_prevphase = STATUS_PHASE; 1965 break; 1966 case INVALID_PHASE: 1967 break; 1968 default: 1969 printf("%s: unexpected bus phase; resetting\n", 1970 sc->sc_dev.dv_xname); 1971 goto reset; 1972 } 1973 } 1974 panic("esp: should not get here.."); 1975 1976 reset: 1977 ncr53c9x_init(sc, 1); 1978 return 1; 1979 1980 finish: 1981 ncr53c9x_done(sc, ecb); 1982 goto out; 1983 1984 sched: 1985 sc->sc_state = NCR_IDLE; 1986 ncr53c9x_sched(sc); 1987 goto out; 1988 1989 out: 1990 return 1; 1991 } 1992 1993 void 1994 ncr53c9x_abort(sc, ecb) 1995 struct ncr53c9x_softc *sc; 1996 struct ncr53c9x_ecb *ecb; 1997 { 1998 1999 /* 2 secs for the abort */ 2000 ecb->timeout = NCR_ABORT_TIMEOUT; 2001 ecb->flags |= ECB_ABORT; 2002 2003 if (ecb == sc->sc_nexus) { 2004 /* 2005 * If we're still selecting, the message will be scheduled 2006 * after selection is complete. 2007 */ 2008 if (sc->sc_state == NCR_CONNECTED) 2009 ncr53c9x_sched_msgout(SEND_ABORT); 2010 2011 /* 2012 * Reschedule timeout. First, cancel a queued timeout (if any) 2013 * in case someone decides to call ncr53c9x_abort() from 2014 * elsewhere. 2015 */ 2016 untimeout(ncr53c9x_timeout, ecb); 2017 timeout(ncr53c9x_timeout, ecb, (ecb->timeout * hz) / 1000); 2018 } else { 2019 ncr53c9x_dequeue(sc, ecb); 2020 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 2021 if (sc->sc_state == NCR_IDLE) 2022 ncr53c9x_sched(sc); 2023 } 2024 } 2025 2026 void 2027 ncr53c9x_timeout(arg) 2028 void *arg; 2029 { 2030 struct ncr53c9x_ecb *ecb = arg; 2031 struct scsipi_xfer *xs = ecb->xs; 2032 struct scsipi_link *sc_link = xs->sc_link; 2033 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 2034 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 2035 int s; 2036 2037 scsi_print_addr(sc_link); 2038 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], " 2039 "<state %d, nexus %p, phase(c %x, p %x), resid %lx, " 2040 "msg(q %x,o %x) %s>", 2041 sc->sc_dev.dv_xname, 2042 ecb, ecb->flags, ecb->dleft, ecb->stat, 2043 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2044 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 2045 NCRDMA_ISACTIVE(sc) ? "DMA active" : ""); 2046 #if NCR53C9X_DEBUG > 1 2047 printf("TRACE: %s.", ecb->trace); 2048 #endif 2049 2050 s = splbio(); 2051 2052 if (ecb->flags & ECB_ABORT) { 2053 /* abort timed out */ 2054 printf(" AGAIN\n"); 2055 2056 ncr53c9x_init(sc, 1); 2057 } else { 2058 /* abort the operation that has timed out */ 2059 printf("\n"); 2060 xs->error = XS_TIMEOUT; 2061 ncr53c9x_abort(sc, ecb); 2062 2063 /* Disable sync mode if stuck in a data phase */ 2064 if (ecb == sc->sc_nexus && 2065 (ti->flags & T_SYNCMODE) != 0 && 2066 (sc->sc_phase & (MSGI|CDI)) == 0) { 2067 scsi_print_addr(sc_link); 2068 printf("sync negotiation disabled\n"); 2069 sc->sc_cfflags |= (1<<(sc_link->scsipi_scsi.target+8)); 2070 } 2071 } 2072 2073 splx(s); 2074 } 2075