xref: /netbsd-src/sys/dev/ic/mlxreg.h (revision 0de5da96785b1112f67c5bf59ccaf6b398a8c422)
1*0de5da96Sgmcgarry /*	$NetBSD: mlxreg.h,v 1.8 2008/09/08 23:36:54 gmcgarry Exp $	*/
28d75ab98Sad 
38d75ab98Sad /*-
48d75ab98Sad  * Copyright (c) 2001 The NetBSD Foundation, Inc.
58d75ab98Sad  * All rights reserved.
68d75ab98Sad  *
78d75ab98Sad  * This code is derived from software contributed to The NetBSD Foundation
88d75ab98Sad  * by Andrew Doran.
98d75ab98Sad  *
108d75ab98Sad  * Redistribution and use in source and binary forms, with or without
118d75ab98Sad  * modification, are permitted provided that the following conditions
128d75ab98Sad  * are met:
138d75ab98Sad  * 1. Redistributions of source code must retain the above copyright
148d75ab98Sad  *    notice, this list of conditions and the following disclaimer.
158d75ab98Sad  * 2. Redistributions in binary form must reproduce the above copyright
168d75ab98Sad  *    notice, this list of conditions and the following disclaimer in the
178d75ab98Sad  *    documentation and/or other materials provided with the distribution.
188d75ab98Sad  *
198d75ab98Sad  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
208d75ab98Sad  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
218d75ab98Sad  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
228d75ab98Sad  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
238d75ab98Sad  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
248d75ab98Sad  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
258d75ab98Sad  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
268d75ab98Sad  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
278d75ab98Sad  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
288d75ab98Sad  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
298d75ab98Sad  * POSSIBILITY OF SUCH DAMAGE.
308d75ab98Sad  */
318d75ab98Sad 
328d75ab98Sad /*-
338d75ab98Sad  * Copyright (c) 1999 Michael Smith
348d75ab98Sad  * All rights reserved.
358d75ab98Sad  *
368d75ab98Sad  * Redistribution and use in source and binary forms, with or without
378d75ab98Sad  * modification, are permitted provided that the following conditions
388d75ab98Sad  * are met:
398d75ab98Sad  * 1. Redistributions of source code must retain the above copyright
408d75ab98Sad  *    notice, this list of conditions and the following disclaimer.
418d75ab98Sad  * 2. Redistributions in binary form must reproduce the above copyright
428d75ab98Sad  *    notice, this list of conditions and the following disclaimer in the
438d75ab98Sad  *    documentation and/or other materials provided with the distribution.
448d75ab98Sad  *
458d75ab98Sad  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
468d75ab98Sad  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
478d75ab98Sad  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
488d75ab98Sad  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
498d75ab98Sad  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
508d75ab98Sad  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
518d75ab98Sad  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
528d75ab98Sad  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
538d75ab98Sad  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
548d75ab98Sad  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
558d75ab98Sad  * SUCH DAMAGE.
568d75ab98Sad  *
578d75ab98Sad  * from FreeBSD: mlxreg.h,v 1.5.2.2 2000/04/24 19:40:50 msmith Exp
588d75ab98Sad  */
598d75ab98Sad 
608d75ab98Sad #ifndef _IC_MLXREG_H_
618d75ab98Sad #define	_IC_MLXREG_H_
628d75ab98Sad 
638d75ab98Sad #define	MLX_SECTOR_SIZE		512
648d75ab98Sad 
658d75ab98Sad /*
668d75ab98Sad  * Selected command codes.
678d75ab98Sad  */
688d75ab98Sad #define	MLX_CMD_ENQUIRY_OLD	0x05
698d75ab98Sad #define	MLX_CMD_ENQUIRY		0x53
708d75ab98Sad #define	MLX_CMD_ENQUIRY2	0x1c
718d75ab98Sad #define	MLX_CMD_ENQSYSDRIVE	0x19
728d75ab98Sad #define	MLX_CMD_READSG		0xb6
738d75ab98Sad #define	MLX_CMD_WRITESG		0xb7
748d75ab98Sad #define	MLX_CMD_READSG_OLD	0x82
758d75ab98Sad #define	MLX_CMD_WRITESG_OLD	0x83
768d75ab98Sad #define	MLX_CMD_FLUSH		0x0a
778d75ab98Sad #define	MLX_CMD_LOGOP		0x72
788d75ab98Sad #define	MLX_CMD_REBUILDASYNC	0x16
798d75ab98Sad #define	MLX_CMD_CHECKASYNC	0x1e
808d75ab98Sad #define	MLX_CMD_REBUILDSTAT	0x0c
818d75ab98Sad #define	MLX_CMD_STOPCHANNEL	0x13
828d75ab98Sad #define	MLX_CMD_STARTCHANNEL	0x12
838d75ab98Sad #define	MLX_CMD_READ_CONFIG	0x4e
848d75ab98Sad #define	MLX_CMD_WRITE_CONFIG	0x4f
858d75ab98Sad #define	MLX_CMD_READ_DK_CONFIG	0x4a
868d75ab98Sad #define	MLX_CMD_WRITE_DK_CONFIG	0x4b
878d75ab98Sad #define	MLX_CMD_DIRECT_CDB	0x04
888d75ab98Sad #define	MLX_CMD_DEVICE_STATE	0x50
898d75ab98Sad #define	MLX_CMD_READ_CONFIG2	0x3d
908d75ab98Sad #define	MLX_CMD_WRITE_CONFIG2	0x3c
918d75ab98Sad 
928d75ab98Sad #ifdef _KERNEL
938d75ab98Sad 
948d75ab98Sad /*
958d75ab98Sad  * Status values.
968d75ab98Sad  */
978d75ab98Sad #define	MLX_STATUS_OK		0x0000
988d75ab98Sad #define	MLX_STATUS_RDWROFFLINE	0x0002	/* read/write claims drive is offline */
998d75ab98Sad #define	MLX_STATUS_WEDGED	0xdeaf	/* controller not listening */
1008d75ab98Sad #define	MLX_STATUS_LOST		0xdead	/* never came back */
1013b6c996dSad #define	MLX_STATUS_BUSY		0xbabe	/* command is in controller */
1028d75ab98Sad 
1038d75ab98Sad /*
1048d75ab98Sad  * V1 (EISA) interface.
1058d75ab98Sad  */
1068d75ab98Sad #define	MLX_V1REG_IE			0x09
1078d75ab98Sad #define	MLX_V1REG_IDB			0x0d
1088d75ab98Sad #define	MLX_V1REG_ODB_EN		0x0e
1098d75ab98Sad #define	MLX_V1REG_ODB			0x0f
1108d75ab98Sad #define	MLX_V1REG_MAILBOX		0x10
1118d75ab98Sad 
1128d75ab98Sad #define	MLX_V1_IDB_FULL		0x01	/* mailbox is full */
1138d75ab98Sad #define	MLX_V1_IDB_INIT_BUSY	0x02	/* init in progress */
1148d75ab98Sad 
1158d75ab98Sad #define	MLX_V1_IDB_SACK		0x02	/* acknowledge status read */
11695450fbcSad #define	MLX_V1_IDB_RESET	0x10	/* reset controller */
1178d75ab98Sad 
1188d75ab98Sad #define	MLX_V1_ODB_SAVAIL	0x01	/* status is available */
11995450fbcSad #define	MLX_V1_ODB_RESET	0x02	/* reset controller */
1208d75ab98Sad 
1218d75ab98Sad #define	MLX_V1_FWERROR_PEND	0x04	/* firmware error pending */
1228d75ab98Sad 
1238d75ab98Sad /*
1248d75ab98Sad  * V2/V3 interface.
1258d75ab98Sad  */
1268d75ab98Sad #define	MLX_V3REG_MAILBOX		0x00
1278d75ab98Sad #define	MLX_V3REG_STATUS_IDENT		0x0d
1288d75ab98Sad #define	MLX_V3REG_STATUS		0x0e
1298d75ab98Sad #define	MLX_V3REG_IDB			0x40
1308d75ab98Sad #define	MLX_V3REG_ODB			0x41
1318d75ab98Sad #define	MLX_V3REG_IE			0x43
1328d75ab98Sad #define	MLX_V3REG_FWERROR		0x3f
1338d75ab98Sad #define	MLX_V3REG_FWERROR_PARAM1	0x00
1348d75ab98Sad #define	MLX_V3REG_FWERROR_PARAM2	0x01
1358d75ab98Sad 
1368d75ab98Sad #define	MLX_V3_IDB_FULL		0x01	/* mailbox is full */
1378d75ab98Sad #define	MLX_V3_IDB_INIT_BUSY	0x02	/* init in progress */
1388d75ab98Sad 
1398d75ab98Sad #define	MLX_V3_IDB_SACK		0x02	/* acknowledge status read */
14095450fbcSad #define	MLX_V3_IDB_RESET	0x08	/* reset controller */
1418d75ab98Sad 
1428d75ab98Sad #define	MLX_V3_ODB_SAVAIL	0x01	/* status is available */
1438d75ab98Sad 
1448d75ab98Sad #define	MLX_V3_FWERROR_PEND	0x04	/* firmware error pending */
1458d75ab98Sad 
1468d75ab98Sad /*
1478d75ab98Sad  * V4 interface.
1488d75ab98Sad  */
1498d75ab98Sad #define	MLX_V4REG_MAILBOX		0x1000
1508d75ab98Sad #define	MLX_V4REG_STATUS_IDENT		0x1018
1518d75ab98Sad #define	MLX_V4REG_STATUS		0x101a
1528d75ab98Sad #define	MLX_V4REG_IDB			0x0020
1538d75ab98Sad #define	MLX_V4REG_ODB			0x002c
1548d75ab98Sad #define	MLX_V4REG_IE			0x0034
1558d75ab98Sad #define	MLX_V4REG_FWERROR		0x103f
1568d75ab98Sad #define	MLX_V4REG_FWERROR_PARAM1	0x1000
1578d75ab98Sad #define	MLX_V4REG_FWERROR_PARAM2	0x1001
1588d75ab98Sad 
1598d75ab98Sad #define	MLX_V4_IDB_FULL		0x01	/* mailbox is full */
1608d75ab98Sad #define	MLX_V4_IDB_INIT_BUSY	0x02	/* initialisation in progress */
1618d75ab98Sad 
1628d75ab98Sad #define	MLX_V4_IDB_HWMBOX_CMD	0x01	/* posted hardware mailbox command */
1638d75ab98Sad #define	MLX_V4_IDB_SACK		0x02	/* acknowledge status read */
1648d75ab98Sad #define	MLX_V4_IDB_MEMMBOX_CMD	0x10	/* posted memory mailbox command */
1658d75ab98Sad 
1668d75ab98Sad #define	MLX_V4_ODB_HWSAVAIL	0x01	/* status available for hardware m/b */
1678d75ab98Sad #define	MLX_V4_ODB_MEMSAVAIL	0x02	/* status available for memory m/b */
1688d75ab98Sad 
1698d75ab98Sad #define	MLX_V4_ODB_HWMBOX_ACK	0x01	/* ack status read from hardware m/b */
1708d75ab98Sad #define	MLX_V4_ODB_MEMMBOX_ACK	0x02	/* ack status read from memory m/b */
1718d75ab98Sad 
1728d75ab98Sad #define	MLX_V4_IE_MASK		0xfb	/* message unit interrupt mask */
1738d75ab98Sad #define	MLX_V4_IE_DISINT	0x04	/* interrupt disable bit */
1748d75ab98Sad 
1758d75ab98Sad #define	MLX_V4_FWERROR_PEND	0x04	/* firmware error pending */
1768d75ab98Sad 
1778d75ab98Sad /*
1788d75ab98Sad  * V5 interface.
1798d75ab98Sad  */
1808d75ab98Sad #define	MLX_V5REG_MAILBOX		0x50
1818d75ab98Sad #define	MLX_V5REG_STATUS_IDENT		0x5d
1828d75ab98Sad #define	MLX_V5REG_STATUS		0x5e
1838d75ab98Sad #define	MLX_V5REG_IDB			0x60
1848d75ab98Sad #define	MLX_V5REG_ODB			0x61
1858d75ab98Sad #define	MLX_V5REG_IE			0x34
1868d75ab98Sad #define	MLX_V5REG_FWERROR		0x63
1878d75ab98Sad #define	MLX_V5REG_FWERROR_PARAM1	0x50
1888d75ab98Sad #define	MLX_V5REG_FWERROR_PARAM2	0x51
1898d75ab98Sad 
1908d75ab98Sad #define	MLX_V5_IDB_EMPTY	0x01	/* mailbox is empty */
1918d75ab98Sad #define	MLX_V5_IDB_INIT_DONE	0x02	/* initialisation has completed */
1928d75ab98Sad 
1938d75ab98Sad #define	MLX_V5_IDB_HWMBOX_CMD	0x01	/* posted hardware mailbox command */
1948d75ab98Sad #define	MLX_V5_IDB_SACK		0x02	/* acknowledge status read */
1958d75ab98Sad #define	MLX_V5_IDB_RESET	0x08	/* reset request */
1968d75ab98Sad #define	MLX_V5_IDB_MEMMBOX_CMD	0x10	/* posted memory mailbox command */
1978d75ab98Sad 
1988d75ab98Sad #define	MLX_V5_ODB_HWSAVAIL	0x01	/* status available for hardware m/b */
1998d75ab98Sad #define	MLX_V5_ODB_MEMSAVAIL	0x02	/* status available for memory m/b */
2008d75ab98Sad 
2018d75ab98Sad #define	MLX_V5_ODB_HWMBOX_ACK	0x01	/* ack status read from hardware m/b */
2028d75ab98Sad #define	MLX_V5_ODB_MEMMBOX_ACK	0x02	/* ack status read from memory m/b */
2038d75ab98Sad 
2048d75ab98Sad #define	MLX_V5_IE_DISINT	0x04	/* interrupt disable bit */
2058d75ab98Sad 
2068d75ab98Sad #define	MLX_V5_FWERROR_PEND	0x04	/* firmware error pending */
2078d75ab98Sad 
2088d75ab98Sad #endif /* _KERNEL */
2098d75ab98Sad 
2108d75ab98Sad /*
2118d75ab98Sad  * Scatter-gather list format, type 1, kind 00.
2128d75ab98Sad  */
2138d75ab98Sad struct mlx_sgentry {
2148d75ab98Sad 	u_int32_t	sge_addr;
2158d75ab98Sad 	u_int32_t	sge_count;
216*0de5da96Sgmcgarry } __packed;
2178d75ab98Sad 
2188d75ab98Sad /*
2198d75ab98Sad  * Command result buffers, as placed in system memory by the controller.
2208d75ab98Sad  */
2218d75ab98Sad struct mlx_enquiry_old {
2228d75ab98Sad 	u_int8_t	me_num_sys_drvs;
2238d75ab98Sad 	u_int8_t	me_res1[3];
2248d75ab98Sad 	u_int32_t	me_drvsize[8];
2258d75ab98Sad 	u_int16_t	me_flash_age;
2268d75ab98Sad 	u_int8_t	me_status_flags;
2278d75ab98Sad 	u_int8_t	me_free_state_change_count;
2288d75ab98Sad 	u_int8_t	me_fwminor;
2298d75ab98Sad 	u_int8_t	me_fwmajor;
2308d75ab98Sad 	u_int8_t	me_rebuild_flag;
2318d75ab98Sad 	u_int8_t	me_max_commands;
2328d75ab98Sad 	u_int8_t	me_offline_sd_count;
2338d75ab98Sad 	u_int8_t	me_res3;
2348d75ab98Sad 	u_int8_t	me_critical_sd_count;
2358d75ab98Sad 	u_int8_t	me_res4[3];
2368d75ab98Sad 	u_int8_t	me_dead_count;
2378d75ab98Sad 	u_int8_t	me_res5;
2388d75ab98Sad 	u_int8_t	me_rebuild_count;
2398d75ab98Sad 	u_int8_t	me_misc_flags;
2408d75ab98Sad 	struct  {
2418d75ab98Sad 		u_int8_t	dd_targ;
2428d75ab98Sad 		u_int8_t	dd_chan;
243*0de5da96Sgmcgarry 	} __packed me_dead[20];
244*0de5da96Sgmcgarry } __packed;
2458d75ab98Sad 
2468d75ab98Sad struct mlx_enquiry {
2478d75ab98Sad 	u_int8_t	me_num_sys_drvs;
2488d75ab98Sad 	u_int8_t	me_res1[3];
2498d75ab98Sad 	u_int32_t	me_drvsize[32];
2508d75ab98Sad 	u_int16_t	me_flash_age;
2518d75ab98Sad 	u_int8_t	me_status_flags;
2528d75ab98Sad #define	MLX_ENQ_SFLAG_DEFWRERR	0x01	/* deferred write error indicator */
2538d75ab98Sad #define	MLX_ENQ_SFLAG_BATTLOW	0x02	/* battery low */
2548d75ab98Sad 	u_int8_t	me_res2;
2558d75ab98Sad 	u_int8_t	me_fwminor;
2568d75ab98Sad 	u_int8_t	me_fwmajor;
2578d75ab98Sad 	u_int8_t	me_rebuild_flag;
2588d75ab98Sad 	u_int8_t	me_max_commands;
2598d75ab98Sad 	u_int8_t	me_offline_sd_count;
2608d75ab98Sad 	u_int8_t	me_res3;
2618d75ab98Sad 	u_int16_t	me_event_log_seq_num;
2628d75ab98Sad 	u_int8_t	me_critical_sd_count;
2638d75ab98Sad 	u_int8_t	me_res4[3];
2648d75ab98Sad 	u_int8_t	me_dead_count;
2658d75ab98Sad 	u_int8_t	me_res5;
2668d75ab98Sad 	u_int8_t	me_rebuild_count;
2678d75ab98Sad 	u_int8_t	me_misc_flags;
2688d75ab98Sad #define	MLX_ENQ_MISC_BBU	0x08	/* battery backup present */
2698d75ab98Sad 	struct {
2708d75ab98Sad 		u_int8_t	dd_targ;
2718d75ab98Sad 		u_int8_t	dd_chan;
272*0de5da96Sgmcgarry 	} __packed me_dead[20];
273*0de5da96Sgmcgarry } __packed;
2748d75ab98Sad 
2758d75ab98Sad struct mlx_enquiry2 {
2768d75ab98Sad 	u_int8_t	me_hardware_id[4];
2778d75ab98Sad 	u_int8_t	me_firmware_id[4];
2788d75ab98Sad 	u_int32_t	me_res1;
2798d75ab98Sad 	u_int8_t	me_configured_channels;
2808d75ab98Sad 	u_int8_t	me_actual_channels;
2818d75ab98Sad 	u_int8_t	me_max_targets;
2828d75ab98Sad 	u_int8_t	me_max_tags;
2838d75ab98Sad 	u_int8_t	me_max_sys_drives;
2848d75ab98Sad 	u_int8_t	me_max_arms;
2858d75ab98Sad 	u_int8_t	me_max_spans;
2868d75ab98Sad 	u_int8_t	me_res2;
2878d75ab98Sad 	u_int32_t	me_res3;
2888d75ab98Sad 	u_int32_t	me_mem_size;
2898d75ab98Sad 	u_int32_t	me_cache_size;
2908d75ab98Sad 	u_int32_t	me_flash_size;
2918d75ab98Sad 	u_int32_t	me_nvram_size;
2928d75ab98Sad 	u_int16_t	me_mem_type;
2938d75ab98Sad 	u_int16_t	me_clock_speed;
2948d75ab98Sad 	u_int16_t	me_mem_speed;
2958d75ab98Sad 	u_int16_t	me_hardware_speed;
2968d75ab98Sad 	u_int8_t	me_res4[12];
2978d75ab98Sad 	u_int16_t	me_max_commands;
2988d75ab98Sad 	u_int16_t	me_max_sg;
2998d75ab98Sad 	u_int16_t	me_max_dp;
3008d75ab98Sad 	u_int16_t	me_max_iod;
3018d75ab98Sad 	u_int16_t	me_max_comb;
3028d75ab98Sad 	u_int8_t	me_latency;
3038d75ab98Sad 	u_int8_t	me_res5;
3048d75ab98Sad 	u_int8_t	me_scsi_timeout;
3058d75ab98Sad 	u_int8_t	me_res6;
3068d75ab98Sad 	u_int16_t	me_min_freelines;
3078d75ab98Sad 	u_int8_t	me_res7[8];
3088d75ab98Sad 	u_int8_t	me_rate_const;
3098d75ab98Sad 	u_int8_t	me_res8[11];
3108d75ab98Sad 	u_int16_t	me_physblk;
3118d75ab98Sad 	u_int16_t	me_logblk;
3128d75ab98Sad 	u_int16_t	me_maxblk;
3138d75ab98Sad 	u_int16_t	me_blocking_factor;
3148d75ab98Sad 	u_int16_t	me_cacheline;
3158d75ab98Sad 	u_int8_t	me_scsi_cap;
3168d75ab98Sad 	u_int8_t	me_res9[5];
3178d75ab98Sad 	u_int16_t	me_firmware_build;
3188d75ab98Sad 	u_int8_t	me_fault_mgmt_type;
3198d75ab98Sad 	u_int8_t	me_res10;
3208d75ab98Sad 	u_int32_t	me_firmware_features;
3218d75ab98Sad 	u_int8_t	me_res11[8];
322*0de5da96Sgmcgarry } __packed;
3238d75ab98Sad 
3248d75ab98Sad /* MLX_CMD_ENQSYSDRIVE returns an array of 32 of these. */
3258d75ab98Sad struct mlx_enq_sys_drive {
3268d75ab98Sad 	u_int32_t	sd_size;
3278d75ab98Sad 	u_int8_t	sd_state;
3288d75ab98Sad 	u_int8_t	sd_raidlevel;
3298d75ab98Sad 	u_int16_t	sd_res1;
330*0de5da96Sgmcgarry } __packed;
3318d75ab98Sad 
3328d75ab98Sad /*
3338d75ab98Sad  * MLX_CMD_LOGOP/MLX_LOGOP_GET
3348d75ab98Sad  *
3358d75ab98Sad  * Bitfields:
3368d75ab98Sad  *
3378d75ab98Sad  * 0-4	el_target	SCSI target
3388d75ab98Sad  * 5-7  el_target	SCSI channel
3398d75ab98Sad  * 0-6	el_errorcode	error code
3408d75ab98Sad  * 7-7	el_errorcode	validity (?)
3418d75ab98Sad  * 0-3	el_sense	sense key
3428d75ab98Sad  * 4-4	el_sense	reserved
3438d75ab98Sad  * 5-5	el_sense	ILI
3448d75ab98Sad  * 6-6	el_sense	EOM
3458d75ab98Sad  * 7-7	el_sense	filemark
3468d75ab98Sad  */
3478d75ab98Sad struct mlx_eventlog_entry {
3488d75ab98Sad 	u_int8_t	el_type;
3498d75ab98Sad 	u_int8_t	el_length;
3508d75ab98Sad 	u_int8_t	el_target;
3518d75ab98Sad 	u_int8_t	el_lun;
3528d75ab98Sad 	u_int16_t	el_seqno;
3538d75ab98Sad 	u_int8_t	el_errorcode;
3548d75ab98Sad 	u_int8_t	el_segment;
3558d75ab98Sad 	u_int8_t	el_sense;
3568d75ab98Sad 	u_int8_t	el_information[4];
3578d75ab98Sad 	u_int8_t	el_addsense;
3588d75ab98Sad 	u_int8_t	el_csi[4];
3598d75ab98Sad 	u_int8_t	el_asc;
3608d75ab98Sad 	u_int8_t	el_asq;
3618d75ab98Sad 	u_int8_t	el_res3[12];
362*0de5da96Sgmcgarry } __packed;
3638d75ab98Sad 
3648d75ab98Sad #define	MLX_LOGOP_GET		0x00	/* operation codes for MLX_CMD_LOGOP */
3658d75ab98Sad #define	MLX_LOGMSG_SENSE	0x00	/* log message contents codes */
3668d75ab98Sad 
3678d75ab98Sad struct mlx_rebuild_stat {
3688d75ab98Sad 	u_int32_t	rb_drive;
3698d75ab98Sad 	u_int32_t	rb_size;
3708d75ab98Sad 	u_int32_t	rb_remaining;
371*0de5da96Sgmcgarry } __packed;
3728d75ab98Sad 
3738d75ab98Sad struct mlx_config {
3748d75ab98Sad 	u_int16_t	cf_flags1;
3758d75ab98Sad #define	MLX_CF2_ACTV_NEG	0x0002
3768d75ab98Sad #define	MLX_CF2_NORSTRTRY	0x0080
3778d75ab98Sad #define	MLX_CF2_STRGWRK		0x0100
3788d75ab98Sad #define	MLX_CF2_HPSUPP		0x0200
3798d75ab98Sad #define	MLX_CF2_NODISCN		0x0400
3808d75ab98Sad #define	MLX_CF2_ARM		0x2000
3818d75ab98Sad #define	MLX_CF2_OFM		0x8000
3828d75ab98Sad #define	MLX_CF2_AEMI		(MLX_CF2_ARM | MLX_CF2_OFM)
3838d75ab98Sad 	u_int8_t	cf_oemid;
3848d75ab98Sad 	u_int8_t	cf_oem_model;
3858d75ab98Sad 	u_int8_t	cf_physical_sector;
3868d75ab98Sad 	u_int8_t	cf_logical_sector;
3878d75ab98Sad 	u_int8_t	cf_blockfactor;
3888d75ab98Sad 	u_int8_t	cf_flags2;
3898d75ab98Sad #define	MLX_CF2_READAH		0x01
3908d75ab98Sad #define	MLX_CF2_BIOSDLY		0x02
3918d75ab98Sad #define	MLX_CF2_REASS1S		0x10
3928d75ab98Sad #define	MLX_CF2_FUAENABL	0x40
3938d75ab98Sad #define	MLX_CF2_R5ALLS		0x80
3948d75ab98Sad 	u_int8_t	cf_rcrate;
3958d75ab98Sad 	u_int8_t	cf_res1;
3968d75ab98Sad 	u_int8_t	cf_blocks_per_cache_line;
3978d75ab98Sad 	u_int8_t	cf_blocks_per_stripe;
3988d75ab98Sad 	u_int8_t	cf_scsi_param_0;
3998d75ab98Sad 	u_int8_t	cf_scsi_param_1;
4008d75ab98Sad 	u_int8_t	cf_scsi_param_2;
4018d75ab98Sad 	u_int8_t	cf_scsi_param_3;
4028d75ab98Sad 	u_int8_t	cf_scsi_param_4;
4038d75ab98Sad 	u_int8_t	cf_scsi_param_5;
4048d75ab98Sad 	u_int8_t	cf_scsi_initiator_id;
4058d75ab98Sad 	u_int8_t	cf_res2;
4068d75ab98Sad 	u_int8_t	cf_startup_mode;
4078d75ab98Sad 	u_int8_t	cf_simultaneous_spinup_devices;
4088d75ab98Sad 	u_int8_t	cf_delay_between_spinups;
4098d75ab98Sad 	u_int8_t	cf_res3;
4108d75ab98Sad 	u_int16_t	cf_checksum;
411*0de5da96Sgmcgarry } __packed;
4128d75ab98Sad 
4138d75ab98Sad struct mlx_config2 {
4148d75ab98Sad 	struct mlx_config cf2_cf;
4158d75ab98Sad 	u_int8_t	cf2_reserved0[26];
4168d75ab98Sad 	u_int8_t	cf2_flags;
4178d75ab98Sad #define	MLX_CF2_BIOS_DIS	0x01
4188d75ab98Sad #define	MLX_CF2_CDROM_DIS	0x02
4198d75ab98Sad #define	MLX_CF2_GEOM_255	0x20
4208d75ab98Sad 	u_int8_t	cf2_reserved1[9];
4218d75ab98Sad 	u_int16_t	cf2_checksum;
422*0de5da96Sgmcgarry } __packed;
4238d75ab98Sad 
4248d75ab98Sad struct mlx_sys_drv_span {
4258d75ab98Sad 	u_int32_t	sp_start_lba;
4268d75ab98Sad 	u_int32_t	sp_nblks;
4278d75ab98Sad 	u_int8_t	sp_arm[8];
428*0de5da96Sgmcgarry } __packed;
4298d75ab98Sad 
4308d75ab98Sad struct mlx_sys_drv {
4318d75ab98Sad 	u_int8_t	sd_status;
4328d75ab98Sad 	u_int8_t	sd_ext_status;
4338d75ab98Sad 	u_int8_t	sd_mod1;
4348d75ab98Sad 	u_int8_t	sd_mod2;
4358d75ab98Sad 	u_int8_t	sd_raidlevel;
4368d75ab98Sad #define	MLX_SYS_DRV_WRITEBACK	(1<<7)
4378d75ab98Sad #define	MLX_SYS_DRV_RAID0	0
4388d75ab98Sad #define	MLX_SYS_DRV_RAID1	1
4398d75ab98Sad #define	MLX_SYS_DRV_RAID3	3
4408d75ab98Sad #define	MLX_SYS_DRV_RAID5	5
4418d75ab98Sad #define	MLX_SYS_DRV_RAID6	6
4428d75ab98Sad #define	MLX_SYS_DRV_JBOD	7
4438d75ab98Sad 	u_int8_t	sd_valid_arms;
4448d75ab98Sad 	u_int8_t	sd_valid_spans;
4458d75ab98Sad 	u_int8_t	sd_init_state;
4468d75ab98Sad #define	MLX_SYS_DRV_INITTED	0x81;
4478d75ab98Sad 	struct	mlx_sys_drv_span sd_span[4];
448*0de5da96Sgmcgarry } __packed;
4498d75ab98Sad 
4508d75ab98Sad struct mlx_phys_drv {
4518d75ab98Sad 	u_int8_t	pd_flags1;
4528d75ab98Sad #define	MLX_PHYS_DRV_PRESENT	0x01
4538d75ab98Sad 	u_int8_t	pd_flags2;
4548d75ab98Sad #define	MLX_PHYS_DRV_OTHER	0x00
4558d75ab98Sad #define	MLX_PHYS_DRV_DISK	0x01
4568d75ab98Sad #define	MLX_PHYS_DRV_SEQUENTIAL	0x02
4578d75ab98Sad #define	MLX_PHYS_DRV_CDROM	0x03
4588d75ab98Sad #define	MLX_PHYS_DRV_FAST20	0x08
4598d75ab98Sad #define	MLX_PHYS_DRV_SYNC	0x10
4608d75ab98Sad #define	MLX_PHYS_DRV_FAST	0x20
4618d75ab98Sad #define	MLX_PHYS_DRV_WIDE	0x40
4628d75ab98Sad #define	MLX_PHYS_DRV_TAG	0x80
4638d75ab98Sad 	u_int8_t	pd_status;
4648d75ab98Sad #define	MLX_PHYS_DRV_DEAD	0x00
4658d75ab98Sad #define	MLX_PHYS_DRV_WRONLY	0x02
4668d75ab98Sad #define	MLX_PHYS_DRV_ONLINE	0x03
4678d75ab98Sad #define	MLX_PHYS_DRV_STANDBY	0x10
4688d75ab98Sad 	u_int8_t	pd_res1;
4698d75ab98Sad 	u_int8_t	pd_period;
4708d75ab98Sad 	u_int8_t	pd_offset;
4718d75ab98Sad 	u_int32_t	pd_config_size;
472*0de5da96Sgmcgarry } __packed;
4738d75ab98Sad 
4748d75ab98Sad struct mlx_core_cfg {
4758d75ab98Sad 	u_int8_t	cc_num_sys_drives;
4768d75ab98Sad 	u_int8_t	cc_res1[3];
4778d75ab98Sad 	struct	mlx_sys_drv cc_sys_drives[32];
4788d75ab98Sad 	struct	mlx_phys_drv cc_phys_drives[5 * 16];
479*0de5da96Sgmcgarry } __packed;
4808d75ab98Sad 
4818d75ab98Sad /*
4828d75ab98Sad  * Bitfields:
4838d75ab98Sad  *
4848d75ab98Sad  * 0-3	dcdb_target	SCSI target
4858d75ab98Sad  * 4-7	dcdb_target	SCSI channel
4868d75ab98Sad  * 0-3	dcdb_length	CDB length
4878d75ab98Sad  * 4-7	dcdb_length	high 4 bits of `datasize'
4888d75ab98Sad  */
4898d75ab98Sad struct mlx_dcdb {
4908d75ab98Sad 	u_int8_t	dcdb_target;
4918d75ab98Sad 	u_int8_t	dcdb_flags;
4928d75ab98Sad #define	MLX_DCDB_NO_DATA	0x00
4938d75ab98Sad #define	MLX_DCDB_DATA_IN	0x01
4948d75ab98Sad #define	MLX_DCDB_DATA_OUT	0x02
4958d75ab98Sad #define	MLX_DCDB_EARLY_STATUS	0x04
4968d75ab98Sad #define	MLX_DCDB_TIMEOUT_10S	0x10	/* This lot is wrong? [ad] */
4978d75ab98Sad #define	MLX_DCDB_TIMEOUT_60S	0x20
4988d75ab98Sad #define	MLX_DCDB_TIMEOUT_20M	0x30
4998d75ab98Sad #define	MLX_DCDB_TIMEOUT_24H	0x40
5008d75ab98Sad #define	MLX_DCDB_NO_AUTO_SENSE	0x40	/* XXX ?? */
5018d75ab98Sad #define	MLX_DCDB_DISCONNECT	0x80
5028d75ab98Sad 	u_int16_t	dcdb_datasize;
5038d75ab98Sad 	u_int32_t	dcdb_physaddr;
5048d75ab98Sad 	u_int8_t	dcdb_length;
5058d75ab98Sad 	u_int8_t	dcdb_sense_length;
5068d75ab98Sad 	u_int8_t	dcdb_cdb[12];
5078d75ab98Sad 	u_int8_t	dcdb_sense[64];
5088d75ab98Sad 	u_int8_t	dcdb_status;
5098d75ab98Sad 	u_int8_t	res1;
510*0de5da96Sgmcgarry } __packed;
5118d75ab98Sad 
5128d75ab98Sad struct mlx_bbtable_entry {
5138d75ab98Sad 	u_int32_t	bbt_block_number;
5148d75ab98Sad 	u_int8_t	bbt_extent;
5158d75ab98Sad 	u_int8_t	bbt_res1;
5168d75ab98Sad 	u_int8_t	bbt_entry_type;
5178d75ab98Sad 	u_int8_t	bbt_system_drive;	/* high 3 bits reserved */
518*0de5da96Sgmcgarry } __packed;
5198d75ab98Sad 
5208d75ab98Sad #endif	/* !_IC_MLXREG_H_ */
521