1 /* $NetBSD: mb89352.c,v 1.15 2003/05/19 14:56:03 tsutsui Exp $ */ 2 /* NecBSD: mb89352.c,v 1.4 1998/03/14 07:31:20 kmatsuda Exp */ 3 4 /*- 5 * Copyright (c) 1996,97,98,99 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Charles M. Hannum. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * Copyright (c) 1994 Jarle Greipsland 26 * All rights reserved. 27 * 28 * Redistribution and use in source and binary forms, with or without 29 * modification, are permitted provided that the following conditions 30 * are met: 31 * 1. Redistributions of source code must retain the above copyright 32 * notice, this list of conditions and the following disclaimer. 33 * 2. Redistributions in binary form must reproduce the above copyright 34 * notice, this list of conditions and the following disclaimer in the 35 * documentation and/or other materials provided with the distribution. 36 * 3. The name of the author may not be used to endorse or promote products 37 * derived from this software without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 40 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 41 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 42 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 43 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 44 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 46 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 47 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 48 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 49 * POSSIBILITY OF SUCH DAMAGE. 50 */ 51 /* 52 * [NetBSD for NEC PC-98 series] 53 * Copyright (c) 1996, 1997, 1998 54 * NetBSD/pc98 porting staff. All rights reserved. 55 * Copyright (c) 1996, 1997, 1998 56 * Kouichi Matsuda. All rights reserved. 57 */ 58 59 /* 60 * Acknowledgements: Many of the algorithms used in this driver are 61 * inspired by the work of Julian Elischer (julian@tfs.com) and 62 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! 63 */ 64 65 /* TODO list: 66 * 1) Get the DMA stuff working. 67 * 2) Get the iov/uio stuff working. Is this a good thing ??? 68 * 3) Get the synch stuff working. 69 * 4) Rewrite it to use malloc for the acb structs instead of static alloc.? 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: mb89352.c,v 1.15 2003/05/19 14:56:03 tsutsui Exp $"); 74 75 #ifdef DDB 76 #define integrate 77 #else 78 #define integrate __inline static 79 #endif 80 81 /* 82 * A few customizable items: 83 */ 84 85 /* Use doubleword transfers to/from SCSI chip. Note: This requires 86 * motherboard support. Basicly, some motherboard chipsets are able to 87 * split a 32 bit I/O operation into two 16 bit I/O operations, 88 * transparently to the processor. This speeds up some things, notably long 89 * data transfers. 90 */ 91 #define SPC_USE_DWORDS 0 92 93 /* Synchronous data transfers? */ 94 #define SPC_USE_SYNCHRONOUS 0 95 #define SPC_SYNC_REQ_ACK_OFS 8 96 97 /* Wide data transfers? */ 98 #define SPC_USE_WIDE 0 99 #define SPC_MAX_WIDTH 0 100 101 /* Max attempts made to transmit a message */ 102 #define SPC_MSG_MAX_ATTEMPT 3 /* Not used now XXX */ 103 104 /* 105 * Some spin loop parameters (essentially how long to wait some places) 106 * The problem(?) is that sometimes we expect either to be able to transmit a 107 * byte or to get a new one from the SCSI bus pretty soon. In order to avoid 108 * returning from the interrupt just to get yanked back for the next byte we 109 * may spin in the interrupt routine waiting for this byte to come. How long? 110 * This is really (SCSI) device and processor dependent. Tuneable, I guess. 111 */ 112 #define SPC_MSGIN_SPIN 1 /* Will spinwait upto ?ms for a new msg byte */ 113 #define SPC_MSGOUT_SPIN 1 114 115 /* Include debug functions? At the end of this file there are a bunch of 116 * functions that will print out various information regarding queued SCSI 117 * commands, driver state and chip contents. You can call them from the 118 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the 119 * kernel uses less memory) but you lose the debugging facilities. 120 */ 121 #define SPC_DEBUG 1 122 123 #define SPC_ABORT_TIMEOUT 2000 /* time to wait for abort */ 124 125 /* End of customizable parameters */ 126 127 /* 128 * MB89352 SCSI Protocol Controller (SPC) routines. 129 */ 130 131 #include "opt_ddb.h" 132 133 #include <sys/param.h> 134 #include <sys/systm.h> 135 #include <sys/kernel.h> 136 #include <sys/errno.h> 137 #include <sys/ioctl.h> 138 #include <sys/device.h> 139 #include <sys/buf.h> 140 #include <sys/proc.h> 141 #include <sys/user.h> 142 #include <sys/queue.h> 143 144 #include <machine/intr.h> 145 #include <machine/bus.h> 146 147 #include <dev/scsipi/scsi_all.h> 148 #include <dev/scsipi/scsipi_all.h> 149 #include <dev/scsipi/scsi_message.h> 150 #include <dev/scsipi/scsiconf.h> 151 152 #include <dev/ic/mb89352reg.h> 153 #include <dev/ic/mb89352var.h> 154 155 #ifndef DDB 156 #define Debugger() panic("should call debugger here (mb89352.c)") 157 #endif /* ! DDB */ 158 159 #if SPC_DEBUG 160 int spc_debug = 0x00; /* SPC_SHOWSTART|SPC_SHOWMISC|SPC_SHOWTRACE; */ 161 #endif 162 163 void spc_minphys __P((struct buf *)); 164 void spc_done __P((struct spc_softc *, struct spc_acb *)); 165 void spc_dequeue __P((struct spc_softc *, struct spc_acb *)); 166 void spc_scsipi_request __P((struct scsipi_channel *, 167 scsipi_adapter_req_t, void *)); 168 int spc_poll __P((struct spc_softc *, struct scsipi_xfer *, int)); 169 integrate void spc_sched_msgout __P((struct spc_softc *, u_char)); 170 integrate void spc_setsync __P((struct spc_softc *, struct spc_tinfo *)); 171 void spc_select __P((struct spc_softc *, struct spc_acb *)); 172 void spc_timeout __P((void *)); 173 void spc_scsi_reset __P((struct spc_softc *)); 174 void spc_reset __P((struct spc_softc *)); 175 void spc_free_acb __P((struct spc_softc *, struct spc_acb *, int)); 176 struct spc_acb* spc_get_acb __P((struct spc_softc *)); 177 int spc_reselect __P((struct spc_softc *, int)); 178 void spc_msgin __P((struct spc_softc *)); 179 void spc_abort __P((struct spc_softc *, struct spc_acb *)); 180 void spc_msgout __P((struct spc_softc *)); 181 int spc_dataout_pio __P((struct spc_softc *, u_char *, int)); 182 int spc_datain_pio __P((struct spc_softc *, u_char *, int)); 183 #if SPC_DEBUG 184 void spc_print_acb __P((struct spc_acb *)); 185 void spc_dump_driver __P((struct spc_softc *)); 186 void spc_dump89352 __P((struct spc_softc *)); 187 void spc_show_scsi_cmd __P((struct spc_acb *)); 188 void spc_print_active_acb __P((void)); 189 #endif 190 191 extern struct cfdriver spc_cd; 192 193 194 /* 195 * INITIALIZATION ROUTINES (probe, attach ++) 196 */ 197 198 /* 199 * Do the real search-for-device. 200 * Prerequisite: sc->sc_iobase should be set to the proper value 201 */ 202 int 203 spc_find(iot, ioh, bdid) 204 bus_space_tag_t iot; 205 bus_space_handle_t ioh; 206 int bdid; 207 { 208 long timeout = SPC_ABORT_TIMEOUT; 209 210 SPC_TRACE(("spc: probing for spc-chip\n")); 211 /* 212 * Disable interrupts then reset the FUJITSU chip. 213 */ 214 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_CTRLRST); 215 bus_space_write_1(iot, ioh, SCMD, 0); 216 bus_space_write_1(iot, ioh, PCTL, 0); 217 bus_space_write_1(iot, ioh, TEMP, 0); 218 bus_space_write_1(iot, ioh, TCH, 0); 219 bus_space_write_1(iot, ioh, TCM, 0); 220 bus_space_write_1(iot, ioh, TCL, 0); 221 bus_space_write_1(iot, ioh, INTS, 0); 222 bus_space_write_1(iot, ioh, SCTL, 223 SCTL_DISABLE | SCTL_ABRT_ENAB | SCTL_PARITY_ENAB | SCTL_RESEL_ENAB); 224 bus_space_write_1(iot, ioh, BDID, bdid); 225 delay(400); 226 bus_space_write_1(iot, ioh, SCTL, 227 bus_space_read_1(iot, ioh, SCTL) & ~SCTL_DISABLE); 228 229 /* The following detection is derived from spc.c 230 * (by Takahide Matsutsuka) in FreeBSD/pccard-test. 231 */ 232 while (bus_space_read_1(iot, ioh, PSNS) && timeout) 233 timeout--; 234 if (!timeout) { 235 printf("spc: find failed\n"); 236 return 0; 237 } 238 239 SPC_START(("SPC found")); 240 return 1; 241 } 242 243 void 244 spcattach(sc) 245 struct spc_softc *sc; 246 { 247 248 SPC_TRACE(("spcattach ")); 249 sc->sc_state = SPC_INIT; 250 251 sc->sc_freq = 20; /* XXXX Assume 20 MHz. */ 252 253 #if SPC_USE_SYNCHRONOUS 254 /* 255 * These are the bounds of the sync period, based on the frequency of 256 * the chip's clock input and the size and offset of the sync period 257 * register. 258 * 259 * For a 20MHz clock, this gives us 25, or 100nS, or 10MB/s, as a 260 * maximum transfer rate, and 112.5, or 450nS, or 2.22MB/s, as a 261 * minimum transfer rate. 262 */ 263 sc->sc_minsync = (2 * 250) / sc->sc_freq; 264 sc->sc_maxsync = (9 * 250) / sc->sc_freq; 265 #endif 266 267 spc_init(sc); /* Init chip and driver */ 268 269 /* 270 * Fill in the adapter. 271 */ 272 sc->sc_adapter.adapt_dev = &sc->sc_dev; 273 sc->sc_adapter.adapt_nchannels = 1; 274 sc->sc_adapter.adapt_openings = 7; 275 sc->sc_adapter.adapt_max_periph = 1; 276 sc->sc_adapter.adapt_minphys = spc_minphys; 277 sc->sc_adapter.adapt_request = spc_scsipi_request; 278 279 sc->sc_channel.chan_adapter = &sc->sc_adapter; 280 sc->sc_channel.chan_bustype = &scsi_bustype; 281 sc->sc_channel.chan_channel = 0; 282 sc->sc_channel.chan_ntargets = 8; 283 sc->sc_channel.chan_nluns = 8; 284 sc->sc_channel.chan_id = sc->sc_initiator; 285 286 /* 287 * ask the adapter what subunits are present 288 */ 289 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 290 } 291 292 /* 293 * Initialize MB89352 chip itself 294 * The following conditions should hold: 295 * spc_isa_probe should have succeeded, i.e. the iobase address in spc_softc 296 * must be valid. 297 */ 298 void 299 spc_reset(sc) 300 struct spc_softc *sc; 301 { 302 bus_space_tag_t iot = sc->sc_iot; 303 bus_space_handle_t ioh = sc->sc_ioh; 304 305 SPC_TRACE(("spc_reset ")); 306 /* 307 * Disable interrupts then reset the FUJITSU chip. 308 */ 309 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_CTRLRST); 310 bus_space_write_1(iot, ioh, SCMD, 0); 311 bus_space_write_1(iot, ioh, PCTL, 0); 312 bus_space_write_1(iot, ioh, TEMP, 0); 313 bus_space_write_1(iot, ioh, TCH, 0); 314 bus_space_write_1(iot, ioh, TCM, 0); 315 bus_space_write_1(iot, ioh, TCL, 0); 316 bus_space_write_1(iot, ioh, INTS, 0); 317 bus_space_write_1(iot, ioh, SCTL, 318 SCTL_DISABLE | SCTL_ABRT_ENAB | SCTL_PARITY_ENAB | SCTL_RESEL_ENAB); 319 bus_space_write_1(iot, ioh, BDID, sc->sc_initiator); 320 delay(400); 321 bus_space_write_1(iot, ioh, SCTL, 322 bus_space_read_1(iot, ioh, SCTL) & ~SCTL_DISABLE); 323 } 324 325 326 /* 327 * Pull the SCSI RST line for 500us. 328 */ 329 void 330 spc_scsi_reset(sc) 331 struct spc_softc *sc; 332 { 333 bus_space_tag_t iot = sc->sc_iot; 334 bus_space_handle_t ioh = sc->sc_ioh; 335 336 SPC_TRACE(("spc_scsi_reset ")); 337 bus_space_write_1(iot, ioh, SCMD, 338 bus_space_read_1(iot, ioh, SCMD) | SCMD_RST); 339 delay(500); 340 bus_space_write_1(iot, ioh, SCMD, 341 bus_space_read_1(iot, ioh, SCMD) & ~SCMD_RST); 342 delay(50); 343 } 344 345 /* 346 * Initialize spc SCSI driver. 347 */ 348 void 349 spc_init(sc) 350 struct spc_softc *sc; 351 { 352 struct spc_acb *acb; 353 int r; 354 355 SPC_TRACE(("spc_init ")); 356 spc_reset(sc); 357 spc_scsi_reset(sc); 358 spc_reset(sc); 359 360 if (sc->sc_state == SPC_INIT) { 361 /* First time through; initialize. */ 362 TAILQ_INIT(&sc->ready_list); 363 TAILQ_INIT(&sc->nexus_list); 364 TAILQ_INIT(&sc->free_list); 365 sc->sc_nexus = NULL; 366 acb = sc->sc_acb; 367 memset(acb, 0, sizeof(sc->sc_acb)); 368 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 369 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 370 acb++; 371 } 372 memset(&sc->sc_tinfo, 0, sizeof(sc->sc_tinfo)); 373 } else { 374 /* Cancel any active commands. */ 375 sc->sc_state = SPC_CLEANING; 376 if ((acb = sc->sc_nexus) != NULL) { 377 acb->xs->error = XS_DRIVER_STUFFUP; 378 callout_stop(&acb->xs->xs_callout); 379 spc_done(sc, acb); 380 } 381 while ((acb = TAILQ_FIRST(&sc->nexus_list)) != NULL) { 382 acb->xs->error = XS_DRIVER_STUFFUP; 383 callout_stop(&acb->xs->xs_callout); 384 spc_done(sc, acb); 385 } 386 } 387 388 sc->sc_prevphase = PH_INVALID; 389 for (r = 0; r < 8; r++) { 390 struct spc_tinfo *ti = &sc->sc_tinfo[r]; 391 392 ti->flags = 0; 393 #if SPC_USE_SYNCHRONOUS 394 ti->flags |= DO_SYNC; 395 ti->period = sc->sc_minsync; 396 ti->offset = SPC_SYNC_REQ_ACK_OFS; 397 #else 398 ti->period = ti->offset = 0; 399 #endif 400 #if SPC_USE_WIDE 401 ti->flags |= DO_WIDE; 402 ti->width = SPC_MAX_WIDTH; 403 #else 404 ti->width = 0; 405 #endif 406 } 407 408 sc->sc_state = SPC_IDLE; 409 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SCTL, 410 bus_space_read_1(sc->sc_iot, sc->sc_ioh, SCTL) | SCTL_INTR_ENAB); 411 } 412 413 void 414 spc_free_acb(sc, acb, flags) 415 struct spc_softc *sc; 416 struct spc_acb *acb; 417 int flags; 418 { 419 int s; 420 421 SPC_TRACE(("spc_free_acb ")); 422 s = splbio(); 423 424 acb->flags = 0; 425 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 426 splx(s); 427 } 428 429 struct spc_acb * 430 spc_get_acb(sc) 431 struct spc_softc *sc; 432 { 433 struct spc_acb *acb; 434 int s; 435 436 SPC_TRACE(("spc_get_acb ")); 437 s = splbio(); 438 acb = TAILQ_FIRST(&sc->free_list); 439 if (acb != NULL) { 440 TAILQ_REMOVE(&sc->free_list, acb, chain); 441 acb->flags |= ACB_ALLOC; 442 } 443 splx(s); 444 return acb; 445 } 446 447 /* 448 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 449 */ 450 451 /* 452 * Expected sequence: 453 * 1) Command inserted into ready list 454 * 2) Command selected for execution 455 * 3) Command won arbitration and has selected target device 456 * 4) Send message out (identify message, eventually also sync.negotiations) 457 * 5) Send command 458 * 5a) Receive disconnect message, disconnect. 459 * 5b) Reselected by target 460 * 5c) Receive identify message from target. 461 * 6) Send or receive data 462 * 7) Receive status 463 * 8) Receive message (command complete etc.) 464 */ 465 466 /* 467 * Start a SCSI-command 468 * This function is called by the higher level SCSI-driver to queue/run 469 * SCSI-commands. 470 */ 471 void 472 spc_scsipi_request(chan, req, arg) 473 struct scsipi_channel *chan; 474 scsipi_adapter_req_t req; 475 void *arg; 476 { 477 struct scsipi_xfer *xs; 478 struct scsipi_periph *periph; 479 struct spc_softc *sc = (void *)chan->chan_adapter->adapt_dev; 480 struct spc_acb *acb; 481 int s, flags; 482 483 switch (req) { 484 case ADAPTER_REQ_RUN_XFER: 485 xs = arg; 486 periph = xs->xs_periph; 487 SPC_TRACE(("spc_scsipi_request ")); 488 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 489 periph->periph_target)); 490 491 flags = xs->xs_control; 492 if ((acb = spc_get_acb(sc)) == NULL) { 493 xs->error = XS_DRIVER_STUFFUP; 494 scsipi_done(xs); 495 return; 496 } 497 498 /* Initialize acb */ 499 acb->xs = xs; 500 acb->timeout = xs->timeout; 501 502 if (xs->xs_control & XS_CTL_RESET) { 503 acb->flags |= ACB_RESET; 504 acb->scsipi_cmd_length = 0; 505 acb->data_length = 0; 506 } else { 507 memcpy(&acb->scsipi_cmd, xs->cmd, xs->cmdlen); 508 #if 1 509 acb->scsipi_cmd.bytes[0] |= periph->periph_lun << 5; /* XXX? */ 510 #endif 511 acb->scsipi_cmd_length = xs->cmdlen; 512 acb->data_addr = xs->data; 513 acb->data_length = xs->datalen; 514 } 515 acb->target_stat = 0; 516 517 s = splbio(); 518 519 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 520 /* 521 * Start scheduling unless a queue process is in progress. 522 */ 523 if (sc->sc_state == SPC_IDLE) 524 spc_sched(sc); 525 /* 526 * After successful sending, check if we should return just now. 527 * If so, return SUCCESSFULLY_QUEUED. 528 */ 529 530 splx(s); 531 532 if ((flags & XS_CTL_POLL) == 0) 533 return; 534 535 /* Not allowed to use interrupts, use polling instead */ 536 s = splbio(); 537 if (spc_poll(sc, xs, acb->timeout)) { 538 spc_timeout(acb); 539 if (spc_poll(sc, xs, acb->timeout)) 540 spc_timeout(acb); 541 } 542 splx(s); 543 return; 544 case ADAPTER_REQ_GROW_RESOURCES: 545 /* XXX Not supported. */ 546 return; 547 case ADAPTER_REQ_SET_XFER_MODE: 548 /* XXX Not supported. */ 549 return; 550 } 551 } 552 553 /* 554 * Adjust transfer size in buffer structure 555 */ 556 void 557 spc_minphys(bp) 558 struct buf *bp; 559 { 560 561 SPC_TRACE(("spc_minphys ")); 562 minphys(bp); 563 } 564 565 /* 566 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 567 */ 568 int 569 spc_poll(sc, xs, count) 570 struct spc_softc *sc; 571 struct scsipi_xfer *xs; 572 int count; 573 { 574 bus_space_tag_t iot = sc->sc_iot; 575 bus_space_handle_t ioh = sc->sc_ioh; 576 577 SPC_TRACE(("spc_poll ")); 578 while (count) { 579 /* 580 * If we had interrupts enabled, would we 581 * have got an interrupt? 582 */ 583 if (bus_space_read_1(iot, ioh, INTS) != 0) 584 spcintr(sc); 585 if ((xs->xs_status & XS_STS_DONE) != 0) 586 return 0; 587 delay(1000); 588 count--; 589 } 590 return 1; 591 } 592 593 /* 594 * LOW LEVEL SCSI UTILITIES 595 */ 596 597 integrate void 598 spc_sched_msgout(sc, m) 599 struct spc_softc *sc; 600 u_char m; 601 { 602 bus_space_tag_t iot = sc->sc_iot; 603 bus_space_handle_t ioh = sc->sc_ioh; 604 605 SPC_TRACE(("spc_sched_msgout ")); 606 if (sc->sc_msgpriq == 0) 607 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN); 608 sc->sc_msgpriq |= m; 609 } 610 611 /* 612 * Set synchronous transfer offset and period. 613 */ 614 integrate void 615 spc_setsync(sc, ti) 616 struct spc_softc *sc; 617 struct spc_tinfo *ti; 618 { 619 #if SPC_USE_SYNCHRONOUS 620 bus_space_tag_t iot = sc->sc_iot; 621 bus_space_handle_t ioh = sc->sc_ioh; 622 623 SPC_TRACE(("spc_setsync ")); 624 if (ti->offset != 0) 625 bus_space_write_1(iot, ioh, TMOD, 626 ((ti->period * sc->sc_freq) / 250 - 2) << 4 | ti->offset); 627 else 628 bus_space_write_1(iot, ioh, TMOD, 0); 629 #endif 630 } 631 632 /* 633 * Start a selection. This is used by spc_sched() to select an idle target. 634 */ 635 void 636 spc_select(sc, acb) 637 struct spc_softc *sc; 638 struct spc_acb *acb; 639 { 640 struct scsipi_periph *periph = acb->xs->xs_periph; 641 int target = periph->periph_target; 642 struct spc_tinfo *ti = &sc->sc_tinfo[target]; 643 bus_space_tag_t iot = sc->sc_iot; 644 bus_space_handle_t ioh = sc->sc_ioh; 645 646 SPC_TRACE(("spc_select ")); 647 spc_setsync(sc, ti); 648 649 #if 0 650 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN); 651 #endif 652 #ifdef x68k /* XXX? */ 653 do { 654 asm ("nop"); 655 } while (bus_space_read_1(iot, ioh, SSTS) & 656 (SSTS_ACTIVE|SSTS_TARGET|SSTS_BUSY)); 657 #endif 658 659 bus_space_write_1(iot, ioh, PCTL, 0); 660 bus_space_write_1(iot, ioh, TEMP, 661 (1 << sc->sc_initiator) | (1 << target)); 662 /* 663 * Setup BSY timeout (selection timeout). 664 * 250ms according to the SCSI specification. 665 * T = (X * 256 + 15) * Tclf * 2 (Tclf = 200ns on x68k) 666 * To setup 256ms timeout, 667 * 128000ns/200ns = X * 256 + 15 668 * 640 - 15 = X * 256 669 * X = 625 / 256 670 * X = 2 + 113 / 256 671 * ==> tch = 2, tcm = 113 (correct?) 672 */ 673 bus_space_write_1(iot, ioh, TCH, 2); 674 bus_space_write_1(iot, ioh, TCM, 113); 675 /* Time to the information transfer phase start. */ 676 bus_space_write_1(iot, ioh, TCL, 3); 677 bus_space_write_1(iot, ioh, SCMD, SCMD_SELECT); 678 679 sc->sc_state = SPC_SELECTING; 680 } 681 682 int 683 spc_reselect(sc, message) 684 struct spc_softc *sc; 685 int message; 686 { 687 u_char selid, target, lun; 688 struct spc_acb *acb; 689 struct scsipi_periph *periph; 690 struct spc_tinfo *ti; 691 692 SPC_TRACE(("spc_reselect ")); 693 /* 694 * The SCSI chip made a snapshot of the data bus while the reselection 695 * was being negotiated. This enables us to determine which target did 696 * the reselect. 697 */ 698 selid = sc->sc_selid & ~(1 << sc->sc_initiator); 699 if (selid & (selid - 1)) { 700 printf("%s: reselect with invalid selid %02x; " 701 "sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 702 SPC_BREAK(); 703 goto reset; 704 } 705 706 /* 707 * Search wait queue for disconnected cmd 708 * The list should be short, so I haven't bothered with 709 * any more sophisticated structures than a simple 710 * singly linked list. 711 */ 712 target = ffs(selid) - 1; 713 lun = message & 0x07; 714 TAILQ_FOREACH(acb, &sc->nexus_list, chain) { 715 periph = acb->xs->xs_periph; 716 if (periph->periph_target == target && 717 periph->periph_lun == lun) 718 break; 719 } 720 if (acb == NULL) { 721 printf("%s: reselect from target %d lun %d with no nexus; " 722 "sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 723 SPC_BREAK(); 724 goto abort; 725 } 726 727 /* Make this nexus active again. */ 728 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 729 sc->sc_state = SPC_CONNECTED; 730 sc->sc_nexus = acb; 731 ti = &sc->sc_tinfo[target]; 732 ti->lubusy |= (1 << lun); 733 spc_setsync(sc, ti); 734 735 if (acb->flags & ACB_RESET) 736 spc_sched_msgout(sc, SEND_DEV_RESET); 737 else if (acb->flags & ACB_ABORT) 738 spc_sched_msgout(sc, SEND_ABORT); 739 740 /* Do an implicit RESTORE POINTERS. */ 741 sc->sc_dp = acb->data_addr; 742 sc->sc_dleft = acb->data_length; 743 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 744 sc->sc_cleft = acb->scsipi_cmd_length; 745 746 return (0); 747 748 reset: 749 spc_sched_msgout(sc, SEND_DEV_RESET); 750 return (1); 751 752 abort: 753 spc_sched_msgout(sc, SEND_ABORT); 754 return (1); 755 } 756 757 /* 758 * Schedule a SCSI operation. This has now been pulled out of the interrupt 759 * handler so that we may call it from spc_scsi_cmd and spc_done. This may 760 * save us an unecessary interrupt just to get things going. Should only be 761 * called when state == SPC_IDLE and at bio pl. 762 */ 763 void 764 spc_sched(sc) 765 struct spc_softc *sc; 766 { 767 struct spc_acb *acb; 768 struct scsipi_periph *periph; 769 struct spc_tinfo *ti; 770 771 /* missing the hw, just return and wait for our hw */ 772 if (sc->sc_flags & SPC_INACTIVE) 773 return; 774 SPC_TRACE(("spc_sched ")); 775 /* 776 * Find first acb in ready queue that is for a target/lunit pair that 777 * is not busy. 778 */ 779 TAILQ_FOREACH(acb, &sc->ready_list, chain) { 780 periph = acb->xs->xs_periph; 781 ti = &sc->sc_tinfo[periph->periph_target]; 782 if ((ti->lubusy & (1 << periph->periph_lun)) == 0) { 783 SPC_MISC(("selecting %d:%d ", 784 periph->periph_target, periph->periph_lun)); 785 TAILQ_REMOVE(&sc->ready_list, acb, chain); 786 sc->sc_nexus = acb; 787 spc_select(sc, acb); 788 return; 789 } else 790 SPC_MISC(("%d:%d busy\n", 791 periph->periph_target, periph->periph_lun)); 792 } 793 SPC_MISC(("idle ")); 794 /* Nothing to start; just enable reselections and wait. */ 795 } 796 797 /* 798 * POST PROCESSING OF SCSI_CMD (usually current) 799 */ 800 void 801 spc_done(sc, acb) 802 struct spc_softc *sc; 803 struct spc_acb *acb; 804 { 805 struct scsipi_xfer *xs = acb->xs; 806 struct scsipi_periph *periph = xs->xs_periph; 807 struct spc_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 808 809 SPC_TRACE(("spc_done ")); 810 811 if (xs->error == XS_NOERROR) { 812 if (acb->flags & ACB_ABORT) { 813 xs->error = XS_DRIVER_STUFFUP; 814 } else { 815 switch (acb->target_stat) { 816 case SCSI_CHECK: 817 /* First, save the return values */ 818 xs->resid = acb->data_length; 819 /* FALLBACK */ 820 case SCSI_BUSY: 821 xs->status = acb->target_stat; 822 xs->error = XS_BUSY; 823 break; 824 case SCSI_OK: 825 xs->resid = acb->data_length; 826 break; 827 default: 828 xs->error = XS_DRIVER_STUFFUP; 829 #if SPC_DEBUG 830 printf("%s: spc_done: bad stat 0x%x\n", 831 sc->sc_dev.dv_xname, acb->target_stat); 832 #endif 833 break; 834 } 835 } 836 } 837 838 #if SPC_DEBUG 839 if ((spc_debug & SPC_SHOWMISC) != 0) { 840 if (xs->resid != 0) 841 printf("resid=%d ", xs->resid); 842 else 843 printf("error=%d\n", xs->error); 844 } 845 #endif 846 847 /* 848 * Remove the ACB from whatever queue it happens to be on. 849 */ 850 if (acb->flags & ACB_NEXUS) 851 ti->lubusy &= ~(1 << periph->periph_lun); 852 if (acb == sc->sc_nexus) { 853 sc->sc_nexus = NULL; 854 sc->sc_state = SPC_IDLE; 855 spc_sched(sc); 856 } else 857 spc_dequeue(sc, acb); 858 859 spc_free_acb(sc, acb, xs->xs_control); 860 ti->cmds++; 861 scsipi_done(xs); 862 } 863 864 void 865 spc_dequeue(sc, acb) 866 struct spc_softc *sc; 867 struct spc_acb *acb; 868 { 869 870 SPC_TRACE(("spc_dequeue ")); 871 if (acb->flags & ACB_NEXUS) 872 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 873 else 874 TAILQ_REMOVE(&sc->ready_list, acb, chain); 875 } 876 877 /* 878 * INTERRUPT/PROTOCOL ENGINE 879 */ 880 881 /* 882 * Precondition: 883 * The SCSI bus is already in the MSGI phase and there is a message byte 884 * on the bus, along with an asserted REQ signal. 885 */ 886 void 887 spc_msgin(sc) 888 struct spc_softc *sc; 889 { 890 bus_space_tag_t iot = sc->sc_iot; 891 bus_space_handle_t ioh = sc->sc_ioh; 892 int n; 893 894 SPC_TRACE(("spc_msgin ")); 895 896 if (sc->sc_prevphase == PH_MSGIN) { 897 /* This is a continuation of the previous message. */ 898 n = sc->sc_imp - sc->sc_imess; 899 goto nextbyte; 900 } 901 902 /* This is a new MESSAGE IN phase. Clean up our state. */ 903 sc->sc_flags &= ~SPC_DROP_MSGIN; 904 905 nextmsg: 906 n = 0; 907 sc->sc_imp = &sc->sc_imess[n]; 908 909 nextbyte: 910 /* 911 * Read a whole message, but don't ack the last byte. If we reject the 912 * message, we have to assert ATN during the message transfer phase 913 * itself. 914 */ 915 for (;;) { 916 #if 0 917 for (;;) { 918 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0) 919 break; 920 /* Wait for REQINIT. XXX Need timeout. */ 921 } 922 #endif 923 if (bus_space_read_1(iot, ioh, INTS) != 0) { 924 /* 925 * Target left MESSAGE IN, probably because it 926 * a) noticed our ATN signal, or 927 * b) ran out of messages. 928 */ 929 goto out; 930 } 931 932 /* If parity error, just dump everything on the floor. */ 933 if ((bus_space_read_1(iot, ioh, SERR) & 934 (SERR_SCSI_PAR|SERR_SPC_PAR)) != 0) { 935 sc->sc_flags |= SPC_DROP_MSGIN; 936 spc_sched_msgout(sc, SEND_PARITY_ERROR); 937 } 938 939 /* send TRANSFER command. */ 940 bus_space_write_1(iot, ioh, TCH, 0); 941 bus_space_write_1(iot, ioh, TCM, 0); 942 bus_space_write_1(iot, ioh, TCL, 1); 943 bus_space_write_1(iot, ioh, PCTL, 944 sc->sc_phase | PCTL_BFINT_ENAB); 945 #ifdef x68k 946 bus_space_write_1(iot, ioh, SCMD, 947 SCMD_XFR /* | SCMD_PROG_XFR */); 948 #else 949 bus_space_write_1(iot, ioh, SCMD, 950 SCMD_XFR | SCMD_PROG_XFR); /* XXX */ 951 #endif 952 for (;;) { 953 #if 0 954 if ((bus_space_read_1(iot, ioh, SSTS) & 955 SSTS_BUSY) != 0 && 956 (bus_space_read_1(iot, ioh, SSTS) & 957 SSTS_DREG_EMPTY) != 0) 958 #endif 959 if ((bus_space_read_1(iot, ioh, SSTS) & 960 SSTS_DREG_EMPTY) == 0) 961 break; 962 if (bus_space_read_1(iot, ioh, INTS) != 0) 963 goto out; 964 } 965 966 /* Gather incoming message bytes if needed. */ 967 if ((sc->sc_flags & SPC_DROP_MSGIN) == 0) { 968 if (n >= SPC_MAX_MSG_LEN) { 969 (void) bus_space_read_1(iot, ioh, DREG); 970 sc->sc_flags |= SPC_DROP_MSGIN; 971 spc_sched_msgout(sc, SEND_REJECT); 972 } else { 973 *sc->sc_imp++ = 974 bus_space_read_1(iot, ioh, DREG); 975 n++; 976 /* 977 * This testing is suboptimal, but most 978 * messages will be of the one byte variety, so 979 * it should not affect performance 980 * significantly. 981 */ 982 if (n == 1 && MSG_IS1BYTE(sc->sc_imess[0])) 983 break; 984 if (n == 2 && MSG_IS2BYTE(sc->sc_imess[0])) 985 break; 986 if (n >= 3 && MSG_ISEXTENDED(sc->sc_imess[0]) && 987 n == sc->sc_imess[1] + 2) 988 break; 989 } 990 } else 991 (void) bus_space_read_1(iot, ioh, DREG); 992 993 /* 994 * If we reach this spot we're either: 995 * a) in the middle of a multi-byte message, or 996 * b) dropping bytes. 997 */ 998 #if 0 999 /* Ack the last byte read. */ 1000 /*(void) bus_space_read_1(iot, ioh, DREG);*/ 1001 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0) 1002 ; 1003 #endif 1004 } 1005 1006 SPC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1007 1008 /* We now have a complete message. Parse it. */ 1009 switch (sc->sc_state) { 1010 struct spc_acb *acb; 1011 struct scsipi_periph *periph; 1012 struct spc_tinfo *ti; 1013 1014 case SPC_CONNECTED: 1015 SPC_ASSERT(sc->sc_nexus != NULL); 1016 acb = sc->sc_nexus; 1017 ti = &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 1018 1019 switch (sc->sc_imess[0]) { 1020 case MSG_CMDCOMPLETE: 1021 if (sc->sc_dleft < 0) { 1022 periph = acb->xs->xs_periph; 1023 printf("%s: %d extra bytes from %d:%d\n", 1024 sc->sc_dev.dv_xname, -sc->sc_dleft, 1025 periph->periph_target, periph->periph_lun); 1026 acb->data_length = 0; 1027 } 1028 acb->xs->resid = acb->data_length = sc->sc_dleft; 1029 sc->sc_state = SPC_CMDCOMPLETE; 1030 break; 1031 1032 case MSG_PARITY_ERROR: 1033 /* Resend the last message. */ 1034 spc_sched_msgout(sc, sc->sc_lastmsg); 1035 break; 1036 1037 case MSG_MESSAGE_REJECT: 1038 SPC_MISC(("message rejected %02x ", sc->sc_lastmsg)); 1039 switch (sc->sc_lastmsg) { 1040 #if SPC_USE_SYNCHRONOUS + SPC_USE_WIDE 1041 case SEND_IDENTIFY: 1042 ti->flags &= ~(DO_SYNC | DO_WIDE); 1043 ti->period = ti->offset = 0; 1044 spc_setsync(sc, ti); 1045 ti->width = 0; 1046 break; 1047 #endif 1048 #if SPC_USE_SYNCHRONOUS 1049 case SEND_SDTR: 1050 ti->flags &= ~DO_SYNC; 1051 ti->period = ti->offset = 0; 1052 spc_setsync(sc, ti); 1053 break; 1054 #endif 1055 #if SPC_USE_WIDE 1056 case SEND_WDTR: 1057 ti->flags &= ~DO_WIDE; 1058 ti->width = 0; 1059 break; 1060 #endif 1061 case SEND_INIT_DET_ERR: 1062 spc_sched_msgout(sc, SEND_ABORT); 1063 break; 1064 } 1065 break; 1066 1067 case MSG_NOOP: 1068 break; 1069 1070 case MSG_DISCONNECT: 1071 ti->dconns++; 1072 sc->sc_state = SPC_DISCONNECT; 1073 break; 1074 1075 case MSG_SAVEDATAPOINTER: 1076 acb->data_addr = sc->sc_dp; 1077 acb->data_length = sc->sc_dleft; 1078 break; 1079 1080 case MSG_RESTOREPOINTERS: 1081 sc->sc_dp = acb->data_addr; 1082 sc->sc_dleft = acb->data_length; 1083 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 1084 sc->sc_cleft = acb->scsipi_cmd_length; 1085 break; 1086 1087 case MSG_EXTENDED: 1088 switch (sc->sc_imess[2]) { 1089 #if SPC_USE_SYNCHRONOUS 1090 case MSG_EXT_SDTR: 1091 if (sc->sc_imess[1] != 3) 1092 goto reject; 1093 ti->period = sc->sc_imess[3]; 1094 ti->offset = sc->sc_imess[4]; 1095 ti->flags &= ~DO_SYNC; 1096 if (ti->offset == 0) { 1097 } else if (ti->period < sc->sc_minsync || 1098 ti->period > sc->sc_maxsync || 1099 ti->offset > 8) { 1100 ti->period = ti->offset = 0; 1101 spc_sched_msgout(sc, SEND_SDTR); 1102 } else { 1103 scsipi_printaddr(acb->xs->xs_periph); 1104 printf("sync, offset %d, " 1105 "period %dnsec\n", 1106 ti->offset, ti->period * 4); 1107 } 1108 spc_setsync(sc, ti); 1109 break; 1110 #endif 1111 1112 #if SPC_USE_WIDE 1113 case MSG_EXT_WDTR: 1114 if (sc->sc_imess[1] != 2) 1115 goto reject; 1116 ti->width = sc->sc_imess[3]; 1117 ti->flags &= ~DO_WIDE; 1118 if (ti->width == 0) { 1119 } else if (ti->width > SPC_MAX_WIDTH) { 1120 ti->width = 0; 1121 spc_sched_msgout(sc, SEND_WDTR); 1122 } else { 1123 scsipi_printaddr(acb->xs->xs_periph); 1124 printf("wide, width %d\n", 1125 1 << (3 + ti->width)); 1126 } 1127 break; 1128 #endif 1129 1130 default: 1131 printf("%s: unrecognized MESSAGE EXTENDED; " 1132 "sending REJECT\n", sc->sc_dev.dv_xname); 1133 SPC_BREAK(); 1134 goto reject; 1135 } 1136 break; 1137 1138 default: 1139 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1140 sc->sc_dev.dv_xname); 1141 SPC_BREAK(); 1142 reject: 1143 spc_sched_msgout(sc, SEND_REJECT); 1144 break; 1145 } 1146 break; 1147 1148 case SPC_RESELECTED: 1149 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1150 printf("%s: reselect without IDENTIFY; " 1151 "sending DEVICE RESET\n", sc->sc_dev.dv_xname); 1152 SPC_BREAK(); 1153 goto reset; 1154 } 1155 1156 (void) spc_reselect(sc, sc->sc_imess[0]); 1157 break; 1158 1159 default: 1160 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1161 sc->sc_dev.dv_xname); 1162 SPC_BREAK(); 1163 reset: 1164 spc_sched_msgout(sc, SEND_DEV_RESET); 1165 break; 1166 1167 #ifdef notdef 1168 abort: 1169 spc_sched_msgout(sc, SEND_ABORT); 1170 break; 1171 #endif 1172 } 1173 1174 /* Ack the last message byte. */ 1175 #if 0 /* XXX? */ 1176 (void) bus_space_read_1(iot, ioh, DREG); 1177 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0) 1178 ; 1179 #endif 1180 1181 /* Go get the next message, if any. */ 1182 goto nextmsg; 1183 1184 out: 1185 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK); 1186 SPC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1187 } 1188 1189 /* 1190 * Send the highest priority, scheduled message. 1191 */ 1192 void 1193 spc_msgout(sc) 1194 struct spc_softc *sc; 1195 { 1196 bus_space_tag_t iot = sc->sc_iot; 1197 bus_space_handle_t ioh = sc->sc_ioh; 1198 #if SPC_USE_SYNCHRONOUS 1199 struct spc_tinfo *ti; 1200 #endif 1201 int n; 1202 1203 SPC_TRACE(("spc_msgout ")); 1204 1205 if (sc->sc_prevphase == PH_MSGOUT) { 1206 if (sc->sc_omp == sc->sc_omess) { 1207 /* 1208 * This is a retransmission. 1209 * 1210 * We get here if the target stayed in MESSAGE OUT 1211 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1212 * that all of the previously transmitted messages must 1213 * be sent again, in the same order. Therefore, we 1214 * requeue all the previously transmitted messages, and 1215 * start again from the top. Our simple priority 1216 * scheme keeps the messages in the right order. 1217 */ 1218 SPC_MISC(("retransmitting ")); 1219 sc->sc_msgpriq |= sc->sc_msgoutq; 1220 /* 1221 * Set ATN. If we're just sending a trivial 1-byte 1222 * message, we'll clear ATN later on anyway. 1223 */ 1224 bus_space_write_1(iot, ioh, SCMD, 1225 SCMD_SET_ATN); /* XXX? */ 1226 } else { 1227 /* This is a continuation of the previous message. */ 1228 n = sc->sc_omp - sc->sc_omess; 1229 goto nextbyte; 1230 } 1231 } 1232 1233 /* No messages transmitted so far. */ 1234 sc->sc_msgoutq = 0; 1235 sc->sc_lastmsg = 0; 1236 1237 nextmsg: 1238 /* Pick up highest priority message. */ 1239 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1240 sc->sc_msgpriq &= ~sc->sc_currmsg; 1241 sc->sc_msgoutq |= sc->sc_currmsg; 1242 1243 /* Build the outgoing message data. */ 1244 switch (sc->sc_currmsg) { 1245 case SEND_IDENTIFY: 1246 SPC_ASSERT(sc->sc_nexus != NULL); 1247 sc->sc_omess[0] = 1248 MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1); 1249 n = 1; 1250 break; 1251 1252 #if SPC_USE_SYNCHRONOUS 1253 case SEND_SDTR: 1254 SPC_ASSERT(sc->sc_nexus != NULL); 1255 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1256 sc->sc_omess[4] = MSG_EXTENDED; 1257 sc->sc_omess[3] = MSG_EXT_SDTR_LEN; 1258 sc->sc_omess[2] = MSG_EXT_SDTR; 1259 sc->sc_omess[1] = ti->period >> 2; 1260 sc->sc_omess[0] = ti->offset; 1261 n = 5; 1262 break; 1263 #endif 1264 1265 #if SPC_USE_WIDE 1266 case SEND_WDTR: 1267 SPC_ASSERT(sc->sc_nexus != NULL); 1268 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1269 sc->sc_omess[3] = MSG_EXTENDED; 1270 sc->sc_omess[2] = MSG_EXT_WDTR_LEN; 1271 sc->sc_omess[1] = MSG_EXT_WDTR; 1272 sc->sc_omess[0] = ti->width; 1273 n = 4; 1274 break; 1275 #endif 1276 1277 case SEND_DEV_RESET: 1278 sc->sc_flags |= SPC_ABORTING; 1279 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1280 n = 1; 1281 break; 1282 1283 case SEND_REJECT: 1284 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1285 n = 1; 1286 break; 1287 1288 case SEND_PARITY_ERROR: 1289 sc->sc_omess[0] = MSG_PARITY_ERROR; 1290 n = 1; 1291 break; 1292 1293 case SEND_INIT_DET_ERR: 1294 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1295 n = 1; 1296 break; 1297 1298 case SEND_ABORT: 1299 sc->sc_flags |= SPC_ABORTING; 1300 sc->sc_omess[0] = MSG_ABORT; 1301 n = 1; 1302 break; 1303 1304 default: 1305 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1306 sc->sc_dev.dv_xname); 1307 SPC_BREAK(); 1308 sc->sc_omess[0] = MSG_NOOP; 1309 n = 1; 1310 break; 1311 } 1312 sc->sc_omp = &sc->sc_omess[n]; 1313 1314 nextbyte: 1315 /* Send message bytes. */ 1316 /* send TRANSFER command. */ 1317 bus_space_write_1(iot, ioh, TCH, n >> 16); 1318 bus_space_write_1(iot, ioh, TCM, n >> 8); 1319 bus_space_write_1(iot, ioh, TCL, n); 1320 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB); 1321 #ifdef x68k 1322 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */ 1323 #else 1324 bus_space_write_1(iot, ioh, SCMD, 1325 SCMD_XFR | SCMD_PROG_XFR | SCMD_ICPT_XFR); 1326 #endif 1327 for (;;) { 1328 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0) 1329 break; 1330 if (bus_space_read_1(iot, ioh, INTS) != 0) 1331 goto out; 1332 } 1333 for (;;) { 1334 #if 0 1335 for (;;) { 1336 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0) 1337 break; 1338 /* Wait for REQINIT. XXX Need timeout. */ 1339 } 1340 #endif 1341 if (bus_space_read_1(iot, ioh, INTS) != 0) { 1342 /* 1343 * Target left MESSAGE OUT, possibly to reject 1344 * our message. 1345 * 1346 * If this is the last message being sent, then we 1347 * deassert ATN, since either the target is going to 1348 * ignore this message, or it's going to ask for a 1349 * retransmission via MESSAGE PARITY ERROR (in which 1350 * case we reassert ATN anyway). 1351 */ 1352 #if 0 1353 if (sc->sc_msgpriq == 0) 1354 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN); 1355 #endif 1356 goto out; 1357 } 1358 1359 #if 0 1360 /* Clear ATN before last byte if this is the last message. */ 1361 if (n == 1 && sc->sc_msgpriq == 0) 1362 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN); 1363 #endif 1364 1365 while ((bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_FULL) != 0) 1366 ; 1367 /* Send message byte. */ 1368 bus_space_write_1(iot, ioh, DREG, *--sc->sc_omp); 1369 --n; 1370 /* Keep track of the last message we've sent any bytes of. */ 1371 sc->sc_lastmsg = sc->sc_currmsg; 1372 #if 0 1373 /* Wait for ACK to be negated. XXX Need timeout. */ 1374 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0) 1375 ; 1376 #endif 1377 1378 if (n == 0) 1379 break; 1380 } 1381 1382 /* We get here only if the entire message has been transmitted. */ 1383 if (sc->sc_msgpriq != 0) { 1384 /* There are more outgoing messages. */ 1385 goto nextmsg; 1386 } 1387 1388 /* 1389 * The last message has been transmitted. We need to remember the last 1390 * message transmitted (in case the target switches to MESSAGE IN phase 1391 * and sends a MESSAGE REJECT), and the list of messages transmitted 1392 * this time around (in case the target stays in MESSAGE OUT phase to 1393 * request a retransmit). 1394 */ 1395 1396 out: 1397 /* Disable REQ/ACK protocol. */ 1398 return; 1399 } 1400 1401 /* 1402 * spc_dataout_pio: perform a data transfer using the FIFO datapath in the spc 1403 * Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted 1404 * and ACK deasserted (i.e. waiting for a data byte) 1405 * 1406 * This new revision has been optimized (I tried) to make the common case fast, 1407 * and the rarer cases (as a result) somewhat more comlex 1408 */ 1409 int 1410 spc_dataout_pio(sc, p, n) 1411 struct spc_softc *sc; 1412 u_char *p; 1413 int n; 1414 { 1415 bus_space_tag_t iot = sc->sc_iot; 1416 bus_space_handle_t ioh = sc->sc_ioh; 1417 u_char intstat = 0; 1418 int out = 0; 1419 #define DOUTAMOUNT 8 /* Full FIFO */ 1420 1421 SPC_TRACE(("spc_dataout_pio ")); 1422 /* send TRANSFER command. */ 1423 bus_space_write_1(iot, ioh, TCH, n >> 16); 1424 bus_space_write_1(iot, ioh, TCM, n >> 8); 1425 bus_space_write_1(iot, ioh, TCL, n); 1426 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB); 1427 #ifdef x68k 1428 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */ 1429 #else 1430 bus_space_write_1(iot, ioh, SCMD, 1431 SCMD_XFR | SCMD_PROG_XFR | SCMD_ICPT_XFR); /* XXX */ 1432 #endif 1433 for (;;) { 1434 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0) 1435 break; 1436 if (bus_space_read_1(iot, ioh, INTS) != 0) 1437 break; 1438 } 1439 1440 /* 1441 * I have tried to make the main loop as tight as possible. This 1442 * means that some of the code following the loop is a bit more 1443 * complex than otherwise. 1444 */ 1445 while (n > 0) { 1446 int xfer; 1447 1448 for (;;) { 1449 intstat = bus_space_read_1(iot, ioh, INTS); 1450 /* Wait till buffer is empty. */ 1451 if ((bus_space_read_1(iot, ioh, SSTS) & 1452 SSTS_DREG_EMPTY) != 0) 1453 break; 1454 /* Break on interrupt. */ 1455 if (intstat != 0) 1456 goto phasechange; 1457 } 1458 1459 xfer = min(DOUTAMOUNT, n); 1460 1461 SPC_MISC(("%d> ", xfer)); 1462 1463 n -= xfer; 1464 out += xfer; 1465 1466 while (xfer-- > 0) { 1467 bus_space_write_1(iot, ioh, DREG, *p++); 1468 } 1469 } 1470 1471 if (out == 0) { 1472 for (;;) { 1473 if (bus_space_read_1(iot, ioh, INTS) != 0) 1474 break; 1475 } 1476 SPC_MISC(("extra data ")); 1477 } else { 1478 /* See the bytes off chip */ 1479 for (;;) { 1480 /* Wait till buffer is empty. */ 1481 if ((bus_space_read_1(iot, ioh, SSTS) & 1482 SSTS_DREG_EMPTY) != 0) 1483 break; 1484 intstat = bus_space_read_1(iot, ioh, INTS); 1485 /* Break on interrupt. */ 1486 if (intstat != 0) 1487 goto phasechange; 1488 } 1489 } 1490 1491 phasechange: 1492 /* Stop the FIFO data path. */ 1493 1494 if (intstat != 0) { 1495 /* Some sort of phase change. */ 1496 int amount; 1497 1498 amount = (bus_space_read_1(iot, ioh, TCH) << 16) | 1499 (bus_space_read_1(iot, ioh, TCM) << 8) | 1500 bus_space_read_1(iot, ioh, TCL); 1501 if (amount > 0) { 1502 out -= amount; 1503 SPC_MISC(("+%d ", amount)); 1504 } 1505 } 1506 1507 /* Turn on ENREQINIT again. */ 1508 1509 return out; 1510 } 1511 1512 /* 1513 * spc_datain_pio: perform data transfers using the FIFO datapath in the spc 1514 * Precondition: The SCSI bus should be in the DIN phase, with REQ asserted 1515 * and ACK deasserted (i.e. at least one byte is ready). 1516 * 1517 * For now, uses a pretty dumb algorithm, hangs around until all data has been 1518 * transferred. This, is OK for fast targets, but not so smart for slow 1519 * targets which don't disconnect or for huge transfers. 1520 */ 1521 int 1522 spc_datain_pio(sc, p, n) 1523 struct spc_softc *sc; 1524 u_char *p; 1525 int n; 1526 { 1527 bus_space_tag_t iot = sc->sc_iot; 1528 bus_space_handle_t ioh = sc->sc_ioh; 1529 u_short intstat; 1530 int in = 0; 1531 #define DINAMOUNT 8 /* Full FIFO */ 1532 1533 SPC_TRACE(("spc_datain_pio ")); 1534 /* send TRANSFER command. */ 1535 bus_space_write_1(iot, ioh, TCH, n >> 16); 1536 bus_space_write_1(iot, ioh, TCM, n >> 8); 1537 bus_space_write_1(iot, ioh, TCL, n); 1538 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB); 1539 #ifdef x68k 1540 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */ 1541 #else 1542 bus_space_write_1(iot, ioh, SCMD, 1543 SCMD_XFR | SCMD_PROG_XFR); /* XXX */ 1544 #endif 1545 for (;;) { 1546 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0) 1547 break; 1548 if (bus_space_read_1(iot, ioh, INTS) != 0) 1549 goto phasechange; 1550 } 1551 1552 /* 1553 * We leave this loop if one or more of the following is true: 1554 * a) phase != PH_DATAIN && FIFOs are empty 1555 * b) reset has occurred or busfree is detected. 1556 */ 1557 while (n > 0) { 1558 int xfer; 1559 1560 #define INTSMASK 0xff 1561 /* Wait for fifo half full or phase mismatch */ 1562 for (;;) { 1563 intstat = (bus_space_read_1(iot, ioh, SSTS) << 8) | 1564 bus_space_read_1(iot, ioh, INTS); 1565 if ((intstat & (INTSMASK | (SSTS_DREG_FULL << 8))) != 1566 0) 1567 break; 1568 if ((intstat & (SSTS_DREG_EMPTY << 8)) == 0) 1569 break; 1570 } 1571 1572 #if 1 1573 if ((intstat & INTSMASK) != 0) 1574 goto phasechange; 1575 #else 1576 if ((intstat & INTSMASK) != 0 && 1577 (intstat & (SSTS_DREG_EMPTY << 8))) 1578 goto phasechange; 1579 #endif 1580 if ((intstat & (SSTS_DREG_FULL << 8)) != 0) 1581 xfer = min(DINAMOUNT, n); 1582 else 1583 xfer = min(1, n); 1584 1585 SPC_MISC((">%d ", xfer)); 1586 1587 n -= xfer; 1588 in += xfer; 1589 1590 while (xfer-- > 0) { 1591 *p++ = bus_space_read_1(iot, ioh, DREG); 1592 } 1593 1594 if ((intstat & INTSMASK) != 0) 1595 goto phasechange; 1596 } 1597 1598 /* 1599 * Some SCSI-devices are rude enough to transfer more data than what 1600 * was requested, e.g. 2048 bytes from a CD-ROM instead of the 1601 * requested 512. Test for progress, i.e. real transfers. If no real 1602 * transfers have been performed (n is probably already zero) and the 1603 * FIFO is not empty, waste some bytes.... 1604 */ 1605 if (in == 0) { 1606 for (;;) { 1607 if (bus_space_read_1(iot, ioh, INTS) != 0) 1608 break; 1609 } 1610 SPC_MISC(("extra data ")); 1611 } 1612 1613 phasechange: 1614 /* Stop the FIFO data path. */ 1615 1616 /* Turn on ENREQINIT again. */ 1617 1618 return in; 1619 } 1620 1621 /* 1622 * Catch an interrupt from the adaptor 1623 */ 1624 /* 1625 * This is the workhorse routine of the driver. 1626 * Deficiencies (for now): 1627 * 1) always uses programmed I/O 1628 */ 1629 int 1630 spcintr(arg) 1631 void *arg; 1632 { 1633 struct spc_softc *sc = arg; 1634 bus_space_tag_t iot = sc->sc_iot; 1635 bus_space_handle_t ioh = sc->sc_ioh; 1636 u_char ints; 1637 struct spc_acb *acb; 1638 struct scsipi_periph *periph; 1639 struct spc_tinfo *ti; 1640 int n; 1641 1642 /* 1643 * Disable interrupt. 1644 */ 1645 bus_space_write_1(iot, ioh, SCTL, 1646 bus_space_read_1(iot, ioh, SCTL) & ~SCTL_INTR_ENAB); 1647 1648 SPC_TRACE(("spcintr ")); 1649 1650 loop: 1651 /* 1652 * Loop until transfer completion. 1653 */ 1654 /* 1655 * First check for abnormal conditions, such as reset. 1656 */ 1657 #ifdef x68k /* XXX? */ 1658 while ((ints = bus_space_read_1(iot, ioh, INTS)) == 0) 1659 delay(1); 1660 SPC_MISC(("ints = 0x%x ", ints)); 1661 #else 1662 ints = bus_space_read_1(iot, ioh, INTS); 1663 SPC_MISC(("ints = 0x%x ", ints)); 1664 #endif 1665 1666 if ((ints & INTS_RST) != 0) { 1667 printf("%s: SCSI bus reset\n", sc->sc_dev.dv_xname); 1668 goto reset; 1669 } 1670 1671 /* 1672 * Check for less serious errors. 1673 */ 1674 if ((bus_space_read_1(iot, ioh, SERR) & (SERR_SCSI_PAR|SERR_SPC_PAR)) 1675 != 0) { 1676 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 1677 if (sc->sc_prevphase == PH_MSGIN) { 1678 sc->sc_flags |= SPC_DROP_MSGIN; 1679 spc_sched_msgout(sc, SEND_PARITY_ERROR); 1680 } else 1681 spc_sched_msgout(sc, SEND_INIT_DET_ERR); 1682 } 1683 1684 /* 1685 * If we're not already busy doing something test for the following 1686 * conditions: 1687 * 1) We have been reselected by something 1688 * 2) We have selected something successfully 1689 * 3) Our selection process has timed out 1690 * 4) This is really a bus free interrupt just to get a new command 1691 * going? 1692 * 5) Spurious interrupt? 1693 */ 1694 switch (sc->sc_state) { 1695 case SPC_IDLE: 1696 case SPC_SELECTING: 1697 SPC_MISC(("ints:0x%02x ", ints)); 1698 1699 if ((ints & INTS_SEL) != 0) { 1700 /* 1701 * We don't currently support target mode. 1702 */ 1703 printf("%s: target mode selected; going to BUS FREE\n", 1704 sc->sc_dev.dv_xname); 1705 1706 goto sched; 1707 } else if ((ints & INTS_RESEL) != 0) { 1708 SPC_MISC(("reselected ")); 1709 1710 /* 1711 * If we're trying to select a target ourselves, 1712 * push our command back into the ready list. 1713 */ 1714 if (sc->sc_state == SPC_SELECTING) { 1715 SPC_MISC(("backoff selector ")); 1716 SPC_ASSERT(sc->sc_nexus != NULL); 1717 acb = sc->sc_nexus; 1718 sc->sc_nexus = NULL; 1719 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 1720 } 1721 1722 /* Save reselection ID. */ 1723 sc->sc_selid = bus_space_read_1(iot, ioh, TEMP); 1724 1725 sc->sc_state = SPC_RESELECTED; 1726 } else if ((ints & INTS_CMD_DONE) != 0) { 1727 SPC_MISC(("selected ")); 1728 1729 /* 1730 * We have selected a target. Things to do: 1731 * a) Determine what message(s) to send. 1732 * b) Verify that we're still selecting the target. 1733 * c) Mark device as busy. 1734 */ 1735 if (sc->sc_state != SPC_SELECTING) { 1736 printf("%s: selection out while idle; " 1737 "resetting\n", sc->sc_dev.dv_xname); 1738 SPC_BREAK(); 1739 goto reset; 1740 } 1741 SPC_ASSERT(sc->sc_nexus != NULL); 1742 acb = sc->sc_nexus; 1743 periph = acb->xs->xs_periph; 1744 ti = &sc->sc_tinfo[periph->periph_target]; 1745 1746 sc->sc_msgpriq = SEND_IDENTIFY; 1747 if (acb->flags & ACB_RESET) 1748 sc->sc_msgpriq |= SEND_DEV_RESET; 1749 else if (acb->flags & ACB_ABORT) 1750 sc->sc_msgpriq |= SEND_ABORT; 1751 else { 1752 #if SPC_USE_SYNCHRONOUS 1753 if ((ti->flags & DO_SYNC) != 0) 1754 sc->sc_msgpriq |= SEND_SDTR; 1755 #endif 1756 #if SPC_USE_WIDE 1757 if ((ti->flags & DO_WIDE) != 0) 1758 sc->sc_msgpriq |= SEND_WDTR; 1759 #endif 1760 } 1761 1762 acb->flags |= ACB_NEXUS; 1763 ti->lubusy |= (1 << periph->periph_lun); 1764 1765 /* Do an implicit RESTORE POINTERS. */ 1766 sc->sc_dp = acb->data_addr; 1767 sc->sc_dleft = acb->data_length; 1768 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 1769 sc->sc_cleft = acb->scsipi_cmd_length; 1770 1771 /* On our first connection, schedule a timeout. */ 1772 if ((acb->xs->xs_control & XS_CTL_POLL) == 0) 1773 callout_reset(&acb->xs->xs_callout, 1774 mstohz(acb->timeout), spc_timeout, acb); 1775 1776 sc->sc_state = SPC_CONNECTED; 1777 } else if ((ints & INTS_TIMEOUT) != 0) { 1778 SPC_MISC(("selection timeout ")); 1779 1780 if (sc->sc_state != SPC_SELECTING) { 1781 printf("%s: selection timeout while idle; " 1782 "resetting\n", sc->sc_dev.dv_xname); 1783 SPC_BREAK(); 1784 goto reset; 1785 } 1786 SPC_ASSERT(sc->sc_nexus != NULL); 1787 acb = sc->sc_nexus; 1788 1789 delay(250); 1790 1791 acb->xs->error = XS_SELTIMEOUT; 1792 goto finish; 1793 } else { 1794 if (sc->sc_state != SPC_IDLE) { 1795 printf("%s: BUS FREE while not idle; " 1796 "state=%d\n", 1797 sc->sc_dev.dv_xname, sc->sc_state); 1798 SPC_BREAK(); 1799 goto out; 1800 } 1801 1802 goto sched; 1803 } 1804 1805 /* 1806 * Turn off selection stuff, and prepare to catch bus free 1807 * interrupts, parity errors, and phase changes. 1808 */ 1809 1810 sc->sc_flags = 0; 1811 sc->sc_prevphase = PH_INVALID; 1812 goto dophase; 1813 } 1814 1815 if ((ints & INTS_DISCON) != 0) { 1816 /* We've gone to BUS FREE phase. */ 1817 /* disable disconnect interrupt */ 1818 bus_space_write_1(iot, ioh, PCTL, 1819 bus_space_read_1(iot, ioh, PCTL) & ~PCTL_BFINT_ENAB); 1820 /* XXX reset interrput */ 1821 bus_space_write_1(iot, ioh, INTS, ints); 1822 1823 switch (sc->sc_state) { 1824 case SPC_RESELECTED: 1825 goto sched; 1826 1827 case SPC_CONNECTED: 1828 SPC_ASSERT(sc->sc_nexus != NULL); 1829 acb = sc->sc_nexus; 1830 1831 #if SPC_USE_SYNCHRONOUS + SPC_USE_WIDE 1832 if (sc->sc_prevphase == PH_MSGOUT) { 1833 /* 1834 * If the target went to BUS FREE phase during 1835 * or immediately after sending a SDTR or WDTR 1836 * message, disable negotiation. 1837 */ 1838 periph = acb->xs->xs_periph; 1839 ti = &sc->sc_tinfo[periph->periph_target]; 1840 switch (sc->sc_lastmsg) { 1841 #if SPC_USE_SYNCHRONOUS 1842 case SEND_SDTR: 1843 ti->flags &= ~DO_SYNC; 1844 ti->period = ti->offset = 0; 1845 break; 1846 #endif 1847 #if SPC_USE_WIDE 1848 case SEND_WDTR: 1849 ti->flags &= ~DO_WIDE; 1850 ti->width = 0; 1851 break; 1852 #endif 1853 } 1854 } 1855 #endif 1856 1857 if ((sc->sc_flags & SPC_ABORTING) == 0) { 1858 /* 1859 * Section 5.1.1 of the SCSI 2 spec suggests 1860 * issuing a REQUEST SENSE following an 1861 * unexpected disconnect. Some devices go into 1862 * a contingent allegiance condition when 1863 * disconnecting, and this is necessary to 1864 * clean up their state. 1865 */ 1866 printf("%s: unexpected disconnect; " 1867 "sending REQUEST SENSE\n", 1868 sc->sc_dev.dv_xname); 1869 SPC_BREAK(); 1870 acb->target_stat = SCSI_CHECK; 1871 acb->xs->error = XS_NOERROR; 1872 goto finish; 1873 } 1874 1875 acb->xs->error = XS_DRIVER_STUFFUP; 1876 goto finish; 1877 1878 case SPC_DISCONNECT: 1879 SPC_ASSERT(sc->sc_nexus != NULL); 1880 acb = sc->sc_nexus; 1881 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1882 sc->sc_nexus = NULL; 1883 goto sched; 1884 1885 case SPC_CMDCOMPLETE: 1886 SPC_ASSERT(sc->sc_nexus != NULL); 1887 acb = sc->sc_nexus; 1888 goto finish; 1889 } 1890 } 1891 else if ((ints & INTS_CMD_DONE) != 0 && 1892 sc->sc_prevphase == PH_MSGIN && 1893 sc->sc_state != SPC_CONNECTED) 1894 goto out; 1895 1896 dophase: 1897 #if 0 1898 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) { 1899 /* Wait for REQINIT. */ 1900 goto out; 1901 } 1902 #else 1903 bus_space_write_1(iot, ioh, INTS, ints); 1904 ints = 0; 1905 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) 1906 delay(1); /* need timeout XXX */ 1907 #endif 1908 1909 /* 1910 * State transition. 1911 */ 1912 sc->sc_phase = bus_space_read_1(iot, ioh, PSNS) & PH_MASK; 1913 #if 0 1914 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase); 1915 #endif 1916 1917 SPC_MISC(("phase=%d\n", sc->sc_phase)); 1918 switch (sc->sc_phase) { 1919 case PH_MSGOUT: 1920 if (sc->sc_state != SPC_CONNECTED && 1921 sc->sc_state != SPC_RESELECTED) 1922 break; 1923 spc_msgout(sc); 1924 sc->sc_prevphase = PH_MSGOUT; 1925 goto loop; 1926 1927 case PH_MSGIN: 1928 if (sc->sc_state != SPC_CONNECTED && 1929 sc->sc_state != SPC_RESELECTED) 1930 break; 1931 spc_msgin(sc); 1932 sc->sc_prevphase = PH_MSGIN; 1933 goto loop; 1934 1935 case PH_CMD: 1936 if (sc->sc_state != SPC_CONNECTED) 1937 break; 1938 #if SPC_DEBUG 1939 if ((spc_debug & SPC_SHOWMISC) != 0) { 1940 SPC_ASSERT(sc->sc_nexus != NULL); 1941 acb = sc->sc_nexus; 1942 printf("cmd=0x%02x+%d ", 1943 acb->scsipi_cmd.opcode, acb->scsipi_cmd_length - 1); 1944 } 1945 #endif 1946 n = spc_dataout_pio(sc, sc->sc_cp, sc->sc_cleft); 1947 sc->sc_cp += n; 1948 sc->sc_cleft -= n; 1949 sc->sc_prevphase = PH_CMD; 1950 goto loop; 1951 1952 case PH_DATAOUT: 1953 if (sc->sc_state != SPC_CONNECTED) 1954 break; 1955 SPC_MISC(("dataout dleft=%d ", sc->sc_dleft)); 1956 n = spc_dataout_pio(sc, sc->sc_dp, sc->sc_dleft); 1957 sc->sc_dp += n; 1958 sc->sc_dleft -= n; 1959 sc->sc_prevphase = PH_DATAOUT; 1960 goto loop; 1961 1962 case PH_DATAIN: 1963 if (sc->sc_state != SPC_CONNECTED) 1964 break; 1965 SPC_MISC(("datain ")); 1966 n = spc_datain_pio(sc, sc->sc_dp, sc->sc_dleft); 1967 sc->sc_dp += n; 1968 sc->sc_dleft -= n; 1969 sc->sc_prevphase = PH_DATAIN; 1970 goto loop; 1971 1972 case PH_STAT: 1973 if (sc->sc_state != SPC_CONNECTED) 1974 break; 1975 SPC_ASSERT(sc->sc_nexus != NULL); 1976 acb = sc->sc_nexus; 1977 #if 0 1978 acb->target_stat = bus_space_read_1(iot, ioh, DREG); 1979 #endif 1980 spc_datain_pio(sc, &acb->target_stat, 1); 1981 SPC_MISC(("target_stat=0x%02x ", acb->target_stat)); 1982 sc->sc_prevphase = PH_STAT; 1983 goto loop; 1984 } 1985 1986 printf("%s: unexpected bus phase; resetting\n", sc->sc_dev.dv_xname); 1987 SPC_BREAK(); 1988 reset: 1989 spc_init(sc); 1990 return 1; 1991 1992 finish: 1993 callout_stop(&acb->xs->xs_callout); 1994 bus_space_write_1(iot, ioh, INTS, ints); 1995 ints = 0; 1996 spc_done(sc, acb); 1997 goto out; 1998 1999 sched: 2000 sc->sc_state = SPC_IDLE; 2001 spc_sched(sc); 2002 goto out; 2003 2004 out: 2005 if (ints) 2006 bus_space_write_1(iot, ioh, INTS, ints); 2007 bus_space_write_1(iot, ioh, SCTL, 2008 bus_space_read_1(iot, ioh, SCTL) | SCTL_INTR_ENAB); 2009 return 1; 2010 } 2011 2012 void 2013 spc_abort(sc, acb) 2014 struct spc_softc *sc; 2015 struct spc_acb *acb; 2016 { 2017 2018 /* 2 secs for the abort */ 2019 acb->timeout = SPC_ABORT_TIMEOUT; 2020 acb->flags |= ACB_ABORT; 2021 2022 if (acb == sc->sc_nexus) { 2023 /* 2024 * If we're still selecting, the message will be scheduled 2025 * after selection is complete. 2026 */ 2027 if (sc->sc_state == SPC_CONNECTED) 2028 spc_sched_msgout(sc, SEND_ABORT); 2029 } else { 2030 spc_dequeue(sc, acb); 2031 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 2032 if (sc->sc_state == SPC_IDLE) 2033 spc_sched(sc); 2034 } 2035 } 2036 2037 void 2038 spc_timeout(arg) 2039 void *arg; 2040 { 2041 struct spc_acb *acb = arg; 2042 struct scsipi_xfer *xs = acb->xs; 2043 struct scsipi_periph *periph = xs->xs_periph; 2044 struct spc_softc *sc; 2045 int s; 2046 2047 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 2048 scsipi_printaddr(periph); 2049 printf("timed out"); 2050 2051 s = splbio(); 2052 2053 if (acb->flags & ACB_ABORT) { 2054 /* abort timed out */ 2055 printf(" AGAIN\n"); 2056 /* XXX Must reset! */ 2057 } else { 2058 /* abort the operation that has timed out */ 2059 printf("\n"); 2060 acb->xs->error = XS_TIMEOUT; 2061 spc_abort(sc, acb); 2062 } 2063 2064 splx(s); 2065 } 2066 2067 #ifdef SPC_DEBUG 2068 /* 2069 * The following functions are mostly used for debugging purposes, either 2070 * directly called from the driver or from the kernel debugger. 2071 */ 2072 2073 void 2074 spc_show_scsi_cmd(acb) 2075 struct spc_acb *acb; 2076 { 2077 u_char *b = (u_char *)&acb->scsipi_cmd; 2078 int i; 2079 2080 scsipi_printaddr(acb->xs->xs_periph); 2081 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2082 for (i = 0; i < acb->scsipi_cmd_length; i++) { 2083 if (i) 2084 printf(","); 2085 printf("%x", b[i]); 2086 } 2087 printf("\n"); 2088 } else 2089 printf("RESET\n"); 2090 } 2091 2092 void 2093 spc_print_acb(acb) 2094 struct spc_acb *acb; 2095 { 2096 2097 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags); 2098 printf(" dp=%p dleft=%d target_stat=%x\n", 2099 acb->data_addr, acb->data_length, acb->target_stat); 2100 spc_show_scsi_cmd(acb); 2101 } 2102 2103 void 2104 spc_print_active_acb() 2105 { 2106 struct spc_acb *acb; 2107 struct spc_softc *sc = spc_cd.cd_devs[0]; /* XXX */ 2108 2109 printf("ready list:\n"); 2110 TAILQ_FOREACH(acb, &sc->ready_list, chain) 2111 spc_print_acb(acb); 2112 printf("nexus:\n"); 2113 if (sc->sc_nexus != NULL) 2114 spc_print_acb(sc->sc_nexus); 2115 printf("nexus list:\n"); 2116 TAILQ_FOREACH(acb, &sc->nexus_list, chain) 2117 spc_print_acb(acb); 2118 } 2119 2120 void 2121 spc_dump89352(sc) 2122 struct spc_softc *sc; 2123 { 2124 bus_space_tag_t iot = sc->sc_iot; 2125 bus_space_handle_t ioh = sc->sc_ioh; 2126 2127 printf("mb89352: BDID=%x SCTL=%x SCMD=%x TMOD=%x\n", 2128 bus_space_read_1(iot, ioh, BDID), 2129 bus_space_read_1(iot, ioh, SCTL), 2130 bus_space_read_1(iot, ioh, SCMD), 2131 bus_space_read_1(iot, ioh, TMOD)); 2132 printf(" INTS=%x PSNS=%x SSTS=%x SERR=%x PCTL=%x\n", 2133 bus_space_read_1(iot, ioh, INTS), 2134 bus_space_read_1(iot, ioh, PSNS), 2135 bus_space_read_1(iot, ioh, SSTS), 2136 bus_space_read_1(iot, ioh, SERR), 2137 bus_space_read_1(iot, ioh, PCTL)); 2138 printf(" MBC=%x DREG=%x TEMP=%x TCH=%x TCM=%x\n", 2139 bus_space_read_1(iot, ioh, MBC), 2140 #if 0 2141 bus_space_read_1(iot, ioh, DREG), 2142 #else 2143 0, 2144 #endif 2145 bus_space_read_1(iot, ioh, TEMP), 2146 bus_space_read_1(iot, ioh, TCH), 2147 bus_space_read_1(iot, ioh, TCM)); 2148 printf(" TCL=%x EXBF=%x\n", 2149 bus_space_read_1(iot, ioh, TCL), 2150 bus_space_read_1(iot, ioh, EXBF)); 2151 } 2152 2153 void 2154 spc_dump_driver(sc) 2155 struct spc_softc *sc; 2156 { 2157 struct spc_tinfo *ti; 2158 int i; 2159 2160 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2161 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x " 2162 "currmsg=%x\n", sc->sc_state, sc->sc_imess[0], 2163 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2164 for (i = 0; i < 7; i++) { 2165 ti = &sc->sc_tinfo[i]; 2166 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2167 i, ti->cmds, ti->dconns, ti->touts); 2168 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2169 } 2170 } 2171 #endif 2172