1 /* $NetBSD: lsi64854.c,v 1.18 2001/06/04 20:56:51 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/errno.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/bus.h> 50 #include <machine/autoconf.h> 51 #include <machine/cpu.h> 52 53 #include <dev/scsipi/scsi_all.h> 54 #include <dev/scsipi/scsipi_all.h> 55 #include <dev/scsipi/scsiconf.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 void lsi64854_reset __P((struct lsi64854_softc *)); 64 int lsi64854_setup __P((struct lsi64854_softc *, caddr_t *, size_t *, 65 int, size_t *)); 66 int lsi64854_setup_pp __P((struct lsi64854_softc *, caddr_t *, size_t *, 67 int, size_t *)); 68 69 #ifdef DEBUG 70 #define LDB_SCSI 1 71 #define LDB_ENET 2 72 #define LDB_PP 4 73 #define LDB_ANY 0xff 74 int lsi64854debug = 0; 75 #define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0) 76 #else 77 #define DPRINTF(a,x) 78 #endif 79 80 #define MAX_DMA_SZ (16*1024*1024) 81 82 /* 83 * Finish attaching this DMA device. 84 * Front-end must fill in these fields: 85 * sc_bustag 86 * sc_dmatag 87 * sc_regs 88 * sc_burst 89 * sc_channel (one of SCSI, ENET, PP) 90 * sc_client (one of SCSI, ENET, PP `soft_c' pointers) 91 */ 92 void 93 lsi64854_attach(sc) 94 struct lsi64854_softc *sc; 95 { 96 u_int32_t csr; 97 98 /* Indirect functions */ 99 switch (sc->sc_channel) { 100 case L64854_CHANNEL_SCSI: 101 sc->intr = lsi64854_scsi_intr; 102 sc->setup = lsi64854_setup; 103 break; 104 case L64854_CHANNEL_ENET: 105 sc->intr = lsi64854_enet_intr; 106 break; 107 case L64854_CHANNEL_PP: 108 sc->setup = lsi64854_setup_pp; 109 break; 110 default: 111 printf("%s: unknown channel\n", sc->sc_dev.dv_xname); 112 } 113 sc->reset = lsi64854_reset; 114 115 /* Allocate a dmamap */ 116 if (bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ, 117 0, BUS_DMA_WAITOK, &sc->sc_dmamap) != 0) { 118 printf("%s: dma map create failed\n", sc->sc_dev.dv_xname); 119 return; 120 } 121 122 printf(": dma rev "); 123 csr = L64854_GCSR(sc); 124 sc->sc_rev = csr & L64854_DEVID; 125 switch (sc->sc_rev) { 126 case DMAREV_0: 127 printf("0"); 128 break; 129 case DMAREV_ESC: 130 printf("esc"); 131 break; 132 case DMAREV_1: 133 printf("1"); 134 break; 135 case DMAREV_PLUS: 136 printf("1+"); 137 break; 138 case DMAREV_2: 139 printf("2"); 140 break; 141 case DMAREV_HME: 142 printf("fas"); 143 break; 144 default: 145 printf("unknown (0x%x)", sc->sc_rev); 146 } 147 148 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr)); 149 printf("\n"); 150 } 151 152 /* 153 * DMAWAIT waits while condition is true 154 */ 155 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 156 int count = 500000; \ 157 while ((COND) && --count > 0) DELAY(1); \ 158 if (count == 0) { \ 159 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ 160 (u_long)L64854_GCSR(SC)); \ 161 if (DONTPANIC) \ 162 printf(MSG); \ 163 else \ 164 panic(MSG); \ 165 } \ 166 } while (0) 167 168 #define DMA_DRAIN(sc, dontpanic) do { \ 169 u_int32_t csr; \ 170 /* \ 171 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 172 * and "drain" bits while it is still thinking about a \ 173 * request. \ 174 * other revs: D_ESC_R_PEND bit reads as 0 \ 175 */ \ 176 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 177 if (sc->sc_rev != DMAREV_HME) { \ 178 /* \ 179 * Select drain bit based on revision \ 180 * also clears errors and D_TC flag \ 181 */ \ 182 csr = L64854_GCSR(sc); \ 183 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 184 csr |= D_ESC_DRAIN; \ 185 else \ 186 csr |= L64854_INVALIDATE; \ 187 \ 188 L64854_SCSR(sc,csr); \ 189 } \ 190 /* \ 191 * Wait for draining to finish \ 192 * rev0 & rev1 call this PACKCNT \ 193 */ \ 194 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ 195 } while(0) 196 197 #define DMA_FLUSH(sc, dontpanic) do { \ 198 u_int32_t csr; \ 199 /* \ 200 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 201 * and "drain" bits while it is still thinking about a \ 202 * request. \ 203 * other revs: D_ESC_R_PEND bit reads as 0 \ 204 */ \ 205 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 206 csr = L64854_GCSR(sc); \ 207 csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \ 208 csr |= L64854_INVALIDATE; /* XXX FAS ? */ \ 209 L64854_SCSR(sc,csr); \ 210 } while(0) 211 212 void 213 lsi64854_reset(sc) 214 struct lsi64854_softc *sc; 215 { 216 u_int32_t csr; 217 218 DMA_FLUSH(sc, 1); 219 csr = L64854_GCSR(sc); 220 221 DPRINTF(LDB_ANY, ("lsi64854_reset: csr 0x%x\n", csr)); 222 223 /* 224 * XXX is sync needed? 225 */ 226 if (sc->sc_dmamap->dm_nsegs > 0) 227 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 228 229 if (sc->sc_rev == DMAREV_HME) 230 L64854_SCSR(sc, csr | D_HW_RESET_FAS366); 231 232 233 csr |= L64854_RESET; /* reset DMA */ 234 L64854_SCSR(sc, csr); 235 DELAY(200); /* > 10 Sbus clocks(?) */ 236 237 /*DMAWAIT1(sc); why was this here? */ 238 csr = L64854_GCSR(sc); 239 csr &= ~L64854_RESET; /* de-assert reset line */ 240 L64854_SCSR(sc, csr); 241 DELAY(5); /* allow a few ticks to settle */ 242 243 csr = L64854_GCSR(sc); 244 csr |= L64854_INT_EN; /* enable interrupts */ 245 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) { 246 if (sc->sc_rev == DMAREV_HME) 247 csr |= D_TWO_CYCLE; 248 else 249 csr |= D_FASTER; 250 } 251 252 /* Set burst */ 253 switch (sc->sc_rev) { 254 case DMAREV_HME: 255 case DMAREV_2: 256 csr &= ~L64854_BURST_SIZE; 257 if (sc->sc_burst == 32) { 258 csr |= L64854_BURST_32; 259 } else if (sc->sc_burst == 16) { 260 csr |= L64854_BURST_16; 261 } else { 262 csr |= L64854_BURST_0; 263 } 264 break; 265 case DMAREV_ESC: 266 csr |= D_ESC_AUTODRAIN; /* Auto-drain */ 267 if (sc->sc_burst == 32) { 268 csr &= ~D_ESC_BURST; 269 } else 270 csr |= D_ESC_BURST; 271 break; 272 default: 273 break; 274 } 275 L64854_SCSR(sc, csr); 276 277 if (sc->sc_rev == DMAREV_HME) { 278 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 0); 279 sc->sc_dmactl = csr; 280 } 281 sc->sc_active = 0; 282 283 DPRINTF(LDB_ANY, ("lsi64854_reset: done, csr 0x%x\n", csr)); 284 } 285 286 287 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 288 /* 289 * setup a dma transfer 290 */ 291 int 292 lsi64854_setup(sc, addr, len, datain, dmasize) 293 struct lsi64854_softc *sc; 294 caddr_t *addr; 295 size_t *len; 296 int datain; 297 size_t *dmasize; /* IN-OUT */ 298 { 299 u_int32_t csr; 300 301 DMA_FLUSH(sc, 0); 302 303 #if 0 304 DMACSR(sc) &= ~D_INT_EN; 305 #endif 306 sc->sc_dmaaddr = addr; 307 sc->sc_dmalen = len; 308 309 /* 310 * the rules say we cannot transfer more than the limit 311 * of this DMA chip (64k for old and 16Mb for new), 312 * and we cannot cross a 16Mb boundary. 313 */ 314 *dmasize = sc->sc_dmasize = 315 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 316 317 DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize)); 318 319 /* 320 * XXX what length? 321 */ 322 if (sc->sc_rev == DMAREV_HME) { 323 324 L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET); 325 L64854_SCSR(sc, sc->sc_dmactl); 326 327 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, *dmasize); 328 } 329 330 /* Program the DMA address */ 331 if (sc->sc_dmasize) { 332 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 333 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 334 *sc->sc_dmaaddr, sc->sc_dmasize, 335 NULL /* kernel address */, 336 BUS_DMA_NOWAIT | BUS_DMA_STREAMING)) 337 panic("%s: cannot allocate DVMA address", 338 sc->sc_dev.dv_xname); 339 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 340 datain 341 ? BUS_DMASYNC_PREREAD 342 : BUS_DMASYNC_PREWRITE); 343 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 344 sc->sc_dmamap->dm_segs[0].ds_addr); 345 } 346 347 if (sc->sc_rev == DMAREV_ESC) { 348 /* DMA ESC chip bug work-around */ 349 long bcnt = sc->sc_dmasize; 350 long eaddr = bcnt + (long)*sc->sc_dmaaddr; 351 if ((eaddr & PGOFSET) != 0) 352 bcnt = roundup(bcnt, PAGE_SIZE); 353 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 354 bcnt); 355 } 356 357 /* Setup DMA control register */ 358 csr = L64854_GCSR(sc); 359 360 if (datain) 361 csr |= L64854_WRITE; 362 else 363 csr &= ~L64854_WRITE; 364 csr |= L64854_INT_EN; 365 366 if (sc->sc_rev == DMAREV_HME) { 367 csr |= (D_DSBL_SCSI_DRN | D_EN_DMA); 368 } 369 370 L64854_SCSR(sc, csr); 371 372 return (0); 373 } 374 375 /* 376 * Pseudo (chained) interrupt from the esp driver to kick the 377 * current running DMA transfer. Called from ncr53c9x_intr() 378 * for now. 379 * 380 * return 1 if it was a DMA continue. 381 */ 382 int 383 lsi64854_scsi_intr(arg) 384 void *arg; 385 { 386 struct lsi64854_softc *sc = arg; 387 struct ncr53c9x_softc *nsc = sc->sc_client; 388 char bits[64]; 389 int trans, resid; 390 u_int32_t csr; 391 392 csr = L64854_GCSR(sc); 393 394 DPRINTF(LDB_SCSI, ("%s: dmaintr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 395 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 396 bitmask_snprintf(csr, DDMACSR_BITS, bits, sizeof(bits)))); 397 398 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { 399 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 400 bitmask_snprintf(csr, DDMACSR_BITS, bits,sizeof(bits))); 401 csr &= ~D_EN_DMA; /* Stop DMA */ 402 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 403 csr |= D_INVALIDATE|D_SLAVE_ERR; 404 L64854_SCSR(sc, csr); 405 return (-1); 406 } 407 408 /* This is an "assertion" :) */ 409 if (sc->sc_active == 0) 410 panic("dmaintr: DMA wasn't active"); 411 412 DMA_DRAIN(sc, 0); 413 414 /* DMA has stopped */ 415 csr &= ~D_EN_DMA; 416 L64854_SCSR(sc, csr); 417 sc->sc_active = 0; 418 419 if (sc->sc_dmasize == 0) { 420 /* A "Transfer Pad" operation completed */ 421 DPRINTF(LDB_SCSI, ("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 422 NCR_READ_REG(nsc, NCR_TCL) | 423 (NCR_READ_REG(nsc, NCR_TCM) << 8), 424 NCR_READ_REG(nsc, NCR_TCL), 425 NCR_READ_REG(nsc, NCR_TCM))); 426 return 0; 427 } 428 429 resid = 0; 430 /* 431 * If a transfer onto the SCSI bus gets interrupted by the device 432 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 433 * as residual since the NCR53C9X counter registers get decremented 434 * as bytes are clocked into the FIFO. 435 */ 436 if (!(csr & D_WRITE) && 437 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 438 DPRINTF(LDB_SCSI, ("dmaintr: empty esp FIFO of %d ", resid)); 439 } 440 441 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 442 /* 443 * `Terminal count' is off, so read the residue 444 * out of the NCR53C9X counter registers. 445 */ 446 resid += (NCR_READ_REG(nsc, NCR_TCL) | 447 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 448 ((nsc->sc_cfg2 & NCRCFG2_FE) 449 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 450 : 0)); 451 452 if (resid == 0 && sc->sc_dmasize == 65536 && 453 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 454 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 455 resid = 65536; 456 } 457 458 trans = sc->sc_dmasize - resid; 459 if (trans < 0) { /* transferred < 0 ? */ 460 #if 0 461 /* 462 * This situation can happen in perfectly normal operation 463 * if the ESP is reselected while using DMA to select 464 * another target. As such, don't print the warning. 465 */ 466 printf("%s: xfer (%d) > req (%d)\n", 467 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 468 #endif 469 trans = sc->sc_dmasize; 470 } 471 472 DPRINTF(LDB_SCSI, ("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 473 NCR_READ_REG(nsc, NCR_TCL), 474 NCR_READ_REG(nsc, NCR_TCM), 475 (nsc->sc_cfg2 & NCRCFG2_FE) 476 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 477 trans, resid)); 478 479 if (sc->sc_dmamap->dm_nsegs > 0) { 480 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 481 (csr & D_WRITE) != 0 482 ? BUS_DMASYNC_POSTREAD 483 : BUS_DMASYNC_POSTWRITE); 484 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 485 } 486 487 *sc->sc_dmalen -= trans; 488 *sc->sc_dmaaddr += trans; 489 490 #if 0 /* this is not normal operation just yet */ 491 if (*sc->sc_dmalen == 0 || 492 nsc->sc_phase != nsc->sc_prevphase) 493 return 0; 494 495 /* and again */ 496 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 497 return 1; 498 #endif 499 return 0; 500 } 501 502 /* 503 * Pseudo (chained) interrupt to le driver to handle DMA errors. 504 */ 505 int 506 lsi64854_enet_intr(arg) 507 void *arg; 508 { 509 struct lsi64854_softc *sc = arg; 510 char bits[64]; 511 u_int32_t csr; 512 static int dodrain = 0; 513 int rv; 514 515 csr = L64854_GCSR(sc); 516 517 /* If the DMA logic shows an interrupt, claim it */ 518 rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; 519 520 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { 521 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 522 bitmask_snprintf(csr, EDMACSR_BITS, bits,sizeof(bits))); 523 csr &= ~L64854_EN_DMA; /* Stop DMA */ 524 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 525 csr |= E_INVALIDATE|E_SLAVE_ERR; 526 L64854_SCSR(sc, csr); 527 DMA_RESET(sc); 528 dodrain = 1; 529 return (1); 530 } 531 532 if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */ 533 int i = 10; 534 csr |= E_DRAIN; 535 L64854_SCSR(sc, csr); 536 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING)) 537 delay(1); 538 } 539 540 return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg)); 541 } 542 543 /* 544 * setup a dma transfer 545 */ 546 int 547 lsi64854_setup_pp(sc, addr, len, datain, dmasize) 548 struct lsi64854_softc *sc; 549 caddr_t *addr; 550 size_t *len; 551 int datain; 552 size_t *dmasize; /* IN-OUT */ 553 { 554 u_int32_t csr; 555 556 DMA_FLUSH(sc, 0); 557 558 sc->sc_dmaaddr = addr; 559 sc->sc_dmalen = len; 560 561 DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->sc_dev.dv_xname, 562 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 563 564 /* 565 * the rules say we cannot transfer more than the limit 566 * of this DMA chip (64k for old and 16Mb for new), 567 * and we cannot cross a 16Mb boundary. 568 */ 569 *dmasize = sc->sc_dmasize = 570 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 571 572 DPRINTF(LDB_PP, ("dma_setup_pp: dmasize = %ld\n", (long)sc->sc_dmasize)); 573 574 /* Program the DMA address */ 575 if (sc->sc_dmasize) { 576 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 577 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 578 *sc->sc_dmaaddr, sc->sc_dmasize, 579 NULL /* kernel address */, 580 BUS_DMA_NOWAIT/*|BUS_DMA_COHERENT*/)) 581 panic("%s: pp cannot allocate DVMA address", 582 sc->sc_dev.dv_xname); 583 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 584 datain 585 ? BUS_DMASYNC_PREREAD 586 : BUS_DMASYNC_PREWRITE); 587 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 588 sc->sc_dmamap->dm_segs[0].ds_addr); 589 590 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 591 sc->sc_dmasize); 592 } 593 594 /* Setup DMA control register */ 595 csr = L64854_GCSR(sc); 596 csr &= ~L64854_BURST_SIZE; 597 if (sc->sc_burst == 32) { 598 csr |= L64854_BURST_32; 599 } else if (sc->sc_burst == 16) { 600 csr |= L64854_BURST_16; 601 } else { 602 csr |= L64854_BURST_0; 603 } 604 csr |= P_EN_DMA|P_INT_EN|P_EN_CNT; 605 #if 0 606 /* This bit is read-only in PP csr register */ 607 if (datain) 608 csr |= P_WRITE; 609 else 610 csr &= ~P_WRITE; 611 #endif 612 L64854_SCSR(sc, csr); 613 614 return (0); 615 } 616 /* 617 * Parallel port DMA interrupt. 618 */ 619 int 620 lsi64854_pp_intr(arg) 621 void *arg; 622 { 623 struct lsi64854_softc *sc = arg; 624 char bits[64]; 625 int ret, trans, resid = 0; 626 u_int32_t csr; 627 628 csr = L64854_GCSR(sc); 629 630 DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 631 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 632 bitmask_snprintf(csr, PDMACSR_BITS, bits, sizeof(bits)))); 633 634 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { 635 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 636 L64854_REG_CNT); 637 printf("%s: pp error: resid %d csr=%s\n", sc->sc_dev.dv_xname, 638 resid, 639 bitmask_snprintf(csr, PDMACSR_BITS, bits,sizeof(bits))); 640 csr &= ~P_EN_DMA; /* Stop DMA */ 641 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 642 csr |= P_INVALIDATE|P_SLAVE_ERR; 643 L64854_SCSR(sc, csr); 644 return (1); 645 } 646 647 ret = (csr & P_INT_PEND) != 0; 648 649 if (sc->sc_active != 0) { 650 DMA_DRAIN(sc, 0); 651 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 652 L64854_REG_CNT); 653 } 654 655 /* DMA has stopped */ 656 csr &= ~D_EN_DMA; 657 L64854_SCSR(sc, csr); 658 sc->sc_active = 0; 659 660 trans = sc->sc_dmasize - resid; 661 if (trans < 0) { /* transferred < 0 ? */ 662 trans = sc->sc_dmasize; 663 } 664 *sc->sc_dmalen -= trans; 665 *sc->sc_dmaaddr += trans; 666 667 if (sc->sc_dmamap->dm_nsegs > 0) { 668 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 669 (csr & D_WRITE) != 0 670 ? BUS_DMASYNC_POSTREAD 671 : BUS_DMASYNC_POSTWRITE); 672 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 673 } 674 675 return (ret != 0); 676 } 677