1 /* $NetBSD: lsi64854.c,v 1.39 2018/09/03 16:29:31 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: lsi64854.c,v 1.39 2018/09/03 16:29:31 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/errno.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 42 #include <sys/bus.h> 43 #include <machine/autoconf.h> 44 #include <sys/cpu.h> 45 46 #include <dev/scsipi/scsi_all.h> 47 #include <dev/scsipi/scsipi_all.h> 48 #include <dev/scsipi/scsiconf.h> 49 50 #include <dev/ic/lsi64854reg.h> 51 #include <dev/ic/lsi64854var.h> 52 53 #include <dev/ic/ncr53c9xreg.h> 54 #include <dev/ic/ncr53c9xvar.h> 55 56 void lsi64854_reset(struct lsi64854_softc *); 57 int lsi64854_setup(struct lsi64854_softc *, uint8_t **, size_t *, 58 int, size_t *); 59 int lsi64854_setup_pp(struct lsi64854_softc *, uint8_t **, size_t *, 60 int, size_t *); 61 62 #ifdef DEBUG 63 #define LDB_SCSI 1 64 #define LDB_ENET 2 65 #define LDB_PP 4 66 #define LDB_ANY 0xff 67 int lsi64854debug = 0; 68 #define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0) 69 #else 70 #define DPRINTF(a,x) 71 #endif 72 73 #define MAX_DMA_SZ (16 * 1024 * 1024) 74 75 /* 76 * Finish attaching this DMA device. 77 * Front-end must fill in these fields: 78 * sc_bustag 79 * sc_dmatag 80 * sc_regs 81 * sc_burst 82 * sc_channel (one of SCSI, ENET, PP) 83 * sc_client (one of SCSI, ENET, PP `soft_c' pointers) 84 */ 85 void 86 lsi64854_attach(struct lsi64854_softc *sc) 87 { 88 uint32_t csr; 89 90 /* Indirect functions */ 91 switch (sc->sc_channel) { 92 case L64854_CHANNEL_SCSI: 93 sc->intr = lsi64854_scsi_intr; 94 sc->setup = lsi64854_setup; 95 break; 96 case L64854_CHANNEL_ENET: 97 sc->intr = lsi64854_enet_intr; 98 break; 99 case L64854_CHANNEL_PP: 100 sc->setup = lsi64854_setup_pp; 101 break; 102 default: 103 aprint_error(": unknown channel"); 104 } 105 sc->reset = lsi64854_reset; 106 107 /* Allocate a dmamap */ 108 if (bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ, 109 0, BUS_DMA_WAITOK, &sc->sc_dmamap) != 0) { 110 aprint_error(": DMA map create failed\n"); 111 return; 112 } 113 114 csr = L64854_GCSR(sc); 115 sc->sc_rev = csr & L64854_DEVID; 116 if (sc->sc_rev == DMAREV_HME) { 117 return; 118 } 119 aprint_normal(": DMA rev "); 120 switch (sc->sc_rev) { 121 case DMAREV_0: 122 aprint_normal("0"); 123 break; 124 case DMAREV_ESC: 125 aprint_normal("esc"); 126 break; 127 case DMAREV_1: 128 aprint_normal("1"); 129 break; 130 case DMAREV_PLUS: 131 aprint_normal("1+"); 132 break; 133 case DMAREV_2: 134 aprint_normal("2"); 135 break; 136 default: 137 aprint_normal("unknown (0x%x)", sc->sc_rev); 138 } 139 140 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr)); 141 aprint_normal("\n"); 142 } 143 144 /* 145 * DMAWAIT waits while condition is true 146 */ 147 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 148 int count = 500000; \ 149 while ((COND) && --count > 0) DELAY(1); \ 150 if (count == 0) { \ 151 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ 152 (u_long)L64854_GCSR(SC)); \ 153 if (DONTPANIC) \ 154 printf(MSG); \ 155 else \ 156 panic(MSG); \ 157 } \ 158 } while (/* CONSTCOND */ 0) 159 160 #define DMA_DRAIN(sc, dontpanic) do { \ 161 uint32_t _csr; \ 162 /* \ 163 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 164 * and "drain" bits while it is still thinking about a \ 165 * request. \ 166 * other revs: D_ESC_R_PEND bit reads as 0 \ 167 */ \ 168 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 169 if (sc->sc_rev != DMAREV_HME) { \ 170 /* \ 171 * Select drain bit based on revision \ 172 * also clears errors and D_TC flag \ 173 */ \ 174 _csr = L64854_GCSR(sc); \ 175 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 176 _csr |= D_ESC_DRAIN; \ 177 else \ 178 _csr |= L64854_INVALIDATE; \ 179 \ 180 L64854_SCSR(sc,_csr); \ 181 } \ 182 /* \ 183 * Wait for draining to finish \ 184 * rev0 & rev1 call this PACKCNT \ 185 */ \ 186 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ 187 } while (/* CONSTCOND */ 0) 188 189 #define DMA_FLUSH(sc, dontpanic) do { \ 190 uint32_t _csr; \ 191 /* \ 192 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 193 * and "drain" bits while it is still thinking about a \ 194 * request. \ 195 * other revs: D_ESC_R_PEND bit reads as 0 \ 196 */ \ 197 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 198 _csr = L64854_GCSR(sc); \ 199 _csr &= ~(L64854_WRITE | L64854_EN_DMA); /* no-ops on ENET */ \ 200 _csr |= L64854_INVALIDATE; /* XXX FAS ? */ \ 201 L64854_SCSR(sc,_csr); \ 202 } while (/* CONSTCOND */ 0) 203 204 void 205 lsi64854_reset(struct lsi64854_softc *sc) 206 { 207 uint32_t csr; 208 209 DMA_FLUSH(sc, 1); 210 csr = L64854_GCSR(sc); 211 212 DPRINTF(LDB_ANY, ("%s: csr 0x%x\n", __func__, csr)); 213 214 /* 215 * XXX is sync needed? 216 */ 217 if (sc->sc_dmamap->dm_nsegs > 0) 218 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 219 220 if (sc->sc_rev == DMAREV_HME) 221 L64854_SCSR(sc, csr | D_HW_RESET_FAS366); 222 223 224 csr |= L64854_RESET; /* reset DMA */ 225 L64854_SCSR(sc, csr); 226 DELAY(200); /* > 10 Sbus clocks(?) */ 227 228 /*DMAWAIT1(sc); why was this here? */ 229 csr = L64854_GCSR(sc); 230 csr &= ~L64854_RESET; /* de-assert reset line */ 231 L64854_SCSR(sc, csr); 232 DELAY(5); /* allow a few ticks to settle */ 233 234 csr = L64854_GCSR(sc); 235 csr |= L64854_INT_EN; /* enable interrupts */ 236 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) { 237 if (sc->sc_rev == DMAREV_HME) 238 csr |= D_TWO_CYCLE; 239 else 240 csr |= D_FASTER; 241 } 242 243 /* Set burst */ 244 switch (sc->sc_rev) { 245 case DMAREV_HME: 246 case DMAREV_2: 247 csr &= ~L64854_BURST_SIZE; 248 if (sc->sc_burst == 32) { 249 csr |= L64854_BURST_32; 250 } else if (sc->sc_burst == 16) { 251 csr |= L64854_BURST_16; 252 } else { 253 csr |= L64854_BURST_0; 254 } 255 break; 256 case DMAREV_ESC: 257 csr |= D_ESC_AUTODRAIN; /* Auto-drain */ 258 if (sc->sc_burst == 32) { 259 csr &= ~D_ESC_BURST; 260 } else 261 csr |= D_ESC_BURST; 262 break; 263 default: 264 break; 265 } 266 L64854_SCSR(sc, csr); 267 268 if (sc->sc_rev == DMAREV_HME) { 269 bus_space_write_4(sc->sc_bustag, sc->sc_regs, 270 L64854_REG_ADDR, 0); 271 sc->sc_dmactl = csr; 272 } 273 sc->sc_active = 0; 274 275 DPRINTF(LDB_ANY, ("%s: done, csr 0x%x\n", __func__, csr)); 276 } 277 278 279 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 280 /* 281 * setup a DMA transfer 282 */ 283 int 284 lsi64854_setup(struct lsi64854_softc *sc, uint8_t **addr, size_t *len, 285 int datain, size_t *dmasize) 286 { 287 uint32_t csr; 288 289 DMA_FLUSH(sc, 0); 290 291 #if 0 292 DMACSR(sc) &= ~D_INT_EN; 293 #endif 294 sc->sc_dmaaddr = addr; 295 sc->sc_dmalen = len; 296 297 /* 298 * the rules say we cannot transfer more than the limit 299 * of this DMA chip (64k for old and 16Mb for new), 300 * and we cannot cross a 16Mb boundary. 301 */ 302 *dmasize = sc->sc_dmasize = 303 uimin(*dmasize, DMAMAX((size_t)*sc->sc_dmaaddr)); 304 305 DPRINTF(LDB_ANY, ("%s: dmasize = %ld\n", 306 __func__, (long)sc->sc_dmasize)); 307 308 /* 309 * XXX what length? 310 */ 311 if (sc->sc_rev == DMAREV_HME) { 312 313 L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET); 314 L64854_SCSR(sc, sc->sc_dmactl); 315 316 bus_space_write_4(sc->sc_bustag, sc->sc_regs, 317 L64854_REG_CNT, *dmasize); 318 } 319 320 /* Program the DMA address */ 321 if (sc->sc_dmasize) { 322 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 323 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 324 *sc->sc_dmaaddr, sc->sc_dmasize, 325 NULL /* kernel address */, 326 BUS_DMA_NOWAIT | BUS_DMA_STREAMING)) 327 panic("%s: cannot allocate DVMA address", 328 device_xname(sc->sc_dev)); 329 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 330 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 331 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 332 sc->sc_dmamap->dm_segs[0].ds_addr); 333 } 334 335 if (sc->sc_rev == DMAREV_ESC) { 336 /* DMA ESC chip bug work-around */ 337 long bcnt = sc->sc_dmasize; 338 long eaddr = bcnt + (long)*sc->sc_dmaaddr; 339 340 if ((eaddr & PGOFSET) != 0) 341 bcnt = roundup(bcnt, PAGE_SIZE); 342 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 343 bcnt); 344 } 345 346 /* Setup DMA control register */ 347 csr = L64854_GCSR(sc); 348 349 if (datain) 350 csr |= L64854_WRITE; 351 else 352 csr &= ~L64854_WRITE; 353 csr |= L64854_INT_EN; 354 355 if (sc->sc_rev == DMAREV_HME) { 356 csr |= (D_DSBL_SCSI_DRN | D_EN_DMA); 357 } 358 359 L64854_SCSR(sc, csr); 360 361 return 0; 362 } 363 364 /* 365 * Pseudo (chained) interrupt from the esp driver to kick the 366 * current running DMA transfer. Called from ncr53c9x_intr() 367 * for now. 368 * 369 * return 1 if it was a DMA continue. 370 */ 371 int 372 lsi64854_scsi_intr(void *arg) 373 { 374 struct lsi64854_softc *sc = arg; 375 struct ncr53c9x_softc *nsc = sc->sc_client; 376 char bits[64]; 377 int trans, resid; 378 uint32_t csr; 379 380 csr = L64854_GCSR(sc); 381 #ifdef DEBUG 382 snprintb(bits, sizeof(bits), DDMACSR_BITS, csr); 383 #endif 384 DPRINTF(LDB_SCSI, ("%s: %s: addr 0x%x, csr %s\n", 385 device_xname(sc->sc_dev), __func__, 386 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 387 bits)); 388 389 390 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { 391 snprintb(bits, sizeof(bits), DDMACSR_BITS, csr); 392 printf("%s: error: csr=%s\n", device_xname(sc->sc_dev), bits); 393 csr &= ~D_EN_DMA; /* Stop DMA */ 394 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 395 csr |= D_INVALIDATE|D_SLAVE_ERR; 396 L64854_SCSR(sc, csr); 397 return -1; 398 } 399 400 /* This is an "assertion" :) */ 401 if (sc->sc_active == 0) 402 panic("%s: DMA wasn't active", __func__); 403 404 DMA_DRAIN(sc, 0); 405 406 /* DMA has stopped */ 407 csr &= ~D_EN_DMA; 408 L64854_SCSR(sc, csr); 409 sc->sc_active = 0; 410 411 if (sc->sc_dmasize == 0) { 412 /* A "Transfer Pad" operation completed */ 413 DPRINTF(LDB_SCSI, ("%s: discarded %d bytes (tcl=%d, tcm=%d)\n", 414 __func__, 415 NCR_READ_REG(nsc, NCR_TCL) | 416 (NCR_READ_REG(nsc, NCR_TCM) << 8), 417 NCR_READ_REG(nsc, NCR_TCL), 418 NCR_READ_REG(nsc, NCR_TCM))); 419 return 0; 420 } 421 422 resid = 0; 423 /* 424 * If a transfer onto the SCSI bus gets interrupted by the device 425 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 426 * as residual since the NCR53C9X counter registers get decremented 427 * as bytes are clocked into the FIFO. 428 */ 429 if (!(csr & D_WRITE) && 430 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 431 DPRINTF(LDB_SCSI, ("%s: empty esp FIFO of %d ", 432 __func__, resid)); 433 if (nsc->sc_rev == NCR_VARIANT_FAS366 && 434 (NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE)) 435 resid <<= 1; 436 } 437 438 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 439 /* 440 * `Terminal count' is off, so read the residue 441 * out of the NCR53C9X counter registers. 442 */ 443 resid += (NCR_READ_REG(nsc, NCR_TCL) | 444 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 445 ((nsc->sc_cfg2 & NCRCFG2_FE) ? 446 (NCR_READ_REG(nsc, NCR_TCH) << 16) : 0)); 447 448 if (resid == 0 && sc->sc_dmasize == 65536 && 449 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 450 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 451 resid = 65536; 452 } 453 454 trans = sc->sc_dmasize - resid; 455 if (trans < 0) { /* transferred < 0 ? */ 456 #if 0 457 /* 458 * This situation can happen in perfectly normal operation 459 * if the ESP is reselected while using DMA to select 460 * another target. As such, don't print the warning. 461 */ 462 printf("%s: xfer (%d) > req (%d)\n", 463 device_xname(sc->sc_dev), trans, sc->sc_dmasize); 464 #endif 465 trans = sc->sc_dmasize; 466 } 467 468 DPRINTF(LDB_SCSI, ("%s: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 469 __func__, 470 NCR_READ_REG(nsc, NCR_TCL), 471 NCR_READ_REG(nsc, NCR_TCM), 472 (nsc->sc_cfg2 & NCRCFG2_FE) ? 473 NCR_READ_REG(nsc, NCR_TCH) : 0, 474 trans, resid)); 475 476 if (sc->sc_dmamap->dm_nsegs > 0) { 477 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 478 (csr & D_WRITE) != 0 ? 479 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 480 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 481 } 482 483 *sc->sc_dmalen -= trans; 484 *sc->sc_dmaaddr += trans; 485 486 #if 0 /* this is not normal operation just yet */ 487 if (*sc->sc_dmalen == 0 || 488 nsc->sc_phase != nsc->sc_prevphase) 489 return 0; 490 491 /* and again */ 492 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 493 return 1; 494 #endif 495 return 0; 496 } 497 498 /* 499 * Pseudo (chained) interrupt to le driver to handle DMA errors. 500 */ 501 int 502 lsi64854_enet_intr(void *arg) 503 { 504 struct lsi64854_softc *sc = arg; 505 char bits[64]; 506 uint32_t csr; 507 static int dodrain = 0; 508 int rv; 509 510 csr = L64854_GCSR(sc); 511 512 /* If the DMA logic shows an interrupt, claim it */ 513 rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; 514 515 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { 516 snprintb(bits, sizeof(bits), EDMACSR_BITS, csr); 517 printf("%s: error: csr=%s\n", device_xname(sc->sc_dev), bits); 518 csr &= ~L64854_EN_DMA; /* Stop DMA */ 519 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 520 csr |= E_INVALIDATE|E_SLAVE_ERR; 521 L64854_SCSR(sc, csr); 522 DMA_RESET(sc); 523 dodrain = 1; 524 return 1; 525 } 526 527 if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */ 528 int i = 10; 529 csr |= E_DRAIN; 530 L64854_SCSR(sc, csr); 531 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING)) 532 delay(1); 533 } 534 535 return rv | (*sc->sc_intrchain)(sc->sc_intrchainarg); 536 } 537 538 /* 539 * setup a DMA transfer 540 */ 541 int 542 lsi64854_setup_pp(struct lsi64854_softc *sc, uint8_t **addr, size_t *len, 543 int datain, size_t *dmasize) 544 { 545 uint32_t csr; 546 547 DMA_FLUSH(sc, 0); 548 549 sc->sc_dmaaddr = addr; 550 sc->sc_dmalen = len; 551 552 DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", device_xname(sc->sc_dev), 553 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 554 555 /* 556 * the rules say we cannot transfer more than the limit 557 * of this DMA chip (64k for old and 16Mb for new), 558 * and we cannot cross a 16Mb boundary. 559 */ 560 *dmasize = sc->sc_dmasize = 561 uimin(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 562 563 DPRINTF(LDB_PP, ("%s: dmasize = %ld\n", 564 __func__, (long)sc->sc_dmasize)); 565 566 /* Program the DMA address */ 567 if (sc->sc_dmasize) { 568 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 569 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 570 *sc->sc_dmaaddr, sc->sc_dmasize, 571 NULL /* kernel address */, 572 BUS_DMA_NOWAIT/*|BUS_DMA_COHERENT*/)) 573 panic("%s: pp cannot allocate DVMA address", 574 device_xname(sc->sc_dev)); 575 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 576 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 577 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 578 sc->sc_dmamap->dm_segs[0].ds_addr); 579 580 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 581 sc->sc_dmasize); 582 } 583 584 /* Setup DMA control register */ 585 csr = L64854_GCSR(sc); 586 csr &= ~L64854_BURST_SIZE; 587 if (sc->sc_burst == 32) { 588 csr |= L64854_BURST_32; 589 } else if (sc->sc_burst == 16) { 590 csr |= L64854_BURST_16; 591 } else { 592 csr |= L64854_BURST_0; 593 } 594 csr |= P_EN_DMA|P_INT_EN|P_EN_CNT; 595 #if 0 596 /* This bit is read-only in PP csr register */ 597 if (datain) 598 csr |= P_WRITE; 599 else 600 csr &= ~P_WRITE; 601 #endif 602 L64854_SCSR(sc, csr); 603 604 return 0; 605 } 606 /* 607 * Parallel port DMA interrupt. 608 */ 609 int 610 lsi64854_pp_intr(void *arg) 611 { 612 struct lsi64854_softc *sc = arg; 613 char bits[64]; 614 int ret, trans, resid = 0; 615 uint32_t csr; 616 617 csr = L64854_GCSR(sc); 618 619 #ifdef DEBUG 620 snprintb(bits, sizeof(bits), PDMACSR_BITS, csr); 621 #endif 622 DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %s\n", 623 device_xname(sc->sc_dev), 624 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 625 bits)); 626 627 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { 628 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 629 L64854_REG_CNT); 630 snprintb(bits, sizeof(bits), PDMACSR_BITS, csr); 631 printf("%s: pp error: resid %d csr=%s\n", 632 device_xname(sc->sc_dev), resid, bits); 633 csr &= ~P_EN_DMA; /* Stop DMA */ 634 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 635 csr |= P_INVALIDATE|P_SLAVE_ERR; 636 L64854_SCSR(sc, csr); 637 return 1; 638 } 639 640 ret = (csr & P_INT_PEND) != 0; 641 642 if (sc->sc_active != 0) { 643 DMA_DRAIN(sc, 0); 644 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 645 L64854_REG_CNT); 646 } 647 648 /* DMA has stopped */ 649 csr &= ~D_EN_DMA; 650 L64854_SCSR(sc, csr); 651 sc->sc_active = 0; 652 653 trans = sc->sc_dmasize - resid; 654 if (trans < 0) { /* transferred < 0 ? */ 655 trans = sc->sc_dmasize; 656 } 657 *sc->sc_dmalen -= trans; 658 *sc->sc_dmaaddr += trans; 659 660 if (sc->sc_dmamap->dm_nsegs > 0) { 661 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 662 (csr & D_WRITE) != 0 ? 663 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 664 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 665 } 666 667 return ret != 0; 668 } 669