1 /* $NetBSD: i82557var.h,v 1.26 2001/06/15 22:16:01 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxpvar.h,v 1.4 1997/11/29 08:11:01 davidg Exp 67 */ 68 69 #include <sys/callout.h> 70 71 /* 72 * Misc. defintions for the Intel i82557 fast Ethernet controller 73 * driver. 74 */ 75 76 /* 77 * Transmit descriptor list size. 78 */ 79 #define FXP_NTXCB 256 80 #define FXP_NTXCB_MASK (FXP_NTXCB - 1) 81 #define FXP_NEXTTX(x) ((x + 1) & FXP_NTXCB_MASK) 82 #define FXP_NTXSEG 8 83 84 /* 85 * Number of receive frame area buffers. These are large, so 86 * choose wisely. 87 */ 88 #define FXP_NRFABUFS 128 89 90 /* 91 * Maximum number of seconds that the receiver can be idle before we 92 * assume it's dead and attempt to reset it by reprogramming the 93 * multicast filter. This is part of a work-around for a bug in the 94 * NIC. See fxp_stats_update(). 95 */ 96 #define FXP_MAX_RX_IDLE 15 97 98 /* 99 * Misc. DMA'd data structures are allocated in a single clump, that 100 * maps to a single DMA segment, to make several things easier (computing 101 * offsets, setting up DMA maps, etc.) 102 */ 103 struct fxp_control_data { 104 /* 105 * The transmit control blocks and transmit buffer descriptors. 106 * We arrange them like this so that everything is all lined 107 * up to use the extended TxCB feature. 108 */ 109 struct fxp_txdesc { 110 struct fxp_cb_tx txd_txcb; 111 struct fxp_tbd txd_tbd[FXP_NTXSEG]; 112 } fcd_txdescs[FXP_NTXCB]; 113 114 /* 115 * The configuration CB. 116 */ 117 struct fxp_cb_config fcd_configcb; 118 119 /* 120 * The Individual Address CB. 121 */ 122 struct fxp_cb_ias fcd_iascb; 123 124 /* 125 * The multicast setup CB. 126 */ 127 struct fxp_cb_mcs fcd_mcscb; 128 129 /* 130 * The NIC statistics. 131 */ 132 struct fxp_stats fcd_stats; 133 }; 134 135 #define FXP_CDOFF(x) offsetof(struct fxp_control_data, x) 136 #define FXP_CDTXOFF(x) FXP_CDOFF(fcd_txdescs[(x)].txd_txcb) 137 #define FXP_CDTBDOFF(x) FXP_CDOFF(fcd_txdescs[(x)].txd_tbd) 138 #define FXP_CDCONFIGOFF FXP_CDOFF(fcd_configcb) 139 #define FXP_CDIASOFF FXP_CDOFF(fcd_iascb) 140 #define FXP_CDMCSOFF FXP_CDOFF(fcd_mcscb) 141 #define FXP_CDSTATSOFF FXP_CDOFF(fcd_stats) 142 143 /* 144 * Software state for transmit descriptors. 145 */ 146 struct fxp_txsoft { 147 struct mbuf *txs_mbuf; /* head of mbuf chain */ 148 bus_dmamap_t txs_dmamap; /* our DMA map */ 149 }; 150 151 /* 152 * Software state per device. 153 */ 154 struct fxp_softc { 155 struct device sc_dev; /* generic device structures */ 156 bus_space_tag_t sc_st; /* bus space tag */ 157 bus_space_handle_t sc_sh; /* bus space handle */ 158 bus_dma_tag_t sc_dmat; /* bus dma tag */ 159 struct ethercom sc_ethercom; /* ethernet common part */ 160 void *sc_sdhook; /* shutdown hook */ 161 void *sc_ih; /* interrupt handler cookie */ 162 void *sc_powerhook; /* power hook */ 163 164 struct mii_data sc_mii; /* MII/media information */ 165 struct callout sc_callout; /* MII callout */ 166 167 /* 168 * We create a single DMA map that maps all data structure 169 * overhead, except for RFAs, which are mapped by the 170 * fxp_rxdesc DMA map on a per-mbuf basis. 171 */ 172 bus_dmamap_t sc_dmamap; 173 #define sc_cddma sc_dmamap->dm_segs[0].ds_addr 174 175 /* 176 * Software state for transmit descriptors. 177 */ 178 struct fxp_txsoft sc_txsoft[FXP_NTXCB]; 179 180 int sc_rfa_size; /* size of the RFA structure */ 181 struct ifqueue sc_rxq; /* receive buffer queue */ 182 bus_dmamap_t sc_rxmaps[FXP_NRFABUFS]; /* free receive buffer DMA maps */ 183 int sc_rxfree; /* free map index */ 184 int sc_rxidle; /* # of seconds RX has been idle */ 185 186 /* 187 * Control data structures. 188 */ 189 struct fxp_control_data *sc_control_data; 190 191 #ifdef FXP_EVENT_COUNTERS 192 struct evcnt sc_ev_txstall; /* Tx stalled */ 193 struct evcnt sc_ev_txintr; /* Tx interrupts */ 194 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 195 #endif /* FXP_EVENT_COUNTERS */ 196 197 bus_dma_segment_t sc_cdseg; /* control dma segment */ 198 int sc_cdnseg; 199 200 int sc_rev; /* chip revision */ 201 int sc_flags; /* misc. flags */ 202 203 #define FXPF_MII 0x0001 /* device uses MII */ 204 #define FXPF_ATTACHED 0x0002 /* attach has succeeded */ 205 #define FXPF_WANTINIT 0x0004 /* want a re-init */ 206 #define FXPF_HAS_RESUME_BUG 0x0008 /* has the resume bug */ 207 #define FXPF_FIX_RESUME_BUG 0x0010 /* currently need to work-around 208 the resume bug */ 209 #define FXPF_MWI 0x0020 /* enable PCI MWI */ 210 #define FXPF_READ_ALIGN 0x0040 /* align read access w/ cacheline */ 211 #define FXPF_WRITE_ALIGN 0x0080 /* end write on cacheline */ 212 #define FXPF_EXT_TXCB 0x0100 /* enable extended TxCB */ 213 214 int sc_txpending; /* number of TX requests pending */ 215 int sc_txdirty; /* first dirty TX descriptor */ 216 int sc_txlast; /* last used TX descriptor */ 217 218 int phy_primary_device; /* device type of primary PHY */ 219 220 int sc_enabled; /* boolean; power enabled on interface */ 221 int (*sc_enable)(struct fxp_softc *); 222 void (*sc_disable)(struct fxp_softc *); 223 224 int sc_eeprom_size; /* log2 size of EEPROM */ 225 #if NRND > 0 226 rndsource_element_t rnd_source; /* random source */ 227 #endif 228 229 }; 230 231 #ifdef FXP_EVENT_COUNTERS 232 #define FXP_EVCNT_INCR(ev) (ev)->ev_count++ 233 #else 234 #define FXP_EVCNT_INCR(ev) /* nothing */ 235 #endif 236 237 #define FXP_RXMAP_GET(sc) ((sc)->sc_rxmaps[(sc)->sc_rxfree++]) 238 #define FXP_RXMAP_PUT(sc, map) (sc)->sc_rxmaps[--(sc)->sc_rxfree] = (map) 239 240 #define FXP_CDTXADDR(sc, x) ((sc)->sc_cddma + FXP_CDTXOFF((x))) 241 #define FXP_CDTBDADDR(sc, x) ((sc)->sc_cddma + FXP_CDTBDOFF((x))) 242 243 #define FXP_CDTX(sc, x) (&(sc)->sc_control_data->fcd_txdescs[(x)]) 244 245 #define FXP_DSTX(sc, x) (&(sc)->sc_txsoft[(x)]) 246 247 #define FXP_CDTXSYNC(sc, x, ops) \ 248 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 249 FXP_CDTXOFF((x)), sizeof(struct fxp_txdesc), (ops)) 250 251 #define FXP_CDCONFIGSYNC(sc, ops) \ 252 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 253 FXP_CDCONFIGOFF, sizeof(struct fxp_cb_config), (ops)) 254 255 #define FXP_CDIASSYNC(sc, ops) \ 256 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 257 FXP_CDIASOFF, sizeof(struct fxp_cb_ias), (ops)) 258 259 #define FXP_CDMCSSYNC(sc, ops) \ 260 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 261 FXP_CDMCSOFF, sizeof(struct fxp_cb_mcs), (ops)) 262 263 #define FXP_CDSTATSSYNC(sc, ops) \ 264 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 265 FXP_CDSTATSOFF, sizeof(struct fxp_stats), (ops)) 266 267 #define FXP_RXBUFSIZE(sc, m) ((m)->m_ext.ext_size - \ 268 (sc->sc_rfa_size + \ 269 RFA_ALIGNMENT_FUDGE)) 270 271 #define FXP_RFASYNC(sc, m, ops) \ 272 bus_dmamap_sync((sc)->sc_dmat, M_GETCTX((m), bus_dmamap_t), \ 273 RFA_ALIGNMENT_FUDGE, (sc)->sc_rfa_size, (ops)) 274 275 #define FXP_RXBUFSYNC(sc, m, ops) \ 276 bus_dmamap_sync((sc)->sc_dmat, M_GETCTX((m), bus_dmamap_t), \ 277 RFA_ALIGNMENT_FUDGE + (sc)->sc_rfa_size, \ 278 FXP_RXBUFSIZE((sc), (m)), (ops)) 279 280 #define FXP_MTORFA(m) (struct fxp_rfa *)((m)->m_ext.ext_buf + \ 281 RFA_ALIGNMENT_FUDGE) 282 283 #define FXP_INIT_RFABUF(sc, m) \ 284 do { \ 285 bus_dmamap_t __rxmap = M_GETCTX((m), bus_dmamap_t); \ 286 struct mbuf *__p_m; \ 287 struct fxp_rfa *__rfa, *__p_rfa; \ 288 u_int32_t __v; \ 289 \ 290 (m)->m_data = (m)->m_ext.ext_buf + (sc)->sc_rfa_size + \ 291 RFA_ALIGNMENT_FUDGE; \ 292 \ 293 __rfa = FXP_MTORFA((m)); \ 294 __rfa->size = htole16(FXP_RXBUFSIZE((sc), (m))); \ 295 /* BIG_ENDIAN: no need to swap to store 0 */ \ 296 __rfa->rfa_status = 0; \ 297 __rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); \ 298 /* BIG_ENDIAN: no need to swap to store 0 */ \ 299 __rfa->actual_size = 0; \ 300 \ 301 /* NOTE: the RFA is misaligned, so we must copy. */ \ 302 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ \ 303 __v = 0xffffffff; \ 304 memcpy((void *)&__rfa->link_addr, &__v, sizeof(__v)); \ 305 memcpy((void *)&__rfa->rbd_addr, &__v, sizeof(__v)); \ 306 \ 307 FXP_RFASYNC((sc), (m), \ 308 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 309 \ 310 FXP_RXBUFSYNC((sc), (m), BUS_DMASYNC_PREREAD); \ 311 \ 312 if ((__p_m = (sc)->sc_rxq.ifq_tail) != NULL) { \ 313 __p_rfa = FXP_MTORFA(__p_m); \ 314 __v = htole32(__rxmap->dm_segs[0].ds_addr + \ 315 RFA_ALIGNMENT_FUDGE); \ 316 FXP_RFASYNC((sc), __p_m, \ 317 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); \ 318 memcpy((void *)&__p_rfa->link_addr, &__v, \ 319 sizeof(__v)); \ 320 __p_rfa->rfa_control &= htole16(~FXP_RFA_CONTROL_EL); \ 321 FXP_RFASYNC((sc), __p_m, \ 322 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 323 } \ 324 IF_ENQUEUE(&(sc)->sc_rxq, (m)); \ 325 } while (0) 326 327 /* Macros to ease CSR access. */ 328 #define CSR_READ_1(sc, reg) \ 329 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 330 #define CSR_READ_2(sc, reg) \ 331 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 332 #define CSR_READ_4(sc, reg) \ 333 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 334 #define CSR_WRITE_1(sc, reg, val) \ 335 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 336 #define CSR_WRITE_2(sc, reg, val) \ 337 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 338 #define CSR_WRITE_4(sc, reg, val) \ 339 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 340 341 void fxp_attach(struct fxp_softc *); 342 int fxp_activate(struct device *, enum devact); 343 int fxp_detach(struct fxp_softc *); 344 int fxp_intr(void *); 345 346 int fxp_enable(struct fxp_softc*); 347 void fxp_disable(struct fxp_softc*); 348