1 /* $NetBSD: i82557var.h,v 1.50 2012/02/02 19:43:03 tls Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, David Greenman 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice unmodified, this list of conditions, and the following 42 * disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58 * 59 * Id: if_fxpvar.h,v 1.4 1997/11/29 08:11:01 davidg Exp 60 */ 61 62 #include <sys/callout.h> 63 64 /* 65 * Misc. definitions for the Intel i82557 fast Ethernet controller 66 * driver. 67 */ 68 69 /* 70 * Transmit descriptor list size. 71 */ 72 #define FXP_NTXCB 256 73 #define FXP_NTXCB_MASK (FXP_NTXCB - 1) 74 #define FXP_NEXTTX(x) ((x + 1) & FXP_NTXCB_MASK) 75 #define FXP_NTXSEG 16 76 #define FXP_IPCB_NTXSEG (FXP_NTXSEG - 1) 77 78 /* 79 * Number of receive frame area buffers. These are large, so 80 * choose wisely. 81 */ 82 #define FXP_NRFABUFS 128 83 84 /* 85 * Maximum number of seconds that the receiver can be idle before we 86 * assume it's dead and attempt to reset it by reprogramming the 87 * multicast filter. This is part of a work-around for a bug in the 88 * NIC. See fxp_stats_update(). 89 */ 90 #define FXP_MAX_RX_IDLE 15 91 92 /* 93 * Misc. DMA'd data structures are allocated in a single clump, that 94 * maps to a single DMA segment, to make several things easier (computing 95 * offsets, setting up DMA maps, etc.) 96 */ 97 struct fxp_control_data { 98 /* 99 * The transmit control blocks and transmit buffer descriptors. 100 * We arrange them like this so that everything is all lined 101 * up to use the extended TxCB feature. 102 */ 103 struct fxp_txdesc { 104 struct fxp_cb_tx txd_txcb; 105 union { 106 struct fxp_ipcb txdu_ipcb; 107 struct fxp_tbd txdu_tbd[FXP_NTXSEG]; 108 } txd_u; 109 } fcd_txdescs[FXP_NTXCB]; 110 111 /* 112 * The configuration CB. 113 */ 114 struct fxp_cb_config fcd_configcb; 115 116 /* 117 * The Individual Address CB. 118 */ 119 struct fxp_cb_ias fcd_iascb; 120 121 /* 122 * The multicast setup CB. 123 */ 124 struct fxp_cb_mcs fcd_mcscb; 125 126 /* 127 * The microcode setup CB. 128 */ 129 struct fxp_cb_ucode fcd_ucode; 130 131 /* 132 * The NIC statistics. 133 */ 134 struct fxp_stats fcd_stats; 135 136 /* 137 * TX pad buffer for ip4csum-tx bug workaround. 138 */ 139 uint8_t fcd_txpad[FXP_IP4CSUMTX_PADLEN]; 140 }; 141 142 #define txd_tbd txd_u.txdu_tbd 143 144 #define FXP_CDOFF(x) offsetof(struct fxp_control_data, x) 145 #define FXP_CDTXOFF(x) FXP_CDOFF(fcd_txdescs[(x)].txd_txcb) 146 #define FXP_CDTBDOFF(x) FXP_CDOFF(fcd_txdescs[(x)].txd_tbd) 147 #define FXP_CDCONFIGOFF FXP_CDOFF(fcd_configcb) 148 #define FXP_CDIASOFF FXP_CDOFF(fcd_iascb) 149 #define FXP_CDMCSOFF FXP_CDOFF(fcd_mcscb) 150 #define FXP_CDUCODEOFF FXP_CDOFF(fcd_ucode) 151 #define FXP_CDSTATSOFF FXP_CDOFF(fcd_stats) 152 #define FXP_CDTXPADOFF FXP_CDOFF(fcd_txpad) 153 154 /* 155 * Software state for transmit descriptors. 156 */ 157 struct fxp_txsoft { 158 struct mbuf *txs_mbuf; /* head of mbuf chain */ 159 bus_dmamap_t txs_dmamap; /* our DMA map */ 160 }; 161 162 /* 163 * Software state per device. 164 */ 165 struct fxp_softc { 166 device_t sc_dev; 167 bus_space_tag_t sc_st; /* bus space tag */ 168 bus_space_handle_t sc_sh; /* bus space handle */ 169 bus_size_t sc_size; /* bus space size */ 170 bus_dma_tag_t sc_dmat; /* bus dma tag */ 171 struct ethercom sc_ethercom; /* ethernet common part */ 172 void *sc_ih; /* interrupt handler cookie */ 173 174 struct mii_data sc_mii; /* MII/media information */ 175 struct callout sc_callout; /* MII callout */ 176 177 /* 178 * We create a single DMA map that maps all data structure 179 * overhead, except for RFAs, which are mapped by the 180 * fxp_rxdesc DMA map on a per-mbuf basis. 181 */ 182 bus_dmamap_t sc_dmamap; 183 #define sc_cddma sc_dmamap->dm_segs[0].ds_addr 184 185 /* 186 * Software state for transmit descriptors. 187 */ 188 struct fxp_txsoft sc_txsoft[FXP_NTXCB]; 189 190 int sc_rfa_size; /* size of the RFA structure */ 191 struct ifqueue sc_rxq; /* receive buffer queue */ 192 bus_dmamap_t sc_rxmaps[FXP_NRFABUFS]; /* free receive buffer DMA maps */ 193 int sc_rxfree; /* free map index */ 194 int sc_rxidle; /* # of seconds RX has been idle */ 195 uint16_t sc_txcmd; /* transmit command (LITTLE ENDIAN) */ 196 197 /* 198 * Control data structures. 199 */ 200 struct fxp_control_data *sc_control_data; 201 202 #ifdef FXP_EVENT_COUNTERS 203 struct evcnt sc_ev_txstall; /* Tx stalled */ 204 struct evcnt sc_ev_txintr; /* Tx interrupts */ 205 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 206 struct evcnt sc_ev_txpause; /* Tx PAUSE frames */ 207 struct evcnt sc_ev_rxpause; /* Rx PAUSE frames */ 208 #endif /* FXP_EVENT_COUNTERS */ 209 210 bus_dma_segment_t sc_cdseg; /* control dma segment */ 211 int sc_cdnseg; 212 213 int sc_rev; /* chip revision */ 214 int sc_flags; /* misc. flags */ 215 216 #define FXPF_MII 0x0001 /* device uses MII */ 217 #define FXPF_ATTACHED 0x0002 /* attach has succeeded */ 218 #define FXPF_WANTINIT 0x0004 /* want a re-init */ 219 #define FXPF_HAS_RESUME_BUG 0x0008 /* has the resume bug */ 220 #define FXPF_MWI 0x0010 /* enable PCI MWI */ 221 #define FXPF_READ_ALIGN 0x0020 /* align read access w/ cacheline */ 222 #define FXPF_WRITE_ALIGN 0x0040 /* end write on cacheline */ 223 #define FXPF_EXT_TXCB 0x0080 /* has extended TxCB */ 224 #define FXPF_UCODE_LOADED 0x0100 /* microcode is loaded */ 225 #define FXPF_EXT_RFA 0x0200 /* has extended RFD and IPCB (82550) */ 226 #define FXPF_RECV_WORKAROUND 0x0800 /* receiver lock-up workaround */ 227 #define FXPF_FC 0x1000 /* has flow control */ 228 #define FXPF_82559_RXCSUM 0x2000 /* has 82559 compat RX checksum */ 229 230 int sc_int_delay; /* interrupt delay */ 231 int sc_bundle_max; /* max packet bundle */ 232 233 int sc_txpending; /* number of TX requests pending */ 234 int sc_txdirty; /* first dirty TX descriptor */ 235 int sc_txlast; /* last used TX descriptor */ 236 237 int phy_primary_device; /* device type of primary PHY */ 238 239 int sc_enabled; /* boolean; power enabled on interface */ 240 int (*sc_enable)(struct fxp_softc *); 241 void (*sc_disable)(struct fxp_softc *); 242 243 int sc_eeprom_size; /* log2 size of EEPROM */ 244 krndsource_t rnd_source; /* random source */ 245 }; 246 247 #ifdef FXP_EVENT_COUNTERS 248 #define FXP_EVCNT_INCR(ev) (ev)->ev_count++ 249 #else 250 #define FXP_EVCNT_INCR(ev) /* nothing */ 251 #endif 252 253 #define FXP_RXMAP_GET(sc) ((sc)->sc_rxmaps[(sc)->sc_rxfree++]) 254 #define FXP_RXMAP_PUT(sc, map) (sc)->sc_rxmaps[--(sc)->sc_rxfree] = (map) 255 256 #define FXP_CDTXADDR(sc, x) ((sc)->sc_cddma + FXP_CDTXOFF((x))) 257 #define FXP_CDTBDADDR(sc, x) ((sc)->sc_cddma + FXP_CDTBDOFF((x))) 258 #define FXP_CDTXPADADDR(sc) ((sc)->sc_cddma + FXP_CDTXPADOFF) 259 260 #define FXP_CDTX(sc, x) (&(sc)->sc_control_data->fcd_txdescs[(x)]) 261 262 #define FXP_DSTX(sc, x) (&(sc)->sc_txsoft[(x)]) 263 264 #define FXP_CDTXSYNC(sc, x, ops) \ 265 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 266 FXP_CDTXOFF((x)), sizeof(struct fxp_txdesc), (ops)) 267 268 #define FXP_CDCONFIGSYNC(sc, ops) \ 269 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 270 FXP_CDCONFIGOFF, sizeof(struct fxp_cb_config), (ops)) 271 272 #define FXP_CDIASSYNC(sc, ops) \ 273 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 274 FXP_CDIASOFF, sizeof(struct fxp_cb_ias), (ops)) 275 276 #define FXP_CDMCSSYNC(sc, ops) \ 277 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 278 FXP_CDMCSOFF, sizeof(struct fxp_cb_mcs), (ops)) 279 280 #define FXP_CDUCODESYNC(sc, ops) \ 281 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 282 FXP_CDUCODEOFF, sizeof(struct fxp_cb_ucode), (ops)) 283 284 #define FXP_CDSTATSSYNC(sc, ops) \ 285 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 286 FXP_CDSTATSOFF, sizeof(struct fxp_stats), (ops)) 287 288 #define FXP_RXBUFSIZE(sc, m) ((m)->m_ext.ext_size - \ 289 (sc->sc_rfa_size + \ 290 RFA_ALIGNMENT_FUDGE)) 291 292 #define FXP_RFASYNC(sc, m, ops) \ 293 bus_dmamap_sync((sc)->sc_dmat, M_GETCTX((m), bus_dmamap_t), \ 294 RFA_ALIGNMENT_FUDGE, (sc)->sc_rfa_size, (ops)) 295 296 #define FXP_RXBUFSYNC(sc, m, ops) \ 297 bus_dmamap_sync((sc)->sc_dmat, M_GETCTX((m), bus_dmamap_t), \ 298 RFA_ALIGNMENT_FUDGE + (sc)->sc_rfa_size, \ 299 FXP_RXBUFSIZE((sc), (m)), (ops)) 300 301 #define FXP_MTORFA(m) (struct fxp_rfa *)((m)->m_ext.ext_buf + \ 302 RFA_ALIGNMENT_FUDGE) 303 304 #define FXP_INIT_RFABUF(sc, m) \ 305 do { \ 306 bus_dmamap_t __rxmap = M_GETCTX((m), bus_dmamap_t); \ 307 struct mbuf *__p_m; \ 308 struct fxp_rfa *__rfa, *__p_rfa; \ 309 uint32_t __v; \ 310 \ 311 (m)->m_data = (m)->m_ext.ext_buf + (sc)->sc_rfa_size + \ 312 RFA_ALIGNMENT_FUDGE; \ 313 \ 314 __rfa = FXP_MTORFA((m)); \ 315 __rfa->size = htole16(FXP_RXBUFSIZE((sc), (m))); \ 316 /* BIG_ENDIAN: no need to swap to store 0 */ \ 317 __rfa->rfa_status = 0; \ 318 __rfa->rfa_control = \ 319 htole16(FXP_RFA_CONTROL_EL | FXP_RFA_CONTROL_S); \ 320 /* BIG_ENDIAN: no need to swap to store 0 */ \ 321 __rfa->actual_size = 0; \ 322 \ 323 /* NOTE: the RFA is misaligned, so we must copy. */ \ 324 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ \ 325 __v = 0xffffffff; \ 326 memcpy((void *)&__rfa->link_addr, &__v, sizeof(__v)); \ 327 memcpy((void *)&__rfa->rbd_addr, &__v, sizeof(__v)); \ 328 \ 329 FXP_RFASYNC((sc), (m), \ 330 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 331 \ 332 FXP_RXBUFSYNC((sc), (m), BUS_DMASYNC_PREREAD); \ 333 \ 334 if ((__p_m = (sc)->sc_rxq.ifq_tail) != NULL) { \ 335 __p_rfa = FXP_MTORFA(__p_m); \ 336 __v = htole32(__rxmap->dm_segs[0].ds_addr + \ 337 RFA_ALIGNMENT_FUDGE); \ 338 FXP_RFASYNC((sc), __p_m, \ 339 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); \ 340 memcpy((void *)&__p_rfa->link_addr, &__v, \ 341 sizeof(__v)); \ 342 __p_rfa->rfa_control &= htole16(~(FXP_RFA_CONTROL_EL| \ 343 FXP_RFA_CONTROL_S)); \ 344 FXP_RFASYNC((sc), __p_m, \ 345 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 346 } \ 347 IF_ENQUEUE(&(sc)->sc_rxq, (m)); \ 348 } while (0) 349 350 /* Macros to ease CSR access. */ 351 #define CSR_READ_1(sc, reg) \ 352 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 353 #define CSR_READ_2(sc, reg) \ 354 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 355 #define CSR_READ_4(sc, reg) \ 356 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 357 #define CSR_WRITE_1(sc, reg, val) \ 358 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 359 #define CSR_WRITE_2(sc, reg, val) \ 360 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 361 #define CSR_WRITE_4(sc, reg, val) \ 362 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 363 364 void fxp_attach(struct fxp_softc *); 365 int fxp_activate(device_t, enum devact); 366 int fxp_detach(struct fxp_softc *, int); 367 int fxp_intr(void *); 368 369 int fxp_enable(struct fxp_softc*); 370 void fxp_disable(struct fxp_softc*); 371