1 /* $NetBSD: i82557.c,v 1.136 2010/11/13 08:55:13 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, David Greenman 35 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice unmodified, this list of conditions, and the following 43 * disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 61 */ 62 63 /* 64 * Device driver for the Intel i82557 fast Ethernet controller, 65 * and its successors, the i82558 and i82559. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.136 2010/11/13 08:55:13 uebayasi Exp $"); 70 71 #include "rnd.h" 72 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/callout.h> 76 #include <sys/mbuf.h> 77 #include <sys/malloc.h> 78 #include <sys/kernel.h> 79 #include <sys/socket.h> 80 #include <sys/ioctl.h> 81 #include <sys/errno.h> 82 #include <sys/device.h> 83 #include <sys/syslog.h> 84 #include <sys/proc.h> 85 86 #include <machine/endian.h> 87 88 #if NRND > 0 89 #include <sys/rnd.h> 90 #endif 91 92 #include <net/if.h> 93 #include <net/if_dl.h> 94 #include <net/if_media.h> 95 #include <net/if_ether.h> 96 97 #include <netinet/in.h> 98 #include <netinet/in_systm.h> 99 #include <netinet/ip.h> 100 #include <netinet/tcp.h> 101 #include <netinet/udp.h> 102 103 #include <net/bpf.h> 104 105 #include <sys/bus.h> 106 #include <sys/intr.h> 107 108 #include <dev/mii/miivar.h> 109 110 #include <dev/ic/i82557reg.h> 111 #include <dev/ic/i82557var.h> 112 113 #include <dev/microcode/i8255x/rcvbundl.h> 114 115 /* 116 * NOTE! On the Alpha, we have an alignment constraint. The 117 * card DMAs the packet immediately following the RFA. However, 118 * the first thing in the packet is a 14-byte Ethernet header. 119 * This means that the packet is misaligned. To compensate, 120 * we actually offset the RFA 2 bytes into the cluster. This 121 * alignes the packet after the Ethernet header at a 32-bit 122 * boundary. HOWEVER! This means that the RFA is misaligned! 123 */ 124 #define RFA_ALIGNMENT_FUDGE 2 125 126 /* 127 * The configuration byte map has several undefined fields which 128 * must be one or must be zero. Set up a template for these bits 129 * only (assuming an i82557 chip), leaving the actual configuration 130 * for fxp_init(). 131 * 132 * See the definition of struct fxp_cb_config for the bit definitions. 133 */ 134 const uint8_t fxp_cb_config_template[] = { 135 0x0, 0x0, /* cb_status */ 136 0x0, 0x0, /* cb_command */ 137 0x0, 0x0, 0x0, 0x0, /* link_addr */ 138 0x0, /* 0 */ 139 0x0, /* 1 */ 140 0x0, /* 2 */ 141 0x0, /* 3 */ 142 0x0, /* 4 */ 143 0x0, /* 5 */ 144 0x32, /* 6 */ 145 0x0, /* 7 */ 146 0x0, /* 8 */ 147 0x0, /* 9 */ 148 0x6, /* 10 */ 149 0x0, /* 11 */ 150 0x0, /* 12 */ 151 0x0, /* 13 */ 152 0xf2, /* 14 */ 153 0x48, /* 15 */ 154 0x0, /* 16 */ 155 0x40, /* 17 */ 156 0xf0, /* 18 */ 157 0x0, /* 19 */ 158 0x3f, /* 20 */ 159 0x5, /* 21 */ 160 0x0, /* 22 */ 161 0x0, /* 23 */ 162 0x0, /* 24 */ 163 0x0, /* 25 */ 164 0x0, /* 26 */ 165 0x0, /* 27 */ 166 0x0, /* 28 */ 167 0x0, /* 29 */ 168 0x0, /* 30 */ 169 0x0, /* 31 */ 170 }; 171 172 void fxp_mii_initmedia(struct fxp_softc *); 173 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 174 175 void fxp_80c24_initmedia(struct fxp_softc *); 176 int fxp_80c24_mediachange(struct ifnet *); 177 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 178 179 void fxp_start(struct ifnet *); 180 int fxp_ioctl(struct ifnet *, u_long, void *); 181 void fxp_watchdog(struct ifnet *); 182 int fxp_init(struct ifnet *); 183 void fxp_stop(struct ifnet *, int); 184 185 void fxp_txintr(struct fxp_softc *); 186 int fxp_rxintr(struct fxp_softc *); 187 188 void fxp_rx_hwcksum(struct fxp_softc *,struct mbuf *, 189 const struct fxp_rfa *, u_int); 190 191 void fxp_rxdrain(struct fxp_softc *); 192 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 193 int fxp_mdi_read(device_t, int, int); 194 void fxp_statchg(device_t); 195 void fxp_mdi_write(device_t, int, int, int); 196 void fxp_autosize_eeprom(struct fxp_softc*); 197 void fxp_read_eeprom(struct fxp_softc *, uint16_t *, int, int); 198 void fxp_write_eeprom(struct fxp_softc *, uint16_t *, int, int); 199 void fxp_eeprom_update_cksum(struct fxp_softc *); 200 void fxp_get_info(struct fxp_softc *, uint8_t *); 201 void fxp_tick(void *); 202 void fxp_mc_setup(struct fxp_softc *); 203 void fxp_load_ucode(struct fxp_softc *); 204 205 int fxp_copy_small = 0; 206 207 /* 208 * Variables for interrupt mitigating microcode. 209 */ 210 int fxp_int_delay = 1000; /* usec */ 211 int fxp_bundle_max = 6; /* packets */ 212 213 struct fxp_phytype { 214 int fp_phy; /* type of PHY, -1 for MII at the end. */ 215 void (*fp_init)(struct fxp_softc *); 216 } fxp_phytype_table[] = { 217 { FXP_PHY_80C24, fxp_80c24_initmedia }, 218 { -1, fxp_mii_initmedia }, 219 }; 220 221 /* 222 * Set initial transmit threshold at 64 (512 bytes). This is 223 * increased by 64 (512 bytes) at a time, to maximum of 192 224 * (1536 bytes), if an underrun occurs. 225 */ 226 static int tx_threshold = 64; 227 228 /* 229 * Wait for the previous command to be accepted (but not necessarily 230 * completed). 231 */ 232 static inline void 233 fxp_scb_wait(struct fxp_softc *sc) 234 { 235 int i = 10000; 236 237 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 238 delay(2); 239 if (i == 0) 240 log(LOG_WARNING, 241 "%s: WARNING: SCB timed out!\n", device_xname(sc->sc_dev)); 242 } 243 244 /* 245 * Submit a command to the i82557. 246 */ 247 static inline void 248 fxp_scb_cmd(struct fxp_softc *sc, uint8_t cmd) 249 { 250 251 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 252 } 253 254 /* 255 * Finish attaching an i82557 interface. Called by bus-specific front-end. 256 */ 257 void 258 fxp_attach(struct fxp_softc *sc) 259 { 260 uint8_t enaddr[ETHER_ADDR_LEN]; 261 struct ifnet *ifp; 262 bus_dma_segment_t seg; 263 int rseg, i, error; 264 struct fxp_phytype *fp; 265 266 callout_init(&sc->sc_callout, 0); 267 268 /* 269 * Enable use of extended RFDs and IPCBs for 82550 and later chips. 270 * Note: to use IPCB we need extended TXCB support too, and 271 * these feature flags should be set in each bus attachment. 272 */ 273 if (sc->sc_flags & FXPF_EXT_RFA) { 274 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 275 sc->sc_rfa_size = RFA_EXT_SIZE; 276 } else { 277 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 278 sc->sc_rfa_size = RFA_SIZE; 279 } 280 281 /* 282 * Allocate the control data structures, and create and load the 283 * DMA map for it. 284 */ 285 if ((error = bus_dmamem_alloc(sc->sc_dmat, 286 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 287 0)) != 0) { 288 aprint_error_dev(sc->sc_dev, 289 "unable to allocate control data, error = %d\n", 290 error); 291 goto fail_0; 292 } 293 294 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 295 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 296 BUS_DMA_COHERENT)) != 0) { 297 aprint_error_dev(sc->sc_dev, 298 "unable to map control data, error = %d\n", error); 299 goto fail_1; 300 } 301 sc->sc_cdseg = seg; 302 sc->sc_cdnseg = rseg; 303 304 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 305 306 if ((error = bus_dmamap_create(sc->sc_dmat, 307 sizeof(struct fxp_control_data), 1, 308 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 309 aprint_error_dev(sc->sc_dev, 310 "unable to create control data DMA map, error = %d\n", 311 error); 312 goto fail_2; 313 } 314 315 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 316 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 317 0)) != 0) { 318 aprint_error_dev(sc->sc_dev, 319 "can't load control data DMA map, error = %d\n", 320 error); 321 goto fail_3; 322 } 323 324 /* 325 * Create the transmit buffer DMA maps. 326 */ 327 for (i = 0; i < FXP_NTXCB; i++) { 328 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 329 (sc->sc_flags & FXPF_EXT_RFA) ? 330 FXP_IPCB_NTXSEG : FXP_NTXSEG, 331 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 332 aprint_error_dev(sc->sc_dev, 333 "unable to create tx DMA map %d, error = %d\n", 334 i, error); 335 goto fail_4; 336 } 337 } 338 339 /* 340 * Create the receive buffer DMA maps. 341 */ 342 for (i = 0; i < FXP_NRFABUFS; i++) { 343 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 344 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 345 aprint_error_dev(sc->sc_dev, 346 "unable to create rx DMA map %d, error = %d\n", 347 i, error); 348 goto fail_5; 349 } 350 } 351 352 /* Initialize MAC address and media structures. */ 353 fxp_get_info(sc, enaddr); 354 355 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 356 ether_sprintf(enaddr)); 357 358 ifp = &sc->sc_ethercom.ec_if; 359 360 /* 361 * Get info about our media interface, and initialize it. Note 362 * the table terminates itself with a phy of -1, indicating 363 * that we're using MII. 364 */ 365 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 366 if (fp->fp_phy == sc->phy_primary_device) 367 break; 368 (*fp->fp_init)(sc); 369 370 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 371 ifp->if_softc = sc; 372 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 373 ifp->if_ioctl = fxp_ioctl; 374 ifp->if_start = fxp_start; 375 ifp->if_watchdog = fxp_watchdog; 376 ifp->if_init = fxp_init; 377 ifp->if_stop = fxp_stop; 378 IFQ_SET_READY(&ifp->if_snd); 379 380 if (sc->sc_flags & FXPF_EXT_RFA) { 381 /* 382 * Enable hardware cksum support by EXT_RFA and IPCB. 383 * 384 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 385 * at least, on i82550 rev.12. 386 * specifically, it doesn't set ipv4 checksum properly 387 * when sending UDP (and probably TCP) packets with 388 * 20 byte ipv4 header + 1 or 2 byte data, 389 * though ICMP packets seem working. 390 * FreeBSD driver has related comments. 391 * We've added a workaround to handle the bug by padding 392 * such packets manually. 393 */ 394 ifp->if_capabilities = 395 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 396 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 397 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 398 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 399 } else if (sc->sc_flags & FXPF_82559_RXCSUM) { 400 ifp->if_capabilities = 401 IFCAP_CSUM_TCPv4_Rx | 402 IFCAP_CSUM_UDPv4_Rx; 403 } 404 405 /* 406 * We can support 802.1Q VLAN-sized frames. 407 */ 408 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 409 410 /* 411 * Attach the interface. 412 */ 413 if_attach(ifp); 414 ether_ifattach(ifp, enaddr); 415 #if NRND > 0 416 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 417 RND_TYPE_NET, 0); 418 #endif 419 420 #ifdef FXP_EVENT_COUNTERS 421 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 422 NULL, device_xname(sc->sc_dev), "txstall"); 423 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 424 NULL, device_xname(sc->sc_dev), "txintr"); 425 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 426 NULL, device_xname(sc->sc_dev), "rxintr"); 427 if (sc->sc_flags & FXPF_FC) { 428 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 429 NULL, device_xname(sc->sc_dev), "txpause"); 430 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 431 NULL, device_xname(sc->sc_dev), "rxpause"); 432 } 433 #endif /* FXP_EVENT_COUNTERS */ 434 435 /* The attach is successful. */ 436 sc->sc_flags |= FXPF_ATTACHED; 437 438 return; 439 440 /* 441 * Free any resources we've allocated during the failed attach 442 * attempt. Do this in reverse order and fall though. 443 */ 444 fail_5: 445 for (i = 0; i < FXP_NRFABUFS; i++) { 446 if (sc->sc_rxmaps[i] != NULL) 447 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 448 } 449 fail_4: 450 for (i = 0; i < FXP_NTXCB; i++) { 451 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 452 bus_dmamap_destroy(sc->sc_dmat, 453 FXP_DSTX(sc, i)->txs_dmamap); 454 } 455 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 456 fail_3: 457 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 458 fail_2: 459 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 460 sizeof(struct fxp_control_data)); 461 fail_1: 462 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 463 fail_0: 464 return; 465 } 466 467 void 468 fxp_mii_initmedia(struct fxp_softc *sc) 469 { 470 int flags; 471 472 sc->sc_flags |= FXPF_MII; 473 474 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 475 sc->sc_mii.mii_readreg = fxp_mdi_read; 476 sc->sc_mii.mii_writereg = fxp_mdi_write; 477 sc->sc_mii.mii_statchg = fxp_statchg; 478 479 sc->sc_ethercom.ec_mii = &sc->sc_mii; 480 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 481 fxp_mii_mediastatus); 482 483 flags = MIIF_NOISOLATE; 484 if (sc->sc_flags & FXPF_FC) 485 flags |= MIIF_FORCEANEG|MIIF_DOPAUSE; 486 /* 487 * The i82557 wedges if all of its PHYs are isolated! 488 */ 489 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 490 MII_OFFSET_ANY, flags); 491 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 492 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 493 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 494 } else 495 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 496 } 497 498 void 499 fxp_80c24_initmedia(struct fxp_softc *sc) 500 { 501 502 /* 503 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 504 * doesn't have a programming interface of any sort. The 505 * media is sensed automatically based on how the link partner 506 * is configured. This is, in essence, manual configuration. 507 */ 508 aprint_normal_dev(sc->sc_dev, 509 "Seeq 80c24 AutoDUPLEX media interface present\n"); 510 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 511 fxp_80c24_mediastatus); 512 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 513 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 514 } 515 516 /* 517 * Initialize the interface media. 518 */ 519 void 520 fxp_get_info(struct fxp_softc *sc, uint8_t *enaddr) 521 { 522 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 523 524 /* 525 * Reset to a stable state. 526 */ 527 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 528 DELAY(100); 529 530 sc->sc_eeprom_size = 0; 531 fxp_autosize_eeprom(sc); 532 if (sc->sc_eeprom_size == 0) { 533 aprint_error_dev(sc->sc_dev, "failed to detect EEPROM size\n"); 534 sc->sc_eeprom_size = 6; /* XXX panic here? */ 535 } 536 #ifdef DEBUG 537 aprint_debug_dev(sc->sc_dev, "detected %d word EEPROM\n", 538 1 << sc->sc_eeprom_size); 539 #endif 540 541 /* 542 * Get info about the primary PHY 543 */ 544 fxp_read_eeprom(sc, &data, 6, 1); 545 sc->phy_primary_device = 546 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 547 548 /* 549 * Read MAC address. 550 */ 551 fxp_read_eeprom(sc, myea, 0, 3); 552 enaddr[0] = myea[0] & 0xff; 553 enaddr[1] = myea[0] >> 8; 554 enaddr[2] = myea[1] & 0xff; 555 enaddr[3] = myea[1] >> 8; 556 enaddr[4] = myea[2] & 0xff; 557 enaddr[5] = myea[2] >> 8; 558 559 /* 560 * Systems based on the ICH2/ICH2-M chip from Intel, as well 561 * as some i82559 designs, have a defect where the chip can 562 * cause a PCI protocol violation if it receives a CU_RESUME 563 * command when it is entering the IDLE state. 564 * 565 * The work-around is to disable Dynamic Standby Mode, so that 566 * the chip never deasserts #CLKRUN, and always remains in the 567 * active state. 568 * 569 * Unfortunately, the only way to disable Dynamic Standby is 570 * to frob an EEPROM setting and reboot (the EEPROM setting 571 * is only consulted when the PCI bus comes out of reset). 572 * 573 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 574 */ 575 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 576 fxp_read_eeprom(sc, &data, 10, 1); 577 if (data & 0x02) { /* STB enable */ 578 aprint_error_dev(sc->sc_dev, "WARNING: " 579 "Disabling dynamic standby mode in EEPROM " 580 "to work around a\n"); 581 aprint_normal_dev(sc->sc_dev, 582 "WARNING: hardware bug. You must reset " 583 "the system before using this\n"); 584 aprint_normal_dev(sc->sc_dev, "WARNING: interface.\n"); 585 data &= ~0x02; 586 fxp_write_eeprom(sc, &data, 10, 1); 587 aprint_normal_dev(sc->sc_dev, "new EEPROM ID: 0x%04x\n", 588 data); 589 fxp_eeprom_update_cksum(sc); 590 } 591 } 592 593 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 594 /* Due to false positives we make it conditional on setting link1 */ 595 fxp_read_eeprom(sc, &data, 3, 1); 596 if ((data & 0x03) != 0x03) { 597 aprint_verbose_dev(sc->sc_dev, 598 "May need receiver lock-up workaround\n"); 599 } 600 } 601 602 static void 603 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 604 { 605 uint16_t reg; 606 int x; 607 608 for (x = 1 << (len - 1); x != 0; x >>= 1) { 609 DELAY(40); 610 if (data & x) 611 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 612 else 613 reg = FXP_EEPROM_EECS; 614 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 615 DELAY(40); 616 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 617 reg | FXP_EEPROM_EESK); 618 DELAY(40); 619 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 620 } 621 DELAY(40); 622 } 623 624 /* 625 * Figure out EEPROM size. 626 * 627 * 559's can have either 64-word or 256-word EEPROMs, the 558 628 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 629 * talks about the existence of 16 to 256 word EEPROMs. 630 * 631 * The only known sizes are 64 and 256, where the 256 version is used 632 * by CardBus cards to store CIS information. 633 * 634 * The address is shifted in msb-to-lsb, and after the last 635 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 636 * after which follows the actual data. We try to detect this zero, by 637 * probing the data-out bit in the EEPROM control register just after 638 * having shifted in a bit. If the bit is zero, we assume we've 639 * shifted enough address bits. The data-out should be tri-state, 640 * before this, which should translate to a logical one. 641 * 642 * Other ways to do this would be to try to read a register with known 643 * contents with a varying number of address bits, but no such 644 * register seem to be available. The high bits of register 10 are 01 645 * on the 558 and 559, but apparently not on the 557. 646 * 647 * The Linux driver computes a checksum on the EEPROM data, but the 648 * value of this checksum is not very well documented. 649 */ 650 651 void 652 fxp_autosize_eeprom(struct fxp_softc *sc) 653 { 654 int x; 655 656 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 657 DELAY(40); 658 659 /* Shift in read opcode. */ 660 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 661 662 /* 663 * Shift in address, wait for the dummy zero following a correct 664 * address shift. 665 */ 666 for (x = 1; x <= 8; x++) { 667 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 668 DELAY(40); 669 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 670 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 671 DELAY(40); 672 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 673 FXP_EEPROM_EEDO) == 0) 674 break; 675 DELAY(40); 676 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 677 DELAY(40); 678 } 679 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 680 DELAY(40); 681 if (x != 6 && x != 8) { 682 #ifdef DEBUG 683 printf("%s: strange EEPROM size (%d)\n", 684 device_xname(sc->sc_dev), 1 << x); 685 #endif 686 } else 687 sc->sc_eeprom_size = x; 688 } 689 690 /* 691 * Read from the serial EEPROM. Basically, you manually shift in 692 * the read opcode (one bit at a time) and then shift in the address, 693 * and then you shift out the data (all of this one bit at a time). 694 * The word size is 16 bits, so you have to provide the address for 695 * every 16 bits of data. 696 */ 697 void 698 fxp_read_eeprom(struct fxp_softc *sc, uint16_t *data, int offset, int words) 699 { 700 uint16_t reg; 701 int i, x; 702 703 for (i = 0; i < words; i++) { 704 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 705 706 /* Shift in read opcode. */ 707 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 708 709 /* Shift in address. */ 710 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 711 712 reg = FXP_EEPROM_EECS; 713 data[i] = 0; 714 715 /* Shift out data. */ 716 for (x = 16; x > 0; x--) { 717 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 718 reg | FXP_EEPROM_EESK); 719 DELAY(40); 720 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 721 FXP_EEPROM_EEDO) 722 data[i] |= (1 << (x - 1)); 723 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 724 DELAY(40); 725 } 726 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 727 DELAY(40); 728 } 729 } 730 731 /* 732 * Write data to the serial EEPROM. 733 */ 734 void 735 fxp_write_eeprom(struct fxp_softc *sc, uint16_t *data, int offset, int words) 736 { 737 int i, j; 738 739 for (i = 0; i < words; i++) { 740 /* Erase/write enable. */ 741 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 742 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 743 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 744 sc->sc_eeprom_size); 745 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 746 DELAY(4); 747 748 /* Shift in write opcode, address, data. */ 749 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 750 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 751 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 752 fxp_eeprom_shiftin(sc, data[i], 16); 753 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 754 DELAY(4); 755 756 /* Wait for the EEPROM to finish up. */ 757 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 758 DELAY(4); 759 for (j = 0; j < 1000; j++) { 760 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 761 FXP_EEPROM_EEDO) 762 break; 763 DELAY(50); 764 } 765 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 766 DELAY(4); 767 768 /* Erase/write disable. */ 769 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 770 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 771 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 772 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 773 DELAY(4); 774 } 775 } 776 777 /* 778 * Update the checksum of the EEPROM. 779 */ 780 void 781 fxp_eeprom_update_cksum(struct fxp_softc *sc) 782 { 783 int i; 784 uint16_t data, cksum; 785 786 cksum = 0; 787 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 788 fxp_read_eeprom(sc, &data, i, 1); 789 cksum += data; 790 } 791 i = (1 << sc->sc_eeprom_size) - 1; 792 cksum = 0xbaba - cksum; 793 fxp_read_eeprom(sc, &data, i, 1); 794 fxp_write_eeprom(sc, &cksum, i, 1); 795 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 796 device_xname(sc->sc_dev), i, data, cksum); 797 } 798 799 /* 800 * Start packet transmission on the interface. 801 */ 802 void 803 fxp_start(struct ifnet *ifp) 804 { 805 struct fxp_softc *sc = ifp->if_softc; 806 struct mbuf *m0, *m; 807 struct fxp_txdesc *txd; 808 struct fxp_txsoft *txs; 809 bus_dmamap_t dmamap; 810 int error, lasttx, nexttx, opending, seg, nsegs, len; 811 812 /* 813 * If we want a re-init, bail out now. 814 */ 815 if (sc->sc_flags & FXPF_WANTINIT) { 816 ifp->if_flags |= IFF_OACTIVE; 817 return; 818 } 819 820 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 821 return; 822 823 /* 824 * Remember the previous txpending and the current lasttx. 825 */ 826 opending = sc->sc_txpending; 827 lasttx = sc->sc_txlast; 828 829 /* 830 * Loop through the send queue, setting up transmit descriptors 831 * until we drain the queue, or use up all available transmit 832 * descriptors. 833 */ 834 for (;;) { 835 struct fxp_tbd *tbdp; 836 int csum_flags; 837 838 /* 839 * Grab a packet off the queue. 840 */ 841 IFQ_POLL(&ifp->if_snd, m0); 842 if (m0 == NULL) 843 break; 844 m = NULL; 845 846 if (sc->sc_txpending == FXP_NTXCB - 1) { 847 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 848 break; 849 } 850 851 /* 852 * Get the next available transmit descriptor. 853 */ 854 nexttx = FXP_NEXTTX(sc->sc_txlast); 855 txd = FXP_CDTX(sc, nexttx); 856 txs = FXP_DSTX(sc, nexttx); 857 dmamap = txs->txs_dmamap; 858 859 /* 860 * Load the DMA map. If this fails, the packet either 861 * didn't fit in the allotted number of frags, or we were 862 * short on resources. In this case, we'll copy and try 863 * again. 864 */ 865 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 866 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 867 MGETHDR(m, M_DONTWAIT, MT_DATA); 868 if (m == NULL) { 869 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 870 device_xname(sc->sc_dev)); 871 break; 872 } 873 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 874 if (m0->m_pkthdr.len > MHLEN) { 875 MCLGET(m, M_DONTWAIT); 876 if ((m->m_flags & M_EXT) == 0) { 877 log(LOG_ERR, "%s: unable to allocate " 878 "Tx cluster\n", 879 device_xname(sc->sc_dev)); 880 m_freem(m); 881 break; 882 } 883 } 884 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 885 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 886 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 887 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 888 if (error) { 889 log(LOG_ERR, "%s: unable to load Tx buffer, " 890 "error = %d\n", 891 device_xname(sc->sc_dev), error); 892 break; 893 } 894 } 895 896 IFQ_DEQUEUE(&ifp->if_snd, m0); 897 csum_flags = m0->m_pkthdr.csum_flags; 898 if (m != NULL) { 899 m_freem(m0); 900 m0 = m; 901 } 902 903 /* Initialize the fraglist. */ 904 tbdp = txd->txd_tbd; 905 len = m0->m_pkthdr.len; 906 nsegs = dmamap->dm_nsegs; 907 if (sc->sc_flags & FXPF_EXT_RFA) 908 tbdp++; 909 for (seg = 0; seg < nsegs; seg++) { 910 tbdp[seg].tb_addr = 911 htole32(dmamap->dm_segs[seg].ds_addr); 912 tbdp[seg].tb_size = 913 htole32(dmamap->dm_segs[seg].ds_len); 914 } 915 if (__predict_false(len <= FXP_IP4CSUMTX_PADLEN && 916 (csum_flags & M_CSUM_IPv4) != 0)) { 917 /* 918 * Pad short packets to avoid ip4csum-tx bug. 919 * 920 * XXX Should we still consider if such short 921 * (36 bytes or less) packets might already 922 * occupy FXP_IPCB_NTXSEG (15) fragments here? 923 */ 924 KASSERT(nsegs < FXP_IPCB_NTXSEG); 925 nsegs++; 926 tbdp[seg].tb_addr = htole32(FXP_CDTXPADADDR(sc)); 927 tbdp[seg].tb_size = 928 htole32(FXP_IP4CSUMTX_PADLEN + 1 - len); 929 } 930 931 /* Sync the DMA map. */ 932 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 933 BUS_DMASYNC_PREWRITE); 934 935 /* 936 * Store a pointer to the packet so we can free it later. 937 */ 938 txs->txs_mbuf = m0; 939 940 /* 941 * Initialize the transmit descriptor. 942 */ 943 /* BIG_ENDIAN: no need to swap to store 0 */ 944 txd->txd_txcb.cb_status = 0; 945 txd->txd_txcb.cb_command = 946 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 947 txd->txd_txcb.tx_threshold = tx_threshold; 948 txd->txd_txcb.tbd_number = nsegs; 949 950 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 951 if (sc->sc_flags & FXPF_EXT_RFA) { 952 struct m_tag *vtag; 953 struct fxp_ipcb *ipcb; 954 /* 955 * Deal with TCP/IP checksum offload. Note that 956 * in order for TCP checksum offload to work, 957 * the pseudo header checksum must have already 958 * been computed and stored in the checksum field 959 * in the TCP header. The stack should have 960 * already done this for us. 961 */ 962 ipcb = &txd->txd_u.txdu_ipcb; 963 memset(ipcb, 0, sizeof(*ipcb)); 964 /* 965 * always do hardware parsing. 966 */ 967 ipcb->ipcb_ip_activation_high = 968 FXP_IPCB_HARDWAREPARSING_ENABLE; 969 /* 970 * ip checksum offloading. 971 */ 972 if (csum_flags & M_CSUM_IPv4) { 973 ipcb->ipcb_ip_schedule |= 974 FXP_IPCB_IP_CHECKSUM_ENABLE; 975 } 976 /* 977 * TCP/UDP checksum offloading. 978 */ 979 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 980 ipcb->ipcb_ip_schedule |= 981 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 982 } 983 984 /* 985 * request VLAN tag insertion if needed. 986 */ 987 vtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 988 if (vtag) { 989 ipcb->ipcb_vlan_id = 990 htobe16(*(u_int *)(vtag + 1)); 991 ipcb->ipcb_ip_activation_high |= 992 FXP_IPCB_INSERTVLAN_ENABLE; 993 } 994 } else { 995 KASSERT((csum_flags & 996 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 997 } 998 999 FXP_CDTXSYNC(sc, nexttx, 1000 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1001 1002 /* Advance the tx pointer. */ 1003 sc->sc_txpending++; 1004 sc->sc_txlast = nexttx; 1005 1006 /* 1007 * Pass packet to bpf if there is a listener. 1008 */ 1009 bpf_mtap(ifp, m0); 1010 } 1011 1012 if (sc->sc_txpending == FXP_NTXCB - 1) { 1013 /* No more slots; notify upper layer. */ 1014 ifp->if_flags |= IFF_OACTIVE; 1015 } 1016 1017 if (sc->sc_txpending != opending) { 1018 /* 1019 * We enqueued packets. If the transmitter was idle, 1020 * reset the txdirty pointer. 1021 */ 1022 if (opending == 0) 1023 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1024 1025 /* 1026 * Cause the chip to interrupt and suspend command 1027 * processing once the last packet we've enqueued 1028 * has been transmitted. 1029 * 1030 * To avoid a race between updating status bits 1031 * by the fxp chip and clearing command bits 1032 * by this function on machines which don't have 1033 * atomic methods to clear/set bits in memory 1034 * smaller than 32bits (both cb_status and cb_command 1035 * members are uint16_t and in the same 32bit word), 1036 * we have to prepare a dummy TX descriptor which has 1037 * NOP command and just causes a TX completion interrupt. 1038 */ 1039 sc->sc_txpending++; 1040 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1041 txd = FXP_CDTX(sc, sc->sc_txlast); 1042 /* BIG_ENDIAN: no need to swap to store 0 */ 1043 txd->txd_txcb.cb_status = 0; 1044 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1045 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1046 FXP_CDTXSYNC(sc, sc->sc_txlast, 1047 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1048 1049 /* 1050 * The entire packet chain is set up. Clear the suspend bit 1051 * on the command prior to the first packet we set up. 1052 */ 1053 FXP_CDTXSYNC(sc, lasttx, 1054 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1055 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1056 htole16(~FXP_CB_COMMAND_S); 1057 FXP_CDTXSYNC(sc, lasttx, 1058 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1059 1060 /* 1061 * Issue a Resume command in case the chip was suspended. 1062 */ 1063 fxp_scb_wait(sc); 1064 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1065 1066 /* Set a watchdog timer in case the chip flakes out. */ 1067 ifp->if_timer = 5; 1068 } 1069 } 1070 1071 /* 1072 * Process interface interrupts. 1073 */ 1074 int 1075 fxp_intr(void *arg) 1076 { 1077 struct fxp_softc *sc = arg; 1078 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1079 bus_dmamap_t rxmap; 1080 int claimed = 0, rnr; 1081 uint8_t statack; 1082 1083 if (!device_is_active(sc->sc_dev) || sc->sc_enabled == 0) 1084 return (0); 1085 /* 1086 * If the interface isn't running, don't try to 1087 * service the interrupt.. just ack it and bail. 1088 */ 1089 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1090 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1091 if (statack) { 1092 claimed = 1; 1093 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1094 } 1095 return (claimed); 1096 } 1097 1098 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1099 claimed = 1; 1100 1101 /* 1102 * First ACK all the interrupts in this pass. 1103 */ 1104 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1105 1106 /* 1107 * Process receiver interrupts. If a no-resource (RNR) 1108 * condition exists, get whatever packets we can and 1109 * re-start the receiver. 1110 */ 1111 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1112 1 : 0; 1113 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1114 FXP_SCB_STATACK_SWI)) { 1115 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1116 rnr |= fxp_rxintr(sc); 1117 } 1118 1119 /* 1120 * Free any finished transmit mbuf chains. 1121 */ 1122 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1123 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1124 fxp_txintr(sc); 1125 1126 /* 1127 * Try to get more packets going. 1128 */ 1129 fxp_start(ifp); 1130 1131 if (sc->sc_txpending == 0) { 1132 /* 1133 * Tell them that they can re-init now. 1134 */ 1135 if (sc->sc_flags & FXPF_WANTINIT) 1136 wakeup(sc); 1137 } 1138 } 1139 1140 if (rnr) { 1141 fxp_scb_wait(sc); 1142 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1143 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1144 fxp_scb_wait(sc); 1145 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1146 rxmap->dm_segs[0].ds_addr + 1147 RFA_ALIGNMENT_FUDGE); 1148 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1149 } 1150 } 1151 1152 #if NRND > 0 1153 if (claimed) 1154 rnd_add_uint32(&sc->rnd_source, statack); 1155 #endif 1156 return (claimed); 1157 } 1158 1159 /* 1160 * Handle transmit completion interrupts. 1161 */ 1162 void 1163 fxp_txintr(struct fxp_softc *sc) 1164 { 1165 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1166 struct fxp_txdesc *txd; 1167 struct fxp_txsoft *txs; 1168 int i; 1169 uint16_t txstat; 1170 1171 ifp->if_flags &= ~IFF_OACTIVE; 1172 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1173 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1174 txd = FXP_CDTX(sc, i); 1175 txs = FXP_DSTX(sc, i); 1176 1177 FXP_CDTXSYNC(sc, i, 1178 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1179 1180 /* skip dummy NOP TX descriptor */ 1181 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1182 == FXP_CB_COMMAND_NOP) 1183 continue; 1184 1185 txstat = le16toh(txd->txd_txcb.cb_status); 1186 1187 if ((txstat & FXP_CB_STATUS_C) == 0) 1188 break; 1189 1190 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1191 0, txs->txs_dmamap->dm_mapsize, 1192 BUS_DMASYNC_POSTWRITE); 1193 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1194 m_freem(txs->txs_mbuf); 1195 txs->txs_mbuf = NULL; 1196 } 1197 1198 /* Update the dirty transmit buffer pointer. */ 1199 sc->sc_txdirty = i; 1200 1201 /* 1202 * Cancel the watchdog timer if there are no pending 1203 * transmissions. 1204 */ 1205 if (sc->sc_txpending == 0) 1206 ifp->if_timer = 0; 1207 } 1208 1209 /* 1210 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1211 */ 1212 1213 void 1214 fxp_rx_hwcksum(struct fxp_softc *sc, struct mbuf *m, const struct fxp_rfa *rfa, 1215 u_int len) 1216 { 1217 uint32_t csum_data; 1218 int csum_flags; 1219 1220 /* 1221 * check H/W Checksumming. 1222 */ 1223 1224 csum_flags = 0; 1225 csum_data = 0; 1226 1227 if ((sc->sc_flags & FXPF_EXT_RFA) != 0) { 1228 uint8_t rxparsestat; 1229 uint8_t csum_stat; 1230 1231 csum_stat = rfa->cksum_stat; 1232 rxparsestat = rfa->rx_parse_stat; 1233 if ((rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE)) == 0) 1234 goto out; 1235 1236 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1237 csum_flags = M_CSUM_IPv4; 1238 if ((csum_stat & FXP_RFDX_CS_IP_CSUM_VALID) == 0) 1239 csum_flags |= M_CSUM_IPv4_BAD; 1240 } 1241 1242 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1243 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1244 if ((csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID) == 0) 1245 csum_flags |= M_CSUM_TCP_UDP_BAD; 1246 } 1247 1248 } else if ((sc->sc_flags & FXPF_82559_RXCSUM) != 0) { 1249 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1250 struct ether_header *eh; 1251 struct ip *ip; 1252 struct udphdr *uh; 1253 u_int hlen, pktlen; 1254 1255 if (len < ETHER_HDR_LEN + sizeof(struct ip)) 1256 goto out; 1257 pktlen = len - ETHER_HDR_LEN; 1258 eh = mtod(m, struct ether_header *); 1259 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1260 goto out; 1261 ip = (struct ip *)((uint8_t *)eh + ETHER_HDR_LEN); 1262 if (ip->ip_v != IPVERSION) 1263 goto out; 1264 1265 hlen = ip->ip_hl << 2; 1266 if (hlen < sizeof(struct ip)) 1267 goto out; 1268 1269 /* 1270 * Bail if too short, has random trailing garbage, truncated, 1271 * fragment, or has ethernet pad. 1272 */ 1273 if (ntohs(ip->ip_len) < hlen || 1274 ntohs(ip->ip_len) != pktlen || 1275 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 1276 goto out; 1277 1278 switch (ip->ip_p) { 1279 case IPPROTO_TCP: 1280 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0 || 1281 pktlen < (hlen + sizeof(struct tcphdr))) 1282 goto out; 1283 csum_flags = 1284 M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1285 break; 1286 case IPPROTO_UDP: 1287 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0 || 1288 pktlen < (hlen + sizeof(struct udphdr))) 1289 goto out; 1290 uh = (struct udphdr *)((uint8_t *)ip + hlen); 1291 if (uh->uh_sum == 0) 1292 goto out; /* no checksum */ 1293 csum_flags = 1294 M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1295 break; 1296 default: 1297 goto out; 1298 } 1299 1300 /* Extract computed checksum. */ 1301 csum_data = be16dec(mtod(m, uint8_t *) + len); 1302 1303 /* 1304 * The computed checksum includes IP headers, 1305 * so we have to deduct them. 1306 */ 1307 #if 0 1308 /* 1309 * But in TCP/UDP layer we can assume the IP header is valid, 1310 * i.e. a sum of the whole IP header should be 0xffff, 1311 * so we don't have to bother to deduct it. 1312 */ 1313 if (hlen > 0) { 1314 uint32_t hsum; 1315 const uint16_t *iphdr; 1316 hsum = 0; 1317 iphdr = (uint16_t *)ip; 1318 1319 while (hlen > 1) { 1320 hsum += ntohs(*iphdr++); 1321 hlen -= sizeof(uint16_t); 1322 } 1323 while (hsum >> 16) 1324 hsum = (hsum >> 16) + (hsum & 0xffff); 1325 1326 csum_data += (uint16_t)~hsum; 1327 1328 while (csum_data >> 16) 1329 csum_data = 1330 (csum_data >> 16) + (csum_data & 0xffff); 1331 } 1332 #endif 1333 } 1334 out: 1335 m->m_pkthdr.csum_flags = csum_flags; 1336 m->m_pkthdr.csum_data = csum_data; 1337 } 1338 1339 /* 1340 * Handle receive interrupts. 1341 */ 1342 int 1343 fxp_rxintr(struct fxp_softc *sc) 1344 { 1345 struct ethercom *ec = &sc->sc_ethercom; 1346 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1347 struct mbuf *m, *m0; 1348 bus_dmamap_t rxmap; 1349 struct fxp_rfa *rfa; 1350 int rnr; 1351 uint16_t len, rxstat; 1352 1353 rnr = 0; 1354 1355 for (;;) { 1356 m = sc->sc_rxq.ifq_head; 1357 rfa = FXP_MTORFA(m); 1358 rxmap = M_GETCTX(m, bus_dmamap_t); 1359 1360 FXP_RFASYNC(sc, m, 1361 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1362 1363 rxstat = le16toh(rfa->rfa_status); 1364 1365 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1366 rnr = 1; 1367 1368 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1369 /* 1370 * We have processed all of the 1371 * receive buffers. 1372 */ 1373 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1374 return rnr; 1375 } 1376 1377 IF_DEQUEUE(&sc->sc_rxq, m); 1378 1379 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1380 1381 len = le16toh(rfa->actual_size) & 1382 (m->m_ext.ext_size - 1); 1383 if ((sc->sc_flags & FXPF_82559_RXCSUM) != 0) { 1384 /* Adjust for appended checksum bytes. */ 1385 len -= sizeof(uint16_t); 1386 } 1387 1388 if (len < sizeof(struct ether_header)) { 1389 /* 1390 * Runt packet; drop it now. 1391 */ 1392 FXP_INIT_RFABUF(sc, m); 1393 continue; 1394 } 1395 1396 /* 1397 * If support for 802.1Q VLAN sized frames is 1398 * enabled, we need to do some additional error 1399 * checking (as we are saving bad frames, in 1400 * order to receive the larger ones). 1401 */ 1402 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1403 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1404 FXP_RFA_STATUS_RNR| 1405 FXP_RFA_STATUS_ALIGN| 1406 FXP_RFA_STATUS_CRC)) != 0) { 1407 FXP_INIT_RFABUF(sc, m); 1408 continue; 1409 } 1410 1411 /* 1412 * check VLAN tag stripping. 1413 */ 1414 if ((sc->sc_flags & FXPF_EXT_RFA) != 0 && 1415 (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) != 0) { 1416 struct m_tag *vtag; 1417 1418 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 1419 M_NOWAIT); 1420 if (vtag == NULL) 1421 goto dropit; 1422 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1423 m_tag_prepend(m, vtag); 1424 } 1425 1426 /* Do checksum checking. */ 1427 if ((ifp->if_csum_flags_rx & (M_CSUM_TCPv4|M_CSUM_UDPv4)) != 0) 1428 fxp_rx_hwcksum(sc, m, rfa, len); 1429 1430 /* 1431 * If the packet is small enough to fit in a 1432 * single header mbuf, allocate one and copy 1433 * the data into it. This greatly reduces 1434 * memory consumption when we receive lots 1435 * of small packets. 1436 * 1437 * Otherwise, we add a new buffer to the receive 1438 * chain. If this fails, we drop the packet and 1439 * recycle the old buffer. 1440 */ 1441 if (fxp_copy_small != 0 && len <= MHLEN) { 1442 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1443 if (m0 == NULL) 1444 goto dropit; 1445 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1446 memcpy(mtod(m0, void *), 1447 mtod(m, void *), len); 1448 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1449 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1450 FXP_INIT_RFABUF(sc, m); 1451 m = m0; 1452 } else { 1453 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1454 dropit: 1455 ifp->if_ierrors++; 1456 FXP_INIT_RFABUF(sc, m); 1457 continue; 1458 } 1459 } 1460 1461 m->m_pkthdr.rcvif = ifp; 1462 m->m_pkthdr.len = m->m_len = len; 1463 1464 /* 1465 * Pass this up to any BPF listeners, but only 1466 * pass it up the stack if it's for us. 1467 */ 1468 bpf_mtap(ifp, m); 1469 1470 /* Pass it on. */ 1471 (*ifp->if_input)(ifp, m); 1472 } 1473 } 1474 1475 /* 1476 * Update packet in/out/collision statistics. The i82557 doesn't 1477 * allow you to access these counters without doing a fairly 1478 * expensive DMA to get _all_ of the statistics it maintains, so 1479 * we do this operation here only once per second. The statistics 1480 * counters in the kernel are updated from the previous dump-stats 1481 * DMA and then a new dump-stats DMA is started. The on-chip 1482 * counters are zeroed when the DMA completes. If we can't start 1483 * the DMA immediately, we don't wait - we just prepare to read 1484 * them again next time. 1485 */ 1486 void 1487 fxp_tick(void *arg) 1488 { 1489 struct fxp_softc *sc = arg; 1490 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1491 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1492 int s; 1493 1494 if (!device_is_active(sc->sc_dev)) 1495 return; 1496 1497 s = splnet(); 1498 1499 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1500 1501 ifp->if_opackets += le32toh(sp->tx_good); 1502 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1503 if (sp->rx_good) { 1504 ifp->if_ipackets += le32toh(sp->rx_good); 1505 sc->sc_rxidle = 0; 1506 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1507 sc->sc_rxidle++; 1508 } 1509 ifp->if_ierrors += 1510 le32toh(sp->rx_crc_errors) + 1511 le32toh(sp->rx_alignment_errors) + 1512 le32toh(sp->rx_rnr_errors) + 1513 le32toh(sp->rx_overrun_errors); 1514 /* 1515 * If any transmit underruns occurred, bump up the transmit 1516 * threshold by another 512 bytes (64 * 8). 1517 */ 1518 if (sp->tx_underruns) { 1519 ifp->if_oerrors += le32toh(sp->tx_underruns); 1520 if (tx_threshold < 192) 1521 tx_threshold += 64; 1522 } 1523 #ifdef FXP_EVENT_COUNTERS 1524 if (sc->sc_flags & FXPF_FC) { 1525 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1526 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1527 } 1528 #endif 1529 1530 /* 1531 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1532 * then assume the receiver has locked up and attempt to clear 1533 * the condition by reprogramming the multicast filter (actually, 1534 * resetting the interface). This is a work-around for a bug in 1535 * the 82557 where the receiver locks up if it gets certain types 1536 * of garbage in the synchronization bits prior to the packet header. 1537 * This bug is supposed to only occur in 10Mbps mode, but has been 1538 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1539 * speed transition). 1540 */ 1541 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1542 (void) fxp_init(ifp); 1543 splx(s); 1544 return; 1545 } 1546 /* 1547 * If there is no pending command, start another stats 1548 * dump. Otherwise punt for now. 1549 */ 1550 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1551 /* 1552 * Start another stats dump. 1553 */ 1554 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1555 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1556 } else { 1557 /* 1558 * A previous command is still waiting to be accepted. 1559 * Just zero our copy of the stats and wait for the 1560 * next timer event to update them. 1561 */ 1562 /* BIG_ENDIAN: no swap required to store 0 */ 1563 sp->tx_good = 0; 1564 sp->tx_underruns = 0; 1565 sp->tx_total_collisions = 0; 1566 1567 sp->rx_good = 0; 1568 sp->rx_crc_errors = 0; 1569 sp->rx_alignment_errors = 0; 1570 sp->rx_rnr_errors = 0; 1571 sp->rx_overrun_errors = 0; 1572 if (sc->sc_flags & FXPF_FC) { 1573 sp->tx_pauseframes = 0; 1574 sp->rx_pauseframes = 0; 1575 } 1576 } 1577 1578 if (sc->sc_flags & FXPF_MII) { 1579 /* Tick the MII clock. */ 1580 mii_tick(&sc->sc_mii); 1581 } 1582 1583 splx(s); 1584 1585 /* 1586 * Schedule another timeout one second from now. 1587 */ 1588 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1589 } 1590 1591 /* 1592 * Drain the receive queue. 1593 */ 1594 void 1595 fxp_rxdrain(struct fxp_softc *sc) 1596 { 1597 bus_dmamap_t rxmap; 1598 struct mbuf *m; 1599 1600 for (;;) { 1601 IF_DEQUEUE(&sc->sc_rxq, m); 1602 if (m == NULL) 1603 break; 1604 rxmap = M_GETCTX(m, bus_dmamap_t); 1605 bus_dmamap_unload(sc->sc_dmat, rxmap); 1606 FXP_RXMAP_PUT(sc, rxmap); 1607 m_freem(m); 1608 } 1609 } 1610 1611 /* 1612 * Stop the interface. Cancels the statistics updater and resets 1613 * the interface. 1614 */ 1615 void 1616 fxp_stop(struct ifnet *ifp, int disable) 1617 { 1618 struct fxp_softc *sc = ifp->if_softc; 1619 struct fxp_txsoft *txs; 1620 int i; 1621 1622 /* 1623 * Turn down interface (done early to avoid bad interactions 1624 * between panics, shutdown hooks, and the watchdog timer) 1625 */ 1626 ifp->if_timer = 0; 1627 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1628 1629 /* 1630 * Cancel stats updater. 1631 */ 1632 callout_stop(&sc->sc_callout); 1633 if (sc->sc_flags & FXPF_MII) { 1634 /* Down the MII. */ 1635 mii_down(&sc->sc_mii); 1636 } 1637 1638 /* 1639 * Issue software reset. This unloads any microcode that 1640 * might already be loaded. 1641 */ 1642 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1643 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1644 DELAY(50); 1645 1646 /* 1647 * Release any xmit buffers. 1648 */ 1649 for (i = 0; i < FXP_NTXCB; i++) { 1650 txs = FXP_DSTX(sc, i); 1651 if (txs->txs_mbuf != NULL) { 1652 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1653 m_freem(txs->txs_mbuf); 1654 txs->txs_mbuf = NULL; 1655 } 1656 } 1657 sc->sc_txpending = 0; 1658 1659 if (disable) { 1660 fxp_rxdrain(sc); 1661 fxp_disable(sc); 1662 } 1663 1664 } 1665 1666 /* 1667 * Watchdog/transmission transmit timeout handler. Called when a 1668 * transmission is started on the interface, but no interrupt is 1669 * received before the timeout. This usually indicates that the 1670 * card has wedged for some reason. 1671 */ 1672 void 1673 fxp_watchdog(struct ifnet *ifp) 1674 { 1675 struct fxp_softc *sc = ifp->if_softc; 1676 1677 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1678 ifp->if_oerrors++; 1679 1680 (void) fxp_init(ifp); 1681 } 1682 1683 /* 1684 * Initialize the interface. Must be called at splnet(). 1685 */ 1686 int 1687 fxp_init(struct ifnet *ifp) 1688 { 1689 struct fxp_softc *sc = ifp->if_softc; 1690 struct fxp_cb_config *cbp; 1691 struct fxp_cb_ias *cb_ias; 1692 struct fxp_txdesc *txd; 1693 bus_dmamap_t rxmap; 1694 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1695 uint16_t status; 1696 1697 if ((error = fxp_enable(sc)) != 0) 1698 goto out; 1699 1700 /* 1701 * Cancel any pending I/O 1702 */ 1703 fxp_stop(ifp, 0); 1704 1705 /* 1706 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1707 * flag, and this prevents the MII from detaching resulting in 1708 * a panic. The flags field should perhaps be split in runtime 1709 * flags and more static information. For now, just clear the 1710 * only other flag set. 1711 */ 1712 1713 sc->sc_flags &= ~FXPF_WANTINIT; 1714 1715 /* 1716 * Initialize base of CBL and RFA memory. Loading with zero 1717 * sets it up for regular linear addressing. 1718 */ 1719 fxp_scb_wait(sc); 1720 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1721 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1722 1723 fxp_scb_wait(sc); 1724 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1725 1726 /* 1727 * Initialize the multicast filter. Do this now, since we might 1728 * have to setup the config block differently. 1729 */ 1730 fxp_mc_setup(sc); 1731 1732 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1733 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1734 1735 /* 1736 * In order to support receiving 802.1Q VLAN frames, we have to 1737 * enable "save bad frames", since they are 4 bytes larger than 1738 * the normal Ethernet maximum frame length. On i82558 and later, 1739 * we have a better mechanism for this. 1740 */ 1741 save_bf = 0; 1742 lrxen = 0; 1743 vlan_drop = 0; 1744 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1745 if (sc->sc_rev < FXP_REV_82558_A4) 1746 save_bf = 1; 1747 else 1748 lrxen = 1; 1749 if (sc->sc_rev >= FXP_REV_82550) 1750 vlan_drop = 1; 1751 } 1752 1753 /* 1754 * Initialize base of dump-stats buffer. 1755 */ 1756 fxp_scb_wait(sc); 1757 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1758 sc->sc_cddma + FXP_CDSTATSOFF); 1759 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1760 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1761 1762 cbp = &sc->sc_control_data->fcd_configcb; 1763 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1764 1765 /* 1766 * Load microcode for this controller. 1767 */ 1768 fxp_load_ucode(sc); 1769 1770 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1771 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1772 else 1773 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1774 1775 /* 1776 * This copy is kind of disgusting, but there are a bunch of must be 1777 * zero and must be one bits in this structure and this is the easiest 1778 * way to initialize them all to proper values. 1779 */ 1780 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1781 1782 /* BIG_ENDIAN: no need to swap to store 0 */ 1783 cbp->cb_status = 0; 1784 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1785 FXP_CB_COMMAND_EL); 1786 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1787 cbp->link_addr = 0xffffffff; /* (no) next command */ 1788 /* bytes in config block */ 1789 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1790 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1791 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1792 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1793 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1794 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1795 cbp->type_enable = 0; /* actually reserved */ 1796 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1797 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1798 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1799 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1800 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1801 cbp->late_scb = 0; /* (don't) defer SCB update */ 1802 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1803 cbp->ci_int = 1; /* interrupt on CU idle */ 1804 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1805 cbp->ext_stats_dis = 1; /* disable extended counters */ 1806 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1807 cbp->save_bf = save_bf;/* save bad frames */ 1808 cbp->disc_short_rx = !prm; /* discard short packets */ 1809 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1810 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1811 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1812 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1813 /* interface mode */ 1814 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1815 cbp->csma_dis = 0; /* (don't) disable link */ 1816 cbp->tcp_udp_cksum = (sc->sc_flags & FXPF_82559_RXCSUM) ? 1 : 0; 1817 /* (don't) enable RX checksum */ 1818 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1819 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1820 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1821 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1822 cbp->nsai = 1; /* (don't) disable source addr insert */ 1823 cbp->preamble_length = 2; /* (7 byte) preamble */ 1824 cbp->loopback = 0; /* (don't) loopback */ 1825 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1826 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1827 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1828 cbp->promiscuous = prm; /* promiscuous mode */ 1829 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1830 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1831 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1832 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1833 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1834 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1835 cbp->padding = 1; /* (do) pad short tx packets */ 1836 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1837 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1838 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1839 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1840 /* must set wake_en in PMCSR also */ 1841 cbp->force_fdx = 0; /* (don't) force full duplex */ 1842 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1843 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1844 cbp->mc_all = allm; /* accept all multicasts */ 1845 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1846 cbp->vlan_drop_en = vlan_drop; 1847 1848 if (!(sc->sc_flags & FXPF_FC)) { 1849 /* 1850 * The i82557 has no hardware flow control, the values 1851 * here are the defaults for the chip. 1852 */ 1853 cbp->fc_delay_lsb = 0; 1854 cbp->fc_delay_msb = 0x40; 1855 cbp->pri_fc_thresh = 3; 1856 cbp->tx_fc_dis = 0; 1857 cbp->rx_fc_restop = 0; 1858 cbp->rx_fc_restart = 0; 1859 cbp->fc_filter = 0; 1860 cbp->pri_fc_loc = 1; 1861 } else { 1862 cbp->fc_delay_lsb = 0x1f; 1863 cbp->fc_delay_msb = 0x01; 1864 cbp->pri_fc_thresh = 3; 1865 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1866 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1867 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1868 cbp->fc_filter = !prm; /* drop FC frames to host */ 1869 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1870 cbp->ext_stats_dis = 0; /* enable extended stats */ 1871 } 1872 1873 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1874 1875 /* 1876 * Start the config command/DMA. 1877 */ 1878 fxp_scb_wait(sc); 1879 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1880 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1881 /* ...and wait for it to complete. */ 1882 for (i = 1000; i > 0; i--) { 1883 FXP_CDCONFIGSYNC(sc, 1884 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1885 status = le16toh(cbp->cb_status); 1886 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD); 1887 if ((status & FXP_CB_STATUS_C) != 0) 1888 break; 1889 DELAY(1); 1890 } 1891 if (i == 0) { 1892 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1893 device_xname(sc->sc_dev), __LINE__); 1894 return (ETIMEDOUT); 1895 } 1896 1897 /* 1898 * Initialize the station address. 1899 */ 1900 cb_ias = &sc->sc_control_data->fcd_iascb; 1901 /* BIG_ENDIAN: no need to swap to store 0 */ 1902 cb_ias->cb_status = 0; 1903 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1904 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1905 cb_ias->link_addr = 0xffffffff; 1906 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1907 1908 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1909 1910 /* 1911 * Start the IAS (Individual Address Setup) command/DMA. 1912 */ 1913 fxp_scb_wait(sc); 1914 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1915 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1916 /* ...and wait for it to complete. */ 1917 for (i = 1000; i > 0; i++) { 1918 FXP_CDIASSYNC(sc, 1919 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1920 status = le16toh(cb_ias->cb_status); 1921 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD); 1922 if ((status & FXP_CB_STATUS_C) != 0) 1923 break; 1924 DELAY(1); 1925 } 1926 if (i == 0) { 1927 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1928 device_xname(sc->sc_dev), __LINE__); 1929 return (ETIMEDOUT); 1930 } 1931 1932 /* 1933 * Initialize the transmit descriptor ring. txlast is initialized 1934 * to the end of the list so that it will wrap around to the first 1935 * descriptor when the first packet is transmitted. 1936 */ 1937 for (i = 0; i < FXP_NTXCB; i++) { 1938 txd = FXP_CDTX(sc, i); 1939 memset(txd, 0, sizeof(*txd)); 1940 txd->txd_txcb.cb_command = 1941 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1942 txd->txd_txcb.link_addr = 1943 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1944 if (sc->sc_flags & FXPF_EXT_TXCB) 1945 txd->txd_txcb.tbd_array_addr = 1946 htole32(FXP_CDTBDADDR(sc, i) + 1947 (2 * sizeof(struct fxp_tbd))); 1948 else 1949 txd->txd_txcb.tbd_array_addr = 1950 htole32(FXP_CDTBDADDR(sc, i)); 1951 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1952 } 1953 sc->sc_txpending = 0; 1954 sc->sc_txdirty = 0; 1955 sc->sc_txlast = FXP_NTXCB - 1; 1956 1957 /* 1958 * Initialize the receive buffer list. 1959 */ 1960 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1961 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1962 rxmap = FXP_RXMAP_GET(sc); 1963 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1964 log(LOG_ERR, "%s: unable to allocate or map rx " 1965 "buffer %d, error = %d\n", 1966 device_xname(sc->sc_dev), 1967 sc->sc_rxq.ifq_len, error); 1968 /* 1969 * XXX Should attempt to run with fewer receive 1970 * XXX buffers instead of just failing. 1971 */ 1972 FXP_RXMAP_PUT(sc, rxmap); 1973 fxp_rxdrain(sc); 1974 goto out; 1975 } 1976 } 1977 sc->sc_rxidle = 0; 1978 1979 /* 1980 * Give the transmit ring to the chip. We do this by pointing 1981 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1982 * issuing a start command. It will execute the NOP and then 1983 * suspend, pointing at the first descriptor. 1984 */ 1985 fxp_scb_wait(sc); 1986 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1987 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1988 1989 /* 1990 * Initialize receiver buffer area - RFA. 1991 */ 1992 #if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 1993 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1994 fxp_scb_wait(sc); 1995 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1996 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1997 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1998 #endif 1999 2000 if (sc->sc_flags & FXPF_MII) { 2001 /* 2002 * Set current media. 2003 */ 2004 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 2005 goto out; 2006 } 2007 2008 /* 2009 * ...all done! 2010 */ 2011 ifp->if_flags |= IFF_RUNNING; 2012 ifp->if_flags &= ~IFF_OACTIVE; 2013 2014 /* 2015 * Request a software generated interrupt that will be used to 2016 * (re)start the RU processing. If we direct the chip to start 2017 * receiving from the start of queue now, instead of letting the 2018 * interrupt handler first process all received packets, we run 2019 * the risk of having it overwrite mbuf clusters while they are 2020 * being processed or after they have been returned to the pool. 2021 */ 2022 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 2023 2024 /* 2025 * Start the one second timer. 2026 */ 2027 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 2028 2029 /* 2030 * Attempt to start output on the interface. 2031 */ 2032 fxp_start(ifp); 2033 2034 out: 2035 if (error) { 2036 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2037 ifp->if_timer = 0; 2038 log(LOG_ERR, "%s: interface not running\n", 2039 device_xname(sc->sc_dev)); 2040 } 2041 return (error); 2042 } 2043 2044 /* 2045 * Notify the world which media we're using. 2046 */ 2047 void 2048 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2049 { 2050 struct fxp_softc *sc = ifp->if_softc; 2051 2052 if (sc->sc_enabled == 0) { 2053 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 2054 ifmr->ifm_status = 0; 2055 return; 2056 } 2057 2058 ether_mediastatus(ifp, ifmr); 2059 } 2060 2061 int 2062 fxp_80c24_mediachange(struct ifnet *ifp) 2063 { 2064 2065 /* Nothing to do here. */ 2066 return (0); 2067 } 2068 2069 void 2070 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2071 { 2072 struct fxp_softc *sc = ifp->if_softc; 2073 2074 /* 2075 * Media is currently-selected media. We cannot determine 2076 * the link status. 2077 */ 2078 ifmr->ifm_status = 0; 2079 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 2080 } 2081 2082 /* 2083 * Add a buffer to the end of the RFA buffer list. 2084 * Return 0 if successful, error code on failure. 2085 * 2086 * The RFA struct is stuck at the beginning of mbuf cluster and the 2087 * data pointer is fixed up to point just past it. 2088 */ 2089 int 2090 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2091 { 2092 struct mbuf *m; 2093 int error; 2094 2095 MGETHDR(m, M_DONTWAIT, MT_DATA); 2096 if (m == NULL) 2097 return (ENOBUFS); 2098 2099 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2100 MCLGET(m, M_DONTWAIT); 2101 if ((m->m_flags & M_EXT) == 0) { 2102 m_freem(m); 2103 return (ENOBUFS); 2104 } 2105 2106 if (unload) 2107 bus_dmamap_unload(sc->sc_dmat, rxmap); 2108 2109 M_SETCTX(m, rxmap); 2110 2111 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2112 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2113 BUS_DMA_READ|BUS_DMA_NOWAIT); 2114 if (error) { 2115 /* XXX XXX XXX */ 2116 aprint_error_dev(sc->sc_dev, 2117 "can't load rx DMA map %d, error = %d\n", 2118 sc->sc_rxq.ifq_len, error); 2119 panic("fxp_add_rfabuf"); 2120 } 2121 2122 FXP_INIT_RFABUF(sc, m); 2123 2124 return (0); 2125 } 2126 2127 int 2128 fxp_mdi_read(device_t self, int phy, int reg) 2129 { 2130 struct fxp_softc *sc = device_private(self); 2131 int count = 10000; 2132 int value; 2133 2134 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2135 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2136 2137 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2138 0x10000000) == 0 && count--) 2139 DELAY(10); 2140 2141 if (count <= 0) 2142 log(LOG_WARNING, 2143 "%s: fxp_mdi_read: timed out\n", device_xname(self)); 2144 2145 return (value & 0xffff); 2146 } 2147 2148 void 2149 fxp_statchg(device_t self) 2150 { 2151 2152 /* Nothing to do. */ 2153 } 2154 2155 void 2156 fxp_mdi_write(device_t self, int phy, int reg, int value) 2157 { 2158 struct fxp_softc *sc = device_private(self); 2159 int count = 10000; 2160 2161 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2162 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2163 (value & 0xffff)); 2164 2165 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2166 count--) 2167 DELAY(10); 2168 2169 if (count <= 0) 2170 log(LOG_WARNING, 2171 "%s: fxp_mdi_write: timed out\n", device_xname(self)); 2172 } 2173 2174 int 2175 fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2176 { 2177 struct fxp_softc *sc = ifp->if_softc; 2178 struct ifreq *ifr = (struct ifreq *)data; 2179 int s, error; 2180 2181 s = splnet(); 2182 2183 switch (cmd) { 2184 case SIOCSIFMEDIA: 2185 case SIOCGIFMEDIA: 2186 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2187 break; 2188 2189 default: 2190 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2191 break; 2192 2193 error = 0; 2194 2195 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2196 ; 2197 else if (ifp->if_flags & IFF_RUNNING) { 2198 /* 2199 * Multicast list has changed; set the 2200 * hardware filter accordingly. 2201 */ 2202 while (sc->sc_txpending) { 2203 sc->sc_flags |= FXPF_WANTINIT; 2204 tsleep(sc, PSOCK, "fxp_init", 0); 2205 } 2206 error = fxp_init(ifp); 2207 } 2208 break; 2209 } 2210 2211 /* Try to get more packets going. */ 2212 if (sc->sc_enabled) 2213 fxp_start(ifp); 2214 2215 splx(s); 2216 return (error); 2217 } 2218 2219 /* 2220 * Program the multicast filter. 2221 * 2222 * This function must be called at splnet(). 2223 */ 2224 void 2225 fxp_mc_setup(struct fxp_softc *sc) 2226 { 2227 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2228 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2229 struct ethercom *ec = &sc->sc_ethercom; 2230 struct ether_multi *enm; 2231 struct ether_multistep step; 2232 int count, nmcasts; 2233 uint16_t status; 2234 2235 #ifdef DIAGNOSTIC 2236 if (sc->sc_txpending) 2237 panic("fxp_mc_setup: pending transmissions"); 2238 #endif 2239 2240 ifp->if_flags &= ~IFF_ALLMULTI; 2241 2242 /* 2243 * Initialize multicast setup descriptor. 2244 */ 2245 nmcasts = 0; 2246 ETHER_FIRST_MULTI(step, ec, enm); 2247 while (enm != NULL) { 2248 /* 2249 * Check for too many multicast addresses or if we're 2250 * listening to a range. Either way, we simply have 2251 * to accept all multicasts. 2252 */ 2253 if (nmcasts >= MAXMCADDR || 2254 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2255 ETHER_ADDR_LEN) != 0) { 2256 /* 2257 * Callers of this function must do the 2258 * right thing with this. If we're called 2259 * from outside fxp_init(), the caller must 2260 * detect if the state if IFF_ALLMULTI changes. 2261 * If it does, the caller must then call 2262 * fxp_init(), since allmulti is handled by 2263 * the config block. 2264 */ 2265 ifp->if_flags |= IFF_ALLMULTI; 2266 return; 2267 } 2268 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2269 ETHER_ADDR_LEN); 2270 nmcasts++; 2271 ETHER_NEXT_MULTI(step, enm); 2272 } 2273 2274 /* BIG_ENDIAN: no need to swap to store 0 */ 2275 mcsp->cb_status = 0; 2276 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2277 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2278 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2279 2280 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2281 2282 /* 2283 * Wait until the command unit is not active. This should never 2284 * happen since nothing is queued, but make sure anyway. 2285 */ 2286 count = 100; 2287 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2288 FXP_SCB_CUS_ACTIVE && --count) 2289 DELAY(1); 2290 if (count == 0) { 2291 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2292 device_xname(sc->sc_dev), __LINE__); 2293 return; 2294 } 2295 2296 /* 2297 * Start the multicast setup command/DMA. 2298 */ 2299 fxp_scb_wait(sc); 2300 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2301 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2302 2303 /* ...and wait for it to complete. */ 2304 for (count = 1000; count > 0; count--) { 2305 FXP_CDMCSSYNC(sc, 2306 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2307 status = le16toh(mcsp->cb_status); 2308 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD); 2309 if ((status & FXP_CB_STATUS_C) != 0) 2310 break; 2311 DELAY(1); 2312 } 2313 if (count == 0) { 2314 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2315 device_xname(sc->sc_dev), __LINE__); 2316 return; 2317 } 2318 } 2319 2320 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2321 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2322 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2323 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2324 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2325 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2326 2327 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2328 2329 static const struct ucode { 2330 int32_t revision; 2331 const uint32_t *ucode; 2332 size_t length; 2333 uint16_t int_delay_offset; 2334 uint16_t bundle_max_offset; 2335 } ucode_table[] = { 2336 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2337 D101_CPUSAVER_DWORD, 0 }, 2338 2339 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2340 D101_CPUSAVER_DWORD, 0 }, 2341 2342 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2343 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2344 2345 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2346 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2347 2348 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2349 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2350 2351 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2352 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2353 2354 { 0, NULL, 0, 0, 0 } 2355 }; 2356 2357 void 2358 fxp_load_ucode(struct fxp_softc *sc) 2359 { 2360 const struct ucode *uc; 2361 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2362 int count, i; 2363 uint16_t status; 2364 2365 if (sc->sc_flags & FXPF_UCODE_LOADED) 2366 return; 2367 2368 /* 2369 * Only load the uCode if the user has requested that 2370 * we do so. 2371 */ 2372 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2373 sc->sc_int_delay = 0; 2374 sc->sc_bundle_max = 0; 2375 return; 2376 } 2377 2378 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2379 if (sc->sc_rev == uc->revision) 2380 break; 2381 } 2382 if (uc->ucode == NULL) 2383 return; 2384 2385 /* BIG ENDIAN: no need to swap to store 0 */ 2386 cbp->cb_status = 0; 2387 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2388 cbp->link_addr = 0xffffffff; /* (no) next command */ 2389 for (i = 0; i < uc->length; i++) 2390 cbp->ucode[i] = htole32(uc->ucode[i]); 2391 2392 if (uc->int_delay_offset) 2393 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2394 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2395 2396 if (uc->bundle_max_offset) 2397 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2398 htole16(fxp_bundle_max); 2399 2400 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2401 2402 /* 2403 * Download the uCode to the chip. 2404 */ 2405 fxp_scb_wait(sc); 2406 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2407 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2408 2409 /* ...and wait for it to complete. */ 2410 for (count = 10000; count > 0; count--) { 2411 FXP_CDUCODESYNC(sc, 2412 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2413 status = le16toh(cbp->cb_status); 2414 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD); 2415 if ((status & FXP_CB_STATUS_C) != 0) 2416 break; 2417 DELAY(2); 2418 } 2419 if (count == 0) { 2420 sc->sc_int_delay = 0; 2421 sc->sc_bundle_max = 0; 2422 log(LOG_WARNING, "%s: timeout loading microcode\n", 2423 device_xname(sc->sc_dev)); 2424 return; 2425 } 2426 2427 if (sc->sc_int_delay != fxp_int_delay || 2428 sc->sc_bundle_max != fxp_bundle_max) { 2429 sc->sc_int_delay = fxp_int_delay; 2430 sc->sc_bundle_max = fxp_bundle_max; 2431 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2432 "max bundle: %d\n", device_xname(sc->sc_dev), 2433 sc->sc_int_delay, 2434 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2435 } 2436 2437 sc->sc_flags |= FXPF_UCODE_LOADED; 2438 } 2439 2440 int 2441 fxp_enable(struct fxp_softc *sc) 2442 { 2443 2444 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2445 if ((*sc->sc_enable)(sc) != 0) { 2446 log(LOG_ERR, "%s: device enable failed\n", 2447 device_xname(sc->sc_dev)); 2448 return (EIO); 2449 } 2450 } 2451 2452 sc->sc_enabled = 1; 2453 return (0); 2454 } 2455 2456 void 2457 fxp_disable(struct fxp_softc *sc) 2458 { 2459 2460 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2461 (*sc->sc_disable)(sc); 2462 sc->sc_enabled = 0; 2463 } 2464 } 2465 2466 /* 2467 * fxp_activate: 2468 * 2469 * Handle device activation/deactivation requests. 2470 */ 2471 int 2472 fxp_activate(device_t self, enum devact act) 2473 { 2474 struct fxp_softc *sc = device_private(self); 2475 2476 switch (act) { 2477 case DVACT_DEACTIVATE: 2478 if_deactivate(&sc->sc_ethercom.ec_if); 2479 return 0; 2480 default: 2481 return EOPNOTSUPP; 2482 } 2483 } 2484 2485 /* 2486 * fxp_detach: 2487 * 2488 * Detach an i82557 interface. 2489 */ 2490 int 2491 fxp_detach(struct fxp_softc *sc, int flags) 2492 { 2493 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2494 int i, s; 2495 2496 /* Succeed now if there's no work to do. */ 2497 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2498 return (0); 2499 2500 s = splnet(); 2501 /* Stop the interface. Callouts are stopped in it. */ 2502 fxp_stop(ifp, 1); 2503 splx(s); 2504 2505 /* Destroy our callout. */ 2506 callout_destroy(&sc->sc_callout); 2507 2508 if (sc->sc_flags & FXPF_MII) { 2509 /* Detach all PHYs */ 2510 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2511 } 2512 2513 /* Delete all remaining media. */ 2514 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2515 2516 #if NRND > 0 2517 rnd_detach_source(&sc->rnd_source); 2518 #endif 2519 ether_ifdetach(ifp); 2520 if_detach(ifp); 2521 2522 for (i = 0; i < FXP_NRFABUFS; i++) { 2523 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2524 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2525 } 2526 2527 for (i = 0; i < FXP_NTXCB; i++) { 2528 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2529 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2530 } 2531 2532 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2533 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2534 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2535 sizeof(struct fxp_control_data)); 2536 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2537 2538 return (0); 2539 } 2540