1 /* $NetBSD: i82557.c,v 1.96 2005/12/24 20:27:30 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.96 2005/12/24 20:27:30 perry Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/syslog.h> 92 93 #include <machine/endian.h> 94 95 #include <uvm/uvm_extern.h> 96 97 #if NRND > 0 98 #include <sys/rnd.h> 99 #endif 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #if NBPFILTER > 0 107 #include <net/bpf.h> 108 #endif 109 110 #include <machine/bus.h> 111 #include <machine/intr.h> 112 113 #include <dev/mii/miivar.h> 114 115 #include <dev/ic/i82557reg.h> 116 #include <dev/ic/i82557var.h> 117 118 #include <dev/microcode/i8255x/rcvbundl.h> 119 120 /* 121 * NOTE! On the Alpha, we have an alignment constraint. The 122 * card DMAs the packet immediately following the RFA. However, 123 * the first thing in the packet is a 14-byte Ethernet header. 124 * This means that the packet is misaligned. To compensate, 125 * we actually offset the RFA 2 bytes into the cluster. This 126 * alignes the packet after the Ethernet header at a 32-bit 127 * boundary. HOWEVER! This means that the RFA is misaligned! 128 */ 129 #define RFA_ALIGNMENT_FUDGE 2 130 131 /* 132 * The configuration byte map has several undefined fields which 133 * must be one or must be zero. Set up a template for these bits 134 * only (assuming an i82557 chip), leaving the actual configuration 135 * for fxp_init(). 136 * 137 * See the definition of struct fxp_cb_config for the bit definitions. 138 */ 139 const u_int8_t fxp_cb_config_template[] = { 140 0x0, 0x0, /* cb_status */ 141 0x0, 0x0, /* cb_command */ 142 0x0, 0x0, 0x0, 0x0, /* link_addr */ 143 0x0, /* 0 */ 144 0x0, /* 1 */ 145 0x0, /* 2 */ 146 0x0, /* 3 */ 147 0x0, /* 4 */ 148 0x0, /* 5 */ 149 0x32, /* 6 */ 150 0x0, /* 7 */ 151 0x0, /* 8 */ 152 0x0, /* 9 */ 153 0x6, /* 10 */ 154 0x0, /* 11 */ 155 0x0, /* 12 */ 156 0x0, /* 13 */ 157 0xf2, /* 14 */ 158 0x48, /* 15 */ 159 0x0, /* 16 */ 160 0x40, /* 17 */ 161 0xf0, /* 18 */ 162 0x0, /* 19 */ 163 0x3f, /* 20 */ 164 0x5, /* 21 */ 165 0x0, /* 22 */ 166 0x0, /* 23 */ 167 0x0, /* 24 */ 168 0x0, /* 25 */ 169 0x0, /* 26 */ 170 0x0, /* 27 */ 171 0x0, /* 28 */ 172 0x0, /* 29 */ 173 0x0, /* 30 */ 174 0x0, /* 31 */ 175 }; 176 177 void fxp_mii_initmedia(struct fxp_softc *); 178 int fxp_mii_mediachange(struct ifnet *); 179 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 180 181 void fxp_80c24_initmedia(struct fxp_softc *); 182 int fxp_80c24_mediachange(struct ifnet *); 183 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 184 185 void fxp_start(struct ifnet *); 186 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 187 void fxp_watchdog(struct ifnet *); 188 int fxp_init(struct ifnet *); 189 void fxp_stop(struct ifnet *, int); 190 191 void fxp_txintr(struct fxp_softc *); 192 void fxp_rxintr(struct fxp_softc *); 193 194 int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 195 196 void fxp_rxdrain(struct fxp_softc *); 197 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 198 int fxp_mdi_read(struct device *, int, int); 199 void fxp_statchg(struct device *); 200 void fxp_mdi_write(struct device *, int, int, int); 201 void fxp_autosize_eeprom(struct fxp_softc*); 202 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 203 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 204 void fxp_eeprom_update_cksum(struct fxp_softc *); 205 void fxp_get_info(struct fxp_softc *, u_int8_t *); 206 void fxp_tick(void *); 207 void fxp_mc_setup(struct fxp_softc *); 208 void fxp_load_ucode(struct fxp_softc *); 209 210 void fxp_shutdown(void *); 211 void fxp_power(int, void *); 212 213 int fxp_copy_small = 0; 214 215 /* 216 * Variables for interrupt mitigating microcode. 217 */ 218 int fxp_int_delay = 1000; /* usec */ 219 int fxp_bundle_max = 6; /* packets */ 220 221 struct fxp_phytype { 222 int fp_phy; /* type of PHY, -1 for MII at the end. */ 223 void (*fp_init)(struct fxp_softc *); 224 } fxp_phytype_table[] = { 225 { FXP_PHY_80C24, fxp_80c24_initmedia }, 226 { -1, fxp_mii_initmedia }, 227 }; 228 229 /* 230 * Set initial transmit threshold at 64 (512 bytes). This is 231 * increased by 64 (512 bytes) at a time, to maximum of 192 232 * (1536 bytes), if an underrun occurs. 233 */ 234 static int tx_threshold = 64; 235 236 /* 237 * Wait for the previous command to be accepted (but not necessarily 238 * completed). 239 */ 240 static inline void 241 fxp_scb_wait(struct fxp_softc *sc) 242 { 243 int i = 10000; 244 245 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 246 delay(2); 247 if (i == 0) 248 log(LOG_WARNING, 249 "%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 250 } 251 252 /* 253 * Submit a command to the i82557. 254 */ 255 static inline void 256 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 257 { 258 259 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 260 } 261 262 /* 263 * Finish attaching an i82557 interface. Called by bus-specific front-end. 264 */ 265 void 266 fxp_attach(struct fxp_softc *sc) 267 { 268 u_int8_t enaddr[ETHER_ADDR_LEN]; 269 struct ifnet *ifp; 270 bus_dma_segment_t seg; 271 int rseg, i, error; 272 struct fxp_phytype *fp; 273 274 callout_init(&sc->sc_callout); 275 276 /* 277 * Enable some good stuff on i82558 and later. 278 */ 279 if (sc->sc_rev >= FXP_REV_82558_A4) { 280 /* Enable the extended TxCB. */ 281 sc->sc_flags |= FXPF_EXT_TXCB; 282 } 283 284 /* 285 * Enable use of extended RFDs and TCBs for 82550 286 * and later chips. Note: we need extended TXCB support 287 * too, but that's already enabled by the code above. 288 * Be careful to do this only on the right devices. 289 */ 290 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 291 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 292 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 293 } else { 294 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 295 } 296 297 sc->sc_rfa_size = 298 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 299 300 /* 301 * Allocate the control data structures, and create and load the 302 * DMA map for it. 303 */ 304 if ((error = bus_dmamem_alloc(sc->sc_dmat, 305 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 306 0)) != 0) { 307 aprint_error( 308 "%s: unable to allocate control data, error = %d\n", 309 sc->sc_dev.dv_xname, error); 310 goto fail_0; 311 } 312 313 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 314 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 315 BUS_DMA_COHERENT)) != 0) { 316 aprint_error("%s: unable to map control data, error = %d\n", 317 sc->sc_dev.dv_xname, error); 318 goto fail_1; 319 } 320 sc->sc_cdseg = seg; 321 sc->sc_cdnseg = rseg; 322 323 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 324 325 if ((error = bus_dmamap_create(sc->sc_dmat, 326 sizeof(struct fxp_control_data), 1, 327 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 328 aprint_error("%s: unable to create control data DMA map, " 329 "error = %d\n", sc->sc_dev.dv_xname, error); 330 goto fail_2; 331 } 332 333 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 334 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 335 0)) != 0) { 336 aprint_error( 337 "%s: can't load control data DMA map, error = %d\n", 338 sc->sc_dev.dv_xname, error); 339 goto fail_3; 340 } 341 342 /* 343 * Create the transmit buffer DMA maps. 344 */ 345 for (i = 0; i < FXP_NTXCB; i++) { 346 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 347 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 348 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 349 aprint_error("%s: unable to create tx DMA map %d, " 350 "error = %d\n", sc->sc_dev.dv_xname, i, error); 351 goto fail_4; 352 } 353 } 354 355 /* 356 * Create the receive buffer DMA maps. 357 */ 358 for (i = 0; i < FXP_NRFABUFS; i++) { 359 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 360 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 361 aprint_error("%s: unable to create rx DMA map %d, " 362 "error = %d\n", sc->sc_dev.dv_xname, i, error); 363 goto fail_5; 364 } 365 } 366 367 /* Initialize MAC address and media structures. */ 368 fxp_get_info(sc, enaddr); 369 370 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 371 ether_sprintf(enaddr)); 372 373 ifp = &sc->sc_ethercom.ec_if; 374 375 /* 376 * Get info about our media interface, and initialize it. Note 377 * the table terminates itself with a phy of -1, indicating 378 * that we're using MII. 379 */ 380 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 381 if (fp->fp_phy == sc->phy_primary_device) 382 break; 383 (*fp->fp_init)(sc); 384 385 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 386 ifp->if_softc = sc; 387 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 388 ifp->if_ioctl = fxp_ioctl; 389 ifp->if_start = fxp_start; 390 ifp->if_watchdog = fxp_watchdog; 391 ifp->if_init = fxp_init; 392 ifp->if_stop = fxp_stop; 393 IFQ_SET_READY(&ifp->if_snd); 394 395 if (sc->sc_flags & FXPF_IPCB) { 396 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 397 /* 398 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 399 * at least, on i82550 rev.12. 400 * specifically, it doesn't calculate ipv4 checksum correctly 401 * when sending 20 byte ipv4 header + 1 or 2 byte data. 402 * FreeBSD driver has related comments. 403 */ 404 ifp->if_capabilities = 405 IFCAP_CSUM_IPv4_Rx | 406 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 407 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 408 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 409 } 410 411 /* 412 * We can support 802.1Q VLAN-sized frames. 413 */ 414 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 415 416 /* 417 * Attach the interface. 418 */ 419 if_attach(ifp); 420 ether_ifattach(ifp, enaddr); 421 #if NRND > 0 422 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 423 RND_TYPE_NET, 0); 424 #endif 425 426 #ifdef FXP_EVENT_COUNTERS 427 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 428 NULL, sc->sc_dev.dv_xname, "txstall"); 429 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 430 NULL, sc->sc_dev.dv_xname, "txintr"); 431 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 432 NULL, sc->sc_dev.dv_xname, "rxintr"); 433 if (sc->sc_rev >= FXP_REV_82558_A4) { 434 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 435 NULL, sc->sc_dev.dv_xname, "txpause"); 436 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 437 NULL, sc->sc_dev.dv_xname, "rxpause"); 438 } 439 #endif /* FXP_EVENT_COUNTERS */ 440 441 /* 442 * Add shutdown hook so that DMA is disabled prior to reboot. Not 443 * doing do could allow DMA to corrupt kernel memory during the 444 * reboot before the driver initializes. 445 */ 446 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 447 if (sc->sc_sdhook == NULL) 448 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 449 sc->sc_dev.dv_xname); 450 /* 451 * Add suspend hook, for similar reasons.. 452 */ 453 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 454 if (sc->sc_powerhook == NULL) 455 aprint_error("%s: WARNING: unable to establish power hook\n", 456 sc->sc_dev.dv_xname); 457 458 /* The attach is successful. */ 459 sc->sc_flags |= FXPF_ATTACHED; 460 461 return; 462 463 /* 464 * Free any resources we've allocated during the failed attach 465 * attempt. Do this in reverse order and fall though. 466 */ 467 fail_5: 468 for (i = 0; i < FXP_NRFABUFS; i++) { 469 if (sc->sc_rxmaps[i] != NULL) 470 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 471 } 472 fail_4: 473 for (i = 0; i < FXP_NTXCB; i++) { 474 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 475 bus_dmamap_destroy(sc->sc_dmat, 476 FXP_DSTX(sc, i)->txs_dmamap); 477 } 478 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 479 fail_3: 480 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 481 fail_2: 482 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 483 sizeof(struct fxp_control_data)); 484 fail_1: 485 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 486 fail_0: 487 return; 488 } 489 490 void 491 fxp_mii_initmedia(struct fxp_softc *sc) 492 { 493 int flags; 494 495 sc->sc_flags |= FXPF_MII; 496 497 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 498 sc->sc_mii.mii_readreg = fxp_mdi_read; 499 sc->sc_mii.mii_writereg = fxp_mdi_write; 500 sc->sc_mii.mii_statchg = fxp_statchg; 501 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, fxp_mii_mediachange, 502 fxp_mii_mediastatus); 503 504 flags = MIIF_NOISOLATE; 505 if (sc->sc_rev >= FXP_REV_82558_A4) 506 flags |= MIIF_DOPAUSE; 507 /* 508 * The i82557 wedges if all of its PHYs are isolated! 509 */ 510 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 511 MII_OFFSET_ANY, flags); 512 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 513 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 514 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 515 } else 516 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 517 } 518 519 void 520 fxp_80c24_initmedia(struct fxp_softc *sc) 521 { 522 523 /* 524 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 525 * doesn't have a programming interface of any sort. The 526 * media is sensed automatically based on how the link partner 527 * is configured. This is, in essence, manual configuration. 528 */ 529 aprint_normal("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 530 sc->sc_dev.dv_xname); 531 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 532 fxp_80c24_mediastatus); 533 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 534 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 535 } 536 537 /* 538 * Device shutdown routine. Called at system shutdown after sync. The 539 * main purpose of this routine is to shut off receiver DMA so that 540 * kernel memory doesn't get clobbered during warmboot. 541 */ 542 void 543 fxp_shutdown(void *arg) 544 { 545 struct fxp_softc *sc = arg; 546 547 /* 548 * Since the system's going to halt shortly, don't bother 549 * freeing mbufs. 550 */ 551 fxp_stop(&sc->sc_ethercom.ec_if, 0); 552 } 553 /* 554 * Power handler routine. Called when the system is transitioning 555 * into/out of power save modes. As with fxp_shutdown, the main 556 * purpose of this routine is to shut off receiver DMA so it doesn't 557 * clobber kernel memory at the wrong time. 558 */ 559 void 560 fxp_power(int why, void *arg) 561 { 562 struct fxp_softc *sc = arg; 563 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 564 int s; 565 566 s = splnet(); 567 switch (why) { 568 case PWR_SUSPEND: 569 case PWR_STANDBY: 570 fxp_stop(ifp, 0); 571 break; 572 case PWR_RESUME: 573 if (ifp->if_flags & IFF_UP) 574 fxp_init(ifp); 575 break; 576 case PWR_SOFTSUSPEND: 577 case PWR_SOFTSTANDBY: 578 case PWR_SOFTRESUME: 579 break; 580 } 581 splx(s); 582 } 583 584 /* 585 * Initialize the interface media. 586 */ 587 void 588 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 589 { 590 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 591 592 /* 593 * Reset to a stable state. 594 */ 595 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 596 DELAY(100); 597 598 sc->sc_eeprom_size = 0; 599 fxp_autosize_eeprom(sc); 600 if (sc->sc_eeprom_size == 0) { 601 aprint_error("%s: failed to detect EEPROM size\n", 602 sc->sc_dev.dv_xname); 603 sc->sc_eeprom_size = 6; /* XXX panic here? */ 604 } 605 #ifdef DEBUG 606 aprint_debug("%s: detected %d word EEPROM\n", 607 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 608 #endif 609 610 /* 611 * Get info about the primary PHY 612 */ 613 fxp_read_eeprom(sc, &data, 6, 1); 614 sc->phy_primary_device = 615 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 616 617 /* 618 * Read MAC address. 619 */ 620 fxp_read_eeprom(sc, myea, 0, 3); 621 enaddr[0] = myea[0] & 0xff; 622 enaddr[1] = myea[0] >> 8; 623 enaddr[2] = myea[1] & 0xff; 624 enaddr[3] = myea[1] >> 8; 625 enaddr[4] = myea[2] & 0xff; 626 enaddr[5] = myea[2] >> 8; 627 628 /* 629 * Systems based on the ICH2/ICH2-M chip from Intel, as well 630 * as some i82559 designs, have a defect where the chip can 631 * cause a PCI protocol violation if it receives a CU_RESUME 632 * command when it is entering the IDLE state. 633 * 634 * The work-around is to disable Dynamic Standby Mode, so that 635 * the chip never deasserts #CLKRUN, and always remains in the 636 * active state. 637 * 638 * Unfortunately, the only way to disable Dynamic Standby is 639 * to frob an EEPROM setting and reboot (the EEPROM setting 640 * is only consulted when the PCI bus comes out of reset). 641 * 642 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 643 */ 644 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 645 fxp_read_eeprom(sc, &data, 10, 1); 646 if (data & 0x02) { /* STB enable */ 647 aprint_error("%s: WARNING: " 648 "Disabling dynamic standby mode in EEPROM " 649 "to work around a\n", 650 sc->sc_dev.dv_xname); 651 aprint_normal( 652 "%s: WARNING: hardware bug. You must reset " 653 "the system before using this\n", 654 sc->sc_dev.dv_xname); 655 aprint_normal("%s: WARNING: interface.\n", 656 sc->sc_dev.dv_xname); 657 data &= ~0x02; 658 fxp_write_eeprom(sc, &data, 10, 1); 659 aprint_normal("%s: new EEPROM ID: 0x%04x\n", 660 sc->sc_dev.dv_xname, data); 661 fxp_eeprom_update_cksum(sc); 662 } 663 } 664 665 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 666 /* Due to false positives we make it conditional on setting link1 */ 667 fxp_read_eeprom(sc, &data, 3, 1); 668 if ((data & 0x03) != 0x03) { 669 aprint_verbose("%s: May need receiver lock-up workaround\n", 670 sc->sc_dev.dv_xname); 671 } 672 } 673 674 static void 675 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 676 { 677 uint16_t reg; 678 int x; 679 680 for (x = 1 << (len - 1); x != 0; x >>= 1) { 681 DELAY(40); 682 if (data & x) 683 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 684 else 685 reg = FXP_EEPROM_EECS; 686 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 687 DELAY(40); 688 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 689 reg | FXP_EEPROM_EESK); 690 DELAY(40); 691 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 692 } 693 DELAY(40); 694 } 695 696 /* 697 * Figure out EEPROM size. 698 * 699 * 559's can have either 64-word or 256-word EEPROMs, the 558 700 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 701 * talks about the existence of 16 to 256 word EEPROMs. 702 * 703 * The only known sizes are 64 and 256, where the 256 version is used 704 * by CardBus cards to store CIS information. 705 * 706 * The address is shifted in msb-to-lsb, and after the last 707 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 708 * after which follows the actual data. We try to detect this zero, by 709 * probing the data-out bit in the EEPROM control register just after 710 * having shifted in a bit. If the bit is zero, we assume we've 711 * shifted enough address bits. The data-out should be tri-state, 712 * before this, which should translate to a logical one. 713 * 714 * Other ways to do this would be to try to read a register with known 715 * contents with a varying number of address bits, but no such 716 * register seem to be available. The high bits of register 10 are 01 717 * on the 558 and 559, but apparently not on the 557. 718 * 719 * The Linux driver computes a checksum on the EEPROM data, but the 720 * value of this checksum is not very well documented. 721 */ 722 723 void 724 fxp_autosize_eeprom(struct fxp_softc *sc) 725 { 726 int x; 727 728 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 729 DELAY(40); 730 731 /* Shift in read opcode. */ 732 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 733 734 /* 735 * Shift in address, wait for the dummy zero following a correct 736 * address shift. 737 */ 738 for (x = 1; x <= 8; x++) { 739 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 740 DELAY(40); 741 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 742 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 743 DELAY(40); 744 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 745 FXP_EEPROM_EEDO) == 0) 746 break; 747 DELAY(40); 748 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 749 DELAY(40); 750 } 751 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 752 DELAY(40); 753 if (x != 6 && x != 8) { 754 #ifdef DEBUG 755 printf("%s: strange EEPROM size (%d)\n", 756 sc->sc_dev.dv_xname, 1 << x); 757 #endif 758 } else 759 sc->sc_eeprom_size = x; 760 } 761 762 /* 763 * Read from the serial EEPROM. Basically, you manually shift in 764 * the read opcode (one bit at a time) and then shift in the address, 765 * and then you shift out the data (all of this one bit at a time). 766 * The word size is 16 bits, so you have to provide the address for 767 * every 16 bits of data. 768 */ 769 void 770 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 771 { 772 u_int16_t reg; 773 int i, x; 774 775 for (i = 0; i < words; i++) { 776 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 777 778 /* Shift in read opcode. */ 779 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 780 781 /* Shift in address. */ 782 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 783 784 reg = FXP_EEPROM_EECS; 785 data[i] = 0; 786 787 /* Shift out data. */ 788 for (x = 16; x > 0; x--) { 789 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 790 reg | FXP_EEPROM_EESK); 791 DELAY(40); 792 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 793 FXP_EEPROM_EEDO) 794 data[i] |= (1 << (x - 1)); 795 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 796 DELAY(40); 797 } 798 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 799 DELAY(40); 800 } 801 } 802 803 /* 804 * Write data to the serial EEPROM. 805 */ 806 void 807 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 808 { 809 int i, j; 810 811 for (i = 0; i < words; i++) { 812 /* Erase/write enable. */ 813 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 814 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 815 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 816 sc->sc_eeprom_size); 817 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 818 DELAY(4); 819 820 /* Shift in write opcode, address, data. */ 821 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 822 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 823 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 824 fxp_eeprom_shiftin(sc, data[i], 16); 825 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 826 DELAY(4); 827 828 /* Wait for the EEPROM to finish up. */ 829 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 830 DELAY(4); 831 for (j = 0; j < 1000; j++) { 832 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 833 FXP_EEPROM_EEDO) 834 break; 835 DELAY(50); 836 } 837 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 838 DELAY(4); 839 840 /* Erase/write disable. */ 841 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 842 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 843 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 844 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 845 DELAY(4); 846 } 847 } 848 849 /* 850 * Update the checksum of the EEPROM. 851 */ 852 void 853 fxp_eeprom_update_cksum(struct fxp_softc *sc) 854 { 855 int i; 856 uint16_t data, cksum; 857 858 cksum = 0; 859 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 860 fxp_read_eeprom(sc, &data, i, 1); 861 cksum += data; 862 } 863 i = (1 << sc->sc_eeprom_size) - 1; 864 cksum = 0xbaba - cksum; 865 fxp_read_eeprom(sc, &data, i, 1); 866 fxp_write_eeprom(sc, &cksum, i, 1); 867 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 868 sc->sc_dev.dv_xname, i, data, cksum); 869 } 870 871 /* 872 * Start packet transmission on the interface. 873 */ 874 void 875 fxp_start(struct ifnet *ifp) 876 { 877 struct fxp_softc *sc = ifp->if_softc; 878 struct mbuf *m0, *m; 879 struct fxp_txdesc *txd; 880 struct fxp_txsoft *txs; 881 bus_dmamap_t dmamap; 882 int error, lasttx, nexttx, opending, seg; 883 884 /* 885 * If we want a re-init, bail out now. 886 */ 887 if (sc->sc_flags & FXPF_WANTINIT) { 888 ifp->if_flags |= IFF_OACTIVE; 889 return; 890 } 891 892 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 893 return; 894 895 /* 896 * Remember the previous txpending and the current lasttx. 897 */ 898 opending = sc->sc_txpending; 899 lasttx = sc->sc_txlast; 900 901 /* 902 * Loop through the send queue, setting up transmit descriptors 903 * until we drain the queue, or use up all available transmit 904 * descriptors. 905 */ 906 for (;;) { 907 struct fxp_tbd *tbdp; 908 int csum_flags; 909 910 /* 911 * Grab a packet off the queue. 912 */ 913 IFQ_POLL(&ifp->if_snd, m0); 914 if (m0 == NULL) 915 break; 916 m = NULL; 917 918 if (sc->sc_txpending == FXP_NTXCB) { 919 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 920 break; 921 } 922 923 /* 924 * Get the next available transmit descriptor. 925 */ 926 nexttx = FXP_NEXTTX(sc->sc_txlast); 927 txd = FXP_CDTX(sc, nexttx); 928 txs = FXP_DSTX(sc, nexttx); 929 dmamap = txs->txs_dmamap; 930 931 /* 932 * Load the DMA map. If this fails, the packet either 933 * didn't fit in the allotted number of frags, or we were 934 * short on resources. In this case, we'll copy and try 935 * again. 936 */ 937 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 938 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 939 MGETHDR(m, M_DONTWAIT, MT_DATA); 940 if (m == NULL) { 941 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 942 sc->sc_dev.dv_xname); 943 break; 944 } 945 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 946 if (m0->m_pkthdr.len > MHLEN) { 947 MCLGET(m, M_DONTWAIT); 948 if ((m->m_flags & M_EXT) == 0) { 949 log(LOG_ERR, 950 "%s: unable to allocate Tx " 951 "cluster\n", sc->sc_dev.dv_xname); 952 m_freem(m); 953 break; 954 } 955 } 956 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 957 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 958 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 959 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 960 if (error) { 961 log(LOG_ERR, "%s: unable to load Tx buffer, " 962 "error = %d\n", sc->sc_dev.dv_xname, error); 963 break; 964 } 965 } 966 967 IFQ_DEQUEUE(&ifp->if_snd, m0); 968 csum_flags = m0->m_pkthdr.csum_flags; 969 if (m != NULL) { 970 m_freem(m0); 971 m0 = m; 972 } 973 974 /* Initialize the fraglist. */ 975 tbdp = txd->txd_tbd; 976 if (sc->sc_flags & FXPF_IPCB) 977 tbdp++; 978 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 979 tbdp[seg].tb_addr = 980 htole32(dmamap->dm_segs[seg].ds_addr); 981 tbdp[seg].tb_size = 982 htole32(dmamap->dm_segs[seg].ds_len); 983 } 984 985 /* Sync the DMA map. */ 986 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 987 BUS_DMASYNC_PREWRITE); 988 989 /* 990 * Store a pointer to the packet so we can free it later. 991 */ 992 txs->txs_mbuf = m0; 993 994 /* 995 * Initialize the transmit descriptor. 996 */ 997 /* BIG_ENDIAN: no need to swap to store 0 */ 998 txd->txd_txcb.cb_status = 0; 999 txd->txd_txcb.cb_command = 1000 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 1001 txd->txd_txcb.tx_threshold = tx_threshold; 1002 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 1003 1004 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 1005 if (sc->sc_flags & FXPF_IPCB) { 1006 struct m_tag *vtag; 1007 struct fxp_ipcb *ipcb; 1008 /* 1009 * Deal with TCP/IP checksum offload. Note that 1010 * in order for TCP checksum offload to work, 1011 * the pseudo header checksum must have already 1012 * been computed and stored in the checksum field 1013 * in the TCP header. The stack should have 1014 * already done this for us. 1015 */ 1016 ipcb = &txd->txd_u.txdu_ipcb; 1017 memset(ipcb, 0, sizeof(*ipcb)); 1018 /* 1019 * always do hardware parsing. 1020 */ 1021 ipcb->ipcb_ip_activation_high = 1022 FXP_IPCB_HARDWAREPARSING_ENABLE; 1023 /* 1024 * ip checksum offloading. 1025 */ 1026 if (csum_flags & M_CSUM_IPv4) { 1027 ipcb->ipcb_ip_schedule |= 1028 FXP_IPCB_IP_CHECKSUM_ENABLE; 1029 } 1030 /* 1031 * TCP/UDP checksum offloading. 1032 */ 1033 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1034 ipcb->ipcb_ip_schedule |= 1035 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1036 } 1037 1038 /* 1039 * request VLAN tag insertion if needed. 1040 */ 1041 vtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 1042 if (vtag) { 1043 ipcb->ipcb_vlan_id = 1044 htobe16(*(u_int *)(vtag + 1)); 1045 ipcb->ipcb_ip_activation_high |= 1046 FXP_IPCB_INSERTVLAN_ENABLE; 1047 } 1048 } else { 1049 KASSERT((csum_flags & 1050 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 1051 } 1052 1053 FXP_CDTXSYNC(sc, nexttx, 1054 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1055 1056 /* Advance the tx pointer. */ 1057 sc->sc_txpending++; 1058 sc->sc_txlast = nexttx; 1059 1060 #if NBPFILTER > 0 1061 /* 1062 * Pass packet to bpf if there is a listener. 1063 */ 1064 if (ifp->if_bpf) 1065 bpf_mtap(ifp->if_bpf, m0); 1066 #endif 1067 } 1068 1069 if (sc->sc_txpending == FXP_NTXCB) { 1070 /* No more slots; notify upper layer. */ 1071 ifp->if_flags |= IFF_OACTIVE; 1072 } 1073 1074 if (sc->sc_txpending != opending) { 1075 /* 1076 * We enqueued packets. If the transmitter was idle, 1077 * reset the txdirty pointer. 1078 */ 1079 if (opending == 0) 1080 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1081 1082 /* 1083 * Cause the chip to interrupt and suspend command 1084 * processing once the last packet we've enqueued 1085 * has been transmitted. 1086 */ 1087 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 1088 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1089 FXP_CDTXSYNC(sc, sc->sc_txlast, 1090 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1091 1092 /* 1093 * The entire packet chain is set up. Clear the suspend bit 1094 * on the command prior to the first packet we set up. 1095 */ 1096 FXP_CDTXSYNC(sc, lasttx, 1097 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1098 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1099 htole16(~FXP_CB_COMMAND_S); 1100 FXP_CDTXSYNC(sc, lasttx, 1101 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1102 1103 /* 1104 * Issue a Resume command in case the chip was suspended. 1105 */ 1106 fxp_scb_wait(sc); 1107 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1108 1109 /* Set a watchdog timer in case the chip flakes out. */ 1110 ifp->if_timer = 5; 1111 } 1112 } 1113 1114 /* 1115 * Process interface interrupts. 1116 */ 1117 int 1118 fxp_intr(void *arg) 1119 { 1120 struct fxp_softc *sc = arg; 1121 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1122 bus_dmamap_t rxmap; 1123 int claimed = 0; 1124 u_int8_t statack; 1125 1126 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0 || sc->sc_enabled == 0) 1127 return (0); 1128 /* 1129 * If the interface isn't running, don't try to 1130 * service the interrupt.. just ack it and bail. 1131 */ 1132 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1133 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1134 if (statack) { 1135 claimed = 1; 1136 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1137 } 1138 return (claimed); 1139 } 1140 1141 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1142 claimed = 1; 1143 1144 /* 1145 * First ACK all the interrupts in this pass. 1146 */ 1147 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1148 1149 /* 1150 * Process receiver interrupts. If a no-resource (RNR) 1151 * condition exists, get whatever packets we can and 1152 * re-start the receiver. 1153 */ 1154 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1155 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1156 fxp_rxintr(sc); 1157 } 1158 1159 if (statack & FXP_SCB_STATACK_RNR) { 1160 fxp_scb_wait(sc); 1161 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1162 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1163 fxp_scb_wait(sc); 1164 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1165 rxmap->dm_segs[0].ds_addr + 1166 RFA_ALIGNMENT_FUDGE); 1167 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1168 } 1169 1170 /* 1171 * Free any finished transmit mbuf chains. 1172 */ 1173 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1174 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1175 fxp_txintr(sc); 1176 1177 /* 1178 * Try to get more packets going. 1179 */ 1180 fxp_start(ifp); 1181 1182 if (sc->sc_txpending == 0) { 1183 /* 1184 * If we want a re-init, do that now. 1185 */ 1186 if (sc->sc_flags & FXPF_WANTINIT) 1187 (void) fxp_init(ifp); 1188 } 1189 } 1190 } 1191 1192 #if NRND > 0 1193 if (claimed) 1194 rnd_add_uint32(&sc->rnd_source, statack); 1195 #endif 1196 return (claimed); 1197 } 1198 1199 /* 1200 * Handle transmit completion interrupts. 1201 */ 1202 void 1203 fxp_txintr(struct fxp_softc *sc) 1204 { 1205 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1206 struct fxp_txdesc *txd; 1207 struct fxp_txsoft *txs; 1208 int i; 1209 u_int16_t txstat; 1210 1211 ifp->if_flags &= ~IFF_OACTIVE; 1212 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1213 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1214 txd = FXP_CDTX(sc, i); 1215 txs = FXP_DSTX(sc, i); 1216 1217 FXP_CDTXSYNC(sc, i, 1218 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1219 1220 txstat = le16toh(txd->txd_txcb.cb_status); 1221 1222 if ((txstat & FXP_CB_STATUS_C) == 0) 1223 break; 1224 1225 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1226 0, txs->txs_dmamap->dm_mapsize, 1227 BUS_DMASYNC_POSTWRITE); 1228 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1229 m_freem(txs->txs_mbuf); 1230 txs->txs_mbuf = NULL; 1231 } 1232 1233 /* Update the dirty transmit buffer pointer. */ 1234 sc->sc_txdirty = i; 1235 1236 /* 1237 * Cancel the watchdog timer if there are no pending 1238 * transmissions. 1239 */ 1240 if (sc->sc_txpending == 0) 1241 ifp->if_timer = 0; 1242 } 1243 1244 /* 1245 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1246 */ 1247 1248 int 1249 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1250 { 1251 u_int16_t rxparsestat; 1252 u_int16_t csum_stat; 1253 u_int32_t csum_data; 1254 int csum_flags; 1255 1256 /* 1257 * check VLAN tag stripping. 1258 */ 1259 1260 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1261 struct m_tag *vtag; 1262 1263 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1264 if (vtag == NULL) 1265 return ENOMEM; 1266 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1267 m_tag_prepend(m, vtag); 1268 } 1269 1270 /* 1271 * check H/W Checksumming. 1272 */ 1273 1274 csum_stat = le16toh(rfa->cksum_stat); 1275 rxparsestat = le16toh(rfa->rx_parse_stat); 1276 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1277 return 0; 1278 1279 csum_flags = 0; 1280 csum_data = 0; 1281 1282 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1283 csum_flags = M_CSUM_IPv4; 1284 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1285 csum_flags |= M_CSUM_IPv4_BAD; 1286 } 1287 1288 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1289 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1290 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1291 csum_flags |= M_CSUM_TCP_UDP_BAD; 1292 } 1293 1294 m->m_pkthdr.csum_flags = csum_flags; 1295 m->m_pkthdr.csum_data = csum_data; 1296 1297 return 0; 1298 } 1299 1300 /* 1301 * Handle receive interrupts. 1302 */ 1303 void 1304 fxp_rxintr(struct fxp_softc *sc) 1305 { 1306 struct ethercom *ec = &sc->sc_ethercom; 1307 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1308 struct mbuf *m, *m0; 1309 bus_dmamap_t rxmap; 1310 struct fxp_rfa *rfa; 1311 u_int16_t len, rxstat; 1312 1313 for (;;) { 1314 m = sc->sc_rxq.ifq_head; 1315 rfa = FXP_MTORFA(m); 1316 rxmap = M_GETCTX(m, bus_dmamap_t); 1317 1318 FXP_RFASYNC(sc, m, 1319 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1320 1321 rxstat = le16toh(rfa->rfa_status); 1322 1323 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1324 /* 1325 * We have processed all of the 1326 * receive buffers. 1327 */ 1328 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1329 return; 1330 } 1331 1332 IF_DEQUEUE(&sc->sc_rxq, m); 1333 1334 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1335 1336 len = le16toh(rfa->actual_size) & 1337 (m->m_ext.ext_size - 1); 1338 1339 if (len < sizeof(struct ether_header)) { 1340 /* 1341 * Runt packet; drop it now. 1342 */ 1343 FXP_INIT_RFABUF(sc, m); 1344 continue; 1345 } 1346 1347 /* 1348 * If support for 802.1Q VLAN sized frames is 1349 * enabled, we need to do some additional error 1350 * checking (as we are saving bad frames, in 1351 * order to receive the larger ones). 1352 */ 1353 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1354 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1355 FXP_RFA_STATUS_RNR| 1356 FXP_RFA_STATUS_ALIGN| 1357 FXP_RFA_STATUS_CRC)) != 0) { 1358 FXP_INIT_RFABUF(sc, m); 1359 continue; 1360 } 1361 1362 /* Do checksum checking. */ 1363 m->m_pkthdr.csum_flags = 0; 1364 if (sc->sc_flags & FXPF_EXT_RFA) 1365 if (fxp_rx_hwcksum(m, rfa)) 1366 goto dropit; 1367 1368 /* 1369 * If the packet is small enough to fit in a 1370 * single header mbuf, allocate one and copy 1371 * the data into it. This greatly reduces 1372 * memory consumption when we receive lots 1373 * of small packets. 1374 * 1375 * Otherwise, we add a new buffer to the receive 1376 * chain. If this fails, we drop the packet and 1377 * recycle the old buffer. 1378 */ 1379 if (fxp_copy_small != 0 && len <= MHLEN) { 1380 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1381 if (m0 == NULL) 1382 goto dropit; 1383 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1384 memcpy(mtod(m0, caddr_t), 1385 mtod(m, caddr_t), len); 1386 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1387 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1388 FXP_INIT_RFABUF(sc, m); 1389 m = m0; 1390 } else { 1391 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1392 dropit: 1393 ifp->if_ierrors++; 1394 FXP_INIT_RFABUF(sc, m); 1395 continue; 1396 } 1397 } 1398 1399 m->m_pkthdr.rcvif = ifp; 1400 m->m_pkthdr.len = m->m_len = len; 1401 1402 #if NBPFILTER > 0 1403 /* 1404 * Pass this up to any BPF listeners, but only 1405 * pass it up the stack it its for us. 1406 */ 1407 if (ifp->if_bpf) 1408 bpf_mtap(ifp->if_bpf, m); 1409 #endif 1410 1411 /* Pass it on. */ 1412 (*ifp->if_input)(ifp, m); 1413 } 1414 } 1415 1416 /* 1417 * Update packet in/out/collision statistics. The i82557 doesn't 1418 * allow you to access these counters without doing a fairly 1419 * expensive DMA to get _all_ of the statistics it maintains, so 1420 * we do this operation here only once per second. The statistics 1421 * counters in the kernel are updated from the previous dump-stats 1422 * DMA and then a new dump-stats DMA is started. The on-chip 1423 * counters are zeroed when the DMA completes. If we can't start 1424 * the DMA immediately, we don't wait - we just prepare to read 1425 * them again next time. 1426 */ 1427 void 1428 fxp_tick(void *arg) 1429 { 1430 struct fxp_softc *sc = arg; 1431 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1432 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1433 int s; 1434 1435 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1436 return; 1437 1438 s = splnet(); 1439 1440 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1441 1442 ifp->if_opackets += le32toh(sp->tx_good); 1443 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1444 if (sp->rx_good) { 1445 ifp->if_ipackets += le32toh(sp->rx_good); 1446 sc->sc_rxidle = 0; 1447 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1448 sc->sc_rxidle++; 1449 } 1450 ifp->if_ierrors += 1451 le32toh(sp->rx_crc_errors) + 1452 le32toh(sp->rx_alignment_errors) + 1453 le32toh(sp->rx_rnr_errors) + 1454 le32toh(sp->rx_overrun_errors); 1455 /* 1456 * If any transmit underruns occurred, bump up the transmit 1457 * threshold by another 512 bytes (64 * 8). 1458 */ 1459 if (sp->tx_underruns) { 1460 ifp->if_oerrors += le32toh(sp->tx_underruns); 1461 if (tx_threshold < 192) 1462 tx_threshold += 64; 1463 } 1464 #ifdef FXP_EVENT_COUNTERS 1465 if (sc->sc_rev >= FXP_REV_82558_A4) { 1466 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1467 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1468 } 1469 #endif 1470 1471 /* 1472 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1473 * then assume the receiver has locked up and attempt to clear 1474 * the condition by reprogramming the multicast filter (actually, 1475 * resetting the interface). This is a work-around for a bug in 1476 * the 82557 where the receiver locks up if it gets certain types 1477 * of garbage in the synchronization bits prior to the packet header. 1478 * This bug is supposed to only occur in 10Mbps mode, but has been 1479 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1480 * speed transition). 1481 */ 1482 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1483 (void) fxp_init(ifp); 1484 splx(s); 1485 return; 1486 } 1487 /* 1488 * If there is no pending command, start another stats 1489 * dump. Otherwise punt for now. 1490 */ 1491 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1492 /* 1493 * Start another stats dump. 1494 */ 1495 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1496 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1497 } else { 1498 /* 1499 * A previous command is still waiting to be accepted. 1500 * Just zero our copy of the stats and wait for the 1501 * next timer event to update them. 1502 */ 1503 /* BIG_ENDIAN: no swap required to store 0 */ 1504 sp->tx_good = 0; 1505 sp->tx_underruns = 0; 1506 sp->tx_total_collisions = 0; 1507 1508 sp->rx_good = 0; 1509 sp->rx_crc_errors = 0; 1510 sp->rx_alignment_errors = 0; 1511 sp->rx_rnr_errors = 0; 1512 sp->rx_overrun_errors = 0; 1513 if (sc->sc_rev >= FXP_REV_82558_A4) { 1514 sp->tx_pauseframes = 0; 1515 sp->rx_pauseframes = 0; 1516 } 1517 } 1518 1519 if (sc->sc_flags & FXPF_MII) { 1520 /* Tick the MII clock. */ 1521 mii_tick(&sc->sc_mii); 1522 } 1523 1524 splx(s); 1525 1526 /* 1527 * Schedule another timeout one second from now. 1528 */ 1529 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1530 } 1531 1532 /* 1533 * Drain the receive queue. 1534 */ 1535 void 1536 fxp_rxdrain(struct fxp_softc *sc) 1537 { 1538 bus_dmamap_t rxmap; 1539 struct mbuf *m; 1540 1541 for (;;) { 1542 IF_DEQUEUE(&sc->sc_rxq, m); 1543 if (m == NULL) 1544 break; 1545 rxmap = M_GETCTX(m, bus_dmamap_t); 1546 bus_dmamap_unload(sc->sc_dmat, rxmap); 1547 FXP_RXMAP_PUT(sc, rxmap); 1548 m_freem(m); 1549 } 1550 } 1551 1552 /* 1553 * Stop the interface. Cancels the statistics updater and resets 1554 * the interface. 1555 */ 1556 void 1557 fxp_stop(struct ifnet *ifp, int disable) 1558 { 1559 struct fxp_softc *sc = ifp->if_softc; 1560 struct fxp_txsoft *txs; 1561 int i; 1562 1563 /* 1564 * Turn down interface (done early to avoid bad interactions 1565 * between panics, shutdown hooks, and the watchdog timer) 1566 */ 1567 ifp->if_timer = 0; 1568 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1569 1570 /* 1571 * Cancel stats updater. 1572 */ 1573 callout_stop(&sc->sc_callout); 1574 if (sc->sc_flags & FXPF_MII) { 1575 /* Down the MII. */ 1576 mii_down(&sc->sc_mii); 1577 } 1578 1579 /* 1580 * Issue software reset. This unloads any microcode that 1581 * might already be loaded. 1582 */ 1583 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1584 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1585 DELAY(50); 1586 1587 /* 1588 * Release any xmit buffers. 1589 */ 1590 for (i = 0; i < FXP_NTXCB; i++) { 1591 txs = FXP_DSTX(sc, i); 1592 if (txs->txs_mbuf != NULL) { 1593 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1594 m_freem(txs->txs_mbuf); 1595 txs->txs_mbuf = NULL; 1596 } 1597 } 1598 sc->sc_txpending = 0; 1599 1600 if (disable) { 1601 fxp_rxdrain(sc); 1602 fxp_disable(sc); 1603 } 1604 1605 } 1606 1607 /* 1608 * Watchdog/transmission transmit timeout handler. Called when a 1609 * transmission is started on the interface, but no interrupt is 1610 * received before the timeout. This usually indicates that the 1611 * card has wedged for some reason. 1612 */ 1613 void 1614 fxp_watchdog(struct ifnet *ifp) 1615 { 1616 struct fxp_softc *sc = ifp->if_softc; 1617 1618 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1619 ifp->if_oerrors++; 1620 1621 (void) fxp_init(ifp); 1622 } 1623 1624 /* 1625 * Initialize the interface. Must be called at splnet(). 1626 */ 1627 int 1628 fxp_init(struct ifnet *ifp) 1629 { 1630 struct fxp_softc *sc = ifp->if_softc; 1631 struct fxp_cb_config *cbp; 1632 struct fxp_cb_ias *cb_ias; 1633 struct fxp_txdesc *txd; 1634 bus_dmamap_t rxmap; 1635 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1636 1637 if ((error = fxp_enable(sc)) != 0) 1638 goto out; 1639 1640 /* 1641 * Cancel any pending I/O 1642 */ 1643 fxp_stop(ifp, 0); 1644 1645 /* 1646 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1647 * flag, and this prevents the MII from detaching resulting in 1648 * a panic. The flags field should perhaps be split in runtime 1649 * flags and more static information. For now, just clear the 1650 * only other flag set. 1651 */ 1652 1653 sc->sc_flags &= ~FXPF_WANTINIT; 1654 1655 /* 1656 * Initialize base of CBL and RFA memory. Loading with zero 1657 * sets it up for regular linear addressing. 1658 */ 1659 fxp_scb_wait(sc); 1660 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1661 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1662 1663 fxp_scb_wait(sc); 1664 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1665 1666 /* 1667 * Initialize the multicast filter. Do this now, since we might 1668 * have to setup the config block differently. 1669 */ 1670 fxp_mc_setup(sc); 1671 1672 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1673 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1674 1675 /* 1676 * In order to support receiving 802.1Q VLAN frames, we have to 1677 * enable "save bad frames", since they are 4 bytes larger than 1678 * the normal Ethernet maximum frame length. On i82558 and later, 1679 * we have a better mechanism for this. 1680 */ 1681 save_bf = 0; 1682 lrxen = 0; 1683 vlan_drop = 0; 1684 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1685 if (sc->sc_rev < FXP_REV_82558_A4) 1686 save_bf = 1; 1687 else 1688 lrxen = 1; 1689 if (sc->sc_rev >= FXP_REV_82550) 1690 vlan_drop = 1; 1691 } 1692 1693 /* 1694 * Initialize base of dump-stats buffer. 1695 */ 1696 fxp_scb_wait(sc); 1697 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1698 sc->sc_cddma + FXP_CDSTATSOFF); 1699 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1700 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1701 1702 cbp = &sc->sc_control_data->fcd_configcb; 1703 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1704 1705 /* 1706 * Load microcode for this controller. 1707 */ 1708 fxp_load_ucode(sc); 1709 1710 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1711 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1712 else 1713 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1714 1715 /* 1716 * This copy is kind of disgusting, but there are a bunch of must be 1717 * zero and must be one bits in this structure and this is the easiest 1718 * way to initialize them all to proper values. 1719 */ 1720 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1721 1722 /* BIG_ENDIAN: no need to swap to store 0 */ 1723 cbp->cb_status = 0; 1724 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1725 FXP_CB_COMMAND_EL); 1726 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1727 cbp->link_addr = 0xffffffff; /* (no) next command */ 1728 /* bytes in config block */ 1729 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1730 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1731 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1732 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1733 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1734 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1735 cbp->type_enable = 0; /* actually reserved */ 1736 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1737 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1738 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1739 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1740 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1741 cbp->late_scb = 0; /* (don't) defer SCB update */ 1742 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1743 cbp->ci_int = 1; /* interrupt on CU idle */ 1744 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1745 cbp->ext_stats_dis = 1; /* disable extended counters */ 1746 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1747 cbp->save_bf = save_bf;/* save bad frames */ 1748 cbp->disc_short_rx = !prm; /* discard short packets */ 1749 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1750 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1751 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1752 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1753 /* interface mode */ 1754 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1755 cbp->csma_dis = 0; /* (don't) disable link */ 1756 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1757 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1758 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1759 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1760 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1761 cbp->nsai = 1; /* (don't) disable source addr insert */ 1762 cbp->preamble_length = 2; /* (7 byte) preamble */ 1763 cbp->loopback = 0; /* (don't) loopback */ 1764 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1765 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1766 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1767 cbp->promiscuous = prm; /* promiscuous mode */ 1768 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1769 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1770 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1771 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1772 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1773 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1774 cbp->padding = 1; /* (do) pad short tx packets */ 1775 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1776 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1777 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1778 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1779 /* must set wake_en in PMCSR also */ 1780 cbp->force_fdx = 0; /* (don't) force full duplex */ 1781 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1782 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1783 cbp->mc_all = allm; /* accept all multicasts */ 1784 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1785 cbp->vlan_drop_en = vlan_drop; 1786 1787 if (sc->sc_rev < FXP_REV_82558_A4) { 1788 /* 1789 * The i82557 has no hardware flow control, the values 1790 * here are the defaults for the chip. 1791 */ 1792 cbp->fc_delay_lsb = 0; 1793 cbp->fc_delay_msb = 0x40; 1794 cbp->pri_fc_thresh = 3; 1795 cbp->tx_fc_dis = 0; 1796 cbp->rx_fc_restop = 0; 1797 cbp->rx_fc_restart = 0; 1798 cbp->fc_filter = 0; 1799 cbp->pri_fc_loc = 1; 1800 } else { 1801 cbp->fc_delay_lsb = 0x1f; 1802 cbp->fc_delay_msb = 0x01; 1803 cbp->pri_fc_thresh = 3; 1804 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1805 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1806 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1807 cbp->fc_filter = !prm; /* drop FC frames to host */ 1808 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1809 cbp->ext_stats_dis = 0; /* enable extended stats */ 1810 } 1811 1812 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1813 1814 /* 1815 * Start the config command/DMA. 1816 */ 1817 fxp_scb_wait(sc); 1818 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1819 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1820 /* ...and wait for it to complete. */ 1821 i = 1000; 1822 do { 1823 FXP_CDCONFIGSYNC(sc, 1824 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1825 DELAY(1); 1826 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1827 if (i == 0) { 1828 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1829 sc->sc_dev.dv_xname, __LINE__); 1830 return (ETIMEDOUT); 1831 } 1832 1833 /* 1834 * Initialize the station address. 1835 */ 1836 cb_ias = &sc->sc_control_data->fcd_iascb; 1837 /* BIG_ENDIAN: no need to swap to store 0 */ 1838 cb_ias->cb_status = 0; 1839 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1840 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1841 cb_ias->link_addr = 0xffffffff; 1842 memcpy(cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1843 1844 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1845 1846 /* 1847 * Start the IAS (Individual Address Setup) command/DMA. 1848 */ 1849 fxp_scb_wait(sc); 1850 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1851 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1852 /* ...and wait for it to complete. */ 1853 i = 1000; 1854 do { 1855 FXP_CDIASSYNC(sc, 1856 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1857 DELAY(1); 1858 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1859 if (i == 0) { 1860 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1861 sc->sc_dev.dv_xname, __LINE__); 1862 return (ETIMEDOUT); 1863 } 1864 1865 /* 1866 * Initialize the transmit descriptor ring. txlast is initialized 1867 * to the end of the list so that it will wrap around to the first 1868 * descriptor when the first packet is transmitted. 1869 */ 1870 for (i = 0; i < FXP_NTXCB; i++) { 1871 txd = FXP_CDTX(sc, i); 1872 memset(txd, 0, sizeof(*txd)); 1873 txd->txd_txcb.cb_command = 1874 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1875 txd->txd_txcb.link_addr = 1876 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1877 if (sc->sc_flags & FXPF_EXT_TXCB) 1878 txd->txd_txcb.tbd_array_addr = 1879 htole32(FXP_CDTBDADDR(sc, i) + 1880 (2 * sizeof(struct fxp_tbd))); 1881 else 1882 txd->txd_txcb.tbd_array_addr = 1883 htole32(FXP_CDTBDADDR(sc, i)); 1884 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1885 } 1886 sc->sc_txpending = 0; 1887 sc->sc_txdirty = 0; 1888 sc->sc_txlast = FXP_NTXCB - 1; 1889 1890 /* 1891 * Initialize the receive buffer list. 1892 */ 1893 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1894 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1895 rxmap = FXP_RXMAP_GET(sc); 1896 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1897 log(LOG_ERR, "%s: unable to allocate or map rx " 1898 "buffer %d, error = %d\n", 1899 sc->sc_dev.dv_xname, 1900 sc->sc_rxq.ifq_len, error); 1901 /* 1902 * XXX Should attempt to run with fewer receive 1903 * XXX buffers instead of just failing. 1904 */ 1905 FXP_RXMAP_PUT(sc, rxmap); 1906 fxp_rxdrain(sc); 1907 goto out; 1908 } 1909 } 1910 sc->sc_rxidle = 0; 1911 1912 /* 1913 * Give the transmit ring to the chip. We do this by pointing 1914 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1915 * issuing a start command. It will execute the NOP and then 1916 * suspend, pointing at the first descriptor. 1917 */ 1918 fxp_scb_wait(sc); 1919 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1920 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1921 1922 /* 1923 * Initialize receiver buffer area - RFA. 1924 */ 1925 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1926 fxp_scb_wait(sc); 1927 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1928 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1929 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1930 1931 if (sc->sc_flags & FXPF_MII) { 1932 /* 1933 * Set current media. 1934 */ 1935 mii_mediachg(&sc->sc_mii); 1936 } 1937 1938 /* 1939 * ...all done! 1940 */ 1941 ifp->if_flags |= IFF_RUNNING; 1942 ifp->if_flags &= ~IFF_OACTIVE; 1943 1944 /* 1945 * Start the one second timer. 1946 */ 1947 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1948 1949 /* 1950 * Attempt to start output on the interface. 1951 */ 1952 fxp_start(ifp); 1953 1954 out: 1955 if (error) { 1956 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1957 ifp->if_timer = 0; 1958 log(LOG_ERR, "%s: interface not running\n", 1959 sc->sc_dev.dv_xname); 1960 } 1961 return (error); 1962 } 1963 1964 /* 1965 * Change media according to request. 1966 */ 1967 int 1968 fxp_mii_mediachange(struct ifnet *ifp) 1969 { 1970 struct fxp_softc *sc = ifp->if_softc; 1971 1972 if (ifp->if_flags & IFF_UP) 1973 mii_mediachg(&sc->sc_mii); 1974 return (0); 1975 } 1976 1977 /* 1978 * Notify the world which media we're using. 1979 */ 1980 void 1981 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1982 { 1983 struct fxp_softc *sc = ifp->if_softc; 1984 1985 if (sc->sc_enabled == 0) { 1986 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1987 ifmr->ifm_status = 0; 1988 return; 1989 } 1990 1991 mii_pollstat(&sc->sc_mii); 1992 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1993 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1994 1995 /* 1996 * XXX Flow control is always turned on if the chip supports 1997 * XXX it; we can't easily control it dynamically, since it 1998 * XXX requires sending a setup packet. 1999 */ 2000 if (sc->sc_rev >= FXP_REV_82558_A4) 2001 ifmr->ifm_active |= IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE; 2002 } 2003 2004 int 2005 fxp_80c24_mediachange(struct ifnet *ifp) 2006 { 2007 2008 /* Nothing to do here. */ 2009 return (0); 2010 } 2011 2012 void 2013 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2014 { 2015 struct fxp_softc *sc = ifp->if_softc; 2016 2017 /* 2018 * Media is currently-selected media. We cannot determine 2019 * the link status. 2020 */ 2021 ifmr->ifm_status = 0; 2022 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 2023 } 2024 2025 /* 2026 * Add a buffer to the end of the RFA buffer list. 2027 * Return 0 if successful, error code on failure. 2028 * 2029 * The RFA struct is stuck at the beginning of mbuf cluster and the 2030 * data pointer is fixed up to point just past it. 2031 */ 2032 int 2033 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2034 { 2035 struct mbuf *m; 2036 int error; 2037 2038 MGETHDR(m, M_DONTWAIT, MT_DATA); 2039 if (m == NULL) 2040 return (ENOBUFS); 2041 2042 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2043 MCLGET(m, M_DONTWAIT); 2044 if ((m->m_flags & M_EXT) == 0) { 2045 m_freem(m); 2046 return (ENOBUFS); 2047 } 2048 2049 if (unload) 2050 bus_dmamap_unload(sc->sc_dmat, rxmap); 2051 2052 M_SETCTX(m, rxmap); 2053 2054 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2055 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2056 BUS_DMA_READ|BUS_DMA_NOWAIT); 2057 if (error) { 2058 /* XXX XXX XXX */ 2059 printf("%s: can't load rx DMA map %d, error = %d\n", 2060 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 2061 panic("fxp_add_rfabuf"); 2062 } 2063 2064 FXP_INIT_RFABUF(sc, m); 2065 2066 return (0); 2067 } 2068 2069 int 2070 fxp_mdi_read(struct device *self, int phy, int reg) 2071 { 2072 struct fxp_softc *sc = (struct fxp_softc *)self; 2073 int count = 10000; 2074 int value; 2075 2076 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2077 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2078 2079 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2080 0x10000000) == 0 && count--) 2081 DELAY(10); 2082 2083 if (count <= 0) 2084 log(LOG_WARNING, 2085 "%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 2086 2087 return (value & 0xffff); 2088 } 2089 2090 void 2091 fxp_statchg(struct device *self) 2092 { 2093 2094 /* Nothing to do. */ 2095 } 2096 2097 void 2098 fxp_mdi_write(struct device *self, int phy, int reg, int value) 2099 { 2100 struct fxp_softc *sc = (struct fxp_softc *)self; 2101 int count = 10000; 2102 2103 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2104 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2105 (value & 0xffff)); 2106 2107 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2108 count--) 2109 DELAY(10); 2110 2111 if (count <= 0) 2112 log(LOG_WARNING, 2113 "%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 2114 } 2115 2116 int 2117 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2118 { 2119 struct fxp_softc *sc = ifp->if_softc; 2120 struct ifreq *ifr = (struct ifreq *)data; 2121 int s, error; 2122 2123 s = splnet(); 2124 2125 switch (cmd) { 2126 case SIOCSIFMEDIA: 2127 case SIOCGIFMEDIA: 2128 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2129 break; 2130 2131 default: 2132 error = ether_ioctl(ifp, cmd, data); 2133 if (error == ENETRESET) { 2134 if (ifp->if_flags & IFF_RUNNING) { 2135 /* 2136 * Multicast list has changed; set the 2137 * hardware filter accordingly. 2138 */ 2139 if (sc->sc_txpending) { 2140 sc->sc_flags |= FXPF_WANTINIT; 2141 error = 0; 2142 } else 2143 error = fxp_init(ifp); 2144 } else 2145 error = 0; 2146 } 2147 break; 2148 } 2149 2150 /* Try to get more packets going. */ 2151 if (sc->sc_enabled) 2152 fxp_start(ifp); 2153 2154 splx(s); 2155 return (error); 2156 } 2157 2158 /* 2159 * Program the multicast filter. 2160 * 2161 * This function must be called at splnet(). 2162 */ 2163 void 2164 fxp_mc_setup(struct fxp_softc *sc) 2165 { 2166 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2167 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2168 struct ethercom *ec = &sc->sc_ethercom; 2169 struct ether_multi *enm; 2170 struct ether_multistep step; 2171 int count, nmcasts; 2172 2173 #ifdef DIAGNOSTIC 2174 if (sc->sc_txpending) 2175 panic("fxp_mc_setup: pending transmissions"); 2176 #endif 2177 2178 ifp->if_flags &= ~IFF_ALLMULTI; 2179 2180 /* 2181 * Initialize multicast setup descriptor. 2182 */ 2183 nmcasts = 0; 2184 ETHER_FIRST_MULTI(step, ec, enm); 2185 while (enm != NULL) { 2186 /* 2187 * Check for too many multicast addresses or if we're 2188 * listening to a range. Either way, we simply have 2189 * to accept all multicasts. 2190 */ 2191 if (nmcasts >= MAXMCADDR || 2192 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2193 ETHER_ADDR_LEN) != 0) { 2194 /* 2195 * Callers of this function must do the 2196 * right thing with this. If we're called 2197 * from outside fxp_init(), the caller must 2198 * detect if the state if IFF_ALLMULTI changes. 2199 * If it does, the caller must then call 2200 * fxp_init(), since allmulti is handled by 2201 * the config block. 2202 */ 2203 ifp->if_flags |= IFF_ALLMULTI; 2204 return; 2205 } 2206 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2207 ETHER_ADDR_LEN); 2208 nmcasts++; 2209 ETHER_NEXT_MULTI(step, enm); 2210 } 2211 2212 /* BIG_ENDIAN: no need to swap to store 0 */ 2213 mcsp->cb_status = 0; 2214 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2215 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2216 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2217 2218 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2219 2220 /* 2221 * Wait until the command unit is not active. This should never 2222 * happen since nothing is queued, but make sure anyway. 2223 */ 2224 count = 100; 2225 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2226 FXP_SCB_CUS_ACTIVE && --count) 2227 DELAY(1); 2228 if (count == 0) { 2229 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2230 sc->sc_dev.dv_xname, __LINE__); 2231 return; 2232 } 2233 2234 /* 2235 * Start the multicast setup command/DMA. 2236 */ 2237 fxp_scb_wait(sc); 2238 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2239 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2240 2241 /* ...and wait for it to complete. */ 2242 count = 1000; 2243 do { 2244 FXP_CDMCSSYNC(sc, 2245 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2246 DELAY(1); 2247 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2248 if (count == 0) { 2249 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2250 sc->sc_dev.dv_xname, __LINE__); 2251 return; 2252 } 2253 } 2254 2255 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2256 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2257 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2258 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2259 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2260 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2261 2262 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2263 2264 static const struct ucode { 2265 int32_t revision; 2266 const uint32_t *ucode; 2267 size_t length; 2268 uint16_t int_delay_offset; 2269 uint16_t bundle_max_offset; 2270 } ucode_table[] = { 2271 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2272 D101_CPUSAVER_DWORD, 0 }, 2273 2274 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2275 D101_CPUSAVER_DWORD, 0 }, 2276 2277 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2278 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2279 2280 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2281 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2282 2283 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2284 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2285 2286 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2287 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2288 2289 { 0, NULL, 0, 0, 0 } 2290 }; 2291 2292 void 2293 fxp_load_ucode(struct fxp_softc *sc) 2294 { 2295 const struct ucode *uc; 2296 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2297 int count, i; 2298 2299 if (sc->sc_flags & FXPF_UCODE_LOADED) 2300 return; 2301 2302 /* 2303 * Only load the uCode if the user has requested that 2304 * we do so. 2305 */ 2306 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2307 sc->sc_int_delay = 0; 2308 sc->sc_bundle_max = 0; 2309 return; 2310 } 2311 2312 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2313 if (sc->sc_rev == uc->revision) 2314 break; 2315 } 2316 if (uc->ucode == NULL) 2317 return; 2318 2319 /* BIG ENDIAN: no need to swap to store 0 */ 2320 cbp->cb_status = 0; 2321 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2322 cbp->link_addr = 0xffffffff; /* (no) next command */ 2323 for (i = 0; i < uc->length; i++) 2324 cbp->ucode[i] = htole32(uc->ucode[i]); 2325 2326 if (uc->int_delay_offset) 2327 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2328 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2329 2330 if (uc->bundle_max_offset) 2331 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2332 htole16(fxp_bundle_max); 2333 2334 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2335 2336 /* 2337 * Download the uCode to the chip. 2338 */ 2339 fxp_scb_wait(sc); 2340 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2341 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2342 2343 /* ...and wait for it to complete. */ 2344 count = 10000; 2345 do { 2346 FXP_CDUCODESYNC(sc, 2347 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2348 DELAY(2); 2349 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2350 if (count == 0) { 2351 sc->sc_int_delay = 0; 2352 sc->sc_bundle_max = 0; 2353 log(LOG_WARNING, "%s: timeout loading microcode\n", 2354 sc->sc_dev.dv_xname); 2355 return; 2356 } 2357 2358 if (sc->sc_int_delay != fxp_int_delay || 2359 sc->sc_bundle_max != fxp_bundle_max) { 2360 sc->sc_int_delay = fxp_int_delay; 2361 sc->sc_bundle_max = fxp_bundle_max; 2362 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2363 "max bundle: %d\n", sc->sc_dev.dv_xname, 2364 sc->sc_int_delay, 2365 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2366 } 2367 2368 sc->sc_flags |= FXPF_UCODE_LOADED; 2369 } 2370 2371 int 2372 fxp_enable(struct fxp_softc *sc) 2373 { 2374 2375 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2376 if ((*sc->sc_enable)(sc) != 0) { 2377 log(LOG_ERR, "%s: device enable failed\n", 2378 sc->sc_dev.dv_xname); 2379 return (EIO); 2380 } 2381 } 2382 2383 sc->sc_enabled = 1; 2384 return (0); 2385 } 2386 2387 void 2388 fxp_disable(struct fxp_softc *sc) 2389 { 2390 2391 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2392 (*sc->sc_disable)(sc); 2393 sc->sc_enabled = 0; 2394 } 2395 } 2396 2397 /* 2398 * fxp_activate: 2399 * 2400 * Handle device activation/deactivation requests. 2401 */ 2402 int 2403 fxp_activate(struct device *self, enum devact act) 2404 { 2405 struct fxp_softc *sc = (void *) self; 2406 int s, error = 0; 2407 2408 s = splnet(); 2409 switch (act) { 2410 case DVACT_ACTIVATE: 2411 error = EOPNOTSUPP; 2412 break; 2413 2414 case DVACT_DEACTIVATE: 2415 if (sc->sc_flags & FXPF_MII) 2416 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2417 MII_OFFSET_ANY); 2418 if_deactivate(&sc->sc_ethercom.ec_if); 2419 break; 2420 } 2421 splx(s); 2422 2423 return (error); 2424 } 2425 2426 /* 2427 * fxp_detach: 2428 * 2429 * Detach an i82557 interface. 2430 */ 2431 int 2432 fxp_detach(struct fxp_softc *sc) 2433 { 2434 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2435 int i; 2436 2437 /* Succeed now if there's no work to do. */ 2438 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2439 return (0); 2440 2441 /* Unhook our tick handler. */ 2442 callout_stop(&sc->sc_callout); 2443 2444 if (sc->sc_flags & FXPF_MII) { 2445 /* Detach all PHYs */ 2446 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2447 } 2448 2449 /* Delete all remaining media. */ 2450 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2451 2452 #if NRND > 0 2453 rnd_detach_source(&sc->rnd_source); 2454 #endif 2455 ether_ifdetach(ifp); 2456 if_detach(ifp); 2457 2458 for (i = 0; i < FXP_NRFABUFS; i++) { 2459 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2460 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2461 } 2462 2463 for (i = 0; i < FXP_NTXCB; i++) { 2464 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2465 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2466 } 2467 2468 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2469 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2470 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2471 sizeof(struct fxp_control_data)); 2472 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2473 2474 shutdownhook_disestablish(sc->sc_sdhook); 2475 powerhook_disestablish(sc->sc_powerhook); 2476 2477 return (0); 2478 } 2479