1 /* $NetBSD: hme.c,v 1.105 2019/05/28 07:41:48 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * HME Ethernet module driver. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.105 2019/05/28 07:41:48 msaitoh Exp $"); 38 39 /* #define HMEDEBUG */ 40 41 #include "opt_inet.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/mbuf.h> 47 #include <sys/syslog.h> 48 #include <sys/socket.h> 49 #include <sys/device.h> 50 #include <sys/malloc.h> 51 #include <sys/ioctl.h> 52 #include <sys/errno.h> 53 #include <sys/rndsource.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_ether.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 61 #ifdef INET 62 #include <net/if_vlanvar.h> 63 #include <netinet/in.h> 64 #include <netinet/if_inarp.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <sys/bus.h> 76 77 #include <dev/ic/hmereg.h> 78 #include <dev/ic/hmevar.h> 79 80 static void hme_start(struct ifnet *); 81 static void hme_stop(struct ifnet *, int); 82 static int hme_ioctl(struct ifnet *, u_long, void *); 83 static void hme_tick(void *); 84 static void hme_watchdog(struct ifnet *); 85 static bool hme_shutdown(device_t, int); 86 static int hme_init(struct ifnet *); 87 static void hme_meminit(struct hme_softc *); 88 static void hme_mifinit(struct hme_softc *); 89 static void hme_reset(struct hme_softc *); 90 static void hme_chipreset(struct hme_softc *); 91 static void hme_setladrf(struct hme_softc *); 92 93 /* MII methods & callbacks */ 94 static int hme_mii_readreg(device_t, int, int, uint16_t *); 95 static int hme_mii_writereg(device_t, int, int, uint16_t); 96 static void hme_mii_statchg(struct ifnet *); 97 98 static int hme_mediachange(struct ifnet *); 99 100 static struct mbuf *hme_get(struct hme_softc *, int, uint32_t); 101 static int hme_put(struct hme_softc *, int, struct mbuf *); 102 static void hme_read(struct hme_softc *, int, uint32_t); 103 static int hme_eint(struct hme_softc *, u_int); 104 static int hme_rint(struct hme_softc *); 105 static int hme_tint(struct hme_softc *); 106 107 #if 0 108 /* Default buffer copy routines */ 109 static void hme_copytobuf_contig(struct hme_softc *, void *, int, int); 110 static void hme_copyfrombuf_contig(struct hme_softc *, void *, int, int); 111 #endif 112 113 void 114 hme_config(struct hme_softc *sc) 115 { 116 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 117 struct mii_data *mii = &sc->sc_mii; 118 struct mii_softc *child; 119 bus_dma_tag_t dmatag = sc->sc_dmatag; 120 bus_dma_segment_t seg; 121 bus_size_t size; 122 int rseg, error; 123 124 /* 125 * HME common initialization. 126 * 127 * hme_softc fields that must be initialized by the front-end: 128 * 129 * the bus tag: 130 * sc_bustag 131 * 132 * the DMA bus tag: 133 * sc_dmatag 134 * 135 * the bus handles: 136 * sc_seb (Shared Ethernet Block registers) 137 * sc_erx (Receiver Unit registers) 138 * sc_etx (Transmitter Unit registers) 139 * sc_mac (MAC registers) 140 * sc_mif (Management Interface registers) 141 * 142 * the maximum bus burst size: 143 * sc_burst 144 * 145 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 146 * rb_membase, rb_dmabase) 147 * 148 * the local Ethernet address: 149 * sc_enaddr 150 * 151 */ 152 153 /* Make sure the chip is stopped. */ 154 hme_chipreset(sc); 155 156 /* 157 * Allocate descriptors and buffers 158 * XXX - do all this differently.. and more configurably, 159 * eg. use things as `dma_load_mbuf()' on transmit, 160 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 161 * all the time) on the receiver side. 162 * 163 * Note: receive buffers must be 64-byte aligned. 164 * Also, apparently, the buffers must extend to a DMA burst 165 * boundary beyond the maximum packet size. 166 */ 167 #define _HME_NDESC 128 168 #define _HME_BUFSZ 1600 169 170 /* Note: the # of descriptors must be a multiple of 16 */ 171 sc->sc_rb.rb_ntbuf = _HME_NDESC; 172 sc->sc_rb.rb_nrbuf = _HME_NDESC; 173 174 /* 175 * Allocate DMA capable memory 176 * Buffer descriptors must be aligned on a 2048 byte boundary; 177 * take this into account when calculating the size. Note that 178 * the maximum number of descriptors (256) occupies 2048 bytes, 179 * so we allocate that much regardless of _HME_NDESC. 180 */ 181 size = 2048 + /* TX descriptors */ 182 2048 + /* RX descriptors */ 183 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 184 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* RX buffers */ 185 186 /* Allocate DMA buffer */ 187 if ((error = bus_dmamem_alloc(dmatag, size, 188 2048, 0, 189 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 190 aprint_error_dev(sc->sc_dev, "DMA buffer alloc error %d\n", 191 error); 192 return; 193 } 194 195 /* Map DMA memory in CPU addressable space */ 196 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 197 &sc->sc_rb.rb_membase, 198 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 199 aprint_error_dev(sc->sc_dev, "DMA buffer map error %d\n", 200 error); 201 bus_dmamap_unload(dmatag, sc->sc_dmamap); 202 bus_dmamem_free(dmatag, &seg, rseg); 203 return; 204 } 205 206 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 207 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 208 aprint_error_dev(sc->sc_dev, "DMA map create error %d\n", 209 error); 210 return; 211 } 212 213 /* Load the buffer */ 214 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 215 sc->sc_rb.rb_membase, size, NULL, 216 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 217 aprint_error_dev(sc->sc_dev, "DMA buffer map load error %d\n", 218 error); 219 bus_dmamem_free(dmatag, &seg, rseg); 220 return; 221 } 222 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 223 224 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 225 ether_sprintf(sc->sc_enaddr)); 226 227 /* Initialize ifnet structure. */ 228 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 229 ifp->if_softc = sc; 230 ifp->if_start = hme_start; 231 ifp->if_stop = hme_stop; 232 ifp->if_ioctl = hme_ioctl; 233 ifp->if_init = hme_init; 234 ifp->if_watchdog = hme_watchdog; 235 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 236 sc->sc_if_flags = ifp->if_flags; 237 ifp->if_capabilities |= 238 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 239 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 240 IFQ_SET_READY(&ifp->if_snd); 241 242 /* Initialize ifmedia structures and MII info */ 243 mii->mii_ifp = ifp; 244 mii->mii_readreg = hme_mii_readreg; 245 mii->mii_writereg = hme_mii_writereg; 246 mii->mii_statchg = hme_mii_statchg; 247 248 sc->sc_ethercom.ec_mii = mii; 249 ifmedia_init(&mii->mii_media, 0, hme_mediachange, ether_mediastatus); 250 251 hme_mifinit(sc); 252 253 mii_attach(sc->sc_dev, mii, 0xffffffff, 254 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 255 256 child = LIST_FIRST(&mii->mii_phys); 257 if (child == NULL) { 258 /* No PHY attached */ 259 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 260 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 261 } else { 262 /* 263 * Walk along the list of attached MII devices and 264 * establish an `MII instance' to `phy number' 265 * mapping. We'll use this mapping in media change 266 * requests to determine which phy to use to program 267 * the MIF configuration register. 268 */ 269 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 270 /* 271 * Note: we support just two PHYs: the built-in 272 * internal device and an external on the MII 273 * connector. 274 */ 275 if (child->mii_phy > 1 || child->mii_inst > 1) { 276 aprint_error_dev(sc->sc_dev, 277 "cannot accommodate MII device %s" 278 " at phy %d, instance %d\n", 279 device_xname(child->mii_dev), 280 child->mii_phy, child->mii_inst); 281 continue; 282 } 283 284 sc->sc_phys[child->mii_inst] = child->mii_phy; 285 } 286 287 /* 288 * Set the default media to auto negotiation if the phy has 289 * the auto negotiation capability. 290 * XXX; What to do otherwise? 291 */ 292 if (ifmedia_match(&mii->mii_media, IFM_ETHER | IFM_AUTO, 0)) 293 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 294 /* 295 else 296 ifmedia_set(&sc->sc_mii.mii_media, sc->sc_defaultmedia); 297 */ 298 } 299 300 /* claim 802.1q capability */ 301 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 302 303 /* Attach the interface. */ 304 if_attach(ifp); 305 if_deferred_start_init(ifp, NULL); 306 ether_ifattach(ifp, sc->sc_enaddr); 307 308 if (pmf_device_register1(sc->sc_dev, NULL, NULL, hme_shutdown)) 309 pmf_class_network_register(sc->sc_dev, ifp); 310 else 311 aprint_error_dev(sc->sc_dev, 312 "couldn't establish power handler\n"); 313 314 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 315 RND_TYPE_NET, RND_FLAG_DEFAULT); 316 317 callout_init(&sc->sc_tick_ch, 0); 318 } 319 320 void 321 hme_tick(void *arg) 322 { 323 struct hme_softc *sc = arg; 324 int s; 325 326 s = splnet(); 327 mii_tick(&sc->sc_mii); 328 splx(s); 329 330 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 331 } 332 333 void 334 hme_reset(struct hme_softc *sc) 335 { 336 int s; 337 338 s = splnet(); 339 (void)hme_init(&sc->sc_ethercom.ec_if); 340 splx(s); 341 } 342 343 void 344 hme_chipreset(struct hme_softc *sc) 345 { 346 bus_space_tag_t t = sc->sc_bustag; 347 bus_space_handle_t seb = sc->sc_seb; 348 int n; 349 350 /* Mask all interrupts */ 351 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff); 352 353 /* Reset transmitter and receiver */ 354 bus_space_write_4(t, seb, HME_SEBI_RESET, 355 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 356 357 for (n = 0; n < 20; n++) { 358 uint32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 359 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 360 return; 361 DELAY(20); 362 } 363 364 printf("%s: %s: reset failed\n", device_xname(sc->sc_dev), __func__); 365 } 366 367 void 368 hme_stop(struct ifnet *ifp, int disable) 369 { 370 struct hme_softc *sc; 371 372 sc = ifp->if_softc; 373 374 ifp->if_timer = 0; 375 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 376 377 callout_stop(&sc->sc_tick_ch); 378 mii_down(&sc->sc_mii); 379 380 hme_chipreset(sc); 381 } 382 383 void 384 hme_meminit(struct hme_softc *sc) 385 { 386 bus_addr_t txbufdma, rxbufdma; 387 bus_addr_t dma; 388 char *p; 389 unsigned int ntbuf, nrbuf, i; 390 struct hme_ring *hr = &sc->sc_rb; 391 392 p = hr->rb_membase; 393 dma = hr->rb_dmabase; 394 395 ntbuf = hr->rb_ntbuf; 396 nrbuf = hr->rb_nrbuf; 397 398 /* 399 * Allocate transmit descriptors 400 */ 401 hr->rb_txd = p; 402 hr->rb_txddma = dma; 403 p += ntbuf * HME_XD_SIZE; 404 dma += ntbuf * HME_XD_SIZE; 405 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 406 dma = (bus_addr_t)roundup((u_long)dma, 2048); 407 p = (void *)roundup((u_long)p, 2048); 408 409 /* 410 * Allocate receive descriptors 411 */ 412 hr->rb_rxd = p; 413 hr->rb_rxddma = dma; 414 p += nrbuf * HME_XD_SIZE; 415 dma += nrbuf * HME_XD_SIZE; 416 /* Again move forward to the next 2048 byte boundary.*/ 417 dma = (bus_addr_t)roundup((u_long)dma, 2048); 418 p = (void *)roundup((u_long)p, 2048); 419 420 421 /* 422 * Allocate transmit buffers 423 */ 424 hr->rb_txbuf = p; 425 txbufdma = dma; 426 p += ntbuf * _HME_BUFSZ; 427 dma += ntbuf * _HME_BUFSZ; 428 429 /* 430 * Allocate receive buffers 431 */ 432 hr->rb_rxbuf = p; 433 rxbufdma = dma; 434 p += nrbuf * _HME_BUFSZ; 435 dma += nrbuf * _HME_BUFSZ; 436 437 /* 438 * Initialize transmit buffer descriptors 439 */ 440 for (i = 0; i < ntbuf; i++) { 441 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 442 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 443 } 444 445 /* 446 * Initialize receive buffer descriptors 447 */ 448 for (i = 0; i < nrbuf; i++) { 449 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 450 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 451 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 452 } 453 454 hr->rb_tdhead = hr->rb_tdtail = 0; 455 hr->rb_td_nbusy = 0; 456 hr->rb_rdtail = 0; 457 } 458 459 /* 460 * Initialization of interface; set up initialization block 461 * and transmit/receive descriptor rings. 462 */ 463 int 464 hme_init(struct ifnet *ifp) 465 { 466 struct hme_softc *sc = ifp->if_softc; 467 bus_space_tag_t t = sc->sc_bustag; 468 bus_space_handle_t seb = sc->sc_seb; 469 bus_space_handle_t etx = sc->sc_etx; 470 bus_space_handle_t erx = sc->sc_erx; 471 bus_space_handle_t mac = sc->sc_mac; 472 uint8_t *ea; 473 uint32_t v; 474 int rc; 475 476 /* 477 * Initialization sequence. The numbered steps below correspond 478 * to the sequence outlined in section 6.3.5.1 in the Ethernet 479 * Channel Engine manual (part of the PCIO manual). 480 * See also the STP2002-STQ document from Sun Microsystems. 481 */ 482 483 /* step 1 & 2. Reset the Ethernet Channel */ 484 hme_stop(ifp, 0); 485 486 /* Re-initialize the MIF */ 487 hme_mifinit(sc); 488 489 /* Call MI reset function if any */ 490 if (sc->sc_hwreset) 491 (*sc->sc_hwreset)(sc); 492 493 #if 0 494 /* Mask all MIF interrupts, just in case */ 495 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 496 #endif 497 498 /* step 3. Setup data structures in host memory */ 499 hme_meminit(sc); 500 501 /* step 4. TX MAC registers & counters */ 502 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 503 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 504 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 505 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 506 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 507 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 508 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 509 sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable; 510 511 /* Load station MAC address */ 512 ea = sc->sc_enaddr; 513 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 514 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 515 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 516 517 /* 518 * Init seed for backoff 519 * (source suggested by manual: low 10 bits of MAC address) 520 */ 521 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 522 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 523 524 525 /* Note: Accepting power-on default for other MAC registers here.. */ 526 527 528 /* step 5. RX MAC registers & counters */ 529 hme_setladrf(sc); 530 531 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 532 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 533 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 534 535 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 536 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 537 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 538 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 539 540 /* step 8. Global Configuration & Interrupt Mask */ 541 bus_space_write_4(t, seb, HME_SEBI_IMASK, 542 ~( 543 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 544 HME_SEB_STAT_HOSTTOTX | 545 HME_SEB_STAT_RXTOHOST | 546 HME_SEB_STAT_TXALL | 547 HME_SEB_STAT_TXPERR | 548 HME_SEB_STAT_RCNTEXP | 549 HME_SEB_STAT_MIFIRQ | 550 HME_SEB_STAT_ALL_ERRORS )); 551 552 switch (sc->sc_burst) { 553 default: 554 v = 0; 555 break; 556 case 16: 557 v = HME_SEB_CFG_BURST16; 558 break; 559 case 32: 560 v = HME_SEB_CFG_BURST32; 561 break; 562 case 64: 563 v = HME_SEB_CFG_BURST64; 564 break; 565 } 566 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 567 568 /* step 9. ETX Configuration: use mostly default values */ 569 570 /* Enable DMA */ 571 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 572 v |= HME_ETX_CFG_DMAENABLE; 573 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 574 575 /* Transmit Descriptor ring size: in increments of 16 */ 576 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 577 578 579 /* step 10. ERX Configuration */ 580 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 581 582 /* Encode Receive Descriptor ring size: four possible values */ 583 switch (_HME_NDESC /*XXX*/) { 584 case 32: 585 v |= HME_ERX_CFG_RINGSIZE32; 586 break; 587 case 64: 588 v |= HME_ERX_CFG_RINGSIZE64; 589 break; 590 case 128: 591 v |= HME_ERX_CFG_RINGSIZE128; 592 break; 593 case 256: 594 v |= HME_ERX_CFG_RINGSIZE256; 595 break; 596 default: 597 printf("hme: invalid Receive Descriptor ring size\n"); 598 break; 599 } 600 601 /* Enable DMA */ 602 v |= HME_ERX_CFG_DMAENABLE; 603 604 /* set h/w rx checksum start offset (# of half-words) */ 605 #ifdef INET 606 v |= (((ETHER_HDR_LEN + sizeof(struct ip)) / sizeof(uint16_t)) 607 << HME_ERX_CFG_CSUMSHIFT) & 608 HME_ERX_CFG_CSUMSTART; 609 #endif 610 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 611 612 /* step 11. XIF Configuration */ 613 v = bus_space_read_4(t, mac, HME_MACI_XIF); 614 v |= HME_MAC_XIF_OE; 615 bus_space_write_4(t, mac, HME_MACI_XIF, v); 616 617 /* step 12. RX_MAC Configuration Register */ 618 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 619 v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP; 620 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 621 622 /* step 13. TX_MAC Configuration Register */ 623 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 624 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 625 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 626 627 /* step 14. Issue Transmit Pending command */ 628 629 /* Call MI initialization function if any */ 630 if (sc->sc_hwinit) 631 (*sc->sc_hwinit)(sc); 632 633 /* Set the current media. */ 634 if ((rc = hme_mediachange(ifp)) != 0) 635 return rc; 636 637 /* Start the one second timer. */ 638 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 639 640 ifp->if_flags |= IFF_RUNNING; 641 ifp->if_flags &= ~IFF_OACTIVE; 642 sc->sc_if_flags = ifp->if_flags; 643 ifp->if_timer = 0; 644 hme_start(ifp); 645 return 0; 646 } 647 648 /* 649 * Routine to copy from mbuf chain to transmit buffer in 650 * network buffer memory. 651 * Returns the amount of data copied. 652 */ 653 int 654 hme_put(struct hme_softc *sc, int ri, struct mbuf *m) 655 /* ri: Ring index */ 656 { 657 struct mbuf *n; 658 int len, tlen = 0; 659 char *bp; 660 661 bp = (char *)sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 662 for (; m; m = n) { 663 len = m->m_len; 664 if (len == 0) { 665 n = m_free(m); 666 continue; 667 } 668 memcpy(bp, mtod(m, void *), len); 669 bp += len; 670 tlen += len; 671 n = m_free(m); 672 } 673 return (tlen); 674 } 675 676 /* 677 * Pull data off an interface. 678 * Len is length of data, with local net header stripped. 679 * We copy the data into mbufs. When full cluster sized units are present 680 * we copy into clusters. 681 */ 682 struct mbuf * 683 hme_get(struct hme_softc *sc, int ri, uint32_t flags) 684 { 685 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 686 struct mbuf *m, *m0, *newm; 687 char *bp; 688 int len, totlen; 689 #ifdef INET 690 int csum_flags; 691 #endif 692 693 totlen = HME_XD_DECODE_RSIZE(flags); 694 MGETHDR(m0, M_DONTWAIT, MT_DATA); 695 if (m0 == 0) 696 return (0); 697 m_set_rcvif(m0, ifp); 698 m0->m_pkthdr.len = totlen; 699 len = MHLEN; 700 m = m0; 701 702 bp = (char *)sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 703 704 while (totlen > 0) { 705 if (totlen >= MINCLSIZE) { 706 MCLGET(m, M_DONTWAIT); 707 if ((m->m_flags & M_EXT) == 0) 708 goto bad; 709 len = MCLBYTES; 710 } 711 712 if (m == m0) { 713 char *newdata = (char *) 714 ALIGN(m->m_data + sizeof(struct ether_header)) - 715 sizeof(struct ether_header); 716 len -= newdata - m->m_data; 717 m->m_data = newdata; 718 } 719 720 m->m_len = len = uimin(totlen, len); 721 memcpy(mtod(m, void *), bp, len); 722 bp += len; 723 724 totlen -= len; 725 if (totlen > 0) { 726 MGET(newm, M_DONTWAIT, MT_DATA); 727 if (newm == 0) 728 goto bad; 729 len = MLEN; 730 m = m->m_next = newm; 731 } 732 } 733 734 #ifdef INET 735 /* hardware checksum */ 736 csum_flags = 0; 737 if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 738 struct ether_header *eh; 739 struct ether_vlan_header *evh; 740 struct ip *ip; 741 struct udphdr *uh; 742 uint16_t *opts; 743 int32_t hlen, pktlen; 744 uint32_t csum_data; 745 746 eh = mtod(m0, struct ether_header *); 747 if (ntohs(eh->ether_type) == ETHERTYPE_IP) { 748 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN); 749 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN; 750 } else if (ntohs(eh->ether_type) == ETHERTYPE_VLAN) { 751 evh = (struct ether_vlan_header *)eh; 752 if (ntohs(evh->evl_proto) != ETHERTYPE_IP) 753 goto swcsum; 754 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN + 755 ETHER_VLAN_ENCAP_LEN); 756 pktlen = m0->m_pkthdr.len - 757 ETHER_HDR_LEN - ETHER_VLAN_ENCAP_LEN; 758 } else 759 goto swcsum; 760 761 /* IPv4 only */ 762 if (ip->ip_v != IPVERSION) 763 goto swcsum; 764 765 hlen = ip->ip_hl << 2; 766 if (hlen < sizeof(struct ip)) 767 goto swcsum; 768 769 /* 770 * bail if too short, has random trailing garbage, truncated, 771 * fragment, or has ethernet pad. 772 */ 773 if (ntohs(ip->ip_len) < hlen || 774 ntohs(ip->ip_len) != pktlen || 775 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 776 goto swcsum; 777 778 switch (ip->ip_p) { 779 case IPPROTO_TCP: 780 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0) 781 goto swcsum; 782 if (pktlen < (hlen + sizeof(struct tcphdr))) 783 goto swcsum; 784 csum_flags = 785 M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 786 break; 787 case IPPROTO_UDP: 788 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0) 789 goto swcsum; 790 if (pktlen < (hlen + sizeof(struct udphdr))) 791 goto swcsum; 792 uh = (struct udphdr *)((char *)ip + hlen); 793 /* no checksum */ 794 if (uh->uh_sum == 0) 795 goto swcsum; 796 csum_flags = 797 M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 798 break; 799 default: 800 goto swcsum; 801 } 802 803 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */ 804 csum_data = ~flags & HME_XD_RXCKSUM; 805 806 /* 807 * If data offset is different from RX cksum start offset, 808 * we have to deduct them. 809 */ 810 hlen = ((char *)ip + hlen) - 811 ((char *)eh + ETHER_HDR_LEN + sizeof(struct ip)); 812 if (hlen > 1) { 813 uint32_t optsum; 814 815 optsum = 0; 816 opts = (uint16_t *)((char *)eh + 817 ETHER_HDR_LEN + sizeof(struct ip)); 818 819 while (hlen > 1) { 820 optsum += ntohs(*opts++); 821 hlen -= 2; 822 } 823 while (optsum >> 16) 824 optsum = (optsum >> 16) + (optsum & 0xffff); 825 826 /* Deduct the ip opts sum from the hwsum. */ 827 csum_data += (uint16_t)~optsum; 828 829 while (csum_data >> 16) 830 csum_data = 831 (csum_data >> 16) + (csum_data & 0xffff); 832 } 833 m0->m_pkthdr.csum_data = csum_data; 834 } 835 swcsum: 836 m0->m_pkthdr.csum_flags = csum_flags; 837 #endif 838 839 return (m0); 840 841 bad: 842 m_freem(m0); 843 return (0); 844 } 845 846 /* 847 * Pass a packet to the higher levels. 848 */ 849 void 850 hme_read(struct hme_softc *sc, int ix, uint32_t flags) 851 { 852 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 853 struct mbuf *m; 854 int len; 855 856 len = HME_XD_DECODE_RSIZE(flags); 857 if (len <= sizeof(struct ether_header) || 858 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 859 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 860 ETHERMTU + sizeof(struct ether_header))) { 861 #ifdef HMEDEBUG 862 printf("%s: invalid packet size %d; dropping\n", 863 device_xname(sc->sc_dev), len); 864 #endif 865 ifp->if_ierrors++; 866 return; 867 } 868 869 /* Pull packet off interface. */ 870 m = hme_get(sc, ix, flags); 871 if (m == 0) { 872 ifp->if_ierrors++; 873 return; 874 } 875 876 /* Pass the packet up. */ 877 if_percpuq_enqueue(ifp->if_percpuq, m); 878 } 879 880 void 881 hme_start(struct ifnet *ifp) 882 { 883 struct hme_softc *sc = ifp->if_softc; 884 void *txd = sc->sc_rb.rb_txd; 885 struct mbuf *m; 886 unsigned int txflags; 887 unsigned int ri, len, obusy; 888 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 889 890 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 891 return; 892 893 ri = sc->sc_rb.rb_tdhead; 894 obusy = sc->sc_rb.rb_td_nbusy; 895 896 for (;;) { 897 IFQ_DEQUEUE(&ifp->if_snd, m); 898 if (m == 0) 899 break; 900 901 /* 902 * If BPF is listening on this interface, let it see the 903 * packet before we commit it to the wire. 904 */ 905 bpf_mtap(ifp, m, BPF_D_OUT); 906 907 #ifdef INET 908 /* collect bits for h/w csum, before hme_put frees the mbuf */ 909 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) && 910 m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 911 struct ether_header *eh; 912 uint16_t offset, start; 913 914 eh = mtod(m, struct ether_header *); 915 switch (ntohs(eh->ether_type)) { 916 case ETHERTYPE_IP: 917 start = ETHER_HDR_LEN; 918 break; 919 case ETHERTYPE_VLAN: 920 start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 921 break; 922 default: 923 /* unsupported, drop it */ 924 m_free(m); 925 continue; 926 } 927 start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 928 offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data) 929 + start; 930 txflags = HME_XD_TXCKSUM | 931 (offset << HME_XD_TXCSSTUFFSHIFT) | 932 (start << HME_XD_TXCSSTARTSHIFT); 933 } else 934 #endif 935 txflags = 0; 936 937 /* 938 * Copy the mbuf chain into the transmit buffer. 939 */ 940 len = hme_put(sc, ri, m); 941 942 /* 943 * Initialize transmit registers and start transmission 944 */ 945 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 946 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 947 HME_XD_ENCODE_TSIZE(len) | txflags); 948 949 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 950 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 951 HME_ETX_TP_DMAWAKEUP); 952 953 if (++ri == ntbuf) 954 ri = 0; 955 956 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 957 ifp->if_flags |= IFF_OACTIVE; 958 break; 959 } 960 } 961 962 if (obusy != sc->sc_rb.rb_td_nbusy) { 963 sc->sc_rb.rb_tdhead = ri; 964 ifp->if_timer = 5; 965 } 966 } 967 968 /* 969 * Transmit interrupt. 970 */ 971 int 972 hme_tint(struct hme_softc *sc) 973 { 974 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 975 bus_space_tag_t t = sc->sc_bustag; 976 bus_space_handle_t mac = sc->sc_mac; 977 unsigned int ri, txflags; 978 979 /* 980 * Unload collision counters 981 */ 982 ifp->if_collisions += 983 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 984 bus_space_read_4(t, mac, HME_MACI_FCCNT); 985 ifp->if_oerrors += 986 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 987 bus_space_read_4(t, mac, HME_MACI_LTCNT); 988 989 /* 990 * then clear the hardware counters. 991 */ 992 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 993 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 994 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 995 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 996 997 /* Fetch current position in the transmit ring */ 998 ri = sc->sc_rb.rb_tdtail; 999 1000 for (;;) { 1001 if (sc->sc_rb.rb_td_nbusy <= 0) 1002 break; 1003 1004 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 1005 1006 if (txflags & HME_XD_OWN) 1007 break; 1008 1009 ifp->if_flags &= ~IFF_OACTIVE; 1010 ifp->if_opackets++; 1011 1012 if (++ri == sc->sc_rb.rb_ntbuf) 1013 ri = 0; 1014 1015 --sc->sc_rb.rb_td_nbusy; 1016 } 1017 1018 /* Update ring */ 1019 sc->sc_rb.rb_tdtail = ri; 1020 1021 if_schedule_deferred_start(ifp); 1022 1023 if (sc->sc_rb.rb_td_nbusy == 0) 1024 ifp->if_timer = 0; 1025 1026 return (1); 1027 } 1028 1029 /* 1030 * Receive interrupt. 1031 */ 1032 int 1033 hme_rint(struct hme_softc *sc) 1034 { 1035 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1036 bus_space_tag_t t = sc->sc_bustag; 1037 bus_space_handle_t mac = sc->sc_mac; 1038 void *xdr = sc->sc_rb.rb_rxd; 1039 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 1040 unsigned int ri; 1041 uint32_t flags; 1042 1043 ri = sc->sc_rb.rb_rdtail; 1044 1045 /* 1046 * Process all buffers with valid data. 1047 */ 1048 for (;;) { 1049 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 1050 if (flags & HME_XD_OWN) 1051 break; 1052 1053 if (flags & HME_XD_OFL) { 1054 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 1055 device_xname(sc->sc_dev), ri, flags); 1056 } else 1057 hme_read(sc, ri, flags); 1058 1059 /* This buffer can be used by the hardware again */ 1060 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 1061 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 1062 1063 if (++ri == nrbuf) 1064 ri = 0; 1065 } 1066 1067 sc->sc_rb.rb_rdtail = ri; 1068 1069 /* Read error counters ... */ 1070 ifp->if_ierrors += 1071 bus_space_read_4(t, mac, HME_MACI_STAT_LCNT) + 1072 bus_space_read_4(t, mac, HME_MACI_STAT_ACNT) + 1073 bus_space_read_4(t, mac, HME_MACI_STAT_CCNT) + 1074 bus_space_read_4(t, mac, HME_MACI_STAT_CVCNT); 1075 1076 /* ... then clear the hardware counters. */ 1077 bus_space_write_4(t, mac, HME_MACI_STAT_LCNT, 0); 1078 bus_space_write_4(t, mac, HME_MACI_STAT_ACNT, 0); 1079 bus_space_write_4(t, mac, HME_MACI_STAT_CCNT, 0); 1080 bus_space_write_4(t, mac, HME_MACI_STAT_CVCNT, 0); 1081 return (1); 1082 } 1083 1084 int 1085 hme_eint(struct hme_softc *sc, u_int status) 1086 { 1087 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1088 char bits[128]; 1089 1090 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 1091 bus_space_tag_t t = sc->sc_bustag; 1092 bus_space_handle_t mif = sc->sc_mif; 1093 uint32_t cf, st, sm; 1094 cf = bus_space_read_4(t, mif, HME_MIFI_CFG); 1095 st = bus_space_read_4(t, mif, HME_MIFI_STAT); 1096 sm = bus_space_read_4(t, mif, HME_MIFI_SM); 1097 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n", 1098 device_xname(sc->sc_dev), cf, st, sm); 1099 return (1); 1100 } 1101 1102 /* Receive error counters rolled over */ 1103 if (status & HME_SEB_STAT_ACNTEXP) 1104 ifp->if_ierrors += 0xff; 1105 if (status & HME_SEB_STAT_CCNTEXP) 1106 ifp->if_ierrors += 0xff; 1107 if (status & HME_SEB_STAT_LCNTEXP) 1108 ifp->if_ierrors += 0xff; 1109 if (status & HME_SEB_STAT_CVCNTEXP) 1110 ifp->if_ierrors += 0xff; 1111 1112 /* RXTERR locks up the interface, so do a reset */ 1113 if (status & HME_SEB_STAT_RXTERR) 1114 hme_reset(sc); 1115 1116 snprintb(bits, sizeof(bits), HME_SEB_STAT_BITS, status); 1117 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1118 1119 return (1); 1120 } 1121 1122 int 1123 hme_intr(void *v) 1124 { 1125 struct hme_softc *sc = v; 1126 bus_space_tag_t t = sc->sc_bustag; 1127 bus_space_handle_t seb = sc->sc_seb; 1128 uint32_t status; 1129 int r = 0; 1130 1131 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 1132 1133 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 1134 r |= hme_eint(sc, status); 1135 1136 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 1137 r |= hme_tint(sc); 1138 1139 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1140 r |= hme_rint(sc); 1141 1142 rnd_add_uint32(&sc->rnd_source, status); 1143 1144 return (r); 1145 } 1146 1147 1148 void 1149 hme_watchdog(struct ifnet *ifp) 1150 { 1151 struct hme_softc *sc = ifp->if_softc; 1152 1153 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1154 ++ifp->if_oerrors; 1155 1156 hme_reset(sc); 1157 } 1158 1159 /* 1160 * Initialize the MII Management Interface 1161 */ 1162 void 1163 hme_mifinit(struct hme_softc *sc) 1164 { 1165 bus_space_tag_t t = sc->sc_bustag; 1166 bus_space_handle_t mif = sc->sc_mif; 1167 bus_space_handle_t mac = sc->sc_mac; 1168 int instance, phy; 1169 uint32_t v; 1170 1171 if (sc->sc_mii.mii_media.ifm_cur != NULL) { 1172 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1173 phy = sc->sc_phys[instance]; 1174 } else 1175 /* No media set yet, pick phy arbitrarily.. */ 1176 phy = HME_PHYAD_EXTERNAL; 1177 1178 /* Configure the MIF in frame mode, no poll, current phy select */ 1179 v = 0; 1180 if (phy == HME_PHYAD_EXTERNAL) 1181 v |= HME_MIF_CFG_PHY; 1182 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1183 1184 /* If an external transceiver is selected, enable its MII drivers */ 1185 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1186 v &= ~HME_MAC_XIF_MIIENABLE; 1187 if (phy == HME_PHYAD_EXTERNAL) 1188 v |= HME_MAC_XIF_MIIENABLE; 1189 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1190 } 1191 1192 /* 1193 * MII interface 1194 */ 1195 static int 1196 hme_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1197 { 1198 struct hme_softc *sc = device_private(self); 1199 bus_space_tag_t t = sc->sc_bustag; 1200 bus_space_handle_t mif = sc->sc_mif; 1201 bus_space_handle_t mac = sc->sc_mac; 1202 uint32_t v, xif_cfg, mifi_cfg; 1203 int n, rv; 1204 1205 /* We can at most have two PHYs */ 1206 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1207 return -1; 1208 1209 /* Select the desired PHY in the MIF configuration register */ 1210 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1211 v &= ~HME_MIF_CFG_PHY; 1212 if (phy == HME_PHYAD_EXTERNAL) 1213 v |= HME_MIF_CFG_PHY; 1214 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1215 1216 /* Enable MII drivers on external transceiver */ 1217 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1218 if (phy == HME_PHYAD_EXTERNAL) 1219 v |= HME_MAC_XIF_MIIENABLE; 1220 else 1221 v &= ~HME_MAC_XIF_MIIENABLE; 1222 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1223 1224 #if 0 1225 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1226 /* 1227 * Check whether a transceiver is connected by testing 1228 * the MIF configuration register's MDI_X bits. Note that 1229 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1230 */ 1231 mif_mdi_bit = 1 << (8 + (1 - phy)); 1232 delay(100); 1233 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1234 if ((v & mif_mdi_bit) == 0) { 1235 rv = -1; 1236 goto out; 1237 } 1238 #endif 1239 1240 /* Construct the frame command */ 1241 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1242 HME_MIF_FO_TAMSB | 1243 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1244 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1245 (reg << HME_MIF_FO_REGAD_SHIFT); 1246 1247 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1248 for (n = 0; n < 100; n++) { 1249 DELAY(1); 1250 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1251 if (v & HME_MIF_FO_TALSB) { 1252 *val = v & HME_MIF_FO_DATA; 1253 rv = 0; 1254 goto out; 1255 } 1256 } 1257 1258 rv = ETIMEDOUT; 1259 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1260 1261 out: 1262 /* Restore MIFI_CFG register */ 1263 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1264 /* Restore XIF register */ 1265 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1266 return rv; 1267 } 1268 1269 static int 1270 hme_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1271 { 1272 struct hme_softc *sc = device_private(self); 1273 bus_space_tag_t t = sc->sc_bustag; 1274 bus_space_handle_t mif = sc->sc_mif; 1275 bus_space_handle_t mac = sc->sc_mac; 1276 uint32_t v, xif_cfg, mifi_cfg; 1277 int n, rv; 1278 1279 /* We can at most have two PHYs */ 1280 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1281 return -1; 1282 1283 /* Select the desired PHY in the MIF configuration register */ 1284 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1285 v &= ~HME_MIF_CFG_PHY; 1286 if (phy == HME_PHYAD_EXTERNAL) 1287 v |= HME_MIF_CFG_PHY; 1288 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1289 1290 /* Enable MII drivers on external transceiver */ 1291 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1292 if (phy == HME_PHYAD_EXTERNAL) 1293 v |= HME_MAC_XIF_MIIENABLE; 1294 else 1295 v &= ~HME_MAC_XIF_MIIENABLE; 1296 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1297 1298 #if 0 1299 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1300 /* 1301 * Check whether a transceiver is connected by testing 1302 * the MIF configuration register's MDI_X bits. Note that 1303 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1304 */ 1305 mif_mdi_bit = 1 << (8 + (1 - phy)); 1306 delay(100); 1307 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1308 if ((v & mif_mdi_bit) == 0) { 1309 rv = -1; 1310 goto out; 1311 } 1312 #endif 1313 1314 /* Construct the frame command */ 1315 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1316 HME_MIF_FO_TAMSB | 1317 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1318 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1319 (reg << HME_MIF_FO_REGAD_SHIFT) | 1320 (val & HME_MIF_FO_DATA); 1321 1322 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1323 for (n = 0; n < 100; n++) { 1324 DELAY(1); 1325 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1326 if (v & HME_MIF_FO_TALSB) { 1327 rv = 0; 1328 goto out; 1329 } 1330 } 1331 1332 rv = ETIMEDOUT; 1333 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1334 out: 1335 /* Restore MIFI_CFG register */ 1336 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1337 /* Restore XIF register */ 1338 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1339 1340 return rv; 1341 } 1342 1343 static void 1344 hme_mii_statchg(struct ifnet *ifp) 1345 { 1346 struct hme_softc *sc = ifp->if_softc; 1347 bus_space_tag_t t = sc->sc_bustag; 1348 bus_space_handle_t mac = sc->sc_mac; 1349 uint32_t v; 1350 1351 #ifdef HMEDEBUG 1352 if (sc->sc_debug) 1353 printf("hme_mii_statchg: status change\n"); 1354 #endif 1355 1356 /* Set the MAC Full Duplex bit appropriately */ 1357 /* Apparently the hme chip is SIMPLEX if working in full duplex mode, 1358 but not otherwise. */ 1359 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1360 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1361 v |= HME_MAC_TXCFG_FULLDPLX; 1362 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX; 1363 } else { 1364 v &= ~HME_MAC_TXCFG_FULLDPLX; 1365 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX; 1366 } 1367 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags; 1368 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1369 } 1370 1371 int 1372 hme_mediachange(struct ifnet *ifp) 1373 { 1374 struct hme_softc *sc = ifp->if_softc; 1375 bus_space_tag_t t = sc->sc_bustag; 1376 bus_space_handle_t mif = sc->sc_mif; 1377 bus_space_handle_t mac = sc->sc_mac; 1378 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1379 int phy = sc->sc_phys[instance]; 1380 int rc; 1381 uint32_t v; 1382 1383 #ifdef HMEDEBUG 1384 if (sc->sc_debug) 1385 printf("hme_mediachange: phy = %d\n", phy); 1386 #endif 1387 1388 /* Select the current PHY in the MIF configuration register */ 1389 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1390 v &= ~HME_MIF_CFG_PHY; 1391 if (phy == HME_PHYAD_EXTERNAL) 1392 v |= HME_MIF_CFG_PHY; 1393 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1394 1395 /* If an external transceiver is selected, enable its MII drivers */ 1396 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1397 v &= ~HME_MAC_XIF_MIIENABLE; 1398 if (phy == HME_PHYAD_EXTERNAL) 1399 v |= HME_MAC_XIF_MIIENABLE; 1400 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1401 1402 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 1403 return 0; 1404 return rc; 1405 } 1406 1407 /* 1408 * Process an ioctl request. 1409 */ 1410 int 1411 hme_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1412 { 1413 struct hme_softc *sc = ifp->if_softc; 1414 struct ifaddr *ifa = (struct ifaddr *)data; 1415 int s, error = 0; 1416 1417 s = splnet(); 1418 1419 switch (cmd) { 1420 1421 case SIOCINITIFADDR: 1422 switch (ifa->ifa_addr->sa_family) { 1423 #ifdef INET 1424 case AF_INET: 1425 if (ifp->if_flags & IFF_UP) 1426 hme_setladrf(sc); 1427 else { 1428 ifp->if_flags |= IFF_UP; 1429 error = hme_init(ifp); 1430 } 1431 arp_ifinit(ifp, ifa); 1432 break; 1433 #endif 1434 default: 1435 ifp->if_flags |= IFF_UP; 1436 error = hme_init(ifp); 1437 break; 1438 } 1439 break; 1440 1441 case SIOCSIFFLAGS: 1442 #ifdef HMEDEBUG 1443 { 1444 struct ifreq *ifr = data; 1445 sc->sc_debug = 1446 (ifr->ifr_flags & IFF_DEBUG) != 0 ? 1 : 0; 1447 } 1448 #endif 1449 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1450 break; 1451 1452 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1453 case IFF_RUNNING: 1454 /* 1455 * If interface is marked down and it is running, then 1456 * stop it. 1457 */ 1458 hme_stop(ifp, 0); 1459 ifp->if_flags &= ~IFF_RUNNING; 1460 break; 1461 case IFF_UP: 1462 /* 1463 * If interface is marked up and it is stopped, then 1464 * start it. 1465 */ 1466 error = hme_init(ifp); 1467 break; 1468 case IFF_UP | IFF_RUNNING: 1469 /* 1470 * If setting debug or promiscuous mode, do not reset 1471 * the chip; for everything else, call hme_init() 1472 * which will trigger a reset. 1473 */ 1474 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG) 1475 if (ifp->if_flags != sc->sc_if_flags) { 1476 if ((ifp->if_flags & (~RESETIGN)) 1477 == (sc->sc_if_flags & (~RESETIGN))) 1478 hme_setladrf(sc); 1479 else 1480 error = hme_init(ifp); 1481 } 1482 #undef RESETIGN 1483 break; 1484 case 0: 1485 break; 1486 } 1487 1488 if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable) 1489 error = hme_init(ifp); 1490 1491 break; 1492 1493 default: 1494 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1495 break; 1496 1497 error = 0; 1498 1499 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1500 ; 1501 else if (ifp->if_flags & IFF_RUNNING) { 1502 /* 1503 * Multicast list has changed; set the hardware filter 1504 * accordingly. 1505 */ 1506 hme_setladrf(sc); 1507 } 1508 break; 1509 } 1510 1511 sc->sc_if_flags = ifp->if_flags; 1512 splx(s); 1513 return (error); 1514 } 1515 1516 bool 1517 hme_shutdown(device_t self, int howto) 1518 { 1519 struct hme_softc *sc; 1520 struct ifnet *ifp; 1521 1522 sc = device_private(self); 1523 ifp = &sc->sc_ethercom.ec_if; 1524 hme_stop(ifp, 1); 1525 1526 return true; 1527 } 1528 1529 /* 1530 * Set up the logical address filter. 1531 */ 1532 void 1533 hme_setladrf(struct hme_softc *sc) 1534 { 1535 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1536 struct ether_multi *enm; 1537 struct ether_multistep step; 1538 struct ethercom *ec = &sc->sc_ethercom; 1539 bus_space_tag_t t = sc->sc_bustag; 1540 bus_space_handle_t mac = sc->sc_mac; 1541 uint32_t v; 1542 uint32_t crc; 1543 uint32_t hash[4]; 1544 1545 /* Clear hash table */ 1546 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1547 1548 /* Get current RX configuration */ 1549 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1550 1551 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1552 /* Turn on promiscuous mode; turn off the hash filter */ 1553 v |= HME_MAC_RXCFG_PMISC; 1554 v &= ~HME_MAC_RXCFG_HENABLE; 1555 ifp->if_flags |= IFF_ALLMULTI; 1556 goto chipit; 1557 } 1558 1559 /* Turn off promiscuous mode; turn on the hash filter */ 1560 v &= ~HME_MAC_RXCFG_PMISC; 1561 v |= HME_MAC_RXCFG_HENABLE; 1562 1563 /* 1564 * Set up multicast address filter by passing all multicast addresses 1565 * through a crc generator, and then using the high order 6 bits as an 1566 * index into the 64 bit logical address filter. The high order bit 1567 * selects the word, while the rest of the bits select the bit within 1568 * the word. 1569 */ 1570 1571 ETHER_LOCK(ec); 1572 ETHER_FIRST_MULTI(step, ec, enm); 1573 while (enm != NULL) { 1574 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1575 /* 1576 * We must listen to a range of multicast addresses. 1577 * For now, just accept all multicasts, rather than 1578 * trying to set only those filter bits needed to match 1579 * the range. (At this time, the only use of address 1580 * ranges is for IP multicast routing, for which the 1581 * range is big enough to require all bits set.) 1582 */ 1583 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1584 ifp->if_flags |= IFF_ALLMULTI; 1585 ETHER_UNLOCK(ec); 1586 goto chipit; 1587 } 1588 1589 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1590 1591 /* Just want the 6 most significant bits. */ 1592 crc >>= 26; 1593 1594 /* Set the corresponding bit in the filter. */ 1595 hash[crc >> 4] |= 1 << (crc & 0xf); 1596 1597 ETHER_NEXT_MULTI(step, enm); 1598 } 1599 ETHER_UNLOCK(ec); 1600 1601 ifp->if_flags &= ~IFF_ALLMULTI; 1602 1603 chipit: 1604 /* Now load the hash table into the chip */ 1605 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1606 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1607 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1608 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1609 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1610 } 1611 1612 /* 1613 * Routines for accessing the transmit and receive buffers. 1614 * The various CPU and adapter configurations supported by this 1615 * driver require three different access methods for buffers 1616 * and descriptors: 1617 * (1) contig (contiguous data; no padding), 1618 * (2) gap2 (two bytes of data followed by two bytes of padding), 1619 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1620 */ 1621 1622 #if 0 1623 /* 1624 * contig: contiguous data with no padding. 1625 * 1626 * Buffers may have any alignment. 1627 */ 1628 1629 void 1630 hme_copytobuf_contig(struct hme_softc *sc, void *from, int ri, int len) 1631 { 1632 volatile void *buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1633 1634 /* 1635 * Just call memcpy() to do the work. 1636 */ 1637 memcpy(buf, from, len); 1638 } 1639 1640 void 1641 hme_copyfrombuf_contig(struct hme_softc *sc, void *to, int boff, int len) 1642 { 1643 volatile void *buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1644 1645 /* 1646 * Just call memcpy() to do the work. 1647 */ 1648 memcpy(to, buf, len); 1649 } 1650 #endif 1651