1 /* $NetBSD: hme.c,v 1.8 2000/02/14 17:14:28 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * HME Ethernet module driver. 41 */ 42 43 #define HMEDEBUG 44 45 #include "opt_inet.h" 46 #include "opt_ns.h" 47 #include "bpfilter.h" 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/mbuf.h> 54 #include <sys/syslog.h> 55 #include <sys/socket.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/ioctl.h> 59 #include <sys/errno.h> 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_ether.h> 67 #include <net/if_media.h> 68 69 #ifdef INET 70 #include <netinet/in.h> 71 #include <netinet/if_inarp.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/in_var.h> 74 #include <netinet/ip.h> 75 #endif 76 77 #ifdef NS 78 #include <netns/ns.h> 79 #include <netns/ns_if.h> 80 #endif 81 82 #if NBPFILTER > 0 83 #include <net/bpf.h> 84 #include <net/bpfdesc.h> 85 #endif 86 87 #include <dev/mii/mii.h> 88 #include <dev/mii/miivar.h> 89 90 #include <machine/bus.h> 91 92 #include <dev/ic/hmereg.h> 93 #include <dev/ic/hmevar.h> 94 95 void hme_start __P((struct ifnet *)); 96 void hme_stop __P((struct hme_softc *)); 97 int hme_ioctl __P((struct ifnet *, u_long, caddr_t)); 98 void hme_tick __P((void *)); 99 void hme_watchdog __P((struct ifnet *)); 100 void hme_shutdown __P((void *)); 101 void hme_init __P((struct hme_softc *)); 102 void hme_meminit __P((struct hme_softc *)); 103 void hme_mifinit __P((struct hme_softc *)); 104 void hme_reset __P((struct hme_softc *)); 105 void hme_setladrf __P((struct hme_softc *)); 106 107 /* MII methods & callbacks */ 108 static int hme_mii_readreg __P((struct device *, int, int)); 109 static void hme_mii_writereg __P((struct device *, int, int, int)); 110 static void hme_mii_statchg __P((struct device *)); 111 112 int hme_mediachange __P((struct ifnet *)); 113 void hme_mediastatus __P((struct ifnet *, struct ifmediareq *)); 114 115 struct mbuf *hme_get __P((struct hme_softc *, int, int)); 116 int hme_put __P((struct hme_softc *, int, struct mbuf *)); 117 void hme_read __P((struct hme_softc *, int, int)); 118 int hme_eint __P((struct hme_softc *, u_int)); 119 int hme_rint __P((struct hme_softc *)); 120 int hme_tint __P((struct hme_softc *)); 121 122 static int ether_cmp __P((u_char *, u_char *)); 123 124 /* Default buffer copy routines */ 125 void hme_copytobuf_contig __P((struct hme_softc *, void *, int, int)); 126 void hme_copyfrombuf_contig __P((struct hme_softc *, void *, int, int)); 127 void hme_zerobuf_contig __P((struct hme_softc *, int, int)); 128 129 130 void 131 hme_config(sc) 132 struct hme_softc *sc; 133 { 134 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 135 struct mii_data *mii = &sc->sc_mii; 136 struct mii_softc *child; 137 bus_dma_segment_t seg; 138 bus_size_t size; 139 int rseg, error; 140 141 /* 142 * HME common initialization. 143 * 144 * hme_softc fields that must be initialized by the front-end: 145 * 146 * the bus tag: 147 * sc_bustag 148 * 149 * the dma bus tag: 150 * sc_dmatag 151 * 152 * the bus handles: 153 * sc_seb (Shared Ethernet Block registers) 154 * sc_erx (Receiver Unit registers) 155 * sc_etx (Transmitter Unit registers) 156 * sc_mac (MAC registers) 157 * sc_mif (Managment Interface registers) 158 * 159 * the maximum bus burst size: 160 * sc_burst 161 * 162 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 163 * rb_membase, rb_dmabase) 164 * 165 * the local Ethernet address: 166 * sc_enaddr 167 * 168 */ 169 170 /* Make sure the chip is stopped. */ 171 hme_stop(sc); 172 173 174 /* 175 * Allocate descriptors and buffers 176 * XXX - do all this differently.. and more configurably, 177 * eg. use things as `dma_load_mbuf()' on transmit, 178 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 179 * all the time) on the reveiver side. 180 * 181 * Note: receive buffers must be 64-byte aligned. 182 * Also, apparently, the buffers must extend to a DMA burst 183 * boundary beyond the maximum packet size. 184 */ 185 #define _HME_NDESC 32 186 #define _HME_BUFSZ 1600 187 188 /* Note: the # of descriptors must be a multiple of 16 */ 189 sc->sc_rb.rb_ntbuf = _HME_NDESC; 190 sc->sc_rb.rb_nrbuf = _HME_NDESC; 191 192 /* 193 * Allocate DMA capable memory 194 * Buffer descriptors must be aligned on a 2048 byte boundary; 195 * take this into account when calculating the size. Note that 196 * the maximum number of descriptors (256) occupies 2048 bytes, 197 * so we allocate that much regardless of _HME_NDESC. 198 */ 199 size = 2048 + /* TX descriptors */ 200 2048 + /* RX descriptors */ 201 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 202 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* TX buffers */ 203 if ((error = bus_dmamem_alloc(sc->sc_dmatag, size, 204 2048, 0, 205 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 206 printf("%s: DMA buffer alloc error %d\n", 207 sc->sc_dev.dv_xname, error); 208 } 209 sc->sc_rb.rb_dmabase = seg.ds_addr; 210 211 /* Map DMA memory in CPU adressable space */ 212 if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, size, 213 &sc->sc_rb.rb_membase, 214 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 215 printf("%s: DMA buffer map error %d\n", 216 sc->sc_dev.dv_xname, error); 217 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 218 return; 219 } 220 221 #if 0 222 /* 223 * Install default copy routines if not supplied. 224 */ 225 if (sc->sc_copytobuf == NULL) 226 sc->sc_copytobuf = hme_copytobuf_contig; 227 228 if (sc->sc_copyfrombuf == NULL) 229 sc->sc_copyfrombuf = hme_copyfrombuf_contig; 230 #endif 231 232 printf(": address %s\n", ether_sprintf(sc->sc_enaddr)); 233 234 /* Initialize ifnet structure. */ 235 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 236 ifp->if_softc = sc; 237 ifp->if_start = hme_start; 238 ifp->if_ioctl = hme_ioctl; 239 ifp->if_watchdog = hme_watchdog; 240 ifp->if_flags = 241 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 242 243 /* Initialize ifmedia structures and MII info */ 244 mii->mii_ifp = ifp; 245 mii->mii_readreg = hme_mii_readreg; 246 mii->mii_writereg = hme_mii_writereg; 247 mii->mii_statchg = hme_mii_statchg; 248 249 ifmedia_init(&mii->mii_media, 0, hme_mediachange, hme_mediastatus); 250 251 hme_mifinit(sc); 252 253 mii_attach(&sc->sc_dev, mii, 0xffffffff, 254 MII_PHY_ANY, MII_OFFSET_ANY, 0); 255 256 child = LIST_FIRST(&mii->mii_phys); 257 if (child == NULL) { 258 /* No PHY attached */ 259 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 260 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 261 } else { 262 /* 263 * Walk along the list of attached MII devices and 264 * establish an `MII instance' to `phy number' 265 * mapping. We'll use this mapping in media change 266 * requests to determine which phy to use to program 267 * the MIF configuration register. 268 */ 269 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 270 /* 271 * Note: we support just two PHYs: the built-in 272 * internal device and an external on the MII 273 * connector. 274 */ 275 if (child->mii_phy > 1 || child->mii_inst > 1) { 276 printf("%s: cannot accomodate MII device %s" 277 " at phy %d, instance %d\n", 278 sc->sc_dev.dv_xname, 279 child->mii_dev.dv_xname, 280 child->mii_phy, child->mii_inst); 281 continue; 282 } 283 284 sc->sc_phys[child->mii_inst] = child->mii_phy; 285 } 286 287 /* 288 * XXX - we can really do the following ONLY if the 289 * phy indeed has the auto negotiation capability!! 290 */ 291 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 292 } 293 294 /* Attach the interface. */ 295 if_attach(ifp); 296 ether_ifattach(ifp, sc->sc_enaddr); 297 298 #if NBPFILTER > 0 299 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 300 #endif 301 302 sc->sc_sh = shutdownhook_establish(hme_shutdown, sc); 303 if (sc->sc_sh == NULL) 304 panic("hme_config: can't establish shutdownhook"); 305 306 #if 0 307 printf("%s: %d receive buffers, %d transmit buffers\n", 308 sc->sc_dev.dv_xname, sc->sc_nrbuf, sc->sc_ntbuf); 309 sc->sc_rbufaddr = malloc(sc->sc_nrbuf * sizeof(int), M_DEVBUF, 310 M_WAITOK); 311 sc->sc_tbufaddr = malloc(sc->sc_ntbuf * sizeof(int), M_DEVBUF, 312 M_WAITOK); 313 #endif 314 315 #if NRND > 0 316 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 317 RND_TYPE_NET, 0); 318 #endif 319 320 /* Start the one second clock */ 321 timeout(hme_tick, sc, hz); 322 } 323 324 void 325 hme_tick(arg) 326 void *arg; 327 { 328 struct hme_softc *sc = arg; 329 int s; 330 331 s = splnet(); 332 mii_tick(&sc->sc_mii); 333 splx(s); 334 335 timeout(hme_tick, sc, hz); 336 } 337 338 void 339 hme_reset(sc) 340 struct hme_softc *sc; 341 { 342 int s; 343 344 s = splnet(); 345 hme_init(sc); 346 splx(s); 347 } 348 349 void 350 hme_stop(sc) 351 struct hme_softc *sc; 352 { 353 bus_space_tag_t t = sc->sc_bustag; 354 bus_space_handle_t seb = sc->sc_seb; 355 int n; 356 357 untimeout(hme_tick, sc); 358 mii_down(&sc->sc_mii); 359 360 /* Reset transmitter and receiver */ 361 bus_space_write_4(t, seb, HME_SEBI_RESET, 362 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 363 364 for (n = 0; n < 20; n++) { 365 u_int32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 366 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 367 return; 368 DELAY(20); 369 } 370 371 printf("%s: hme_stop: reset failed\n", sc->sc_dev.dv_xname); 372 } 373 374 void 375 hme_meminit(sc) 376 struct hme_softc *sc; 377 { 378 bus_addr_t txbufdma, rxbufdma; 379 bus_addr_t dma; 380 caddr_t p; 381 unsigned int ntbuf, nrbuf, i; 382 struct hme_ring *hr = &sc->sc_rb; 383 384 p = hr->rb_membase; 385 dma = hr->rb_dmabase; 386 387 ntbuf = hr->rb_ntbuf; 388 nrbuf = hr->rb_nrbuf; 389 390 /* 391 * Allocate transmit descriptors 392 */ 393 hr->rb_txd = p; 394 hr->rb_txddma = dma; 395 p += ntbuf * HME_XD_SIZE; 396 dma += ntbuf * HME_XD_SIZE; 397 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 398 dma = (bus_addr_t)roundup((u_long)dma, 2048); 399 p = (caddr_t)roundup((u_long)p, 2048); 400 401 /* 402 * Allocate receive descriptors 403 */ 404 hr->rb_rxd = p; 405 hr->rb_rxddma = dma; 406 p += nrbuf * HME_XD_SIZE; 407 dma += nrbuf * HME_XD_SIZE; 408 /* Again move forward to the next 2048 byte boundary.*/ 409 dma = (bus_addr_t)roundup((u_long)dma, 2048); 410 p = (caddr_t)roundup((u_long)p, 2048); 411 412 413 /* 414 * Allocate transmit buffers 415 */ 416 hr->rb_txbuf = p; 417 txbufdma = dma; 418 p += ntbuf * _HME_BUFSZ; 419 dma += ntbuf * _HME_BUFSZ; 420 421 /* 422 * Allocate receive buffers 423 */ 424 hr->rb_rxbuf = p; 425 rxbufdma = dma; 426 p += nrbuf * _HME_BUFSZ; 427 dma += nrbuf * _HME_BUFSZ; 428 429 /* 430 * Initialize transmit buffer descriptors 431 */ 432 for (i = 0; i < ntbuf; i++) { 433 HME_XD_SETADDR(hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 434 HME_XD_SETFLAGS(hr->rb_txd, i, 0); 435 } 436 437 /* 438 * Initialize receive buffer descriptors 439 */ 440 for (i = 0; i < nrbuf; i++) { 441 HME_XD_SETADDR(hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 442 HME_XD_SETFLAGS(hr->rb_rxd, i, 443 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 444 } 445 446 hr->rb_tdhead = hr->rb_tdtail = 0; 447 hr->rb_td_nbusy = 0; 448 hr->rb_rdtail = 0; 449 } 450 451 /* 452 * Initialization of interface; set up initialization block 453 * and transmit/receive descriptor rings. 454 */ 455 void 456 hme_init(sc) 457 struct hme_softc *sc; 458 { 459 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 460 bus_space_tag_t t = sc->sc_bustag; 461 bus_space_handle_t seb = sc->sc_seb; 462 bus_space_handle_t etx = sc->sc_etx; 463 bus_space_handle_t erx = sc->sc_erx; 464 bus_space_handle_t mac = sc->sc_mac; 465 bus_space_handle_t mif = sc->sc_mif; 466 u_int8_t *ea; 467 u_int32_t v; 468 469 /* 470 * Initialization sequence. The numbered steps below correspond 471 * to the sequence outlined in section 6.3.5.1 in the Ethernet 472 * Channel Engine manual (part of the PCIO manual). 473 * See also the STP2002-STQ document from Sun Microsystems. 474 */ 475 476 /* step 1 & 2. Reset the Ethernet Channel */ 477 hme_stop(sc); 478 479 /* Re-initialize the MIF */ 480 hme_mifinit(sc); 481 482 /* Call MI reset function if any */ 483 if (sc->sc_hwreset) 484 (*sc->sc_hwreset)(sc); 485 486 #if 0 487 /* Mask all MIF interrupts, just in case */ 488 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 489 #endif 490 491 /* step 3. Setup data structures in host memory */ 492 hme_meminit(sc); 493 494 /* step 4. TX MAC registers & counters */ 495 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 496 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 497 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 498 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 499 500 /* Load station MAC address */ 501 ea = sc->sc_enaddr; 502 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 503 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 504 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 505 506 /* 507 * Init seed for backoff 508 * (source suggested by manual: low 10 bits of MAC address) 509 */ 510 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 511 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 512 513 514 /* Note: Accepting power-on default for other MAC registers here.. */ 515 516 517 /* step 5. RX MAC registers & counters */ 518 hme_setladrf(sc); 519 520 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 521 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 522 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 523 524 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 525 526 527 /* step 8. Global Configuration & Interrupt Mask */ 528 bus_space_write_4(t, seb, HME_SEBI_IMASK, 529 ~( 530 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 531 HME_SEB_STAT_HOSTTOTX | 532 HME_SEB_STAT_RXTOHOST | 533 HME_SEB_STAT_TXALL | 534 HME_SEB_STAT_TXPERR | 535 HME_SEB_STAT_RCNTEXP | 536 HME_SEB_STAT_ALL_ERRORS )); 537 538 switch (sc->sc_burst) { 539 default: 540 v = 0; 541 break; 542 case 16: 543 v = HME_SEB_CFG_BURST16; 544 break; 545 case 32: 546 v = HME_SEB_CFG_BURST32; 547 break; 548 case 64: 549 v = HME_SEB_CFG_BURST64; 550 break; 551 } 552 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 553 554 /* step 9. ETX Configuration: use mostly default values */ 555 556 /* Enable DMA */ 557 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 558 v |= HME_ETX_CFG_DMAENABLE; 559 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 560 561 /* Transmit Descriptor ring size: in increments of 16 */ 562 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 563 564 565 /* step 10. ERX Configuration */ 566 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 567 568 /* Encode Receive Descriptor ring size: four possible values */ 569 switch (_HME_NDESC /*XXX*/) { 570 case 32: 571 v |= HME_ERX_CFG_RINGSIZE32; 572 break; 573 case 64: 574 v |= HME_ERX_CFG_RINGSIZE64; 575 break; 576 case 128: 577 v |= HME_ERX_CFG_RINGSIZE128; 578 break; 579 case 256: 580 v |= HME_ERX_CFG_RINGSIZE256; 581 break; 582 default: 583 printf("hme: invalid Receive Descriptor ring size\n"); 584 break; 585 } 586 587 /* Enable DMA */ 588 v |= HME_ERX_CFG_DMAENABLE; 589 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 590 591 /* step 11. XIF Configuration */ 592 v = bus_space_read_4(t, mac, HME_MACI_XIF); 593 v |= HME_MAC_XIF_OE; 594 /* If an external transceiver is connected, enable its MII drivers */ 595 if ((bus_space_read_4(t, mif, HME_MIFI_CFG) & HME_MIF_CFG_MDI1) != 0) 596 v |= HME_MAC_XIF_MIIENABLE; 597 bus_space_write_4(t, mac, HME_MACI_XIF, v); 598 599 600 /* step 12. RX_MAC Configuration Register */ 601 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 602 v |= HME_MAC_RXCFG_ENABLE; 603 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 604 605 /* step 13. TX_MAC Configuration Register */ 606 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 607 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 608 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 609 610 /* step 14. Issue Transmit Pending command */ 611 612 /* Call MI initialization function if any */ 613 if (sc->sc_hwinit) 614 (*sc->sc_hwinit)(sc); 615 616 ifp->if_flags |= IFF_RUNNING; 617 ifp->if_flags &= ~IFF_OACTIVE; 618 ifp->if_timer = 0; 619 hme_start(ifp); 620 } 621 622 /* 623 * Compare two Ether/802 addresses for equality, inlined and unrolled for 624 * speed. 625 */ 626 static __inline__ int 627 ether_cmp(a, b) 628 u_char *a, *b; 629 { 630 631 if (a[5] != b[5] || a[4] != b[4] || a[3] != b[3] || 632 a[2] != b[2] || a[1] != b[1] || a[0] != b[0]) 633 return (0); 634 return (1); 635 } 636 637 638 /* 639 * Routine to copy from mbuf chain to transmit buffer in 640 * network buffer memory. 641 * Returns the amount of data copied. 642 */ 643 int 644 hme_put(sc, ri, m) 645 struct hme_softc *sc; 646 int ri; /* Ring index */ 647 struct mbuf *m; 648 { 649 struct mbuf *n; 650 int len, tlen = 0; 651 caddr_t bp; 652 653 bp = sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 654 for (; m; m = n) { 655 len = m->m_len; 656 if (len == 0) { 657 MFREE(m, n); 658 continue; 659 } 660 bcopy(mtod(m, caddr_t), bp, len); 661 bp += len; 662 tlen += len; 663 MFREE(m, n); 664 } 665 return (tlen); 666 } 667 668 /* 669 * Pull data off an interface. 670 * Len is length of data, with local net header stripped. 671 * We copy the data into mbufs. When full cluster sized units are present 672 * we copy into clusters. 673 */ 674 struct mbuf * 675 hme_get(sc, ri, totlen) 676 struct hme_softc *sc; 677 int ri, totlen; 678 { 679 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 680 struct mbuf *m, *m0, *newm; 681 caddr_t bp; 682 int len; 683 684 MGETHDR(m0, M_DONTWAIT, MT_DATA); 685 if (m0 == 0) 686 return (0); 687 m0->m_pkthdr.rcvif = ifp; 688 m0->m_pkthdr.len = totlen; 689 len = MHLEN; 690 m = m0; 691 692 bp = sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 693 694 while (totlen > 0) { 695 if (totlen >= MINCLSIZE) { 696 MCLGET(m, M_DONTWAIT); 697 if ((m->m_flags & M_EXT) == 0) 698 goto bad; 699 len = MCLBYTES; 700 } 701 702 if (m == m0) { 703 caddr_t newdata = (caddr_t) 704 ALIGN(m->m_data + sizeof(struct ether_header)) - 705 sizeof(struct ether_header); 706 len -= newdata - m->m_data; 707 m->m_data = newdata; 708 } 709 710 m->m_len = len = min(totlen, len); 711 bcopy(bp, mtod(m, caddr_t), len); 712 bp += len; 713 714 totlen -= len; 715 if (totlen > 0) { 716 MGET(newm, M_DONTWAIT, MT_DATA); 717 if (newm == 0) 718 goto bad; 719 len = MLEN; 720 m = m->m_next = newm; 721 } 722 } 723 724 return (m0); 725 726 bad: 727 m_freem(m0); 728 return (0); 729 } 730 731 /* 732 * Pass a packet to the higher levels. 733 */ 734 void 735 hme_read(sc, ix, len) 736 struct hme_softc *sc; 737 int ix, len; 738 { 739 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 740 struct mbuf *m; 741 742 if (len <= sizeof(struct ether_header) || 743 len > ETHERMTU + sizeof(struct ether_header)) { 744 #ifdef HMEDEBUG 745 printf("%s: invalid packet size %d; dropping\n", 746 sc->sc_dev.dv_xname, len); 747 #endif 748 ifp->if_ierrors++; 749 return; 750 } 751 752 /* Pull packet off interface. */ 753 m = hme_get(sc, ix, len); 754 if (m == 0) { 755 ifp->if_ierrors++; 756 return; 757 } 758 759 ifp->if_ipackets++; 760 761 #if NBPFILTER > 0 762 /* 763 * Check if there's a BPF listener on this interface. 764 * If so, hand off the raw packet to BPF. 765 */ 766 if (ifp->if_bpf) { 767 struct ether_header *eh; 768 769 bpf_mtap(ifp->if_bpf, m); 770 771 /* 772 * Note that the interface cannot be in promiscuous mode if 773 * there are no BPF listeners. And if we are in promiscuous 774 * mode, we have to check if this packet is really ours. 775 */ 776 777 /* We assume that the header fit entirely in one mbuf. */ 778 eh = mtod(m, struct ether_header *); 779 780 if ((ifp->if_flags & IFF_PROMISC) != 0 && 781 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 782 ether_cmp(eh->ether_dhost, sc->sc_enaddr) == 0) { 783 m_freem(m); 784 return; 785 } 786 } 787 #endif 788 789 /* Pass the packet up. */ 790 (*ifp->if_input)(ifp, m); 791 } 792 793 void 794 hme_start(ifp) 795 struct ifnet *ifp; 796 { 797 struct hme_softc *sc = (struct hme_softc *)ifp->if_softc; 798 caddr_t txd = sc->sc_rb.rb_txd; 799 struct mbuf *m; 800 unsigned int ri, len; 801 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 802 803 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 804 return; 805 806 ri = sc->sc_rb.rb_tdhead; 807 808 for (;;) { 809 IF_DEQUEUE(&ifp->if_snd, m); 810 if (m == 0) 811 break; 812 813 #if NBPFILTER > 0 814 /* 815 * If BPF is listening on this interface, let it see the 816 * packet before we commit it to the wire. 817 */ 818 if (ifp->if_bpf) 819 bpf_mtap(ifp->if_bpf, m); 820 #endif 821 822 /* 823 * Copy the mbuf chain into the transmit buffer. 824 */ 825 len = hme_put(sc, ri, m); 826 827 /* 828 * Initialize transmit registers and start transmission 829 */ 830 HME_XD_SETFLAGS(txd, ri, 831 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 832 HME_XD_ENCODE_TSIZE(len)); 833 834 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 835 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 836 HME_ETX_TP_DMAWAKEUP); 837 838 if (++ri == ntbuf) 839 ri = 0; 840 841 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 842 ifp->if_flags |= IFF_OACTIVE; 843 break; 844 } 845 } 846 847 sc->sc_rb.rb_tdhead = ri; 848 } 849 850 /* 851 * Transmit interrupt. 852 */ 853 int 854 hme_tint(sc) 855 struct hme_softc *sc; 856 { 857 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 858 bus_space_tag_t t = sc->sc_bustag; 859 bus_space_handle_t mac = sc->sc_mac; 860 unsigned int ri, txflags; 861 862 /* 863 * Unload collision counters 864 */ 865 ifp->if_collisions += 866 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 867 bus_space_read_4(t, mac, HME_MACI_FCCNT) + 868 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 869 bus_space_read_4(t, mac, HME_MACI_LTCNT); 870 871 /* 872 * then clear the hardware counters. 873 */ 874 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 875 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 876 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 877 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 878 879 /* Fetch current position in the transmit ring */ 880 ri = sc->sc_rb.rb_tdtail; 881 882 for (;;) { 883 if (sc->sc_rb.rb_td_nbusy <= 0) 884 break; 885 886 txflags = HME_XD_GETFLAGS(sc->sc_rb.rb_txd, ri); 887 888 if (txflags & HME_XD_OWN) 889 break; 890 891 ifp->if_flags &= ~IFF_OACTIVE; 892 ifp->if_opackets++; 893 894 if (++ri == sc->sc_rb.rb_ntbuf) 895 ri = 0; 896 897 --sc->sc_rb.rb_td_nbusy; 898 } 899 900 /* Update ring */ 901 sc->sc_rb.rb_tdtail = ri; 902 903 hme_start(ifp); 904 905 if (sc->sc_rb.rb_td_nbusy == 0) 906 ifp->if_timer = 0; 907 908 return (1); 909 } 910 911 /* 912 * Receive interrupt. 913 */ 914 int 915 hme_rint(sc) 916 struct hme_softc *sc; 917 { 918 caddr_t xdr = sc->sc_rb.rb_rxd; 919 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 920 unsigned int ri, len; 921 u_int32_t flags; 922 923 ri = sc->sc_rb.rb_rdtail; 924 925 /* 926 * Process all buffers with valid data. 927 */ 928 for (;;) { 929 flags = HME_XD_GETFLAGS(xdr, ri); 930 if (flags & HME_XD_OWN) 931 break; 932 933 if (flags & HME_XD_OFL) { 934 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 935 sc->sc_dev.dv_xname, ri, flags); 936 } else { 937 len = HME_XD_DECODE_RSIZE(flags); 938 hme_read(sc, ri, len); 939 } 940 941 /* This buffer can be used by the hardware again */ 942 HME_XD_SETFLAGS(xdr, ri, 943 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 944 945 if (++ri == nrbuf) 946 ri = 0; 947 } 948 949 sc->sc_rb.rb_rdtail = ri; 950 951 return (1); 952 } 953 954 int 955 hme_eint(sc, status) 956 struct hme_softc *sc; 957 u_int status; 958 { 959 char bits[128]; 960 961 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 962 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 963 return (1); 964 } 965 966 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 967 bitmask_snprintf(status, HME_SEB_STAT_BITS, bits,sizeof(bits))); 968 return (1); 969 } 970 971 int 972 hme_intr(v) 973 void *v; 974 { 975 struct hme_softc *sc = (struct hme_softc *)v; 976 bus_space_tag_t t = sc->sc_bustag; 977 bus_space_handle_t seb = sc->sc_seb; 978 u_int32_t status; 979 int r = 0; 980 981 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 982 983 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 984 r |= hme_eint(sc, status); 985 986 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 987 r |= hme_tint(sc); 988 989 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 990 r |= hme_rint(sc); 991 992 return (r); 993 } 994 995 996 void 997 hme_watchdog(ifp) 998 struct ifnet *ifp; 999 { 1000 struct hme_softc *sc = ifp->if_softc; 1001 1002 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1003 ++ifp->if_oerrors; 1004 1005 hme_reset(sc); 1006 } 1007 1008 /* 1009 * Initialize the MII Management Interface 1010 */ 1011 void 1012 hme_mifinit(sc) 1013 struct hme_softc *sc; 1014 { 1015 bus_space_tag_t t = sc->sc_bustag; 1016 bus_space_handle_t mif = sc->sc_mif; 1017 u_int32_t v; 1018 1019 /* Configure the MIF in frame mode */ 1020 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1021 v &= ~HME_MIF_CFG_BBMODE; 1022 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1023 } 1024 1025 /* 1026 * MII interface 1027 */ 1028 static int 1029 hme_mii_readreg(self, phy, reg) 1030 struct device *self; 1031 int phy, reg; 1032 { 1033 struct hme_softc *sc = (void *)self; 1034 bus_space_tag_t t = sc->sc_bustag; 1035 bus_space_handle_t mif = sc->sc_mif; 1036 int n; 1037 u_int32_t v; 1038 1039 /* Select the desired PHY in the MIF configuration register */ 1040 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1041 /* Clear PHY select bit */ 1042 v &= ~HME_MIF_CFG_PHY; 1043 if (phy == HME_PHYAD_EXTERNAL) 1044 /* Set PHY select bit to get at external device */ 1045 v |= HME_MIF_CFG_PHY; 1046 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1047 1048 /* Construct the frame command */ 1049 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1050 HME_MIF_FO_TAMSB | 1051 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1052 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1053 (reg << HME_MIF_FO_REGAD_SHIFT); 1054 1055 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1056 for (n = 0; n < 100; n++) { 1057 DELAY(1); 1058 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1059 if (v & HME_MIF_FO_TALSB) 1060 return (v & HME_MIF_FO_DATA); 1061 } 1062 1063 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1064 return (0); 1065 } 1066 1067 static void 1068 hme_mii_writereg(self, phy, reg, val) 1069 struct device *self; 1070 int phy, reg, val; 1071 { 1072 struct hme_softc *sc = (void *)self; 1073 bus_space_tag_t t = sc->sc_bustag; 1074 bus_space_handle_t mif = sc->sc_mif; 1075 int n; 1076 u_int32_t v; 1077 1078 /* Select the desired PHY in the MIF configuration register */ 1079 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1080 /* Clear PHY select bit */ 1081 v &= ~HME_MIF_CFG_PHY; 1082 if (phy == HME_PHYAD_EXTERNAL) 1083 /* Set PHY select bit to get at external device */ 1084 v |= HME_MIF_CFG_PHY; 1085 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1086 1087 /* Construct the frame command */ 1088 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1089 HME_MIF_FO_TAMSB | 1090 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1091 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1092 (reg << HME_MIF_FO_REGAD_SHIFT) | 1093 (val & HME_MIF_FO_DATA); 1094 1095 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1096 for (n = 0; n < 100; n++) { 1097 DELAY(1); 1098 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1099 if (v & HME_MIF_FO_TALSB) 1100 return; 1101 } 1102 1103 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1104 } 1105 1106 static void 1107 hme_mii_statchg(dev) 1108 struct device *dev; 1109 { 1110 struct hme_softc *sc = (void *)dev; 1111 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1112 int phy = sc->sc_phys[instance]; 1113 bus_space_tag_t t = sc->sc_bustag; 1114 bus_space_handle_t mif = sc->sc_mif; 1115 bus_space_handle_t mac = sc->sc_mac; 1116 u_int32_t v; 1117 1118 #ifdef HMEDEBUG 1119 if (sc->sc_debug) 1120 printf("hme_mii_statchg: status change: phy = %d\n", phy); 1121 #endif 1122 1123 /* Select the current PHY in the MIF configuration register */ 1124 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1125 v &= ~HME_MIF_CFG_PHY; 1126 if (phy == HME_PHYAD_EXTERNAL) 1127 v |= HME_MIF_CFG_PHY; 1128 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1129 1130 /* Set the MAC Full Duplex bit appropriately */ 1131 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1132 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1133 v |= HME_MAC_TXCFG_FULLDPLX; 1134 else 1135 v &= ~HME_MAC_TXCFG_FULLDPLX; 1136 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1137 1138 /* If an external transceiver is selected, enable its MII drivers */ 1139 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1140 v &= ~HME_MAC_XIF_MIIENABLE; 1141 if (phy == HME_PHYAD_EXTERNAL) 1142 v |= HME_MAC_XIF_MIIENABLE; 1143 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1144 } 1145 1146 int 1147 hme_mediachange(ifp) 1148 struct ifnet *ifp; 1149 { 1150 struct hme_softc *sc = ifp->if_softc; 1151 1152 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1153 return (EINVAL); 1154 1155 return (mii_mediachg(&sc->sc_mii)); 1156 } 1157 1158 void 1159 hme_mediastatus(ifp, ifmr) 1160 struct ifnet *ifp; 1161 struct ifmediareq *ifmr; 1162 { 1163 struct hme_softc *sc = ifp->if_softc; 1164 1165 if ((ifp->if_flags & IFF_UP) == 0) 1166 return; 1167 1168 mii_pollstat(&sc->sc_mii); 1169 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1170 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1171 } 1172 1173 /* 1174 * Process an ioctl request. 1175 */ 1176 int 1177 hme_ioctl(ifp, cmd, data) 1178 struct ifnet *ifp; 1179 u_long cmd; 1180 caddr_t data; 1181 { 1182 struct hme_softc *sc = ifp->if_softc; 1183 struct ifaddr *ifa = (struct ifaddr *)data; 1184 struct ifreq *ifr = (struct ifreq *)data; 1185 int s, error = 0; 1186 1187 s = splnet(); 1188 1189 switch (cmd) { 1190 1191 case SIOCSIFADDR: 1192 ifp->if_flags |= IFF_UP; 1193 1194 switch (ifa->ifa_addr->sa_family) { 1195 #ifdef INET 1196 case AF_INET: 1197 hme_init(sc); 1198 arp_ifinit(ifp, ifa); 1199 break; 1200 #endif 1201 #ifdef NS 1202 case AF_NS: 1203 { 1204 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1205 1206 if (ns_nullhost(*ina)) 1207 ina->x_host = 1208 *(union ns_host *)LLADDR(ifp->if_sadl); 1209 else { 1210 bcopy(ina->x_host.c_host, 1211 LLADDR(ifp->if_sadl), 1212 sizeof(sc->sc_enaddr)); 1213 } 1214 /* Set new address. */ 1215 hme_init(sc); 1216 break; 1217 } 1218 #endif 1219 default: 1220 hme_init(sc); 1221 break; 1222 } 1223 break; 1224 1225 case SIOCSIFFLAGS: 1226 if ((ifp->if_flags & IFF_UP) == 0 && 1227 (ifp->if_flags & IFF_RUNNING) != 0) { 1228 /* 1229 * If interface is marked down and it is running, then 1230 * stop it. 1231 */ 1232 hme_stop(sc); 1233 ifp->if_flags &= ~IFF_RUNNING; 1234 } else if ((ifp->if_flags & IFF_UP) != 0 && 1235 (ifp->if_flags & IFF_RUNNING) == 0) { 1236 /* 1237 * If interface is marked up and it is stopped, then 1238 * start it. 1239 */ 1240 hme_init(sc); 1241 } else if ((ifp->if_flags & IFF_UP) != 0) { 1242 /* 1243 * Reset the interface to pick up changes in any other 1244 * flags that affect hardware registers. 1245 */ 1246 /*hme_stop(sc);*/ 1247 hme_init(sc); 1248 } 1249 #ifdef HMEDEBUG 1250 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1251 #endif 1252 break; 1253 1254 case SIOCADDMULTI: 1255 case SIOCDELMULTI: 1256 error = (cmd == SIOCADDMULTI) ? 1257 ether_addmulti(ifr, &sc->sc_ethercom) : 1258 ether_delmulti(ifr, &sc->sc_ethercom); 1259 1260 if (error == ENETRESET) { 1261 /* 1262 * Multicast list has changed; set the hardware filter 1263 * accordingly. 1264 */ 1265 hme_setladrf(sc); 1266 error = 0; 1267 } 1268 break; 1269 1270 case SIOCGIFMEDIA: 1271 case SIOCSIFMEDIA: 1272 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1273 break; 1274 1275 default: 1276 error = EINVAL; 1277 break; 1278 } 1279 1280 splx(s); 1281 return (error); 1282 } 1283 1284 void 1285 hme_shutdown(arg) 1286 void *arg; 1287 { 1288 1289 hme_stop((struct hme_softc *)arg); 1290 } 1291 1292 /* 1293 * Set up the logical address filter. 1294 */ 1295 void 1296 hme_setladrf(sc) 1297 struct hme_softc *sc; 1298 { 1299 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1300 struct ether_multi *enm; 1301 struct ether_multistep step; 1302 struct ethercom *ec = &sc->sc_ethercom; 1303 bus_space_tag_t t = sc->sc_bustag; 1304 bus_space_handle_t mac = sc->sc_mac; 1305 u_char *cp; 1306 u_int32_t crc; 1307 u_int32_t hash[4]; 1308 int len; 1309 1310 /* 1311 * Set up multicast address filter by passing all multicast addresses 1312 * through a crc generator, and then using the high order 6 bits as an 1313 * index into the 64 bit logical address filter. The high order bit 1314 * selects the word, while the rest of the bits select the bit within 1315 * the word. 1316 */ 1317 1318 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1319 u_int32_t v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1320 v |= HME_MAC_RXCFG_PMISC; 1321 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1322 goto allmulti; 1323 } 1324 1325 /* Clear hash table */ 1326 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1327 ETHER_FIRST_MULTI(step, ec, enm); 1328 while (enm != NULL) { 1329 if (ether_cmp(enm->enm_addrlo, enm->enm_addrhi)) { 1330 /* 1331 * We must listen to a range of multicast addresses. 1332 * For now, just accept all multicasts, rather than 1333 * trying to set only those filter bits needed to match 1334 * the range. (At this time, the only use of address 1335 * ranges is for IP multicast routing, for which the 1336 * range is big enough to require all bits set.) 1337 */ 1338 goto allmulti; 1339 } 1340 1341 cp = enm->enm_addrlo; 1342 crc = 0xffffffff; 1343 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1344 int octet = *cp++; 1345 int i; 1346 1347 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1348 for (i = 0; i < 8; i++) { 1349 if ((crc & 1) ^ (octet & 1)) { 1350 crc >>= 1; 1351 crc ^= MC_POLY_LE; 1352 } else { 1353 crc >>= 1; 1354 } 1355 octet >>= 1; 1356 } 1357 } 1358 /* Just want the 6 most significant bits. */ 1359 crc >>= 26; 1360 1361 /* Set the corresponding bit in the filter. */ 1362 hash[crc >> 4] |= 1 << (crc & 0xf); 1363 1364 ETHER_NEXT_MULTI(step, enm); 1365 } 1366 1367 /* Now load the hash table onto the chip */ 1368 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1369 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1370 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1371 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1372 1373 ifp->if_flags &= ~IFF_ALLMULTI; 1374 return; 1375 1376 allmulti: 1377 ifp->if_flags |= IFF_ALLMULTI; 1378 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, 0xffff); 1379 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, 0xffff); 1380 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, 0xffff); 1381 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, 0xffff); 1382 } 1383 1384 /* 1385 * Routines for accessing the transmit and receive buffers. 1386 * The various CPU and adapter configurations supported by this 1387 * driver require three different access methods for buffers 1388 * and descriptors: 1389 * (1) contig (contiguous data; no padding), 1390 * (2) gap2 (two bytes of data followed by two bytes of padding), 1391 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1392 */ 1393 1394 #if 0 1395 /* 1396 * contig: contiguous data with no padding. 1397 * 1398 * Buffers may have any alignment. 1399 */ 1400 1401 void 1402 hme_copytobuf_contig(sc, from, ri, len) 1403 struct hme_softc *sc; 1404 void *from; 1405 int ri, len; 1406 { 1407 volatile caddr_t buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1408 1409 /* 1410 * Just call bcopy() to do the work. 1411 */ 1412 bcopy(from, buf, len); 1413 } 1414 1415 void 1416 hme_copyfrombuf_contig(sc, to, boff, len) 1417 struct hme_softc *sc; 1418 void *to; 1419 int boff, len; 1420 { 1421 volatile caddr_t buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1422 1423 /* 1424 * Just call bcopy() to do the work. 1425 */ 1426 bcopy(buf, to, len); 1427 } 1428 #endif 1429