1 /* $NetBSD: hme.c,v 1.96 2017/05/23 02:19:14 ozaki-r Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * HME Ethernet module driver. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.96 2017/05/23 02:19:14 ozaki-r Exp $"); 38 39 /* #define HMEDEBUG */ 40 41 #include "opt_inet.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/mbuf.h> 47 #include <sys/syslog.h> 48 #include <sys/socket.h> 49 #include <sys/device.h> 50 #include <sys/malloc.h> 51 #include <sys/ioctl.h> 52 #include <sys/errno.h> 53 #include <sys/rndsource.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_ether.h> 58 #include <net/if_media.h> 59 60 #ifdef INET 61 #include <net/if_vlanvar.h> 62 #include <netinet/in.h> 63 #include <netinet/if_inarp.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <netinet/ip.h> 67 #include <netinet/tcp.h> 68 #include <netinet/udp.h> 69 #endif 70 71 72 #include <net/bpf.h> 73 #include <net/bpfdesc.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 78 #include <sys/bus.h> 79 80 #include <dev/ic/hmereg.h> 81 #include <dev/ic/hmevar.h> 82 83 static void hme_start(struct ifnet *); 84 static void hme_stop(struct ifnet *, int); 85 static int hme_ioctl(struct ifnet *, u_long, void *); 86 static void hme_tick(void *); 87 static void hme_watchdog(struct ifnet *); 88 static bool hme_shutdown(device_t, int); 89 static int hme_init(struct ifnet *); 90 static void hme_meminit(struct hme_softc *); 91 static void hme_mifinit(struct hme_softc *); 92 static void hme_reset(struct hme_softc *); 93 static void hme_chipreset(struct hme_softc *); 94 static void hme_setladrf(struct hme_softc *); 95 96 /* MII methods & callbacks */ 97 static int hme_mii_readreg(device_t, int, int); 98 static void hme_mii_writereg(device_t, int, int, int); 99 static void hme_mii_statchg(struct ifnet *); 100 101 static int hme_mediachange(struct ifnet *); 102 103 static struct mbuf *hme_get(struct hme_softc *, int, uint32_t); 104 static int hme_put(struct hme_softc *, int, struct mbuf *); 105 static void hme_read(struct hme_softc *, int, uint32_t); 106 static int hme_eint(struct hme_softc *, u_int); 107 static int hme_rint(struct hme_softc *); 108 static int hme_tint(struct hme_softc *); 109 110 #if 0 111 /* Default buffer copy routines */ 112 static void hme_copytobuf_contig(struct hme_softc *, void *, int, int); 113 static void hme_copyfrombuf_contig(struct hme_softc *, void *, int, int); 114 #endif 115 116 void 117 hme_config(struct hme_softc *sc) 118 { 119 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 120 struct mii_data *mii = &sc->sc_mii; 121 struct mii_softc *child; 122 bus_dma_tag_t dmatag = sc->sc_dmatag; 123 bus_dma_segment_t seg; 124 bus_size_t size; 125 int rseg, error; 126 127 /* 128 * HME common initialization. 129 * 130 * hme_softc fields that must be initialized by the front-end: 131 * 132 * the bus tag: 133 * sc_bustag 134 * 135 * the DMA bus tag: 136 * sc_dmatag 137 * 138 * the bus handles: 139 * sc_seb (Shared Ethernet Block registers) 140 * sc_erx (Receiver Unit registers) 141 * sc_etx (Transmitter Unit registers) 142 * sc_mac (MAC registers) 143 * sc_mif (Management Interface registers) 144 * 145 * the maximum bus burst size: 146 * sc_burst 147 * 148 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 149 * rb_membase, rb_dmabase) 150 * 151 * the local Ethernet address: 152 * sc_enaddr 153 * 154 */ 155 156 /* Make sure the chip is stopped. */ 157 hme_chipreset(sc); 158 159 /* 160 * Allocate descriptors and buffers 161 * XXX - do all this differently.. and more configurably, 162 * eg. use things as `dma_load_mbuf()' on transmit, 163 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 164 * all the time) on the receiver side. 165 * 166 * Note: receive buffers must be 64-byte aligned. 167 * Also, apparently, the buffers must extend to a DMA burst 168 * boundary beyond the maximum packet size. 169 */ 170 #define _HME_NDESC 128 171 #define _HME_BUFSZ 1600 172 173 /* Note: the # of descriptors must be a multiple of 16 */ 174 sc->sc_rb.rb_ntbuf = _HME_NDESC; 175 sc->sc_rb.rb_nrbuf = _HME_NDESC; 176 177 /* 178 * Allocate DMA capable memory 179 * Buffer descriptors must be aligned on a 2048 byte boundary; 180 * take this into account when calculating the size. Note that 181 * the maximum number of descriptors (256) occupies 2048 bytes, 182 * so we allocate that much regardless of _HME_NDESC. 183 */ 184 size = 2048 + /* TX descriptors */ 185 2048 + /* RX descriptors */ 186 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 187 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* RX buffers */ 188 189 /* Allocate DMA buffer */ 190 if ((error = bus_dmamem_alloc(dmatag, size, 191 2048, 0, 192 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 193 aprint_error_dev(sc->sc_dev, "DMA buffer alloc error %d\n", 194 error); 195 return; 196 } 197 198 /* Map DMA memory in CPU addressable space */ 199 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 200 &sc->sc_rb.rb_membase, 201 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 202 aprint_error_dev(sc->sc_dev, "DMA buffer map error %d\n", 203 error); 204 bus_dmamap_unload(dmatag, sc->sc_dmamap); 205 bus_dmamem_free(dmatag, &seg, rseg); 206 return; 207 } 208 209 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 210 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 211 aprint_error_dev(sc->sc_dev, "DMA map create error %d\n", 212 error); 213 return; 214 } 215 216 /* Load the buffer */ 217 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 218 sc->sc_rb.rb_membase, size, NULL, 219 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 220 aprint_error_dev(sc->sc_dev, "DMA buffer map load error %d\n", 221 error); 222 bus_dmamem_free(dmatag, &seg, rseg); 223 return; 224 } 225 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 226 227 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 228 ether_sprintf(sc->sc_enaddr)); 229 230 /* Initialize ifnet structure. */ 231 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 232 ifp->if_softc = sc; 233 ifp->if_start = hme_start; 234 ifp->if_stop = hme_stop; 235 ifp->if_ioctl = hme_ioctl; 236 ifp->if_init = hme_init; 237 ifp->if_watchdog = hme_watchdog; 238 ifp->if_flags = 239 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 240 sc->sc_if_flags = ifp->if_flags; 241 ifp->if_capabilities |= 242 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 243 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 244 IFQ_SET_READY(&ifp->if_snd); 245 246 /* Initialize ifmedia structures and MII info */ 247 mii->mii_ifp = ifp; 248 mii->mii_readreg = hme_mii_readreg; 249 mii->mii_writereg = hme_mii_writereg; 250 mii->mii_statchg = hme_mii_statchg; 251 252 sc->sc_ethercom.ec_mii = mii; 253 ifmedia_init(&mii->mii_media, 0, hme_mediachange, ether_mediastatus); 254 255 hme_mifinit(sc); 256 257 mii_attach(sc->sc_dev, mii, 0xffffffff, 258 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 259 260 child = LIST_FIRST(&mii->mii_phys); 261 if (child == NULL) { 262 /* No PHY attached */ 263 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 264 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 265 } else { 266 /* 267 * Walk along the list of attached MII devices and 268 * establish an `MII instance' to `phy number' 269 * mapping. We'll use this mapping in media change 270 * requests to determine which phy to use to program 271 * the MIF configuration register. 272 */ 273 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 274 /* 275 * Note: we support just two PHYs: the built-in 276 * internal device and an external on the MII 277 * connector. 278 */ 279 if (child->mii_phy > 1 || child->mii_inst > 1) { 280 aprint_error_dev(sc->sc_dev, 281 "cannot accommodate MII device %s" 282 " at phy %d, instance %d\n", 283 device_xname(child->mii_dev), 284 child->mii_phy, child->mii_inst); 285 continue; 286 } 287 288 sc->sc_phys[child->mii_inst] = child->mii_phy; 289 } 290 291 /* 292 * Set the default media to auto negotiation if the phy has 293 * the auto negotiation capability. 294 * XXX; What to do otherwise? 295 */ 296 if (ifmedia_match(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0)) 297 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 298 /* 299 else 300 ifmedia_set(&sc->sc_mii.mii_media, sc->sc_defaultmedia); 301 */ 302 } 303 304 /* claim 802.1q capability */ 305 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 306 307 /* Attach the interface. */ 308 if_attach(ifp); 309 if_deferred_start_init(ifp, NULL); 310 ether_ifattach(ifp, sc->sc_enaddr); 311 312 if (pmf_device_register1(sc->sc_dev, NULL, NULL, hme_shutdown)) 313 pmf_class_network_register(sc->sc_dev, ifp); 314 else 315 aprint_error_dev(sc->sc_dev, 316 "couldn't establish power handler\n"); 317 318 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 319 RND_TYPE_NET, RND_FLAG_DEFAULT); 320 321 callout_init(&sc->sc_tick_ch, 0); 322 } 323 324 void 325 hme_tick(void *arg) 326 { 327 struct hme_softc *sc = arg; 328 int s; 329 330 s = splnet(); 331 mii_tick(&sc->sc_mii); 332 splx(s); 333 334 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 335 } 336 337 void 338 hme_reset(struct hme_softc *sc) 339 { 340 int s; 341 342 s = splnet(); 343 (void)hme_init(&sc->sc_ethercom.ec_if); 344 splx(s); 345 } 346 347 void 348 hme_chipreset(struct hme_softc *sc) 349 { 350 bus_space_tag_t t = sc->sc_bustag; 351 bus_space_handle_t seb = sc->sc_seb; 352 int n; 353 354 /* Mask all interrupts */ 355 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff); 356 357 /* Reset transmitter and receiver */ 358 bus_space_write_4(t, seb, HME_SEBI_RESET, 359 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 360 361 for (n = 0; n < 20; n++) { 362 uint32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 363 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 364 return; 365 DELAY(20); 366 } 367 368 printf("%s: %s: reset failed\n", device_xname(sc->sc_dev), __func__); 369 } 370 371 void 372 hme_stop(struct ifnet *ifp, int disable) 373 { 374 struct hme_softc *sc; 375 376 sc = ifp->if_softc; 377 378 ifp->if_timer = 0; 379 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 380 381 callout_stop(&sc->sc_tick_ch); 382 mii_down(&sc->sc_mii); 383 384 hme_chipreset(sc); 385 } 386 387 void 388 hme_meminit(struct hme_softc *sc) 389 { 390 bus_addr_t txbufdma, rxbufdma; 391 bus_addr_t dma; 392 char *p; 393 unsigned int ntbuf, nrbuf, i; 394 struct hme_ring *hr = &sc->sc_rb; 395 396 p = hr->rb_membase; 397 dma = hr->rb_dmabase; 398 399 ntbuf = hr->rb_ntbuf; 400 nrbuf = hr->rb_nrbuf; 401 402 /* 403 * Allocate transmit descriptors 404 */ 405 hr->rb_txd = p; 406 hr->rb_txddma = dma; 407 p += ntbuf * HME_XD_SIZE; 408 dma += ntbuf * HME_XD_SIZE; 409 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 410 dma = (bus_addr_t)roundup((u_long)dma, 2048); 411 p = (void *)roundup((u_long)p, 2048); 412 413 /* 414 * Allocate receive descriptors 415 */ 416 hr->rb_rxd = p; 417 hr->rb_rxddma = dma; 418 p += nrbuf * HME_XD_SIZE; 419 dma += nrbuf * HME_XD_SIZE; 420 /* Again move forward to the next 2048 byte boundary.*/ 421 dma = (bus_addr_t)roundup((u_long)dma, 2048); 422 p = (void *)roundup((u_long)p, 2048); 423 424 425 /* 426 * Allocate transmit buffers 427 */ 428 hr->rb_txbuf = p; 429 txbufdma = dma; 430 p += ntbuf * _HME_BUFSZ; 431 dma += ntbuf * _HME_BUFSZ; 432 433 /* 434 * Allocate receive buffers 435 */ 436 hr->rb_rxbuf = p; 437 rxbufdma = dma; 438 p += nrbuf * _HME_BUFSZ; 439 dma += nrbuf * _HME_BUFSZ; 440 441 /* 442 * Initialize transmit buffer descriptors 443 */ 444 for (i = 0; i < ntbuf; i++) { 445 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 446 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 447 } 448 449 /* 450 * Initialize receive buffer descriptors 451 */ 452 for (i = 0; i < nrbuf; i++) { 453 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 454 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 455 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 456 } 457 458 hr->rb_tdhead = hr->rb_tdtail = 0; 459 hr->rb_td_nbusy = 0; 460 hr->rb_rdtail = 0; 461 } 462 463 /* 464 * Initialization of interface; set up initialization block 465 * and transmit/receive descriptor rings. 466 */ 467 int 468 hme_init(struct ifnet *ifp) 469 { 470 struct hme_softc *sc = ifp->if_softc; 471 bus_space_tag_t t = sc->sc_bustag; 472 bus_space_handle_t seb = sc->sc_seb; 473 bus_space_handle_t etx = sc->sc_etx; 474 bus_space_handle_t erx = sc->sc_erx; 475 bus_space_handle_t mac = sc->sc_mac; 476 uint8_t *ea; 477 uint32_t v; 478 int rc; 479 480 /* 481 * Initialization sequence. The numbered steps below correspond 482 * to the sequence outlined in section 6.3.5.1 in the Ethernet 483 * Channel Engine manual (part of the PCIO manual). 484 * See also the STP2002-STQ document from Sun Microsystems. 485 */ 486 487 /* step 1 & 2. Reset the Ethernet Channel */ 488 hme_stop(ifp, 0); 489 490 /* Re-initialize the MIF */ 491 hme_mifinit(sc); 492 493 /* Call MI reset function if any */ 494 if (sc->sc_hwreset) 495 (*sc->sc_hwreset)(sc); 496 497 #if 0 498 /* Mask all MIF interrupts, just in case */ 499 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 500 #endif 501 502 /* step 3. Setup data structures in host memory */ 503 hme_meminit(sc); 504 505 /* step 4. TX MAC registers & counters */ 506 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 507 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 508 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 509 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 510 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 511 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 512 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 513 sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable; 514 515 /* Load station MAC address */ 516 ea = sc->sc_enaddr; 517 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 518 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 519 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 520 521 /* 522 * Init seed for backoff 523 * (source suggested by manual: low 10 bits of MAC address) 524 */ 525 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 526 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 527 528 529 /* Note: Accepting power-on default for other MAC registers here.. */ 530 531 532 /* step 5. RX MAC registers & counters */ 533 hme_setladrf(sc); 534 535 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 536 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 537 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 538 539 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 540 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 541 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 542 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 543 544 /* step 8. Global Configuration & Interrupt Mask */ 545 bus_space_write_4(t, seb, HME_SEBI_IMASK, 546 ~( 547 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 548 HME_SEB_STAT_HOSTTOTX | 549 HME_SEB_STAT_RXTOHOST | 550 HME_SEB_STAT_TXALL | 551 HME_SEB_STAT_TXPERR | 552 HME_SEB_STAT_RCNTEXP | 553 HME_SEB_STAT_MIFIRQ | 554 HME_SEB_STAT_ALL_ERRORS )); 555 556 switch (sc->sc_burst) { 557 default: 558 v = 0; 559 break; 560 case 16: 561 v = HME_SEB_CFG_BURST16; 562 break; 563 case 32: 564 v = HME_SEB_CFG_BURST32; 565 break; 566 case 64: 567 v = HME_SEB_CFG_BURST64; 568 break; 569 } 570 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 571 572 /* step 9. ETX Configuration: use mostly default values */ 573 574 /* Enable DMA */ 575 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 576 v |= HME_ETX_CFG_DMAENABLE; 577 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 578 579 /* Transmit Descriptor ring size: in increments of 16 */ 580 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 581 582 583 /* step 10. ERX Configuration */ 584 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 585 586 /* Encode Receive Descriptor ring size: four possible values */ 587 switch (_HME_NDESC /*XXX*/) { 588 case 32: 589 v |= HME_ERX_CFG_RINGSIZE32; 590 break; 591 case 64: 592 v |= HME_ERX_CFG_RINGSIZE64; 593 break; 594 case 128: 595 v |= HME_ERX_CFG_RINGSIZE128; 596 break; 597 case 256: 598 v |= HME_ERX_CFG_RINGSIZE256; 599 break; 600 default: 601 printf("hme: invalid Receive Descriptor ring size\n"); 602 break; 603 } 604 605 /* Enable DMA */ 606 v |= HME_ERX_CFG_DMAENABLE; 607 608 /* set h/w rx checksum start offset (# of half-words) */ 609 #ifdef INET 610 v |= (((ETHER_HDR_LEN + sizeof(struct ip)) / sizeof(uint16_t)) 611 << HME_ERX_CFG_CSUMSHIFT) & 612 HME_ERX_CFG_CSUMSTART; 613 #endif 614 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 615 616 /* step 11. XIF Configuration */ 617 v = bus_space_read_4(t, mac, HME_MACI_XIF); 618 v |= HME_MAC_XIF_OE; 619 bus_space_write_4(t, mac, HME_MACI_XIF, v); 620 621 /* step 12. RX_MAC Configuration Register */ 622 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 623 v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP; 624 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 625 626 /* step 13. TX_MAC Configuration Register */ 627 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 628 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 629 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 630 631 /* step 14. Issue Transmit Pending command */ 632 633 /* Call MI initialization function if any */ 634 if (sc->sc_hwinit) 635 (*sc->sc_hwinit)(sc); 636 637 /* Set the current media. */ 638 if ((rc = hme_mediachange(ifp)) != 0) 639 return rc; 640 641 /* Start the one second timer. */ 642 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 643 644 ifp->if_flags |= IFF_RUNNING; 645 ifp->if_flags &= ~IFF_OACTIVE; 646 sc->sc_if_flags = ifp->if_flags; 647 ifp->if_timer = 0; 648 hme_start(ifp); 649 return 0; 650 } 651 652 /* 653 * Routine to copy from mbuf chain to transmit buffer in 654 * network buffer memory. 655 * Returns the amount of data copied. 656 */ 657 int 658 hme_put(struct hme_softc *sc, int ri, struct mbuf *m) 659 /* ri: Ring index */ 660 { 661 struct mbuf *n; 662 int len, tlen = 0; 663 char *bp; 664 665 bp = (char *)sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 666 for (; m; m = n) { 667 len = m->m_len; 668 if (len == 0) { 669 n = m_free(m); 670 continue; 671 } 672 memcpy(bp, mtod(m, void *), len); 673 bp += len; 674 tlen += len; 675 n = m_free(m); 676 } 677 return (tlen); 678 } 679 680 /* 681 * Pull data off an interface. 682 * Len is length of data, with local net header stripped. 683 * We copy the data into mbufs. When full cluster sized units are present 684 * we copy into clusters. 685 */ 686 struct mbuf * 687 hme_get(struct hme_softc *sc, int ri, uint32_t flags) 688 { 689 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 690 struct mbuf *m, *m0, *newm; 691 char *bp; 692 int len, totlen; 693 #ifdef INET 694 int csum_flags; 695 #endif 696 697 totlen = HME_XD_DECODE_RSIZE(flags); 698 MGETHDR(m0, M_DONTWAIT, MT_DATA); 699 if (m0 == 0) 700 return (0); 701 m_set_rcvif(m0, ifp); 702 m0->m_pkthdr.len = totlen; 703 len = MHLEN; 704 m = m0; 705 706 bp = (char *)sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 707 708 while (totlen > 0) { 709 if (totlen >= MINCLSIZE) { 710 MCLGET(m, M_DONTWAIT); 711 if ((m->m_flags & M_EXT) == 0) 712 goto bad; 713 len = MCLBYTES; 714 } 715 716 if (m == m0) { 717 char *newdata = (char *) 718 ALIGN(m->m_data + sizeof(struct ether_header)) - 719 sizeof(struct ether_header); 720 len -= newdata - m->m_data; 721 m->m_data = newdata; 722 } 723 724 m->m_len = len = min(totlen, len); 725 memcpy(mtod(m, void *), bp, len); 726 bp += len; 727 728 totlen -= len; 729 if (totlen > 0) { 730 MGET(newm, M_DONTWAIT, MT_DATA); 731 if (newm == 0) 732 goto bad; 733 len = MLEN; 734 m = m->m_next = newm; 735 } 736 } 737 738 #ifdef INET 739 /* hardware checksum */ 740 csum_flags = 0; 741 if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 742 struct ether_header *eh; 743 struct ether_vlan_header *evh; 744 struct ip *ip; 745 struct udphdr *uh; 746 uint16_t *opts; 747 int32_t hlen, pktlen; 748 uint32_t csum_data; 749 750 eh = mtod(m0, struct ether_header *); 751 if (ntohs(eh->ether_type) == ETHERTYPE_IP) { 752 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN); 753 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN; 754 } else if (ntohs(eh->ether_type) == ETHERTYPE_VLAN) { 755 evh = (struct ether_vlan_header *)eh; 756 if (ntohs(evh->evl_proto != ETHERTYPE_IP)) 757 goto swcsum; 758 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN + 759 ETHER_VLAN_ENCAP_LEN); 760 pktlen = m0->m_pkthdr.len - 761 ETHER_HDR_LEN - ETHER_VLAN_ENCAP_LEN; 762 } else 763 goto swcsum; 764 765 /* IPv4 only */ 766 if (ip->ip_v != IPVERSION) 767 goto swcsum; 768 769 hlen = ip->ip_hl << 2; 770 if (hlen < sizeof(struct ip)) 771 goto swcsum; 772 773 /* 774 * bail if too short, has random trailing garbage, truncated, 775 * fragment, or has ethernet pad. 776 */ 777 if (ntohs(ip->ip_len) < hlen || 778 ntohs(ip->ip_len) != pktlen || 779 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 780 goto swcsum; 781 782 switch (ip->ip_p) { 783 case IPPROTO_TCP: 784 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0) 785 goto swcsum; 786 if (pktlen < (hlen + sizeof(struct tcphdr))) 787 goto swcsum; 788 csum_flags = 789 M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 790 break; 791 case IPPROTO_UDP: 792 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0) 793 goto swcsum; 794 if (pktlen < (hlen + sizeof(struct udphdr))) 795 goto swcsum; 796 uh = (struct udphdr *)((char *)ip + hlen); 797 /* no checksum */ 798 if (uh->uh_sum == 0) 799 goto swcsum; 800 csum_flags = 801 M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 802 break; 803 default: 804 goto swcsum; 805 } 806 807 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */ 808 csum_data = ~flags & HME_XD_RXCKSUM; 809 810 /* 811 * If data offset is different from RX cksum start offset, 812 * we have to deduct them. 813 */ 814 hlen = ((char *)ip + hlen) - 815 ((char *)eh + ETHER_HDR_LEN + sizeof(struct ip)); 816 if (hlen > 1) { 817 uint32_t optsum; 818 819 optsum = 0; 820 opts = (uint16_t *)((char *)eh + 821 ETHER_HDR_LEN + sizeof(struct ip)); 822 823 while (hlen > 1) { 824 optsum += ntohs(*opts++); 825 hlen -= 2; 826 } 827 while (optsum >> 16) 828 optsum = (optsum >> 16) + (optsum & 0xffff); 829 830 /* Deduct the ip opts sum from the hwsum. */ 831 csum_data += (uint16_t)~optsum; 832 833 while (csum_data >> 16) 834 csum_data = 835 (csum_data >> 16) + (csum_data & 0xffff); 836 } 837 m0->m_pkthdr.csum_data = csum_data; 838 } 839 swcsum: 840 m0->m_pkthdr.csum_flags = csum_flags; 841 #endif 842 843 return (m0); 844 845 bad: 846 m_freem(m0); 847 return (0); 848 } 849 850 /* 851 * Pass a packet to the higher levels. 852 */ 853 void 854 hme_read(struct hme_softc *sc, int ix, uint32_t flags) 855 { 856 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 857 struct mbuf *m; 858 int len; 859 860 len = HME_XD_DECODE_RSIZE(flags); 861 if (len <= sizeof(struct ether_header) || 862 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 863 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 864 ETHERMTU + sizeof(struct ether_header))) { 865 #ifdef HMEDEBUG 866 printf("%s: invalid packet size %d; dropping\n", 867 device_xname(sc->sc_dev), len); 868 #endif 869 ifp->if_ierrors++; 870 return; 871 } 872 873 /* Pull packet off interface. */ 874 m = hme_get(sc, ix, flags); 875 if (m == 0) { 876 ifp->if_ierrors++; 877 return; 878 } 879 880 /* Pass the packet up. */ 881 if_percpuq_enqueue(ifp->if_percpuq, m); 882 } 883 884 void 885 hme_start(struct ifnet *ifp) 886 { 887 struct hme_softc *sc = ifp->if_softc; 888 void *txd = sc->sc_rb.rb_txd; 889 struct mbuf *m; 890 unsigned int txflags; 891 unsigned int ri, len, obusy; 892 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 893 894 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 895 return; 896 897 ri = sc->sc_rb.rb_tdhead; 898 obusy = sc->sc_rb.rb_td_nbusy; 899 900 for (;;) { 901 IFQ_DEQUEUE(&ifp->if_snd, m); 902 if (m == 0) 903 break; 904 905 /* 906 * If BPF is listening on this interface, let it see the 907 * packet before we commit it to the wire. 908 */ 909 bpf_mtap(ifp, m); 910 911 #ifdef INET 912 /* collect bits for h/w csum, before hme_put frees the mbuf */ 913 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) && 914 m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 915 struct ether_header *eh; 916 uint16_t offset, start; 917 918 eh = mtod(m, struct ether_header *); 919 switch (ntohs(eh->ether_type)) { 920 case ETHERTYPE_IP: 921 start = ETHER_HDR_LEN; 922 break; 923 case ETHERTYPE_VLAN: 924 start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 925 break; 926 default: 927 /* unsupported, drop it */ 928 m_free(m); 929 continue; 930 } 931 start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 932 offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data) 933 + start; 934 txflags = HME_XD_TXCKSUM | 935 (offset << HME_XD_TXCSSTUFFSHIFT) | 936 (start << HME_XD_TXCSSTARTSHIFT); 937 } else 938 #endif 939 txflags = 0; 940 941 /* 942 * Copy the mbuf chain into the transmit buffer. 943 */ 944 len = hme_put(sc, ri, m); 945 946 /* 947 * Initialize transmit registers and start transmission 948 */ 949 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 950 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 951 HME_XD_ENCODE_TSIZE(len) | txflags); 952 953 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 954 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 955 HME_ETX_TP_DMAWAKEUP); 956 957 if (++ri == ntbuf) 958 ri = 0; 959 960 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 961 ifp->if_flags |= IFF_OACTIVE; 962 break; 963 } 964 } 965 966 if (obusy != sc->sc_rb.rb_td_nbusy) { 967 sc->sc_rb.rb_tdhead = ri; 968 ifp->if_timer = 5; 969 } 970 } 971 972 /* 973 * Transmit interrupt. 974 */ 975 int 976 hme_tint(struct hme_softc *sc) 977 { 978 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 979 bus_space_tag_t t = sc->sc_bustag; 980 bus_space_handle_t mac = sc->sc_mac; 981 unsigned int ri, txflags; 982 983 /* 984 * Unload collision counters 985 */ 986 ifp->if_collisions += 987 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 988 bus_space_read_4(t, mac, HME_MACI_FCCNT); 989 ifp->if_oerrors += 990 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 991 bus_space_read_4(t, mac, HME_MACI_LTCNT); 992 993 /* 994 * then clear the hardware counters. 995 */ 996 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 997 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 998 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 999 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 1000 1001 /* Fetch current position in the transmit ring */ 1002 ri = sc->sc_rb.rb_tdtail; 1003 1004 for (;;) { 1005 if (sc->sc_rb.rb_td_nbusy <= 0) 1006 break; 1007 1008 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 1009 1010 if (txflags & HME_XD_OWN) 1011 break; 1012 1013 ifp->if_flags &= ~IFF_OACTIVE; 1014 ifp->if_opackets++; 1015 1016 if (++ri == sc->sc_rb.rb_ntbuf) 1017 ri = 0; 1018 1019 --sc->sc_rb.rb_td_nbusy; 1020 } 1021 1022 /* Update ring */ 1023 sc->sc_rb.rb_tdtail = ri; 1024 1025 if_schedule_deferred_start(ifp); 1026 1027 if (sc->sc_rb.rb_td_nbusy == 0) 1028 ifp->if_timer = 0; 1029 1030 return (1); 1031 } 1032 1033 /* 1034 * Receive interrupt. 1035 */ 1036 int 1037 hme_rint(struct hme_softc *sc) 1038 { 1039 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1040 bus_space_tag_t t = sc->sc_bustag; 1041 bus_space_handle_t mac = sc->sc_mac; 1042 void *xdr = sc->sc_rb.rb_rxd; 1043 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 1044 unsigned int ri; 1045 uint32_t flags; 1046 1047 ri = sc->sc_rb.rb_rdtail; 1048 1049 /* 1050 * Process all buffers with valid data. 1051 */ 1052 for (;;) { 1053 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 1054 if (flags & HME_XD_OWN) 1055 break; 1056 1057 if (flags & HME_XD_OFL) { 1058 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 1059 device_xname(sc->sc_dev), ri, flags); 1060 } else 1061 hme_read(sc, ri, flags); 1062 1063 /* This buffer can be used by the hardware again */ 1064 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 1065 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 1066 1067 if (++ri == nrbuf) 1068 ri = 0; 1069 } 1070 1071 sc->sc_rb.rb_rdtail = ri; 1072 1073 /* Read error counters ... */ 1074 ifp->if_ierrors += 1075 bus_space_read_4(t, mac, HME_MACI_STAT_LCNT) + 1076 bus_space_read_4(t, mac, HME_MACI_STAT_ACNT) + 1077 bus_space_read_4(t, mac, HME_MACI_STAT_CCNT) + 1078 bus_space_read_4(t, mac, HME_MACI_STAT_CVCNT); 1079 1080 /* ... then clear the hardware counters. */ 1081 bus_space_write_4(t, mac, HME_MACI_STAT_LCNT, 0); 1082 bus_space_write_4(t, mac, HME_MACI_STAT_ACNT, 0); 1083 bus_space_write_4(t, mac, HME_MACI_STAT_CCNT, 0); 1084 bus_space_write_4(t, mac, HME_MACI_STAT_CVCNT, 0); 1085 return (1); 1086 } 1087 1088 int 1089 hme_eint(struct hme_softc *sc, u_int status) 1090 { 1091 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1092 char bits[128]; 1093 1094 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 1095 bus_space_tag_t t = sc->sc_bustag; 1096 bus_space_handle_t mif = sc->sc_mif; 1097 uint32_t cf, st, sm; 1098 cf = bus_space_read_4(t, mif, HME_MIFI_CFG); 1099 st = bus_space_read_4(t, mif, HME_MIFI_STAT); 1100 sm = bus_space_read_4(t, mif, HME_MIFI_SM); 1101 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n", 1102 device_xname(sc->sc_dev), cf, st, sm); 1103 return (1); 1104 } 1105 1106 /* Receive error counters rolled over */ 1107 if (status & HME_SEB_STAT_ACNTEXP) 1108 ifp->if_ierrors += 0xff; 1109 if (status & HME_SEB_STAT_CCNTEXP) 1110 ifp->if_ierrors += 0xff; 1111 if (status & HME_SEB_STAT_LCNTEXP) 1112 ifp->if_ierrors += 0xff; 1113 if (status & HME_SEB_STAT_CVCNTEXP) 1114 ifp->if_ierrors += 0xff; 1115 1116 /* RXTERR locks up the interface, so do a reset */ 1117 if (status & HME_SEB_STAT_RXTERR) 1118 hme_reset(sc); 1119 1120 snprintb(bits, sizeof(bits), HME_SEB_STAT_BITS, status); 1121 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1122 1123 return (1); 1124 } 1125 1126 int 1127 hme_intr(void *v) 1128 { 1129 struct hme_softc *sc = v; 1130 bus_space_tag_t t = sc->sc_bustag; 1131 bus_space_handle_t seb = sc->sc_seb; 1132 uint32_t status; 1133 int r = 0; 1134 1135 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 1136 1137 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 1138 r |= hme_eint(sc, status); 1139 1140 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 1141 r |= hme_tint(sc); 1142 1143 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1144 r |= hme_rint(sc); 1145 1146 rnd_add_uint32(&sc->rnd_source, status); 1147 1148 return (r); 1149 } 1150 1151 1152 void 1153 hme_watchdog(struct ifnet *ifp) 1154 { 1155 struct hme_softc *sc = ifp->if_softc; 1156 1157 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1158 ++ifp->if_oerrors; 1159 1160 hme_reset(sc); 1161 } 1162 1163 /* 1164 * Initialize the MII Management Interface 1165 */ 1166 void 1167 hme_mifinit(struct hme_softc *sc) 1168 { 1169 bus_space_tag_t t = sc->sc_bustag; 1170 bus_space_handle_t mif = sc->sc_mif; 1171 bus_space_handle_t mac = sc->sc_mac; 1172 int instance, phy; 1173 uint32_t v; 1174 1175 if (sc->sc_mii.mii_media.ifm_cur != NULL) { 1176 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1177 phy = sc->sc_phys[instance]; 1178 } else 1179 /* No media set yet, pick phy arbitrarily.. */ 1180 phy = HME_PHYAD_EXTERNAL; 1181 1182 /* Configure the MIF in frame mode, no poll, current phy select */ 1183 v = 0; 1184 if (phy == HME_PHYAD_EXTERNAL) 1185 v |= HME_MIF_CFG_PHY; 1186 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1187 1188 /* If an external transceiver is selected, enable its MII drivers */ 1189 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1190 v &= ~HME_MAC_XIF_MIIENABLE; 1191 if (phy == HME_PHYAD_EXTERNAL) 1192 v |= HME_MAC_XIF_MIIENABLE; 1193 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1194 } 1195 1196 /* 1197 * MII interface 1198 */ 1199 static int 1200 hme_mii_readreg(device_t self, int phy, int reg) 1201 { 1202 struct hme_softc *sc = device_private(self); 1203 bus_space_tag_t t = sc->sc_bustag; 1204 bus_space_handle_t mif = sc->sc_mif; 1205 bus_space_handle_t mac = sc->sc_mac; 1206 uint32_t v, xif_cfg, mifi_cfg; 1207 int n; 1208 1209 /* We can at most have two PHYs */ 1210 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1211 return (0); 1212 1213 /* Select the desired PHY in the MIF configuration register */ 1214 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1215 v &= ~HME_MIF_CFG_PHY; 1216 if (phy == HME_PHYAD_EXTERNAL) 1217 v |= HME_MIF_CFG_PHY; 1218 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1219 1220 /* Enable MII drivers on external transceiver */ 1221 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1222 if (phy == HME_PHYAD_EXTERNAL) 1223 v |= HME_MAC_XIF_MIIENABLE; 1224 else 1225 v &= ~HME_MAC_XIF_MIIENABLE; 1226 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1227 1228 #if 0 1229 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1230 /* 1231 * Check whether a transceiver is connected by testing 1232 * the MIF configuration register's MDI_X bits. Note that 1233 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1234 */ 1235 mif_mdi_bit = 1 << (8 + (1 - phy)); 1236 delay(100); 1237 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1238 if ((v & mif_mdi_bit) == 0) 1239 return (0); 1240 #endif 1241 1242 /* Construct the frame command */ 1243 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1244 HME_MIF_FO_TAMSB | 1245 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1246 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1247 (reg << HME_MIF_FO_REGAD_SHIFT); 1248 1249 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1250 for (n = 0; n < 100; n++) { 1251 DELAY(1); 1252 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1253 if (v & HME_MIF_FO_TALSB) { 1254 v &= HME_MIF_FO_DATA; 1255 goto out; 1256 } 1257 } 1258 1259 v = 0; 1260 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1261 1262 out: 1263 /* Restore MIFI_CFG register */ 1264 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1265 /* Restore XIF register */ 1266 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1267 return (v); 1268 } 1269 1270 static void 1271 hme_mii_writereg(device_t self, int phy, int reg, int val) 1272 { 1273 struct hme_softc *sc = device_private(self); 1274 bus_space_tag_t t = sc->sc_bustag; 1275 bus_space_handle_t mif = sc->sc_mif; 1276 bus_space_handle_t mac = sc->sc_mac; 1277 uint32_t v, xif_cfg, mifi_cfg; 1278 int n; 1279 1280 /* We can at most have two PHYs */ 1281 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1282 return; 1283 1284 /* Select the desired PHY in the MIF configuration register */ 1285 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1286 v &= ~HME_MIF_CFG_PHY; 1287 if (phy == HME_PHYAD_EXTERNAL) 1288 v |= HME_MIF_CFG_PHY; 1289 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1290 1291 /* Enable MII drivers on external transceiver */ 1292 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1293 if (phy == HME_PHYAD_EXTERNAL) 1294 v |= HME_MAC_XIF_MIIENABLE; 1295 else 1296 v &= ~HME_MAC_XIF_MIIENABLE; 1297 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1298 1299 #if 0 1300 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1301 /* 1302 * Check whether a transceiver is connected by testing 1303 * the MIF configuration register's MDI_X bits. Note that 1304 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1305 */ 1306 mif_mdi_bit = 1 << (8 + (1 - phy)); 1307 delay(100); 1308 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1309 if ((v & mif_mdi_bit) == 0) 1310 return; 1311 #endif 1312 1313 /* Construct the frame command */ 1314 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1315 HME_MIF_FO_TAMSB | 1316 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1317 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1318 (reg << HME_MIF_FO_REGAD_SHIFT) | 1319 (val & HME_MIF_FO_DATA); 1320 1321 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1322 for (n = 0; n < 100; n++) { 1323 DELAY(1); 1324 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1325 if (v & HME_MIF_FO_TALSB) 1326 goto out; 1327 } 1328 1329 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1330 out: 1331 /* Restore MIFI_CFG register */ 1332 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1333 /* Restore XIF register */ 1334 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1335 } 1336 1337 static void 1338 hme_mii_statchg(struct ifnet *ifp) 1339 { 1340 struct hme_softc *sc = ifp->if_softc; 1341 bus_space_tag_t t = sc->sc_bustag; 1342 bus_space_handle_t mac = sc->sc_mac; 1343 uint32_t v; 1344 1345 #ifdef HMEDEBUG 1346 if (sc->sc_debug) 1347 printf("hme_mii_statchg: status change\n"); 1348 #endif 1349 1350 /* Set the MAC Full Duplex bit appropriately */ 1351 /* Apparently the hme chip is SIMPLEX if working in full duplex mode, 1352 but not otherwise. */ 1353 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1354 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1355 v |= HME_MAC_TXCFG_FULLDPLX; 1356 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX; 1357 } else { 1358 v &= ~HME_MAC_TXCFG_FULLDPLX; 1359 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX; 1360 } 1361 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags; 1362 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1363 } 1364 1365 int 1366 hme_mediachange(struct ifnet *ifp) 1367 { 1368 struct hme_softc *sc = ifp->if_softc; 1369 bus_space_tag_t t = sc->sc_bustag; 1370 bus_space_handle_t mif = sc->sc_mif; 1371 bus_space_handle_t mac = sc->sc_mac; 1372 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1373 int phy = sc->sc_phys[instance]; 1374 int rc; 1375 uint32_t v; 1376 1377 #ifdef HMEDEBUG 1378 if (sc->sc_debug) 1379 printf("hme_mediachange: phy = %d\n", phy); 1380 #endif 1381 1382 /* Select the current PHY in the MIF configuration register */ 1383 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1384 v &= ~HME_MIF_CFG_PHY; 1385 if (phy == HME_PHYAD_EXTERNAL) 1386 v |= HME_MIF_CFG_PHY; 1387 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1388 1389 /* If an external transceiver is selected, enable its MII drivers */ 1390 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1391 v &= ~HME_MAC_XIF_MIIENABLE; 1392 if (phy == HME_PHYAD_EXTERNAL) 1393 v |= HME_MAC_XIF_MIIENABLE; 1394 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1395 1396 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 1397 return 0; 1398 return rc; 1399 } 1400 1401 /* 1402 * Process an ioctl request. 1403 */ 1404 int 1405 hme_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1406 { 1407 struct hme_softc *sc = ifp->if_softc; 1408 struct ifaddr *ifa = (struct ifaddr *)data; 1409 int s, error = 0; 1410 1411 s = splnet(); 1412 1413 switch (cmd) { 1414 1415 case SIOCINITIFADDR: 1416 switch (ifa->ifa_addr->sa_family) { 1417 #ifdef INET 1418 case AF_INET: 1419 if (ifp->if_flags & IFF_UP) 1420 hme_setladrf(sc); 1421 else { 1422 ifp->if_flags |= IFF_UP; 1423 error = hme_init(ifp); 1424 } 1425 arp_ifinit(ifp, ifa); 1426 break; 1427 #endif 1428 default: 1429 ifp->if_flags |= IFF_UP; 1430 error = hme_init(ifp); 1431 break; 1432 } 1433 break; 1434 1435 case SIOCSIFFLAGS: 1436 #ifdef HMEDEBUG 1437 { 1438 struct ifreq *ifr = data; 1439 sc->sc_debug = 1440 (ifr->ifr_flags & IFF_DEBUG) != 0 ? 1 : 0; 1441 } 1442 #endif 1443 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1444 break; 1445 1446 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1447 case IFF_RUNNING: 1448 /* 1449 * If interface is marked down and it is running, then 1450 * stop it. 1451 */ 1452 hme_stop(ifp, 0); 1453 ifp->if_flags &= ~IFF_RUNNING; 1454 break; 1455 case IFF_UP: 1456 /* 1457 * If interface is marked up and it is stopped, then 1458 * start it. 1459 */ 1460 error = hme_init(ifp); 1461 break; 1462 case IFF_UP|IFF_RUNNING: 1463 /* 1464 * If setting debug or promiscuous mode, do not reset 1465 * the chip; for everything else, call hme_init() 1466 * which will trigger a reset. 1467 */ 1468 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG) 1469 if (ifp->if_flags != sc->sc_if_flags) { 1470 if ((ifp->if_flags & (~RESETIGN)) 1471 == (sc->sc_if_flags & (~RESETIGN))) 1472 hme_setladrf(sc); 1473 else 1474 error = hme_init(ifp); 1475 } 1476 #undef RESETIGN 1477 break; 1478 case 0: 1479 break; 1480 } 1481 1482 if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable) 1483 error = hme_init(ifp); 1484 1485 break; 1486 1487 default: 1488 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1489 break; 1490 1491 error = 0; 1492 1493 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1494 ; 1495 else if (ifp->if_flags & IFF_RUNNING) { 1496 /* 1497 * Multicast list has changed; set the hardware filter 1498 * accordingly. 1499 */ 1500 hme_setladrf(sc); 1501 } 1502 break; 1503 } 1504 1505 sc->sc_if_flags = ifp->if_flags; 1506 splx(s); 1507 return (error); 1508 } 1509 1510 bool 1511 hme_shutdown(device_t self, int howto) 1512 { 1513 struct hme_softc *sc; 1514 struct ifnet *ifp; 1515 1516 sc = device_private(self); 1517 ifp = &sc->sc_ethercom.ec_if; 1518 hme_stop(ifp, 1); 1519 1520 return true; 1521 } 1522 1523 /* 1524 * Set up the logical address filter. 1525 */ 1526 void 1527 hme_setladrf(struct hme_softc *sc) 1528 { 1529 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1530 struct ether_multi *enm; 1531 struct ether_multistep step; 1532 struct ethercom *ec = &sc->sc_ethercom; 1533 bus_space_tag_t t = sc->sc_bustag; 1534 bus_space_handle_t mac = sc->sc_mac; 1535 uint32_t v; 1536 uint32_t crc; 1537 uint32_t hash[4]; 1538 1539 /* Clear hash table */ 1540 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1541 1542 /* Get current RX configuration */ 1543 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1544 1545 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1546 /* Turn on promiscuous mode; turn off the hash filter */ 1547 v |= HME_MAC_RXCFG_PMISC; 1548 v &= ~HME_MAC_RXCFG_HENABLE; 1549 ifp->if_flags |= IFF_ALLMULTI; 1550 goto chipit; 1551 } 1552 1553 /* Turn off promiscuous mode; turn on the hash filter */ 1554 v &= ~HME_MAC_RXCFG_PMISC; 1555 v |= HME_MAC_RXCFG_HENABLE; 1556 1557 /* 1558 * Set up multicast address filter by passing all multicast addresses 1559 * through a crc generator, and then using the high order 6 bits as an 1560 * index into the 64 bit logical address filter. The high order bit 1561 * selects the word, while the rest of the bits select the bit within 1562 * the word. 1563 */ 1564 1565 ETHER_FIRST_MULTI(step, ec, enm); 1566 while (enm != NULL) { 1567 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1568 /* 1569 * We must listen to a range of multicast addresses. 1570 * For now, just accept all multicasts, rather than 1571 * trying to set only those filter bits needed to match 1572 * the range. (At this time, the only use of address 1573 * ranges is for IP multicast routing, for which the 1574 * range is big enough to require all bits set.) 1575 */ 1576 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1577 ifp->if_flags |= IFF_ALLMULTI; 1578 goto chipit; 1579 } 1580 1581 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1582 1583 /* Just want the 6 most significant bits. */ 1584 crc >>= 26; 1585 1586 /* Set the corresponding bit in the filter. */ 1587 hash[crc >> 4] |= 1 << (crc & 0xf); 1588 1589 ETHER_NEXT_MULTI(step, enm); 1590 } 1591 1592 ifp->if_flags &= ~IFF_ALLMULTI; 1593 1594 chipit: 1595 /* Now load the hash table into the chip */ 1596 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1597 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1598 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1599 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1600 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1601 } 1602 1603 /* 1604 * Routines for accessing the transmit and receive buffers. 1605 * The various CPU and adapter configurations supported by this 1606 * driver require three different access methods for buffers 1607 * and descriptors: 1608 * (1) contig (contiguous data; no padding), 1609 * (2) gap2 (two bytes of data followed by two bytes of padding), 1610 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1611 */ 1612 1613 #if 0 1614 /* 1615 * contig: contiguous data with no padding. 1616 * 1617 * Buffers may have any alignment. 1618 */ 1619 1620 void 1621 hme_copytobuf_contig(struct hme_softc *sc, void *from, int ri, int len) 1622 { 1623 volatile void *buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1624 1625 /* 1626 * Just call memcpy() to do the work. 1627 */ 1628 memcpy(buf, from, len); 1629 } 1630 1631 void 1632 hme_copyfrombuf_contig(struct hme_softc *sc, void *to, int boff, int len) 1633 { 1634 volatile void *buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1635 1636 /* 1637 * Just call memcpy() to do the work. 1638 */ 1639 memcpy(to, buf, len); 1640 } 1641 #endif 1642