1 /* $NetBSD: hme.c,v 1.99 2018/06/26 06:48:00 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * HME Ethernet module driver. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.99 2018/06/26 06:48:00 msaitoh Exp $"); 38 39 /* #define HMEDEBUG */ 40 41 #include "opt_inet.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/mbuf.h> 47 #include <sys/syslog.h> 48 #include <sys/socket.h> 49 #include <sys/device.h> 50 #include <sys/malloc.h> 51 #include <sys/ioctl.h> 52 #include <sys/errno.h> 53 #include <sys/rndsource.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_ether.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 61 #ifdef INET 62 #include <net/if_vlanvar.h> 63 #include <netinet/in.h> 64 #include <netinet/if_inarp.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <sys/bus.h> 76 77 #include <dev/ic/hmereg.h> 78 #include <dev/ic/hmevar.h> 79 80 static void hme_start(struct ifnet *); 81 static void hme_stop(struct ifnet *, int); 82 static int hme_ioctl(struct ifnet *, u_long, void *); 83 static void hme_tick(void *); 84 static void hme_watchdog(struct ifnet *); 85 static bool hme_shutdown(device_t, int); 86 static int hme_init(struct ifnet *); 87 static void hme_meminit(struct hme_softc *); 88 static void hme_mifinit(struct hme_softc *); 89 static void hme_reset(struct hme_softc *); 90 static void hme_chipreset(struct hme_softc *); 91 static void hme_setladrf(struct hme_softc *); 92 93 /* MII methods & callbacks */ 94 static int hme_mii_readreg(device_t, int, int); 95 static void hme_mii_writereg(device_t, int, int, int); 96 static void hme_mii_statchg(struct ifnet *); 97 98 static int hme_mediachange(struct ifnet *); 99 100 static struct mbuf *hme_get(struct hme_softc *, int, uint32_t); 101 static int hme_put(struct hme_softc *, int, struct mbuf *); 102 static void hme_read(struct hme_softc *, int, uint32_t); 103 static int hme_eint(struct hme_softc *, u_int); 104 static int hme_rint(struct hme_softc *); 105 static int hme_tint(struct hme_softc *); 106 107 #if 0 108 /* Default buffer copy routines */ 109 static void hme_copytobuf_contig(struct hme_softc *, void *, int, int); 110 static void hme_copyfrombuf_contig(struct hme_softc *, void *, int, int); 111 #endif 112 113 void 114 hme_config(struct hme_softc *sc) 115 { 116 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 117 struct mii_data *mii = &sc->sc_mii; 118 struct mii_softc *child; 119 bus_dma_tag_t dmatag = sc->sc_dmatag; 120 bus_dma_segment_t seg; 121 bus_size_t size; 122 int rseg, error; 123 124 /* 125 * HME common initialization. 126 * 127 * hme_softc fields that must be initialized by the front-end: 128 * 129 * the bus tag: 130 * sc_bustag 131 * 132 * the DMA bus tag: 133 * sc_dmatag 134 * 135 * the bus handles: 136 * sc_seb (Shared Ethernet Block registers) 137 * sc_erx (Receiver Unit registers) 138 * sc_etx (Transmitter Unit registers) 139 * sc_mac (MAC registers) 140 * sc_mif (Management Interface registers) 141 * 142 * the maximum bus burst size: 143 * sc_burst 144 * 145 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 146 * rb_membase, rb_dmabase) 147 * 148 * the local Ethernet address: 149 * sc_enaddr 150 * 151 */ 152 153 /* Make sure the chip is stopped. */ 154 hme_chipreset(sc); 155 156 /* 157 * Allocate descriptors and buffers 158 * XXX - do all this differently.. and more configurably, 159 * eg. use things as `dma_load_mbuf()' on transmit, 160 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 161 * all the time) on the receiver side. 162 * 163 * Note: receive buffers must be 64-byte aligned. 164 * Also, apparently, the buffers must extend to a DMA burst 165 * boundary beyond the maximum packet size. 166 */ 167 #define _HME_NDESC 128 168 #define _HME_BUFSZ 1600 169 170 /* Note: the # of descriptors must be a multiple of 16 */ 171 sc->sc_rb.rb_ntbuf = _HME_NDESC; 172 sc->sc_rb.rb_nrbuf = _HME_NDESC; 173 174 /* 175 * Allocate DMA capable memory 176 * Buffer descriptors must be aligned on a 2048 byte boundary; 177 * take this into account when calculating the size. Note that 178 * the maximum number of descriptors (256) occupies 2048 bytes, 179 * so we allocate that much regardless of _HME_NDESC. 180 */ 181 size = 2048 + /* TX descriptors */ 182 2048 + /* RX descriptors */ 183 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 184 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* RX buffers */ 185 186 /* Allocate DMA buffer */ 187 if ((error = bus_dmamem_alloc(dmatag, size, 188 2048, 0, 189 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 190 aprint_error_dev(sc->sc_dev, "DMA buffer alloc error %d\n", 191 error); 192 return; 193 } 194 195 /* Map DMA memory in CPU addressable space */ 196 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 197 &sc->sc_rb.rb_membase, 198 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 199 aprint_error_dev(sc->sc_dev, "DMA buffer map error %d\n", 200 error); 201 bus_dmamap_unload(dmatag, sc->sc_dmamap); 202 bus_dmamem_free(dmatag, &seg, rseg); 203 return; 204 } 205 206 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 207 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 208 aprint_error_dev(sc->sc_dev, "DMA map create error %d\n", 209 error); 210 return; 211 } 212 213 /* Load the buffer */ 214 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 215 sc->sc_rb.rb_membase, size, NULL, 216 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 217 aprint_error_dev(sc->sc_dev, "DMA buffer map load error %d\n", 218 error); 219 bus_dmamem_free(dmatag, &seg, rseg); 220 return; 221 } 222 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 223 224 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 225 ether_sprintf(sc->sc_enaddr)); 226 227 /* Initialize ifnet structure. */ 228 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 229 ifp->if_softc = sc; 230 ifp->if_start = hme_start; 231 ifp->if_stop = hme_stop; 232 ifp->if_ioctl = hme_ioctl; 233 ifp->if_init = hme_init; 234 ifp->if_watchdog = hme_watchdog; 235 ifp->if_flags = 236 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 237 sc->sc_if_flags = ifp->if_flags; 238 ifp->if_capabilities |= 239 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 240 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 241 IFQ_SET_READY(&ifp->if_snd); 242 243 /* Initialize ifmedia structures and MII info */ 244 mii->mii_ifp = ifp; 245 mii->mii_readreg = hme_mii_readreg; 246 mii->mii_writereg = hme_mii_writereg; 247 mii->mii_statchg = hme_mii_statchg; 248 249 sc->sc_ethercom.ec_mii = mii; 250 ifmedia_init(&mii->mii_media, 0, hme_mediachange, ether_mediastatus); 251 252 hme_mifinit(sc); 253 254 mii_attach(sc->sc_dev, mii, 0xffffffff, 255 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 256 257 child = LIST_FIRST(&mii->mii_phys); 258 if (child == NULL) { 259 /* No PHY attached */ 260 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 261 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 262 } else { 263 /* 264 * Walk along the list of attached MII devices and 265 * establish an `MII instance' to `phy number' 266 * mapping. We'll use this mapping in media change 267 * requests to determine which phy to use to program 268 * the MIF configuration register. 269 */ 270 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 271 /* 272 * Note: we support just two PHYs: the built-in 273 * internal device and an external on the MII 274 * connector. 275 */ 276 if (child->mii_phy > 1 || child->mii_inst > 1) { 277 aprint_error_dev(sc->sc_dev, 278 "cannot accommodate MII device %s" 279 " at phy %d, instance %d\n", 280 device_xname(child->mii_dev), 281 child->mii_phy, child->mii_inst); 282 continue; 283 } 284 285 sc->sc_phys[child->mii_inst] = child->mii_phy; 286 } 287 288 /* 289 * Set the default media to auto negotiation if the phy has 290 * the auto negotiation capability. 291 * XXX; What to do otherwise? 292 */ 293 if (ifmedia_match(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0)) 294 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 295 /* 296 else 297 ifmedia_set(&sc->sc_mii.mii_media, sc->sc_defaultmedia); 298 */ 299 } 300 301 /* claim 802.1q capability */ 302 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 303 304 /* Attach the interface. */ 305 if_attach(ifp); 306 if_deferred_start_init(ifp, NULL); 307 ether_ifattach(ifp, sc->sc_enaddr); 308 309 if (pmf_device_register1(sc->sc_dev, NULL, NULL, hme_shutdown)) 310 pmf_class_network_register(sc->sc_dev, ifp); 311 else 312 aprint_error_dev(sc->sc_dev, 313 "couldn't establish power handler\n"); 314 315 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 316 RND_TYPE_NET, RND_FLAG_DEFAULT); 317 318 callout_init(&sc->sc_tick_ch, 0); 319 } 320 321 void 322 hme_tick(void *arg) 323 { 324 struct hme_softc *sc = arg; 325 int s; 326 327 s = splnet(); 328 mii_tick(&sc->sc_mii); 329 splx(s); 330 331 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 332 } 333 334 void 335 hme_reset(struct hme_softc *sc) 336 { 337 int s; 338 339 s = splnet(); 340 (void)hme_init(&sc->sc_ethercom.ec_if); 341 splx(s); 342 } 343 344 void 345 hme_chipreset(struct hme_softc *sc) 346 { 347 bus_space_tag_t t = sc->sc_bustag; 348 bus_space_handle_t seb = sc->sc_seb; 349 int n; 350 351 /* Mask all interrupts */ 352 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff); 353 354 /* Reset transmitter and receiver */ 355 bus_space_write_4(t, seb, HME_SEBI_RESET, 356 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 357 358 for (n = 0; n < 20; n++) { 359 uint32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 360 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 361 return; 362 DELAY(20); 363 } 364 365 printf("%s: %s: reset failed\n", device_xname(sc->sc_dev), __func__); 366 } 367 368 void 369 hme_stop(struct ifnet *ifp, int disable) 370 { 371 struct hme_softc *sc; 372 373 sc = ifp->if_softc; 374 375 ifp->if_timer = 0; 376 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 377 378 callout_stop(&sc->sc_tick_ch); 379 mii_down(&sc->sc_mii); 380 381 hme_chipreset(sc); 382 } 383 384 void 385 hme_meminit(struct hme_softc *sc) 386 { 387 bus_addr_t txbufdma, rxbufdma; 388 bus_addr_t dma; 389 char *p; 390 unsigned int ntbuf, nrbuf, i; 391 struct hme_ring *hr = &sc->sc_rb; 392 393 p = hr->rb_membase; 394 dma = hr->rb_dmabase; 395 396 ntbuf = hr->rb_ntbuf; 397 nrbuf = hr->rb_nrbuf; 398 399 /* 400 * Allocate transmit descriptors 401 */ 402 hr->rb_txd = p; 403 hr->rb_txddma = dma; 404 p += ntbuf * HME_XD_SIZE; 405 dma += ntbuf * HME_XD_SIZE; 406 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 407 dma = (bus_addr_t)roundup((u_long)dma, 2048); 408 p = (void *)roundup((u_long)p, 2048); 409 410 /* 411 * Allocate receive descriptors 412 */ 413 hr->rb_rxd = p; 414 hr->rb_rxddma = dma; 415 p += nrbuf * HME_XD_SIZE; 416 dma += nrbuf * HME_XD_SIZE; 417 /* Again move forward to the next 2048 byte boundary.*/ 418 dma = (bus_addr_t)roundup((u_long)dma, 2048); 419 p = (void *)roundup((u_long)p, 2048); 420 421 422 /* 423 * Allocate transmit buffers 424 */ 425 hr->rb_txbuf = p; 426 txbufdma = dma; 427 p += ntbuf * _HME_BUFSZ; 428 dma += ntbuf * _HME_BUFSZ; 429 430 /* 431 * Allocate receive buffers 432 */ 433 hr->rb_rxbuf = p; 434 rxbufdma = dma; 435 p += nrbuf * _HME_BUFSZ; 436 dma += nrbuf * _HME_BUFSZ; 437 438 /* 439 * Initialize transmit buffer descriptors 440 */ 441 for (i = 0; i < ntbuf; i++) { 442 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 443 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 444 } 445 446 /* 447 * Initialize receive buffer descriptors 448 */ 449 for (i = 0; i < nrbuf; i++) { 450 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 451 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 452 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 453 } 454 455 hr->rb_tdhead = hr->rb_tdtail = 0; 456 hr->rb_td_nbusy = 0; 457 hr->rb_rdtail = 0; 458 } 459 460 /* 461 * Initialization of interface; set up initialization block 462 * and transmit/receive descriptor rings. 463 */ 464 int 465 hme_init(struct ifnet *ifp) 466 { 467 struct hme_softc *sc = ifp->if_softc; 468 bus_space_tag_t t = sc->sc_bustag; 469 bus_space_handle_t seb = sc->sc_seb; 470 bus_space_handle_t etx = sc->sc_etx; 471 bus_space_handle_t erx = sc->sc_erx; 472 bus_space_handle_t mac = sc->sc_mac; 473 uint8_t *ea; 474 uint32_t v; 475 int rc; 476 477 /* 478 * Initialization sequence. The numbered steps below correspond 479 * to the sequence outlined in section 6.3.5.1 in the Ethernet 480 * Channel Engine manual (part of the PCIO manual). 481 * See also the STP2002-STQ document from Sun Microsystems. 482 */ 483 484 /* step 1 & 2. Reset the Ethernet Channel */ 485 hme_stop(ifp, 0); 486 487 /* Re-initialize the MIF */ 488 hme_mifinit(sc); 489 490 /* Call MI reset function if any */ 491 if (sc->sc_hwreset) 492 (*sc->sc_hwreset)(sc); 493 494 #if 0 495 /* Mask all MIF interrupts, just in case */ 496 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 497 #endif 498 499 /* step 3. Setup data structures in host memory */ 500 hme_meminit(sc); 501 502 /* step 4. TX MAC registers & counters */ 503 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 504 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 505 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 506 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 507 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 508 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 509 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 510 sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable; 511 512 /* Load station MAC address */ 513 ea = sc->sc_enaddr; 514 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 515 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 516 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 517 518 /* 519 * Init seed for backoff 520 * (source suggested by manual: low 10 bits of MAC address) 521 */ 522 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 523 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 524 525 526 /* Note: Accepting power-on default for other MAC registers here.. */ 527 528 529 /* step 5. RX MAC registers & counters */ 530 hme_setladrf(sc); 531 532 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 533 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 534 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 535 536 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 537 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 538 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 539 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 540 541 /* step 8. Global Configuration & Interrupt Mask */ 542 bus_space_write_4(t, seb, HME_SEBI_IMASK, 543 ~( 544 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 545 HME_SEB_STAT_HOSTTOTX | 546 HME_SEB_STAT_RXTOHOST | 547 HME_SEB_STAT_TXALL | 548 HME_SEB_STAT_TXPERR | 549 HME_SEB_STAT_RCNTEXP | 550 HME_SEB_STAT_MIFIRQ | 551 HME_SEB_STAT_ALL_ERRORS )); 552 553 switch (sc->sc_burst) { 554 default: 555 v = 0; 556 break; 557 case 16: 558 v = HME_SEB_CFG_BURST16; 559 break; 560 case 32: 561 v = HME_SEB_CFG_BURST32; 562 break; 563 case 64: 564 v = HME_SEB_CFG_BURST64; 565 break; 566 } 567 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 568 569 /* step 9. ETX Configuration: use mostly default values */ 570 571 /* Enable DMA */ 572 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 573 v |= HME_ETX_CFG_DMAENABLE; 574 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 575 576 /* Transmit Descriptor ring size: in increments of 16 */ 577 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 578 579 580 /* step 10. ERX Configuration */ 581 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 582 583 /* Encode Receive Descriptor ring size: four possible values */ 584 switch (_HME_NDESC /*XXX*/) { 585 case 32: 586 v |= HME_ERX_CFG_RINGSIZE32; 587 break; 588 case 64: 589 v |= HME_ERX_CFG_RINGSIZE64; 590 break; 591 case 128: 592 v |= HME_ERX_CFG_RINGSIZE128; 593 break; 594 case 256: 595 v |= HME_ERX_CFG_RINGSIZE256; 596 break; 597 default: 598 printf("hme: invalid Receive Descriptor ring size\n"); 599 break; 600 } 601 602 /* Enable DMA */ 603 v |= HME_ERX_CFG_DMAENABLE; 604 605 /* set h/w rx checksum start offset (# of half-words) */ 606 #ifdef INET 607 v |= (((ETHER_HDR_LEN + sizeof(struct ip)) / sizeof(uint16_t)) 608 << HME_ERX_CFG_CSUMSHIFT) & 609 HME_ERX_CFG_CSUMSTART; 610 #endif 611 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 612 613 /* step 11. XIF Configuration */ 614 v = bus_space_read_4(t, mac, HME_MACI_XIF); 615 v |= HME_MAC_XIF_OE; 616 bus_space_write_4(t, mac, HME_MACI_XIF, v); 617 618 /* step 12. RX_MAC Configuration Register */ 619 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 620 v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP; 621 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 622 623 /* step 13. TX_MAC Configuration Register */ 624 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 625 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 626 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 627 628 /* step 14. Issue Transmit Pending command */ 629 630 /* Call MI initialization function if any */ 631 if (sc->sc_hwinit) 632 (*sc->sc_hwinit)(sc); 633 634 /* Set the current media. */ 635 if ((rc = hme_mediachange(ifp)) != 0) 636 return rc; 637 638 /* Start the one second timer. */ 639 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 640 641 ifp->if_flags |= IFF_RUNNING; 642 ifp->if_flags &= ~IFF_OACTIVE; 643 sc->sc_if_flags = ifp->if_flags; 644 ifp->if_timer = 0; 645 hme_start(ifp); 646 return 0; 647 } 648 649 /* 650 * Routine to copy from mbuf chain to transmit buffer in 651 * network buffer memory. 652 * Returns the amount of data copied. 653 */ 654 int 655 hme_put(struct hme_softc *sc, int ri, struct mbuf *m) 656 /* ri: Ring index */ 657 { 658 struct mbuf *n; 659 int len, tlen = 0; 660 char *bp; 661 662 bp = (char *)sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 663 for (; m; m = n) { 664 len = m->m_len; 665 if (len == 0) { 666 n = m_free(m); 667 continue; 668 } 669 memcpy(bp, mtod(m, void *), len); 670 bp += len; 671 tlen += len; 672 n = m_free(m); 673 } 674 return (tlen); 675 } 676 677 /* 678 * Pull data off an interface. 679 * Len is length of data, with local net header stripped. 680 * We copy the data into mbufs. When full cluster sized units are present 681 * we copy into clusters. 682 */ 683 struct mbuf * 684 hme_get(struct hme_softc *sc, int ri, uint32_t flags) 685 { 686 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 687 struct mbuf *m, *m0, *newm; 688 char *bp; 689 int len, totlen; 690 #ifdef INET 691 int csum_flags; 692 #endif 693 694 totlen = HME_XD_DECODE_RSIZE(flags); 695 MGETHDR(m0, M_DONTWAIT, MT_DATA); 696 if (m0 == 0) 697 return (0); 698 m_set_rcvif(m0, ifp); 699 m0->m_pkthdr.len = totlen; 700 len = MHLEN; 701 m = m0; 702 703 bp = (char *)sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 704 705 while (totlen > 0) { 706 if (totlen >= MINCLSIZE) { 707 MCLGET(m, M_DONTWAIT); 708 if ((m->m_flags & M_EXT) == 0) 709 goto bad; 710 len = MCLBYTES; 711 } 712 713 if (m == m0) { 714 char *newdata = (char *) 715 ALIGN(m->m_data + sizeof(struct ether_header)) - 716 sizeof(struct ether_header); 717 len -= newdata - m->m_data; 718 m->m_data = newdata; 719 } 720 721 m->m_len = len = min(totlen, len); 722 memcpy(mtod(m, void *), bp, len); 723 bp += len; 724 725 totlen -= len; 726 if (totlen > 0) { 727 MGET(newm, M_DONTWAIT, MT_DATA); 728 if (newm == 0) 729 goto bad; 730 len = MLEN; 731 m = m->m_next = newm; 732 } 733 } 734 735 #ifdef INET 736 /* hardware checksum */ 737 csum_flags = 0; 738 if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 739 struct ether_header *eh; 740 struct ether_vlan_header *evh; 741 struct ip *ip; 742 struct udphdr *uh; 743 uint16_t *opts; 744 int32_t hlen, pktlen; 745 uint32_t csum_data; 746 747 eh = mtod(m0, struct ether_header *); 748 if (ntohs(eh->ether_type) == ETHERTYPE_IP) { 749 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN); 750 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN; 751 } else if (ntohs(eh->ether_type) == ETHERTYPE_VLAN) { 752 evh = (struct ether_vlan_header *)eh; 753 if (ntohs(evh->evl_proto) != ETHERTYPE_IP) 754 goto swcsum; 755 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN + 756 ETHER_VLAN_ENCAP_LEN); 757 pktlen = m0->m_pkthdr.len - 758 ETHER_HDR_LEN - ETHER_VLAN_ENCAP_LEN; 759 } else 760 goto swcsum; 761 762 /* IPv4 only */ 763 if (ip->ip_v != IPVERSION) 764 goto swcsum; 765 766 hlen = ip->ip_hl << 2; 767 if (hlen < sizeof(struct ip)) 768 goto swcsum; 769 770 /* 771 * bail if too short, has random trailing garbage, truncated, 772 * fragment, or has ethernet pad. 773 */ 774 if (ntohs(ip->ip_len) < hlen || 775 ntohs(ip->ip_len) != pktlen || 776 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 777 goto swcsum; 778 779 switch (ip->ip_p) { 780 case IPPROTO_TCP: 781 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0) 782 goto swcsum; 783 if (pktlen < (hlen + sizeof(struct tcphdr))) 784 goto swcsum; 785 csum_flags = 786 M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 787 break; 788 case IPPROTO_UDP: 789 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0) 790 goto swcsum; 791 if (pktlen < (hlen + sizeof(struct udphdr))) 792 goto swcsum; 793 uh = (struct udphdr *)((char *)ip + hlen); 794 /* no checksum */ 795 if (uh->uh_sum == 0) 796 goto swcsum; 797 csum_flags = 798 M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 799 break; 800 default: 801 goto swcsum; 802 } 803 804 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */ 805 csum_data = ~flags & HME_XD_RXCKSUM; 806 807 /* 808 * If data offset is different from RX cksum start offset, 809 * we have to deduct them. 810 */ 811 hlen = ((char *)ip + hlen) - 812 ((char *)eh + ETHER_HDR_LEN + sizeof(struct ip)); 813 if (hlen > 1) { 814 uint32_t optsum; 815 816 optsum = 0; 817 opts = (uint16_t *)((char *)eh + 818 ETHER_HDR_LEN + sizeof(struct ip)); 819 820 while (hlen > 1) { 821 optsum += ntohs(*opts++); 822 hlen -= 2; 823 } 824 while (optsum >> 16) 825 optsum = (optsum >> 16) + (optsum & 0xffff); 826 827 /* Deduct the ip opts sum from the hwsum. */ 828 csum_data += (uint16_t)~optsum; 829 830 while (csum_data >> 16) 831 csum_data = 832 (csum_data >> 16) + (csum_data & 0xffff); 833 } 834 m0->m_pkthdr.csum_data = csum_data; 835 } 836 swcsum: 837 m0->m_pkthdr.csum_flags = csum_flags; 838 #endif 839 840 return (m0); 841 842 bad: 843 m_freem(m0); 844 return (0); 845 } 846 847 /* 848 * Pass a packet to the higher levels. 849 */ 850 void 851 hme_read(struct hme_softc *sc, int ix, uint32_t flags) 852 { 853 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 854 struct mbuf *m; 855 int len; 856 857 len = HME_XD_DECODE_RSIZE(flags); 858 if (len <= sizeof(struct ether_header) || 859 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 860 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 861 ETHERMTU + sizeof(struct ether_header))) { 862 #ifdef HMEDEBUG 863 printf("%s: invalid packet size %d; dropping\n", 864 device_xname(sc->sc_dev), len); 865 #endif 866 ifp->if_ierrors++; 867 return; 868 } 869 870 /* Pull packet off interface. */ 871 m = hme_get(sc, ix, flags); 872 if (m == 0) { 873 ifp->if_ierrors++; 874 return; 875 } 876 877 /* Pass the packet up. */ 878 if_percpuq_enqueue(ifp->if_percpuq, m); 879 } 880 881 void 882 hme_start(struct ifnet *ifp) 883 { 884 struct hme_softc *sc = ifp->if_softc; 885 void *txd = sc->sc_rb.rb_txd; 886 struct mbuf *m; 887 unsigned int txflags; 888 unsigned int ri, len, obusy; 889 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 890 891 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 892 return; 893 894 ri = sc->sc_rb.rb_tdhead; 895 obusy = sc->sc_rb.rb_td_nbusy; 896 897 for (;;) { 898 IFQ_DEQUEUE(&ifp->if_snd, m); 899 if (m == 0) 900 break; 901 902 /* 903 * If BPF is listening on this interface, let it see the 904 * packet before we commit it to the wire. 905 */ 906 bpf_mtap(ifp, m, BPF_D_OUT); 907 908 #ifdef INET 909 /* collect bits for h/w csum, before hme_put frees the mbuf */ 910 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) && 911 m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 912 struct ether_header *eh; 913 uint16_t offset, start; 914 915 eh = mtod(m, struct ether_header *); 916 switch (ntohs(eh->ether_type)) { 917 case ETHERTYPE_IP: 918 start = ETHER_HDR_LEN; 919 break; 920 case ETHERTYPE_VLAN: 921 start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 922 break; 923 default: 924 /* unsupported, drop it */ 925 m_free(m); 926 continue; 927 } 928 start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 929 offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data) 930 + start; 931 txflags = HME_XD_TXCKSUM | 932 (offset << HME_XD_TXCSSTUFFSHIFT) | 933 (start << HME_XD_TXCSSTARTSHIFT); 934 } else 935 #endif 936 txflags = 0; 937 938 /* 939 * Copy the mbuf chain into the transmit buffer. 940 */ 941 len = hme_put(sc, ri, m); 942 943 /* 944 * Initialize transmit registers and start transmission 945 */ 946 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 947 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 948 HME_XD_ENCODE_TSIZE(len) | txflags); 949 950 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 951 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 952 HME_ETX_TP_DMAWAKEUP); 953 954 if (++ri == ntbuf) 955 ri = 0; 956 957 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 958 ifp->if_flags |= IFF_OACTIVE; 959 break; 960 } 961 } 962 963 if (obusy != sc->sc_rb.rb_td_nbusy) { 964 sc->sc_rb.rb_tdhead = ri; 965 ifp->if_timer = 5; 966 } 967 } 968 969 /* 970 * Transmit interrupt. 971 */ 972 int 973 hme_tint(struct hme_softc *sc) 974 { 975 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 976 bus_space_tag_t t = sc->sc_bustag; 977 bus_space_handle_t mac = sc->sc_mac; 978 unsigned int ri, txflags; 979 980 /* 981 * Unload collision counters 982 */ 983 ifp->if_collisions += 984 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 985 bus_space_read_4(t, mac, HME_MACI_FCCNT); 986 ifp->if_oerrors += 987 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 988 bus_space_read_4(t, mac, HME_MACI_LTCNT); 989 990 /* 991 * then clear the hardware counters. 992 */ 993 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 994 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 995 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 996 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 997 998 /* Fetch current position in the transmit ring */ 999 ri = sc->sc_rb.rb_tdtail; 1000 1001 for (;;) { 1002 if (sc->sc_rb.rb_td_nbusy <= 0) 1003 break; 1004 1005 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 1006 1007 if (txflags & HME_XD_OWN) 1008 break; 1009 1010 ifp->if_flags &= ~IFF_OACTIVE; 1011 ifp->if_opackets++; 1012 1013 if (++ri == sc->sc_rb.rb_ntbuf) 1014 ri = 0; 1015 1016 --sc->sc_rb.rb_td_nbusy; 1017 } 1018 1019 /* Update ring */ 1020 sc->sc_rb.rb_tdtail = ri; 1021 1022 if_schedule_deferred_start(ifp); 1023 1024 if (sc->sc_rb.rb_td_nbusy == 0) 1025 ifp->if_timer = 0; 1026 1027 return (1); 1028 } 1029 1030 /* 1031 * Receive interrupt. 1032 */ 1033 int 1034 hme_rint(struct hme_softc *sc) 1035 { 1036 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1037 bus_space_tag_t t = sc->sc_bustag; 1038 bus_space_handle_t mac = sc->sc_mac; 1039 void *xdr = sc->sc_rb.rb_rxd; 1040 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 1041 unsigned int ri; 1042 uint32_t flags; 1043 1044 ri = sc->sc_rb.rb_rdtail; 1045 1046 /* 1047 * Process all buffers with valid data. 1048 */ 1049 for (;;) { 1050 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 1051 if (flags & HME_XD_OWN) 1052 break; 1053 1054 if (flags & HME_XD_OFL) { 1055 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 1056 device_xname(sc->sc_dev), ri, flags); 1057 } else 1058 hme_read(sc, ri, flags); 1059 1060 /* This buffer can be used by the hardware again */ 1061 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 1062 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 1063 1064 if (++ri == nrbuf) 1065 ri = 0; 1066 } 1067 1068 sc->sc_rb.rb_rdtail = ri; 1069 1070 /* Read error counters ... */ 1071 ifp->if_ierrors += 1072 bus_space_read_4(t, mac, HME_MACI_STAT_LCNT) + 1073 bus_space_read_4(t, mac, HME_MACI_STAT_ACNT) + 1074 bus_space_read_4(t, mac, HME_MACI_STAT_CCNT) + 1075 bus_space_read_4(t, mac, HME_MACI_STAT_CVCNT); 1076 1077 /* ... then clear the hardware counters. */ 1078 bus_space_write_4(t, mac, HME_MACI_STAT_LCNT, 0); 1079 bus_space_write_4(t, mac, HME_MACI_STAT_ACNT, 0); 1080 bus_space_write_4(t, mac, HME_MACI_STAT_CCNT, 0); 1081 bus_space_write_4(t, mac, HME_MACI_STAT_CVCNT, 0); 1082 return (1); 1083 } 1084 1085 int 1086 hme_eint(struct hme_softc *sc, u_int status) 1087 { 1088 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1089 char bits[128]; 1090 1091 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 1092 bus_space_tag_t t = sc->sc_bustag; 1093 bus_space_handle_t mif = sc->sc_mif; 1094 uint32_t cf, st, sm; 1095 cf = bus_space_read_4(t, mif, HME_MIFI_CFG); 1096 st = bus_space_read_4(t, mif, HME_MIFI_STAT); 1097 sm = bus_space_read_4(t, mif, HME_MIFI_SM); 1098 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n", 1099 device_xname(sc->sc_dev), cf, st, sm); 1100 return (1); 1101 } 1102 1103 /* Receive error counters rolled over */ 1104 if (status & HME_SEB_STAT_ACNTEXP) 1105 ifp->if_ierrors += 0xff; 1106 if (status & HME_SEB_STAT_CCNTEXP) 1107 ifp->if_ierrors += 0xff; 1108 if (status & HME_SEB_STAT_LCNTEXP) 1109 ifp->if_ierrors += 0xff; 1110 if (status & HME_SEB_STAT_CVCNTEXP) 1111 ifp->if_ierrors += 0xff; 1112 1113 /* RXTERR locks up the interface, so do a reset */ 1114 if (status & HME_SEB_STAT_RXTERR) 1115 hme_reset(sc); 1116 1117 snprintb(bits, sizeof(bits), HME_SEB_STAT_BITS, status); 1118 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1119 1120 return (1); 1121 } 1122 1123 int 1124 hme_intr(void *v) 1125 { 1126 struct hme_softc *sc = v; 1127 bus_space_tag_t t = sc->sc_bustag; 1128 bus_space_handle_t seb = sc->sc_seb; 1129 uint32_t status; 1130 int r = 0; 1131 1132 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 1133 1134 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 1135 r |= hme_eint(sc, status); 1136 1137 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 1138 r |= hme_tint(sc); 1139 1140 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1141 r |= hme_rint(sc); 1142 1143 rnd_add_uint32(&sc->rnd_source, status); 1144 1145 return (r); 1146 } 1147 1148 1149 void 1150 hme_watchdog(struct ifnet *ifp) 1151 { 1152 struct hme_softc *sc = ifp->if_softc; 1153 1154 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1155 ++ifp->if_oerrors; 1156 1157 hme_reset(sc); 1158 } 1159 1160 /* 1161 * Initialize the MII Management Interface 1162 */ 1163 void 1164 hme_mifinit(struct hme_softc *sc) 1165 { 1166 bus_space_tag_t t = sc->sc_bustag; 1167 bus_space_handle_t mif = sc->sc_mif; 1168 bus_space_handle_t mac = sc->sc_mac; 1169 int instance, phy; 1170 uint32_t v; 1171 1172 if (sc->sc_mii.mii_media.ifm_cur != NULL) { 1173 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1174 phy = sc->sc_phys[instance]; 1175 } else 1176 /* No media set yet, pick phy arbitrarily.. */ 1177 phy = HME_PHYAD_EXTERNAL; 1178 1179 /* Configure the MIF in frame mode, no poll, current phy select */ 1180 v = 0; 1181 if (phy == HME_PHYAD_EXTERNAL) 1182 v |= HME_MIF_CFG_PHY; 1183 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1184 1185 /* If an external transceiver is selected, enable its MII drivers */ 1186 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1187 v &= ~HME_MAC_XIF_MIIENABLE; 1188 if (phy == HME_PHYAD_EXTERNAL) 1189 v |= HME_MAC_XIF_MIIENABLE; 1190 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1191 } 1192 1193 /* 1194 * MII interface 1195 */ 1196 static int 1197 hme_mii_readreg(device_t self, int phy, int reg) 1198 { 1199 struct hme_softc *sc = device_private(self); 1200 bus_space_tag_t t = sc->sc_bustag; 1201 bus_space_handle_t mif = sc->sc_mif; 1202 bus_space_handle_t mac = sc->sc_mac; 1203 uint32_t v, xif_cfg, mifi_cfg; 1204 int n; 1205 1206 /* We can at most have two PHYs */ 1207 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1208 return (0); 1209 1210 /* Select the desired PHY in the MIF configuration register */ 1211 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1212 v &= ~HME_MIF_CFG_PHY; 1213 if (phy == HME_PHYAD_EXTERNAL) 1214 v |= HME_MIF_CFG_PHY; 1215 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1216 1217 /* Enable MII drivers on external transceiver */ 1218 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1219 if (phy == HME_PHYAD_EXTERNAL) 1220 v |= HME_MAC_XIF_MIIENABLE; 1221 else 1222 v &= ~HME_MAC_XIF_MIIENABLE; 1223 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1224 1225 #if 0 1226 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1227 /* 1228 * Check whether a transceiver is connected by testing 1229 * the MIF configuration register's MDI_X bits. Note that 1230 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1231 */ 1232 mif_mdi_bit = 1 << (8 + (1 - phy)); 1233 delay(100); 1234 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1235 if ((v & mif_mdi_bit) == 0) 1236 return (0); 1237 #endif 1238 1239 /* Construct the frame command */ 1240 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1241 HME_MIF_FO_TAMSB | 1242 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1243 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1244 (reg << HME_MIF_FO_REGAD_SHIFT); 1245 1246 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1247 for (n = 0; n < 100; n++) { 1248 DELAY(1); 1249 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1250 if (v & HME_MIF_FO_TALSB) { 1251 v &= HME_MIF_FO_DATA; 1252 goto out; 1253 } 1254 } 1255 1256 v = 0; 1257 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1258 1259 out: 1260 /* Restore MIFI_CFG register */ 1261 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1262 /* Restore XIF register */ 1263 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1264 return (v); 1265 } 1266 1267 static void 1268 hme_mii_writereg(device_t self, int phy, int reg, int val) 1269 { 1270 struct hme_softc *sc = device_private(self); 1271 bus_space_tag_t t = sc->sc_bustag; 1272 bus_space_handle_t mif = sc->sc_mif; 1273 bus_space_handle_t mac = sc->sc_mac; 1274 uint32_t v, xif_cfg, mifi_cfg; 1275 int n; 1276 1277 /* We can at most have two PHYs */ 1278 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1279 return; 1280 1281 /* Select the desired PHY in the MIF configuration register */ 1282 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1283 v &= ~HME_MIF_CFG_PHY; 1284 if (phy == HME_PHYAD_EXTERNAL) 1285 v |= HME_MIF_CFG_PHY; 1286 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1287 1288 /* Enable MII drivers on external transceiver */ 1289 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1290 if (phy == HME_PHYAD_EXTERNAL) 1291 v |= HME_MAC_XIF_MIIENABLE; 1292 else 1293 v &= ~HME_MAC_XIF_MIIENABLE; 1294 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1295 1296 #if 0 1297 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1298 /* 1299 * Check whether a transceiver is connected by testing 1300 * the MIF configuration register's MDI_X bits. Note that 1301 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1302 */ 1303 mif_mdi_bit = 1 << (8 + (1 - phy)); 1304 delay(100); 1305 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1306 if ((v & mif_mdi_bit) == 0) 1307 return; 1308 #endif 1309 1310 /* Construct the frame command */ 1311 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1312 HME_MIF_FO_TAMSB | 1313 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1314 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1315 (reg << HME_MIF_FO_REGAD_SHIFT) | 1316 (val & HME_MIF_FO_DATA); 1317 1318 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1319 for (n = 0; n < 100; n++) { 1320 DELAY(1); 1321 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1322 if (v & HME_MIF_FO_TALSB) 1323 goto out; 1324 } 1325 1326 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1327 out: 1328 /* Restore MIFI_CFG register */ 1329 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1330 /* Restore XIF register */ 1331 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1332 } 1333 1334 static void 1335 hme_mii_statchg(struct ifnet *ifp) 1336 { 1337 struct hme_softc *sc = ifp->if_softc; 1338 bus_space_tag_t t = sc->sc_bustag; 1339 bus_space_handle_t mac = sc->sc_mac; 1340 uint32_t v; 1341 1342 #ifdef HMEDEBUG 1343 if (sc->sc_debug) 1344 printf("hme_mii_statchg: status change\n"); 1345 #endif 1346 1347 /* Set the MAC Full Duplex bit appropriately */ 1348 /* Apparently the hme chip is SIMPLEX if working in full duplex mode, 1349 but not otherwise. */ 1350 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1351 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1352 v |= HME_MAC_TXCFG_FULLDPLX; 1353 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX; 1354 } else { 1355 v &= ~HME_MAC_TXCFG_FULLDPLX; 1356 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX; 1357 } 1358 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags; 1359 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1360 } 1361 1362 int 1363 hme_mediachange(struct ifnet *ifp) 1364 { 1365 struct hme_softc *sc = ifp->if_softc; 1366 bus_space_tag_t t = sc->sc_bustag; 1367 bus_space_handle_t mif = sc->sc_mif; 1368 bus_space_handle_t mac = sc->sc_mac; 1369 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1370 int phy = sc->sc_phys[instance]; 1371 int rc; 1372 uint32_t v; 1373 1374 #ifdef HMEDEBUG 1375 if (sc->sc_debug) 1376 printf("hme_mediachange: phy = %d\n", phy); 1377 #endif 1378 1379 /* Select the current PHY in the MIF configuration register */ 1380 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1381 v &= ~HME_MIF_CFG_PHY; 1382 if (phy == HME_PHYAD_EXTERNAL) 1383 v |= HME_MIF_CFG_PHY; 1384 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1385 1386 /* If an external transceiver is selected, enable its MII drivers */ 1387 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1388 v &= ~HME_MAC_XIF_MIIENABLE; 1389 if (phy == HME_PHYAD_EXTERNAL) 1390 v |= HME_MAC_XIF_MIIENABLE; 1391 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1392 1393 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 1394 return 0; 1395 return rc; 1396 } 1397 1398 /* 1399 * Process an ioctl request. 1400 */ 1401 int 1402 hme_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1403 { 1404 struct hme_softc *sc = ifp->if_softc; 1405 struct ifaddr *ifa = (struct ifaddr *)data; 1406 int s, error = 0; 1407 1408 s = splnet(); 1409 1410 switch (cmd) { 1411 1412 case SIOCINITIFADDR: 1413 switch (ifa->ifa_addr->sa_family) { 1414 #ifdef INET 1415 case AF_INET: 1416 if (ifp->if_flags & IFF_UP) 1417 hme_setladrf(sc); 1418 else { 1419 ifp->if_flags |= IFF_UP; 1420 error = hme_init(ifp); 1421 } 1422 arp_ifinit(ifp, ifa); 1423 break; 1424 #endif 1425 default: 1426 ifp->if_flags |= IFF_UP; 1427 error = hme_init(ifp); 1428 break; 1429 } 1430 break; 1431 1432 case SIOCSIFFLAGS: 1433 #ifdef HMEDEBUG 1434 { 1435 struct ifreq *ifr = data; 1436 sc->sc_debug = 1437 (ifr->ifr_flags & IFF_DEBUG) != 0 ? 1 : 0; 1438 } 1439 #endif 1440 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1441 break; 1442 1443 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1444 case IFF_RUNNING: 1445 /* 1446 * If interface is marked down and it is running, then 1447 * stop it. 1448 */ 1449 hme_stop(ifp, 0); 1450 ifp->if_flags &= ~IFF_RUNNING; 1451 break; 1452 case IFF_UP: 1453 /* 1454 * If interface is marked up and it is stopped, then 1455 * start it. 1456 */ 1457 error = hme_init(ifp); 1458 break; 1459 case IFF_UP|IFF_RUNNING: 1460 /* 1461 * If setting debug or promiscuous mode, do not reset 1462 * the chip; for everything else, call hme_init() 1463 * which will trigger a reset. 1464 */ 1465 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG) 1466 if (ifp->if_flags != sc->sc_if_flags) { 1467 if ((ifp->if_flags & (~RESETIGN)) 1468 == (sc->sc_if_flags & (~RESETIGN))) 1469 hme_setladrf(sc); 1470 else 1471 error = hme_init(ifp); 1472 } 1473 #undef RESETIGN 1474 break; 1475 case 0: 1476 break; 1477 } 1478 1479 if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable) 1480 error = hme_init(ifp); 1481 1482 break; 1483 1484 default: 1485 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1486 break; 1487 1488 error = 0; 1489 1490 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1491 ; 1492 else if (ifp->if_flags & IFF_RUNNING) { 1493 /* 1494 * Multicast list has changed; set the hardware filter 1495 * accordingly. 1496 */ 1497 hme_setladrf(sc); 1498 } 1499 break; 1500 } 1501 1502 sc->sc_if_flags = ifp->if_flags; 1503 splx(s); 1504 return (error); 1505 } 1506 1507 bool 1508 hme_shutdown(device_t self, int howto) 1509 { 1510 struct hme_softc *sc; 1511 struct ifnet *ifp; 1512 1513 sc = device_private(self); 1514 ifp = &sc->sc_ethercom.ec_if; 1515 hme_stop(ifp, 1); 1516 1517 return true; 1518 } 1519 1520 /* 1521 * Set up the logical address filter. 1522 */ 1523 void 1524 hme_setladrf(struct hme_softc *sc) 1525 { 1526 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1527 struct ether_multi *enm; 1528 struct ether_multistep step; 1529 struct ethercom *ec = &sc->sc_ethercom; 1530 bus_space_tag_t t = sc->sc_bustag; 1531 bus_space_handle_t mac = sc->sc_mac; 1532 uint32_t v; 1533 uint32_t crc; 1534 uint32_t hash[4]; 1535 1536 /* Clear hash table */ 1537 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1538 1539 /* Get current RX configuration */ 1540 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1541 1542 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1543 /* Turn on promiscuous mode; turn off the hash filter */ 1544 v |= HME_MAC_RXCFG_PMISC; 1545 v &= ~HME_MAC_RXCFG_HENABLE; 1546 ifp->if_flags |= IFF_ALLMULTI; 1547 goto chipit; 1548 } 1549 1550 /* Turn off promiscuous mode; turn on the hash filter */ 1551 v &= ~HME_MAC_RXCFG_PMISC; 1552 v |= HME_MAC_RXCFG_HENABLE; 1553 1554 /* 1555 * Set up multicast address filter by passing all multicast addresses 1556 * through a crc generator, and then using the high order 6 bits as an 1557 * index into the 64 bit logical address filter. The high order bit 1558 * selects the word, while the rest of the bits select the bit within 1559 * the word. 1560 */ 1561 1562 ETHER_FIRST_MULTI(step, ec, enm); 1563 while (enm != NULL) { 1564 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1565 /* 1566 * We must listen to a range of multicast addresses. 1567 * For now, just accept all multicasts, rather than 1568 * trying to set only those filter bits needed to match 1569 * the range. (At this time, the only use of address 1570 * ranges is for IP multicast routing, for which the 1571 * range is big enough to require all bits set.) 1572 */ 1573 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1574 ifp->if_flags |= IFF_ALLMULTI; 1575 goto chipit; 1576 } 1577 1578 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1579 1580 /* Just want the 6 most significant bits. */ 1581 crc >>= 26; 1582 1583 /* Set the corresponding bit in the filter. */ 1584 hash[crc >> 4] |= 1 << (crc & 0xf); 1585 1586 ETHER_NEXT_MULTI(step, enm); 1587 } 1588 1589 ifp->if_flags &= ~IFF_ALLMULTI; 1590 1591 chipit: 1592 /* Now load the hash table into the chip */ 1593 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1594 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1595 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1596 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1597 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1598 } 1599 1600 /* 1601 * Routines for accessing the transmit and receive buffers. 1602 * The various CPU and adapter configurations supported by this 1603 * driver require three different access methods for buffers 1604 * and descriptors: 1605 * (1) contig (contiguous data; no padding), 1606 * (2) gap2 (two bytes of data followed by two bytes of padding), 1607 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1608 */ 1609 1610 #if 0 1611 /* 1612 * contig: contiguous data with no padding. 1613 * 1614 * Buffers may have any alignment. 1615 */ 1616 1617 void 1618 hme_copytobuf_contig(struct hme_softc *sc, void *from, int ri, int len) 1619 { 1620 volatile void *buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1621 1622 /* 1623 * Just call memcpy() to do the work. 1624 */ 1625 memcpy(buf, from, len); 1626 } 1627 1628 void 1629 hme_copyfrombuf_contig(struct hme_softc *sc, void *to, int boff, int len) 1630 { 1631 volatile void *buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1632 1633 /* 1634 * Just call memcpy() to do the work. 1635 */ 1636 memcpy(to, buf, len); 1637 } 1638 #endif 1639