1 /* $NetBSD: hme.c,v 1.86 2010/04/05 07:19:34 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * HME Ethernet module driver. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.86 2010/04/05 07:19:34 joerg Exp $"); 38 39 /* #define HMEDEBUG */ 40 41 #include "opt_inet.h" 42 #include "rnd.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/mbuf.h> 48 #include <sys/syslog.h> 49 #include <sys/socket.h> 50 #include <sys/device.h> 51 #include <sys/malloc.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #if NRND > 0 55 #include <sys/rnd.h> 56 #endif 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_ether.h> 61 #include <net/if_media.h> 62 63 #ifdef INET 64 #include <net/if_vlanvar.h> 65 #include <netinet/in.h> 66 #include <netinet/if_inarp.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/in_var.h> 69 #include <netinet/ip.h> 70 #include <netinet/tcp.h> 71 #include <netinet/udp.h> 72 #endif 73 74 75 #include <net/bpf.h> 76 #include <net/bpfdesc.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 81 #include <sys/bus.h> 82 83 #include <dev/ic/hmereg.h> 84 #include <dev/ic/hmevar.h> 85 86 static void hme_start(struct ifnet *); 87 static void hme_stop(struct ifnet *, int); 88 static int hme_ioctl(struct ifnet *, u_long, void *); 89 static void hme_tick(void *); 90 static void hme_watchdog(struct ifnet *); 91 static bool hme_shutdown(device_t, int); 92 static int hme_init(struct ifnet *); 93 static void hme_meminit(struct hme_softc *); 94 static void hme_mifinit(struct hme_softc *); 95 static void hme_reset(struct hme_softc *); 96 static void hme_chipreset(struct hme_softc *); 97 static void hme_setladrf(struct hme_softc *); 98 99 /* MII methods & callbacks */ 100 static int hme_mii_readreg(device_t, int, int); 101 static void hme_mii_writereg(device_t, int, int, int); 102 static void hme_mii_statchg(device_t); 103 104 static int hme_mediachange(struct ifnet *); 105 106 static struct mbuf *hme_get(struct hme_softc *, int, uint32_t); 107 static int hme_put(struct hme_softc *, int, struct mbuf *); 108 static void hme_read(struct hme_softc *, int, uint32_t); 109 static int hme_eint(struct hme_softc *, u_int); 110 static int hme_rint(struct hme_softc *); 111 static int hme_tint(struct hme_softc *); 112 113 #if 0 114 /* Default buffer copy routines */ 115 static void hme_copytobuf_contig(struct hme_softc *, void *, int, int); 116 static void hme_copyfrombuf_contig(struct hme_softc *, void *, int, int); 117 #endif 118 119 void 120 hme_config(struct hme_softc *sc) 121 { 122 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 123 struct mii_data *mii = &sc->sc_mii; 124 struct mii_softc *child; 125 bus_dma_tag_t dmatag = sc->sc_dmatag; 126 bus_dma_segment_t seg; 127 bus_size_t size; 128 int rseg, error; 129 130 /* 131 * HME common initialization. 132 * 133 * hme_softc fields that must be initialized by the front-end: 134 * 135 * the bus tag: 136 * sc_bustag 137 * 138 * the DMA bus tag: 139 * sc_dmatag 140 * 141 * the bus handles: 142 * sc_seb (Shared Ethernet Block registers) 143 * sc_erx (Receiver Unit registers) 144 * sc_etx (Transmitter Unit registers) 145 * sc_mac (MAC registers) 146 * sc_mif (Management Interface registers) 147 * 148 * the maximum bus burst size: 149 * sc_burst 150 * 151 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 152 * rb_membase, rb_dmabase) 153 * 154 * the local Ethernet address: 155 * sc_enaddr 156 * 157 */ 158 159 /* Make sure the chip is stopped. */ 160 hme_chipreset(sc); 161 162 /* 163 * Allocate descriptors and buffers 164 * XXX - do all this differently.. and more configurably, 165 * eg. use things as `dma_load_mbuf()' on transmit, 166 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 167 * all the time) on the receiver side. 168 * 169 * Note: receive buffers must be 64-byte aligned. 170 * Also, apparently, the buffers must extend to a DMA burst 171 * boundary beyond the maximum packet size. 172 */ 173 #define _HME_NDESC 128 174 #define _HME_BUFSZ 1600 175 176 /* Note: the # of descriptors must be a multiple of 16 */ 177 sc->sc_rb.rb_ntbuf = _HME_NDESC; 178 sc->sc_rb.rb_nrbuf = _HME_NDESC; 179 180 /* 181 * Allocate DMA capable memory 182 * Buffer descriptors must be aligned on a 2048 byte boundary; 183 * take this into account when calculating the size. Note that 184 * the maximum number of descriptors (256) occupies 2048 bytes, 185 * so we allocate that much regardless of _HME_NDESC. 186 */ 187 size = 2048 + /* TX descriptors */ 188 2048 + /* RX descriptors */ 189 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 190 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* RX buffers */ 191 192 /* Allocate DMA buffer */ 193 if ((error = bus_dmamem_alloc(dmatag, size, 194 2048, 0, 195 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 196 aprint_error_dev(sc->sc_dev, "DMA buffer alloc error %d\n", 197 error); 198 return; 199 } 200 201 /* Map DMA memory in CPU addressable space */ 202 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 203 &sc->sc_rb.rb_membase, 204 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 205 aprint_error_dev(sc->sc_dev, "DMA buffer map error %d\n", 206 error); 207 bus_dmamap_unload(dmatag, sc->sc_dmamap); 208 bus_dmamem_free(dmatag, &seg, rseg); 209 return; 210 } 211 212 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 213 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 214 aprint_error_dev(sc->sc_dev, "DMA map create error %d\n", 215 error); 216 return; 217 } 218 219 /* Load the buffer */ 220 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 221 sc->sc_rb.rb_membase, size, NULL, 222 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 223 aprint_error_dev(sc->sc_dev, "DMA buffer map load error %d\n", 224 error); 225 bus_dmamem_free(dmatag, &seg, rseg); 226 return; 227 } 228 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 229 230 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 231 ether_sprintf(sc->sc_enaddr)); 232 233 /* Initialize ifnet structure. */ 234 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 235 ifp->if_softc = sc; 236 ifp->if_start = hme_start; 237 ifp->if_stop = hme_stop; 238 ifp->if_ioctl = hme_ioctl; 239 ifp->if_init = hme_init; 240 ifp->if_watchdog = hme_watchdog; 241 ifp->if_flags = 242 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 243 sc->sc_if_flags = ifp->if_flags; 244 ifp->if_capabilities |= 245 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 246 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 247 IFQ_SET_READY(&ifp->if_snd); 248 249 /* Initialize ifmedia structures and MII info */ 250 mii->mii_ifp = ifp; 251 mii->mii_readreg = hme_mii_readreg; 252 mii->mii_writereg = hme_mii_writereg; 253 mii->mii_statchg = hme_mii_statchg; 254 255 sc->sc_ethercom.ec_mii = mii; 256 ifmedia_init(&mii->mii_media, 0, hme_mediachange, ether_mediastatus); 257 258 hme_mifinit(sc); 259 260 /* 261 * Some HME's have an MII connector, as well as RJ45. Try attaching 262 * the RJ45 (internal) PHY first, so that the MII PHY is always 263 * instance 1. 264 */ 265 mii_attach(sc->sc_dev, mii, 0xffffffff, 266 HME_PHYAD_INTERNAL, MII_OFFSET_ANY, MIIF_FORCEANEG); 267 mii_attach(sc->sc_dev, mii, 0xffffffff, 268 HME_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_FORCEANEG); 269 270 child = LIST_FIRST(&mii->mii_phys); 271 if (child == NULL) { 272 /* No PHY attached */ 273 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 274 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 275 } else { 276 /* 277 * Walk along the list of attached MII devices and 278 * establish an `MII instance' to `phy number' 279 * mapping. We'll use this mapping in media change 280 * requests to determine which phy to use to program 281 * the MIF configuration register. 282 */ 283 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 284 /* 285 * Note: we support just two PHYs: the built-in 286 * internal device and an external on the MII 287 * connector. 288 */ 289 if (child->mii_phy > 1 || child->mii_inst > 1) { 290 aprint_error_dev(sc->sc_dev, 291 "cannot accommodate MII device %s" 292 " at phy %d, instance %d\n", 293 device_xname(child->mii_dev), 294 child->mii_phy, child->mii_inst); 295 continue; 296 } 297 298 sc->sc_phys[child->mii_inst] = child->mii_phy; 299 } 300 301 /* 302 * Set the default media to auto negotiation if the phy has 303 * the auto negotiation capability. 304 * XXX; What to do otherwise? 305 */ 306 if (ifmedia_match(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0)) 307 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 308 /* 309 else 310 ifmedia_set(&sc->sc_mii.mii_media, sc->sc_defaultmedia); 311 */ 312 } 313 314 /* claim 802.1q capability */ 315 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 316 317 /* Attach the interface. */ 318 if_attach(ifp); 319 ether_ifattach(ifp, sc->sc_enaddr); 320 321 if (pmf_device_register1(sc->sc_dev, NULL, NULL, hme_shutdown)) 322 pmf_class_network_register(sc->sc_dev, ifp); 323 else 324 aprint_error_dev(sc->sc_dev, 325 "couldn't establish power handler\n"); 326 327 #if NRND > 0 328 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 329 RND_TYPE_NET, 0); 330 #endif 331 332 callout_init(&sc->sc_tick_ch, 0); 333 } 334 335 void 336 hme_tick(void *arg) 337 { 338 struct hme_softc *sc = arg; 339 int s; 340 341 s = splnet(); 342 mii_tick(&sc->sc_mii); 343 splx(s); 344 345 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 346 } 347 348 void 349 hme_reset(struct hme_softc *sc) 350 { 351 int s; 352 353 s = splnet(); 354 (void)hme_init(&sc->sc_ethercom.ec_if); 355 splx(s); 356 } 357 358 void 359 hme_chipreset(struct hme_softc *sc) 360 { 361 bus_space_tag_t t = sc->sc_bustag; 362 bus_space_handle_t seb = sc->sc_seb; 363 int n; 364 365 /* Mask all interrupts */ 366 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff); 367 368 /* Reset transmitter and receiver */ 369 bus_space_write_4(t, seb, HME_SEBI_RESET, 370 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 371 372 for (n = 0; n < 20; n++) { 373 uint32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 374 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 375 return; 376 DELAY(20); 377 } 378 379 printf("%s: %s: reset failed\n", device_xname(sc->sc_dev), __func__); 380 } 381 382 void 383 hme_stop(struct ifnet *ifp, int disable) 384 { 385 struct hme_softc *sc; 386 387 sc = ifp->if_softc; 388 389 ifp->if_timer = 0; 390 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 391 392 callout_stop(&sc->sc_tick_ch); 393 mii_down(&sc->sc_mii); 394 395 hme_chipreset(sc); 396 } 397 398 void 399 hme_meminit(struct hme_softc *sc) 400 { 401 bus_addr_t txbufdma, rxbufdma; 402 bus_addr_t dma; 403 char *p; 404 unsigned int ntbuf, nrbuf, i; 405 struct hme_ring *hr = &sc->sc_rb; 406 407 p = hr->rb_membase; 408 dma = hr->rb_dmabase; 409 410 ntbuf = hr->rb_ntbuf; 411 nrbuf = hr->rb_nrbuf; 412 413 /* 414 * Allocate transmit descriptors 415 */ 416 hr->rb_txd = p; 417 hr->rb_txddma = dma; 418 p += ntbuf * HME_XD_SIZE; 419 dma += ntbuf * HME_XD_SIZE; 420 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 421 dma = (bus_addr_t)roundup((u_long)dma, 2048); 422 p = (void *)roundup((u_long)p, 2048); 423 424 /* 425 * Allocate receive descriptors 426 */ 427 hr->rb_rxd = p; 428 hr->rb_rxddma = dma; 429 p += nrbuf * HME_XD_SIZE; 430 dma += nrbuf * HME_XD_SIZE; 431 /* Again move forward to the next 2048 byte boundary.*/ 432 dma = (bus_addr_t)roundup((u_long)dma, 2048); 433 p = (void *)roundup((u_long)p, 2048); 434 435 436 /* 437 * Allocate transmit buffers 438 */ 439 hr->rb_txbuf = p; 440 txbufdma = dma; 441 p += ntbuf * _HME_BUFSZ; 442 dma += ntbuf * _HME_BUFSZ; 443 444 /* 445 * Allocate receive buffers 446 */ 447 hr->rb_rxbuf = p; 448 rxbufdma = dma; 449 p += nrbuf * _HME_BUFSZ; 450 dma += nrbuf * _HME_BUFSZ; 451 452 /* 453 * Initialize transmit buffer descriptors 454 */ 455 for (i = 0; i < ntbuf; i++) { 456 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 457 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 458 } 459 460 /* 461 * Initialize receive buffer descriptors 462 */ 463 for (i = 0; i < nrbuf; i++) { 464 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 465 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 466 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 467 } 468 469 hr->rb_tdhead = hr->rb_tdtail = 0; 470 hr->rb_td_nbusy = 0; 471 hr->rb_rdtail = 0; 472 } 473 474 /* 475 * Initialization of interface; set up initialization block 476 * and transmit/receive descriptor rings. 477 */ 478 int 479 hme_init(struct ifnet *ifp) 480 { 481 struct hme_softc *sc = ifp->if_softc; 482 bus_space_tag_t t = sc->sc_bustag; 483 bus_space_handle_t seb = sc->sc_seb; 484 bus_space_handle_t etx = sc->sc_etx; 485 bus_space_handle_t erx = sc->sc_erx; 486 bus_space_handle_t mac = sc->sc_mac; 487 uint8_t *ea; 488 uint32_t v; 489 int rc; 490 491 /* 492 * Initialization sequence. The numbered steps below correspond 493 * to the sequence outlined in section 6.3.5.1 in the Ethernet 494 * Channel Engine manual (part of the PCIO manual). 495 * See also the STP2002-STQ document from Sun Microsystems. 496 */ 497 498 /* step 1 & 2. Reset the Ethernet Channel */ 499 hme_stop(ifp, 0); 500 501 /* Re-initialize the MIF */ 502 hme_mifinit(sc); 503 504 /* Call MI reset function if any */ 505 if (sc->sc_hwreset) 506 (*sc->sc_hwreset)(sc); 507 508 #if 0 509 /* Mask all MIF interrupts, just in case */ 510 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 511 #endif 512 513 /* step 3. Setup data structures in host memory */ 514 hme_meminit(sc); 515 516 /* step 4. TX MAC registers & counters */ 517 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 518 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 519 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 520 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 521 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 522 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 523 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 524 sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable; 525 526 /* Load station MAC address */ 527 ea = sc->sc_enaddr; 528 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 529 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 530 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 531 532 /* 533 * Init seed for backoff 534 * (source suggested by manual: low 10 bits of MAC address) 535 */ 536 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 537 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 538 539 540 /* Note: Accepting power-on default for other MAC registers here.. */ 541 542 543 /* step 5. RX MAC registers & counters */ 544 hme_setladrf(sc); 545 546 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 547 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 548 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 549 550 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 551 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 552 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 553 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 554 555 /* step 8. Global Configuration & Interrupt Mask */ 556 bus_space_write_4(t, seb, HME_SEBI_IMASK, 557 ~( 558 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 559 HME_SEB_STAT_HOSTTOTX | 560 HME_SEB_STAT_RXTOHOST | 561 HME_SEB_STAT_TXALL | 562 HME_SEB_STAT_TXPERR | 563 HME_SEB_STAT_RCNTEXP | 564 HME_SEB_STAT_MIFIRQ | 565 HME_SEB_STAT_ALL_ERRORS )); 566 567 switch (sc->sc_burst) { 568 default: 569 v = 0; 570 break; 571 case 16: 572 v = HME_SEB_CFG_BURST16; 573 break; 574 case 32: 575 v = HME_SEB_CFG_BURST32; 576 break; 577 case 64: 578 v = HME_SEB_CFG_BURST64; 579 break; 580 } 581 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 582 583 /* step 9. ETX Configuration: use mostly default values */ 584 585 /* Enable DMA */ 586 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 587 v |= HME_ETX_CFG_DMAENABLE; 588 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 589 590 /* Transmit Descriptor ring size: in increments of 16 */ 591 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 592 593 594 /* step 10. ERX Configuration */ 595 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 596 597 /* Encode Receive Descriptor ring size: four possible values */ 598 switch (_HME_NDESC /*XXX*/) { 599 case 32: 600 v |= HME_ERX_CFG_RINGSIZE32; 601 break; 602 case 64: 603 v |= HME_ERX_CFG_RINGSIZE64; 604 break; 605 case 128: 606 v |= HME_ERX_CFG_RINGSIZE128; 607 break; 608 case 256: 609 v |= HME_ERX_CFG_RINGSIZE256; 610 break; 611 default: 612 printf("hme: invalid Receive Descriptor ring size\n"); 613 break; 614 } 615 616 /* Enable DMA */ 617 v |= HME_ERX_CFG_DMAENABLE; 618 619 /* set h/w rx checksum start offset (# of half-words) */ 620 #ifdef INET 621 v |= (((ETHER_HDR_LEN + sizeof(struct ip)) / sizeof(uint16_t)) 622 << HME_ERX_CFG_CSUMSHIFT) & 623 HME_ERX_CFG_CSUMSTART; 624 #endif 625 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 626 627 /* step 11. XIF Configuration */ 628 v = bus_space_read_4(t, mac, HME_MACI_XIF); 629 v |= HME_MAC_XIF_OE; 630 bus_space_write_4(t, mac, HME_MACI_XIF, v); 631 632 /* step 12. RX_MAC Configuration Register */ 633 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 634 v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP; 635 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 636 637 /* step 13. TX_MAC Configuration Register */ 638 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 639 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 640 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 641 642 /* step 14. Issue Transmit Pending command */ 643 644 /* Call MI initialization function if any */ 645 if (sc->sc_hwinit) 646 (*sc->sc_hwinit)(sc); 647 648 /* Set the current media. */ 649 if ((rc = hme_mediachange(ifp)) != 0) 650 return rc; 651 652 /* Start the one second timer. */ 653 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 654 655 ifp->if_flags |= IFF_RUNNING; 656 ifp->if_flags &= ~IFF_OACTIVE; 657 sc->sc_if_flags = ifp->if_flags; 658 ifp->if_timer = 0; 659 hme_start(ifp); 660 return 0; 661 } 662 663 /* 664 * Routine to copy from mbuf chain to transmit buffer in 665 * network buffer memory. 666 * Returns the amount of data copied. 667 */ 668 int 669 hme_put(struct hme_softc *sc, int ri, struct mbuf *m) 670 /* ri: Ring index */ 671 { 672 struct mbuf *n; 673 int len, tlen = 0; 674 char *bp; 675 676 bp = (char *)sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 677 for (; m; m = n) { 678 len = m->m_len; 679 if (len == 0) { 680 MFREE(m, n); 681 continue; 682 } 683 memcpy(bp, mtod(m, void *), len); 684 bp += len; 685 tlen += len; 686 MFREE(m, n); 687 } 688 return (tlen); 689 } 690 691 /* 692 * Pull data off an interface. 693 * Len is length of data, with local net header stripped. 694 * We copy the data into mbufs. When full cluster sized units are present 695 * we copy into clusters. 696 */ 697 struct mbuf * 698 hme_get(struct hme_softc *sc, int ri, uint32_t flags) 699 { 700 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 701 struct mbuf *m, *m0, *newm; 702 char *bp; 703 int len, totlen; 704 #ifdef INET 705 int csum_flags; 706 #endif 707 708 totlen = HME_XD_DECODE_RSIZE(flags); 709 MGETHDR(m0, M_DONTWAIT, MT_DATA); 710 if (m0 == 0) 711 return (0); 712 m0->m_pkthdr.rcvif = ifp; 713 m0->m_pkthdr.len = totlen; 714 len = MHLEN; 715 m = m0; 716 717 bp = (char *)sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 718 719 while (totlen > 0) { 720 if (totlen >= MINCLSIZE) { 721 MCLGET(m, M_DONTWAIT); 722 if ((m->m_flags & M_EXT) == 0) 723 goto bad; 724 len = MCLBYTES; 725 } 726 727 if (m == m0) { 728 char *newdata = (char *) 729 ALIGN(m->m_data + sizeof(struct ether_header)) - 730 sizeof(struct ether_header); 731 len -= newdata - m->m_data; 732 m->m_data = newdata; 733 } 734 735 m->m_len = len = min(totlen, len); 736 memcpy(mtod(m, void *), bp, len); 737 bp += len; 738 739 totlen -= len; 740 if (totlen > 0) { 741 MGET(newm, M_DONTWAIT, MT_DATA); 742 if (newm == 0) 743 goto bad; 744 len = MLEN; 745 m = m->m_next = newm; 746 } 747 } 748 749 #ifdef INET 750 /* hardware checksum */ 751 csum_flags = 0; 752 if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 753 struct ether_header *eh; 754 struct ether_vlan_header *evh; 755 struct ip *ip; 756 struct udphdr *uh; 757 uint16_t *opts; 758 int32_t hlen, pktlen; 759 uint32_t csum_data; 760 761 eh = mtod(m0, struct ether_header *); 762 if (ntohs(eh->ether_type) == ETHERTYPE_IP) { 763 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN); 764 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN; 765 } else if (ntohs(eh->ether_type) == ETHERTYPE_VLAN) { 766 evh = (struct ether_vlan_header *)eh; 767 if (ntohs(evh->evl_proto != ETHERTYPE_IP)) 768 goto swcsum; 769 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN + 770 ETHER_VLAN_ENCAP_LEN); 771 pktlen = m0->m_pkthdr.len - 772 ETHER_HDR_LEN - ETHER_VLAN_ENCAP_LEN; 773 } else 774 goto swcsum; 775 776 /* IPv4 only */ 777 if (ip->ip_v != IPVERSION) 778 goto swcsum; 779 780 hlen = ip->ip_hl << 2; 781 if (hlen < sizeof(struct ip)) 782 goto swcsum; 783 784 /* 785 * bail if too short, has random trailing garbage, truncated, 786 * fragment, or has ethernet pad. 787 */ 788 if (ntohs(ip->ip_len) < hlen || 789 ntohs(ip->ip_len) != pktlen || 790 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 791 goto swcsum; 792 793 switch (ip->ip_p) { 794 case IPPROTO_TCP: 795 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0) 796 goto swcsum; 797 if (pktlen < (hlen + sizeof(struct tcphdr))) 798 goto swcsum; 799 csum_flags = 800 M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 801 break; 802 case IPPROTO_UDP: 803 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0) 804 goto swcsum; 805 if (pktlen < (hlen + sizeof(struct udphdr))) 806 goto swcsum; 807 uh = (struct udphdr *)((char *)ip + hlen); 808 /* no checksum */ 809 if (uh->uh_sum == 0) 810 goto swcsum; 811 csum_flags = 812 M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 813 break; 814 default: 815 goto swcsum; 816 } 817 818 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */ 819 csum_data = ~flags & HME_XD_RXCKSUM; 820 821 /* 822 * If data offset is different from RX cksum start offset, 823 * we have to deduct them. 824 */ 825 hlen = ((char *)ip + hlen) - 826 ((char *)eh + ETHER_HDR_LEN + sizeof(struct ip)); 827 if (hlen > 1) { 828 uint32_t optsum; 829 830 optsum = 0; 831 opts = (uint16_t *)((char *)eh + 832 ETHER_HDR_LEN + sizeof(struct ip)); 833 834 while (hlen > 1) { 835 optsum += ntohs(*opts++); 836 hlen -= 2; 837 } 838 while (optsum >> 16) 839 optsum = (optsum >> 16) + (optsum & 0xffff); 840 841 /* Deduct the ip opts sum from the hwsum. */ 842 csum_data += (uint16_t)~optsum; 843 844 while (csum_data >> 16) 845 csum_data = 846 (csum_data >> 16) + (csum_data & 0xffff); 847 } 848 m0->m_pkthdr.csum_data = csum_data; 849 } 850 swcsum: 851 m0->m_pkthdr.csum_flags = csum_flags; 852 #endif 853 854 return (m0); 855 856 bad: 857 m_freem(m0); 858 return (0); 859 } 860 861 /* 862 * Pass a packet to the higher levels. 863 */ 864 void 865 hme_read(struct hme_softc *sc, int ix, uint32_t flags) 866 { 867 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 868 struct mbuf *m; 869 int len; 870 871 len = HME_XD_DECODE_RSIZE(flags); 872 if (len <= sizeof(struct ether_header) || 873 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 874 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 875 ETHERMTU + sizeof(struct ether_header))) { 876 #ifdef HMEDEBUG 877 printf("%s: invalid packet size %d; dropping\n", 878 device_xname(sc->sc_dev), len); 879 #endif 880 ifp->if_ierrors++; 881 return; 882 } 883 884 /* Pull packet off interface. */ 885 m = hme_get(sc, ix, flags); 886 if (m == 0) { 887 ifp->if_ierrors++; 888 return; 889 } 890 891 ifp->if_ipackets++; 892 893 /* 894 * Check if there's a BPF listener on this interface. 895 * If so, hand off the raw packet to BPF. 896 */ 897 bpf_mtap(ifp, m); 898 899 /* Pass the packet up. */ 900 (*ifp->if_input)(ifp, m); 901 } 902 903 void 904 hme_start(struct ifnet *ifp) 905 { 906 struct hme_softc *sc = ifp->if_softc; 907 void *txd = sc->sc_rb.rb_txd; 908 struct mbuf *m; 909 unsigned int txflags; 910 unsigned int ri, len, obusy; 911 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 912 913 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 914 return; 915 916 ri = sc->sc_rb.rb_tdhead; 917 obusy = sc->sc_rb.rb_td_nbusy; 918 919 for (;;) { 920 IFQ_DEQUEUE(&ifp->if_snd, m); 921 if (m == 0) 922 break; 923 924 /* 925 * If BPF is listening on this interface, let it see the 926 * packet before we commit it to the wire. 927 */ 928 bpf_mtap(ifp, m); 929 930 #ifdef INET 931 /* collect bits for h/w csum, before hme_put frees the mbuf */ 932 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) && 933 m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 934 struct ether_header *eh; 935 uint16_t offset, start; 936 937 eh = mtod(m, struct ether_header *); 938 switch (ntohs(eh->ether_type)) { 939 case ETHERTYPE_IP: 940 start = ETHER_HDR_LEN; 941 break; 942 case ETHERTYPE_VLAN: 943 start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 944 break; 945 default: 946 /* unsupported, drop it */ 947 m_free(m); 948 continue; 949 } 950 start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 951 offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data) 952 + start; 953 txflags = HME_XD_TXCKSUM | 954 (offset << HME_XD_TXCSSTUFFSHIFT) | 955 (start << HME_XD_TXCSSTARTSHIFT); 956 } else 957 #endif 958 txflags = 0; 959 960 /* 961 * Copy the mbuf chain into the transmit buffer. 962 */ 963 len = hme_put(sc, ri, m); 964 965 /* 966 * Initialize transmit registers and start transmission 967 */ 968 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 969 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 970 HME_XD_ENCODE_TSIZE(len) | txflags); 971 972 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 973 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 974 HME_ETX_TP_DMAWAKEUP); 975 976 if (++ri == ntbuf) 977 ri = 0; 978 979 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 980 ifp->if_flags |= IFF_OACTIVE; 981 break; 982 } 983 } 984 985 if (obusy != sc->sc_rb.rb_td_nbusy) { 986 sc->sc_rb.rb_tdhead = ri; 987 ifp->if_timer = 5; 988 } 989 } 990 991 /* 992 * Transmit interrupt. 993 */ 994 int 995 hme_tint(struct hme_softc *sc) 996 { 997 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 998 bus_space_tag_t t = sc->sc_bustag; 999 bus_space_handle_t mac = sc->sc_mac; 1000 unsigned int ri, txflags; 1001 1002 /* 1003 * Unload collision counters 1004 */ 1005 ifp->if_collisions += 1006 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 1007 bus_space_read_4(t, mac, HME_MACI_FCCNT); 1008 ifp->if_oerrors += 1009 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 1010 bus_space_read_4(t, mac, HME_MACI_LTCNT); 1011 1012 /* 1013 * then clear the hardware counters. 1014 */ 1015 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 1016 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 1017 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 1018 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 1019 1020 /* Fetch current position in the transmit ring */ 1021 ri = sc->sc_rb.rb_tdtail; 1022 1023 for (;;) { 1024 if (sc->sc_rb.rb_td_nbusy <= 0) 1025 break; 1026 1027 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 1028 1029 if (txflags & HME_XD_OWN) 1030 break; 1031 1032 ifp->if_flags &= ~IFF_OACTIVE; 1033 ifp->if_opackets++; 1034 1035 if (++ri == sc->sc_rb.rb_ntbuf) 1036 ri = 0; 1037 1038 --sc->sc_rb.rb_td_nbusy; 1039 } 1040 1041 /* Update ring */ 1042 sc->sc_rb.rb_tdtail = ri; 1043 1044 hme_start(ifp); 1045 1046 if (sc->sc_rb.rb_td_nbusy == 0) 1047 ifp->if_timer = 0; 1048 1049 return (1); 1050 } 1051 1052 /* 1053 * Receive interrupt. 1054 */ 1055 int 1056 hme_rint(struct hme_softc *sc) 1057 { 1058 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1059 bus_space_tag_t t = sc->sc_bustag; 1060 bus_space_handle_t mac = sc->sc_mac; 1061 void *xdr = sc->sc_rb.rb_rxd; 1062 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 1063 unsigned int ri; 1064 uint32_t flags; 1065 1066 ri = sc->sc_rb.rb_rdtail; 1067 1068 /* 1069 * Process all buffers with valid data. 1070 */ 1071 for (;;) { 1072 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 1073 if (flags & HME_XD_OWN) 1074 break; 1075 1076 if (flags & HME_XD_OFL) { 1077 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 1078 device_xname(sc->sc_dev), ri, flags); 1079 } else 1080 hme_read(sc, ri, flags); 1081 1082 /* This buffer can be used by the hardware again */ 1083 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 1084 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 1085 1086 if (++ri == nrbuf) 1087 ri = 0; 1088 } 1089 1090 sc->sc_rb.rb_rdtail = ri; 1091 1092 /* Read error counters ... */ 1093 ifp->if_ierrors += 1094 bus_space_read_4(t, mac, HME_MACI_STAT_LCNT) + 1095 bus_space_read_4(t, mac, HME_MACI_STAT_ACNT) + 1096 bus_space_read_4(t, mac, HME_MACI_STAT_CCNT) + 1097 bus_space_read_4(t, mac, HME_MACI_STAT_CVCNT); 1098 1099 /* ... then clear the hardware counters. */ 1100 bus_space_write_4(t, mac, HME_MACI_STAT_LCNT, 0); 1101 bus_space_write_4(t, mac, HME_MACI_STAT_ACNT, 0); 1102 bus_space_write_4(t, mac, HME_MACI_STAT_CCNT, 0); 1103 bus_space_write_4(t, mac, HME_MACI_STAT_CVCNT, 0); 1104 return (1); 1105 } 1106 1107 int 1108 hme_eint(struct hme_softc *sc, u_int status) 1109 { 1110 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1111 char bits[128]; 1112 1113 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 1114 bus_space_tag_t t = sc->sc_bustag; 1115 bus_space_handle_t mif = sc->sc_mif; 1116 uint32_t cf, st, sm; 1117 cf = bus_space_read_4(t, mif, HME_MIFI_CFG); 1118 st = bus_space_read_4(t, mif, HME_MIFI_STAT); 1119 sm = bus_space_read_4(t, mif, HME_MIFI_SM); 1120 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n", 1121 device_xname(sc->sc_dev), cf, st, sm); 1122 return (1); 1123 } 1124 1125 /* Receive error counters rolled over */ 1126 if (status & HME_SEB_STAT_ACNTEXP) 1127 ifp->if_ierrors += 0xff; 1128 if (status & HME_SEB_STAT_CCNTEXP) 1129 ifp->if_ierrors += 0xff; 1130 if (status & HME_SEB_STAT_LCNTEXP) 1131 ifp->if_ierrors += 0xff; 1132 if (status & HME_SEB_STAT_CVCNTEXP) 1133 ifp->if_ierrors += 0xff; 1134 1135 /* RXTERR locks up the interface, so do a reset */ 1136 if (status & HME_SEB_STAT_RXTERR) 1137 hme_reset(sc); 1138 1139 snprintb(bits, sizeof(bits), HME_SEB_STAT_BITS, status); 1140 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1141 1142 return (1); 1143 } 1144 1145 int 1146 hme_intr(void *v) 1147 { 1148 struct hme_softc *sc = v; 1149 bus_space_tag_t t = sc->sc_bustag; 1150 bus_space_handle_t seb = sc->sc_seb; 1151 uint32_t status; 1152 int r = 0; 1153 1154 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 1155 1156 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 1157 r |= hme_eint(sc, status); 1158 1159 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 1160 r |= hme_tint(sc); 1161 1162 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1163 r |= hme_rint(sc); 1164 1165 #if NRND > 0 1166 rnd_add_uint32(&sc->rnd_source, status); 1167 #endif 1168 1169 return (r); 1170 } 1171 1172 1173 void 1174 hme_watchdog(struct ifnet *ifp) 1175 { 1176 struct hme_softc *sc = ifp->if_softc; 1177 1178 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1179 ++ifp->if_oerrors; 1180 1181 hme_reset(sc); 1182 } 1183 1184 /* 1185 * Initialize the MII Management Interface 1186 */ 1187 void 1188 hme_mifinit(struct hme_softc *sc) 1189 { 1190 bus_space_tag_t t = sc->sc_bustag; 1191 bus_space_handle_t mif = sc->sc_mif; 1192 bus_space_handle_t mac = sc->sc_mac; 1193 int instance, phy; 1194 uint32_t v; 1195 1196 if (sc->sc_mii.mii_media.ifm_cur != NULL) { 1197 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1198 phy = sc->sc_phys[instance]; 1199 } else 1200 /* No media set yet, pick phy arbitrarily.. */ 1201 phy = HME_PHYAD_EXTERNAL; 1202 1203 /* Configure the MIF in frame mode, no poll, current phy select */ 1204 v = 0; 1205 if (phy == HME_PHYAD_EXTERNAL) 1206 v |= HME_MIF_CFG_PHY; 1207 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1208 1209 /* If an external transceiver is selected, enable its MII drivers */ 1210 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1211 v &= ~HME_MAC_XIF_MIIENABLE; 1212 if (phy == HME_PHYAD_EXTERNAL) 1213 v |= HME_MAC_XIF_MIIENABLE; 1214 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1215 } 1216 1217 /* 1218 * MII interface 1219 */ 1220 static int 1221 hme_mii_readreg(device_t self, int phy, int reg) 1222 { 1223 struct hme_softc *sc = device_private(self); 1224 bus_space_tag_t t = sc->sc_bustag; 1225 bus_space_handle_t mif = sc->sc_mif; 1226 bus_space_handle_t mac = sc->sc_mac; 1227 uint32_t v, xif_cfg, mifi_cfg; 1228 int n; 1229 1230 /* We can at most have two PHYs */ 1231 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1232 return (0); 1233 1234 /* Select the desired PHY in the MIF configuration register */ 1235 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1236 v &= ~HME_MIF_CFG_PHY; 1237 if (phy == HME_PHYAD_EXTERNAL) 1238 v |= HME_MIF_CFG_PHY; 1239 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1240 1241 /* Enable MII drivers on external transceiver */ 1242 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1243 if (phy == HME_PHYAD_EXTERNAL) 1244 v |= HME_MAC_XIF_MIIENABLE; 1245 else 1246 v &= ~HME_MAC_XIF_MIIENABLE; 1247 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1248 1249 #if 0 1250 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1251 /* 1252 * Check whether a transceiver is connected by testing 1253 * the MIF configuration register's MDI_X bits. Note that 1254 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1255 */ 1256 mif_mdi_bit = 1 << (8 + (1 - phy)); 1257 delay(100); 1258 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1259 if ((v & mif_mdi_bit) == 0) 1260 return (0); 1261 #endif 1262 1263 /* Construct the frame command */ 1264 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1265 HME_MIF_FO_TAMSB | 1266 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1267 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1268 (reg << HME_MIF_FO_REGAD_SHIFT); 1269 1270 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1271 for (n = 0; n < 100; n++) { 1272 DELAY(1); 1273 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1274 if (v & HME_MIF_FO_TALSB) { 1275 v &= HME_MIF_FO_DATA; 1276 goto out; 1277 } 1278 } 1279 1280 v = 0; 1281 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1282 1283 out: 1284 /* Restore MIFI_CFG register */ 1285 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1286 /* Restore XIF register */ 1287 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1288 return (v); 1289 } 1290 1291 static void 1292 hme_mii_writereg(device_t self, int phy, int reg, int val) 1293 { 1294 struct hme_softc *sc = device_private(self); 1295 bus_space_tag_t t = sc->sc_bustag; 1296 bus_space_handle_t mif = sc->sc_mif; 1297 bus_space_handle_t mac = sc->sc_mac; 1298 uint32_t v, xif_cfg, mifi_cfg; 1299 int n; 1300 1301 /* We can at most have two PHYs */ 1302 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1303 return; 1304 1305 /* Select the desired PHY in the MIF configuration register */ 1306 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1307 v &= ~HME_MIF_CFG_PHY; 1308 if (phy == HME_PHYAD_EXTERNAL) 1309 v |= HME_MIF_CFG_PHY; 1310 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1311 1312 /* Enable MII drivers on external transceiver */ 1313 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1314 if (phy == HME_PHYAD_EXTERNAL) 1315 v |= HME_MAC_XIF_MIIENABLE; 1316 else 1317 v &= ~HME_MAC_XIF_MIIENABLE; 1318 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1319 1320 #if 0 1321 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1322 /* 1323 * Check whether a transceiver is connected by testing 1324 * the MIF configuration register's MDI_X bits. Note that 1325 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1326 */ 1327 mif_mdi_bit = 1 << (8 + (1 - phy)); 1328 delay(100); 1329 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1330 if ((v & mif_mdi_bit) == 0) 1331 return; 1332 #endif 1333 1334 /* Construct the frame command */ 1335 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1336 HME_MIF_FO_TAMSB | 1337 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1338 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1339 (reg << HME_MIF_FO_REGAD_SHIFT) | 1340 (val & HME_MIF_FO_DATA); 1341 1342 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1343 for (n = 0; n < 100; n++) { 1344 DELAY(1); 1345 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1346 if (v & HME_MIF_FO_TALSB) 1347 goto out; 1348 } 1349 1350 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1351 out: 1352 /* Restore MIFI_CFG register */ 1353 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1354 /* Restore XIF register */ 1355 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1356 } 1357 1358 static void 1359 hme_mii_statchg(device_t dev) 1360 { 1361 struct hme_softc *sc = device_private(dev); 1362 bus_space_tag_t t = sc->sc_bustag; 1363 bus_space_handle_t mac = sc->sc_mac; 1364 uint32_t v; 1365 1366 #ifdef HMEDEBUG 1367 if (sc->sc_debug) 1368 printf("hme_mii_statchg: status change\n"); 1369 #endif 1370 1371 /* Set the MAC Full Duplex bit appropriately */ 1372 /* Apparently the hme chip is SIMPLEX if working in full duplex mode, 1373 but not otherwise. */ 1374 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1375 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1376 v |= HME_MAC_TXCFG_FULLDPLX; 1377 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX; 1378 } else { 1379 v &= ~HME_MAC_TXCFG_FULLDPLX; 1380 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX; 1381 } 1382 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags; 1383 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1384 } 1385 1386 int 1387 hme_mediachange(struct ifnet *ifp) 1388 { 1389 struct hme_softc *sc = ifp->if_softc; 1390 bus_space_tag_t t = sc->sc_bustag; 1391 bus_space_handle_t mif = sc->sc_mif; 1392 bus_space_handle_t mac = sc->sc_mac; 1393 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1394 int phy = sc->sc_phys[instance]; 1395 int rc; 1396 uint32_t v; 1397 1398 #ifdef HMEDEBUG 1399 if (sc->sc_debug) 1400 printf("hme_mediachange: phy = %d\n", phy); 1401 #endif 1402 1403 /* Select the current PHY in the MIF configuration register */ 1404 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1405 v &= ~HME_MIF_CFG_PHY; 1406 if (phy == HME_PHYAD_EXTERNAL) 1407 v |= HME_MIF_CFG_PHY; 1408 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1409 1410 /* If an external transceiver is selected, enable its MII drivers */ 1411 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1412 v &= ~HME_MAC_XIF_MIIENABLE; 1413 if (phy == HME_PHYAD_EXTERNAL) 1414 v |= HME_MAC_XIF_MIIENABLE; 1415 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1416 1417 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 1418 return 0; 1419 return rc; 1420 } 1421 1422 /* 1423 * Process an ioctl request. 1424 */ 1425 int 1426 hme_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1427 { 1428 struct hme_softc *sc = ifp->if_softc; 1429 struct ifaddr *ifa = (struct ifaddr *)data; 1430 int s, error = 0; 1431 1432 s = splnet(); 1433 1434 switch (cmd) { 1435 1436 case SIOCINITIFADDR: 1437 switch (ifa->ifa_addr->sa_family) { 1438 #ifdef INET 1439 case AF_INET: 1440 if (ifp->if_flags & IFF_UP) 1441 hme_setladrf(sc); 1442 else { 1443 ifp->if_flags |= IFF_UP; 1444 error = hme_init(ifp); 1445 } 1446 arp_ifinit(ifp, ifa); 1447 break; 1448 #endif 1449 default: 1450 ifp->if_flags |= IFF_UP; 1451 error = hme_init(ifp); 1452 break; 1453 } 1454 break; 1455 1456 case SIOCSIFFLAGS: 1457 #ifdef HMEDEBUG 1458 { 1459 struct ifreq *ifr = data; 1460 sc->sc_debug = 1461 (ifr->ifr_flags & IFF_DEBUG) != 0 ? 1 : 0; 1462 } 1463 #endif 1464 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1465 break; 1466 1467 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1468 case IFF_RUNNING: 1469 /* 1470 * If interface is marked down and it is running, then 1471 * stop it. 1472 */ 1473 hme_stop(ifp, 0); 1474 ifp->if_flags &= ~IFF_RUNNING; 1475 break; 1476 case IFF_UP: 1477 /* 1478 * If interface is marked up and it is stopped, then 1479 * start it. 1480 */ 1481 error = hme_init(ifp); 1482 break; 1483 case IFF_UP|IFF_RUNNING: 1484 /* 1485 * If setting debug or promiscuous mode, do not reset 1486 * the chip; for everything else, call hme_init() 1487 * which will trigger a reset. 1488 */ 1489 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG) 1490 if (ifp->if_flags != sc->sc_if_flags) { 1491 if ((ifp->if_flags & (~RESETIGN)) 1492 == (sc->sc_if_flags & (~RESETIGN))) 1493 hme_setladrf(sc); 1494 else 1495 error = hme_init(ifp); 1496 } 1497 #undef RESETIGN 1498 break; 1499 case 0: 1500 break; 1501 } 1502 1503 if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable) 1504 error = hme_init(ifp); 1505 1506 break; 1507 1508 default: 1509 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1510 break; 1511 1512 error = 0; 1513 1514 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1515 ; 1516 else if (ifp->if_flags & IFF_RUNNING) { 1517 /* 1518 * Multicast list has changed; set the hardware filter 1519 * accordingly. 1520 */ 1521 hme_setladrf(sc); 1522 } 1523 break; 1524 } 1525 1526 sc->sc_if_flags = ifp->if_flags; 1527 splx(s); 1528 return (error); 1529 } 1530 1531 bool 1532 hme_shutdown(device_t self, int howto) 1533 { 1534 struct hme_softc *sc; 1535 struct ifnet *ifp; 1536 1537 sc = device_private(self); 1538 ifp = &sc->sc_ethercom.ec_if; 1539 hme_stop(ifp, 1); 1540 1541 return true; 1542 } 1543 1544 /* 1545 * Set up the logical address filter. 1546 */ 1547 void 1548 hme_setladrf(struct hme_softc *sc) 1549 { 1550 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1551 struct ether_multi *enm; 1552 struct ether_multistep step; 1553 struct ethercom *ec = &sc->sc_ethercom; 1554 bus_space_tag_t t = sc->sc_bustag; 1555 bus_space_handle_t mac = sc->sc_mac; 1556 uint32_t v; 1557 uint32_t crc; 1558 uint32_t hash[4]; 1559 1560 /* Clear hash table */ 1561 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1562 1563 /* Get current RX configuration */ 1564 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1565 1566 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1567 /* Turn on promiscuous mode; turn off the hash filter */ 1568 v |= HME_MAC_RXCFG_PMISC; 1569 v &= ~HME_MAC_RXCFG_HENABLE; 1570 ifp->if_flags |= IFF_ALLMULTI; 1571 goto chipit; 1572 } 1573 1574 /* Turn off promiscuous mode; turn on the hash filter */ 1575 v &= ~HME_MAC_RXCFG_PMISC; 1576 v |= HME_MAC_RXCFG_HENABLE; 1577 1578 /* 1579 * Set up multicast address filter by passing all multicast addresses 1580 * through a crc generator, and then using the high order 6 bits as an 1581 * index into the 64 bit logical address filter. The high order bit 1582 * selects the word, while the rest of the bits select the bit within 1583 * the word. 1584 */ 1585 1586 ETHER_FIRST_MULTI(step, ec, enm); 1587 while (enm != NULL) { 1588 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1589 /* 1590 * We must listen to a range of multicast addresses. 1591 * For now, just accept all multicasts, rather than 1592 * trying to set only those filter bits needed to match 1593 * the range. (At this time, the only use of address 1594 * ranges is for IP multicast routing, for which the 1595 * range is big enough to require all bits set.) 1596 */ 1597 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1598 ifp->if_flags |= IFF_ALLMULTI; 1599 goto chipit; 1600 } 1601 1602 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1603 1604 /* Just want the 6 most significant bits. */ 1605 crc >>= 26; 1606 1607 /* Set the corresponding bit in the filter. */ 1608 hash[crc >> 4] |= 1 << (crc & 0xf); 1609 1610 ETHER_NEXT_MULTI(step, enm); 1611 } 1612 1613 ifp->if_flags &= ~IFF_ALLMULTI; 1614 1615 chipit: 1616 /* Now load the hash table into the chip */ 1617 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1618 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1619 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1620 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1621 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1622 } 1623 1624 /* 1625 * Routines for accessing the transmit and receive buffers. 1626 * The various CPU and adapter configurations supported by this 1627 * driver require three different access methods for buffers 1628 * and descriptors: 1629 * (1) contig (contiguous data; no padding), 1630 * (2) gap2 (two bytes of data followed by two bytes of padding), 1631 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1632 */ 1633 1634 #if 0 1635 /* 1636 * contig: contiguous data with no padding. 1637 * 1638 * Buffers may have any alignment. 1639 */ 1640 1641 void 1642 hme_copytobuf_contig(struct hme_softc *sc, void *from, int ri, int len) 1643 { 1644 volatile void *buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1645 1646 /* 1647 * Just call memcpy() to do the work. 1648 */ 1649 memcpy(buf, from, len); 1650 } 1651 1652 void 1653 hme_copyfrombuf_contig(struct hme_softc *sc, void *to, int boff, int len) 1654 { 1655 volatile void *buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1656 1657 /* 1658 * Just call memcpy() to do the work. 1659 */ 1660 memcpy(to, buf, len); 1661 } 1662 #endif 1663