1 /* $NetBSD: hme.c,v 1.53 2005/12/24 23:41:33 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * HME Ethernet module driver. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.53 2005/12/24 23:41:33 perry Exp $"); 45 46 /* #define HMEDEBUG */ 47 48 #include "opt_inet.h" 49 #include "opt_ns.h" 50 #include "bpfilter.h" 51 #include "rnd.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/mbuf.h> 57 #include <sys/syslog.h> 58 #include <sys/socket.h> 59 #include <sys/device.h> 60 #include <sys/malloc.h> 61 #include <sys/ioctl.h> 62 #include <sys/errno.h> 63 #if NRND > 0 64 #include <sys/rnd.h> 65 #endif 66 67 #include <net/if.h> 68 #include <net/if_dl.h> 69 #include <net/if_ether.h> 70 #include <net/if_media.h> 71 72 #ifdef INET 73 #include <netinet/in.h> 74 #include <netinet/if_inarp.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/in_var.h> 77 #include <netinet/ip.h> 78 #include <netinet/tcp.h> 79 #include <netinet/udp.h> 80 #endif 81 82 #ifdef NS 83 #include <netns/ns.h> 84 #include <netns/ns_if.h> 85 #endif 86 87 #if NBPFILTER > 0 88 #include <net/bpf.h> 89 #include <net/bpfdesc.h> 90 #endif 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 95 #include <machine/bus.h> 96 97 #include <dev/ic/hmereg.h> 98 #include <dev/ic/hmevar.h> 99 100 void hme_start(struct ifnet *); 101 void hme_stop(struct hme_softc *); 102 int hme_ioctl(struct ifnet *, u_long, caddr_t); 103 void hme_tick(void *); 104 void hme_watchdog(struct ifnet *); 105 void hme_shutdown(void *); 106 void hme_init(struct hme_softc *); 107 void hme_meminit(struct hme_softc *); 108 void hme_mifinit(struct hme_softc *); 109 void hme_reset(struct hme_softc *); 110 void hme_setladrf(struct hme_softc *); 111 112 /* MII methods & callbacks */ 113 static int hme_mii_readreg(struct device *, int, int); 114 static void hme_mii_writereg(struct device *, int, int, int); 115 static void hme_mii_statchg(struct device *); 116 117 int hme_mediachange(struct ifnet *); 118 void hme_mediastatus(struct ifnet *, struct ifmediareq *); 119 120 struct mbuf *hme_get(struct hme_softc *, int, uint32_t); 121 int hme_put(struct hme_softc *, int, struct mbuf *); 122 void hme_read(struct hme_softc *, int, uint32_t); 123 int hme_eint(struct hme_softc *, u_int); 124 int hme_rint(struct hme_softc *); 125 int hme_tint(struct hme_softc *); 126 127 static int ether_cmp(u_char *, u_char *); 128 129 /* Default buffer copy routines */ 130 void hme_copytobuf_contig(struct hme_softc *, void *, int, int); 131 void hme_copyfrombuf_contig(struct hme_softc *, void *, int, int); 132 void hme_zerobuf_contig(struct hme_softc *, int, int); 133 134 135 void 136 hme_config(sc) 137 struct hme_softc *sc; 138 { 139 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 140 struct mii_data *mii = &sc->sc_mii; 141 struct mii_softc *child; 142 bus_dma_tag_t dmatag = sc->sc_dmatag; 143 bus_dma_segment_t seg; 144 bus_size_t size; 145 int rseg, error; 146 147 /* 148 * HME common initialization. 149 * 150 * hme_softc fields that must be initialized by the front-end: 151 * 152 * the bus tag: 153 * sc_bustag 154 * 155 * the DMA bus tag: 156 * sc_dmatag 157 * 158 * the bus handles: 159 * sc_seb (Shared Ethernet Block registers) 160 * sc_erx (Receiver Unit registers) 161 * sc_etx (Transmitter Unit registers) 162 * sc_mac (MAC registers) 163 * sc_mif (Management Interface registers) 164 * 165 * the maximum bus burst size: 166 * sc_burst 167 * 168 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 169 * rb_membase, rb_dmabase) 170 * 171 * the local Ethernet address: 172 * sc_enaddr 173 * 174 */ 175 176 /* Make sure the chip is stopped. */ 177 hme_stop(sc); 178 179 180 /* 181 * Allocate descriptors and buffers 182 * XXX - do all this differently.. and more configurably, 183 * eg. use things as `dma_load_mbuf()' on transmit, 184 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 185 * all the time) on the receiver side. 186 * 187 * Note: receive buffers must be 64-byte aligned. 188 * Also, apparently, the buffers must extend to a DMA burst 189 * boundary beyond the maximum packet size. 190 */ 191 #define _HME_NDESC 128 192 #define _HME_BUFSZ 1600 193 194 /* Note: the # of descriptors must be a multiple of 16 */ 195 sc->sc_rb.rb_ntbuf = _HME_NDESC; 196 sc->sc_rb.rb_nrbuf = _HME_NDESC; 197 198 /* 199 * Allocate DMA capable memory 200 * Buffer descriptors must be aligned on a 2048 byte boundary; 201 * take this into account when calculating the size. Note that 202 * the maximum number of descriptors (256) occupies 2048 bytes, 203 * so we allocate that much regardless of _HME_NDESC. 204 */ 205 size = 2048 + /* TX descriptors */ 206 2048 + /* RX descriptors */ 207 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 208 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* RX buffers */ 209 210 /* Allocate DMA buffer */ 211 if ((error = bus_dmamem_alloc(dmatag, size, 212 2048, 0, 213 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 214 printf("%s: DMA buffer alloc error %d\n", 215 sc->sc_dev.dv_xname, error); 216 return; 217 } 218 219 /* Map DMA memory in CPU addressable space */ 220 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 221 &sc->sc_rb.rb_membase, 222 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 223 printf("%s: DMA buffer map error %d\n", 224 sc->sc_dev.dv_xname, error); 225 bus_dmamap_unload(dmatag, sc->sc_dmamap); 226 bus_dmamem_free(dmatag, &seg, rseg); 227 return; 228 } 229 230 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 231 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 232 printf("%s: DMA map create error %d\n", 233 sc->sc_dev.dv_xname, error); 234 return; 235 } 236 237 /* Load the buffer */ 238 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 239 sc->sc_rb.rb_membase, size, NULL, 240 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 241 printf("%s: DMA buffer map load error %d\n", 242 sc->sc_dev.dv_xname, error); 243 bus_dmamem_free(dmatag, &seg, rseg); 244 return; 245 } 246 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 247 248 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 249 ether_sprintf(sc->sc_enaddr)); 250 251 /* Initialize ifnet structure. */ 252 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 253 ifp->if_softc = sc; 254 ifp->if_start = hme_start; 255 ifp->if_ioctl = hme_ioctl; 256 ifp->if_watchdog = hme_watchdog; 257 ifp->if_flags = 258 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 259 sc->sc_if_flags = ifp->if_flags; 260 ifp->if_capabilities |= 261 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 262 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 263 IFQ_SET_READY(&ifp->if_snd); 264 265 /* Initialize ifmedia structures and MII info */ 266 mii->mii_ifp = ifp; 267 mii->mii_readreg = hme_mii_readreg; 268 mii->mii_writereg = hme_mii_writereg; 269 mii->mii_statchg = hme_mii_statchg; 270 271 ifmedia_init(&mii->mii_media, 0, hme_mediachange, hme_mediastatus); 272 273 hme_mifinit(sc); 274 275 mii_attach(&sc->sc_dev, mii, 0xffffffff, 276 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 277 278 child = LIST_FIRST(&mii->mii_phys); 279 if (child == NULL) { 280 /* No PHY attached */ 281 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 282 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 283 } else { 284 /* 285 * Walk along the list of attached MII devices and 286 * establish an `MII instance' to `phy number' 287 * mapping. We'll use this mapping in media change 288 * requests to determine which phy to use to program 289 * the MIF configuration register. 290 */ 291 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 292 /* 293 * Note: we support just two PHYs: the built-in 294 * internal device and an external on the MII 295 * connector. 296 */ 297 if (child->mii_phy > 1 || child->mii_inst > 1) { 298 printf("%s: cannot accomodate MII device %s" 299 " at phy %d, instance %d\n", 300 sc->sc_dev.dv_xname, 301 child->mii_dev.dv_xname, 302 child->mii_phy, child->mii_inst); 303 continue; 304 } 305 306 sc->sc_phys[child->mii_inst] = child->mii_phy; 307 } 308 309 /* 310 * XXX - we can really do the following ONLY if the 311 * phy indeed has the auto negotiation capability!! 312 */ 313 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 314 } 315 316 /* claim 802.1q capability */ 317 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 318 319 /* Attach the interface. */ 320 if_attach(ifp); 321 ether_ifattach(ifp, sc->sc_enaddr); 322 323 sc->sc_sh = shutdownhook_establish(hme_shutdown, sc); 324 if (sc->sc_sh == NULL) 325 panic("hme_config: can't establish shutdownhook"); 326 327 #if NRND > 0 328 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 329 RND_TYPE_NET, 0); 330 #endif 331 332 callout_init(&sc->sc_tick_ch); 333 } 334 335 void 336 hme_tick(arg) 337 void *arg; 338 { 339 struct hme_softc *sc = arg; 340 int s; 341 342 s = splnet(); 343 mii_tick(&sc->sc_mii); 344 splx(s); 345 346 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 347 } 348 349 void 350 hme_reset(sc) 351 struct hme_softc *sc; 352 { 353 int s; 354 355 s = splnet(); 356 hme_init(sc); 357 splx(s); 358 } 359 360 void 361 hme_stop(sc) 362 struct hme_softc *sc; 363 { 364 bus_space_tag_t t = sc->sc_bustag; 365 bus_space_handle_t seb = sc->sc_seb; 366 int n; 367 368 callout_stop(&sc->sc_tick_ch); 369 mii_down(&sc->sc_mii); 370 371 /* Mask all interrupts */ 372 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff); 373 374 /* Reset transmitter and receiver */ 375 bus_space_write_4(t, seb, HME_SEBI_RESET, 376 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 377 378 for (n = 0; n < 20; n++) { 379 u_int32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 380 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 381 return; 382 DELAY(20); 383 } 384 385 printf("%s: hme_stop: reset failed\n", sc->sc_dev.dv_xname); 386 } 387 388 void 389 hme_meminit(sc) 390 struct hme_softc *sc; 391 { 392 bus_addr_t txbufdma, rxbufdma; 393 bus_addr_t dma; 394 caddr_t p; 395 unsigned int ntbuf, nrbuf, i; 396 struct hme_ring *hr = &sc->sc_rb; 397 398 p = hr->rb_membase; 399 dma = hr->rb_dmabase; 400 401 ntbuf = hr->rb_ntbuf; 402 nrbuf = hr->rb_nrbuf; 403 404 /* 405 * Allocate transmit descriptors 406 */ 407 hr->rb_txd = p; 408 hr->rb_txddma = dma; 409 p += ntbuf * HME_XD_SIZE; 410 dma += ntbuf * HME_XD_SIZE; 411 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 412 dma = (bus_addr_t)roundup((u_long)dma, 2048); 413 p = (caddr_t)roundup((u_long)p, 2048); 414 415 /* 416 * Allocate receive descriptors 417 */ 418 hr->rb_rxd = p; 419 hr->rb_rxddma = dma; 420 p += nrbuf * HME_XD_SIZE; 421 dma += nrbuf * HME_XD_SIZE; 422 /* Again move forward to the next 2048 byte boundary.*/ 423 dma = (bus_addr_t)roundup((u_long)dma, 2048); 424 p = (caddr_t)roundup((u_long)p, 2048); 425 426 427 /* 428 * Allocate transmit buffers 429 */ 430 hr->rb_txbuf = p; 431 txbufdma = dma; 432 p += ntbuf * _HME_BUFSZ; 433 dma += ntbuf * _HME_BUFSZ; 434 435 /* 436 * Allocate receive buffers 437 */ 438 hr->rb_rxbuf = p; 439 rxbufdma = dma; 440 p += nrbuf * _HME_BUFSZ; 441 dma += nrbuf * _HME_BUFSZ; 442 443 /* 444 * Initialize transmit buffer descriptors 445 */ 446 for (i = 0; i < ntbuf; i++) { 447 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 448 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 449 } 450 451 /* 452 * Initialize receive buffer descriptors 453 */ 454 for (i = 0; i < nrbuf; i++) { 455 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 456 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 457 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 458 } 459 460 hr->rb_tdhead = hr->rb_tdtail = 0; 461 hr->rb_td_nbusy = 0; 462 hr->rb_rdtail = 0; 463 } 464 465 /* 466 * Initialization of interface; set up initialization block 467 * and transmit/receive descriptor rings. 468 */ 469 void 470 hme_init(sc) 471 struct hme_softc *sc; 472 { 473 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 474 bus_space_tag_t t = sc->sc_bustag; 475 bus_space_handle_t seb = sc->sc_seb; 476 bus_space_handle_t etx = sc->sc_etx; 477 bus_space_handle_t erx = sc->sc_erx; 478 bus_space_handle_t mac = sc->sc_mac; 479 u_int8_t *ea; 480 u_int32_t v; 481 482 /* 483 * Initialization sequence. The numbered steps below correspond 484 * to the sequence outlined in section 6.3.5.1 in the Ethernet 485 * Channel Engine manual (part of the PCIO manual). 486 * See also the STP2002-STQ document from Sun Microsystems. 487 */ 488 489 /* step 1 & 2. Reset the Ethernet Channel */ 490 hme_stop(sc); 491 492 /* Re-initialize the MIF */ 493 hme_mifinit(sc); 494 495 /* Call MI reset function if any */ 496 if (sc->sc_hwreset) 497 (*sc->sc_hwreset)(sc); 498 499 #if 0 500 /* Mask all MIF interrupts, just in case */ 501 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 502 #endif 503 504 /* step 3. Setup data structures in host memory */ 505 hme_meminit(sc); 506 507 /* step 4. TX MAC registers & counters */ 508 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 509 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 510 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 511 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 512 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 513 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 514 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 515 sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable; 516 517 /* Load station MAC address */ 518 ea = sc->sc_enaddr; 519 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 520 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 521 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 522 523 /* 524 * Init seed for backoff 525 * (source suggested by manual: low 10 bits of MAC address) 526 */ 527 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 528 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 529 530 531 /* Note: Accepting power-on default for other MAC registers here.. */ 532 533 534 /* step 5. RX MAC registers & counters */ 535 hme_setladrf(sc); 536 537 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 538 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 539 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 540 541 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 542 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 543 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 544 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 545 546 /* step 8. Global Configuration & Interrupt Mask */ 547 bus_space_write_4(t, seb, HME_SEBI_IMASK, 548 ~( 549 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 550 HME_SEB_STAT_HOSTTOTX | 551 HME_SEB_STAT_RXTOHOST | 552 HME_SEB_STAT_TXALL | 553 HME_SEB_STAT_TXPERR | 554 HME_SEB_STAT_RCNTEXP | 555 /*HME_SEB_STAT_MIFIRQ |*/ 556 HME_SEB_STAT_ALL_ERRORS )); 557 558 switch (sc->sc_burst) { 559 default: 560 v = 0; 561 break; 562 case 16: 563 v = HME_SEB_CFG_BURST16; 564 break; 565 case 32: 566 v = HME_SEB_CFG_BURST32; 567 break; 568 case 64: 569 v = HME_SEB_CFG_BURST64; 570 break; 571 } 572 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 573 574 /* step 9. ETX Configuration: use mostly default values */ 575 576 /* Enable DMA */ 577 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 578 v |= HME_ETX_CFG_DMAENABLE; 579 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 580 581 /* Transmit Descriptor ring size: in increments of 16 */ 582 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 583 584 585 /* step 10. ERX Configuration */ 586 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 587 588 /* Encode Receive Descriptor ring size: four possible values */ 589 switch (_HME_NDESC /*XXX*/) { 590 case 32: 591 v |= HME_ERX_CFG_RINGSIZE32; 592 break; 593 case 64: 594 v |= HME_ERX_CFG_RINGSIZE64; 595 break; 596 case 128: 597 v |= HME_ERX_CFG_RINGSIZE128; 598 break; 599 case 256: 600 v |= HME_ERX_CFG_RINGSIZE256; 601 break; 602 default: 603 printf("hme: invalid Receive Descriptor ring size\n"); 604 break; 605 } 606 607 /* Enable DMA */ 608 v |= HME_ERX_CFG_DMAENABLE; 609 610 /* set h/w rx checksum start offset (# of half-words) */ 611 #ifdef INET 612 v |= (((ETHER_HDR_LEN + sizeof(struct ip) + 613 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 614 ETHER_VLAN_ENCAP_LEN : 0)) / 2) << HME_ERX_CFG_CSUMSHIFT) & 615 HME_ERX_CFG_CSUMSTART; 616 #endif 617 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 618 619 /* step 11. XIF Configuration */ 620 v = bus_space_read_4(t, mac, HME_MACI_XIF); 621 v |= HME_MAC_XIF_OE; 622 bus_space_write_4(t, mac, HME_MACI_XIF, v); 623 624 /* step 12. RX_MAC Configuration Register */ 625 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 626 v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP; 627 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 628 629 /* step 13. TX_MAC Configuration Register */ 630 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 631 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 632 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 633 634 /* step 14. Issue Transmit Pending command */ 635 636 /* Call MI initialization function if any */ 637 if (sc->sc_hwinit) 638 (*sc->sc_hwinit)(sc); 639 640 /* Set the current media. */ 641 mii_mediachg(&sc->sc_mii); 642 643 /* Start the one second timer. */ 644 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 645 646 ifp->if_flags |= IFF_RUNNING; 647 ifp->if_flags &= ~IFF_OACTIVE; 648 sc->sc_if_flags = ifp->if_flags; 649 ifp->if_timer = 0; 650 hme_start(ifp); 651 } 652 653 /* 654 * Compare two Ether/802 addresses for equality, inlined and unrolled for 655 * speed. 656 */ 657 static inline int 658 ether_cmp(a, b) 659 u_char *a, *b; 660 { 661 662 if (a[5] != b[5] || a[4] != b[4] || a[3] != b[3] || 663 a[2] != b[2] || a[1] != b[1] || a[0] != b[0]) 664 return (0); 665 return (1); 666 } 667 668 669 /* 670 * Routine to copy from mbuf chain to transmit buffer in 671 * network buffer memory. 672 * Returns the amount of data copied. 673 */ 674 int 675 hme_put(sc, ri, m) 676 struct hme_softc *sc; 677 int ri; /* Ring index */ 678 struct mbuf *m; 679 { 680 struct mbuf *n; 681 int len, tlen = 0; 682 caddr_t bp; 683 684 bp = sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 685 for (; m; m = n) { 686 len = m->m_len; 687 if (len == 0) { 688 MFREE(m, n); 689 continue; 690 } 691 memcpy(bp, mtod(m, caddr_t), len); 692 bp += len; 693 tlen += len; 694 MFREE(m, n); 695 } 696 return (tlen); 697 } 698 699 /* 700 * Pull data off an interface. 701 * Len is length of data, with local net header stripped. 702 * We copy the data into mbufs. When full cluster sized units are present 703 * we copy into clusters. 704 */ 705 struct mbuf * 706 hme_get(sc, ri, flags) 707 struct hme_softc *sc; 708 int ri; 709 u_int32_t flags; 710 { 711 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 712 struct mbuf *m, *m0, *newm; 713 caddr_t bp; 714 int len, totlen; 715 716 totlen = HME_XD_DECODE_RSIZE(flags); 717 MGETHDR(m0, M_DONTWAIT, MT_DATA); 718 if (m0 == 0) 719 return (0); 720 m0->m_pkthdr.rcvif = ifp; 721 m0->m_pkthdr.len = totlen; 722 len = MHLEN; 723 m = m0; 724 725 bp = sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 726 727 while (totlen > 0) { 728 if (totlen >= MINCLSIZE) { 729 MCLGET(m, M_DONTWAIT); 730 if ((m->m_flags & M_EXT) == 0) 731 goto bad; 732 len = MCLBYTES; 733 } 734 735 if (m == m0) { 736 caddr_t newdata = (caddr_t) 737 ALIGN(m->m_data + sizeof(struct ether_header)) - 738 sizeof(struct ether_header); 739 len -= newdata - m->m_data; 740 m->m_data = newdata; 741 } 742 743 m->m_len = len = min(totlen, len); 744 memcpy(mtod(m, caddr_t), bp, len); 745 bp += len; 746 747 totlen -= len; 748 if (totlen > 0) { 749 MGET(newm, M_DONTWAIT, MT_DATA); 750 if (newm == 0) 751 goto bad; 752 len = MLEN; 753 m = m->m_next = newm; 754 } 755 } 756 757 #ifdef INET 758 /* hardware checksum */ 759 if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 760 struct ether_header *eh; 761 struct ip *ip; 762 struct udphdr *uh; 763 uint16_t *opts; 764 int32_t hlen, pktlen; 765 uint32_t temp; 766 767 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 768 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN - 769 ETHER_VLAN_ENCAP_LEN; 770 eh = (struct ether_header *) mtod(m0, caddr_t) + 771 ETHER_VLAN_ENCAP_LEN; 772 } else { 773 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN; 774 eh = mtod(m0, struct ether_header *); 775 } 776 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 777 goto swcsum; 778 ip = (struct ip *) ((caddr_t) eh + ETHER_HDR_LEN); 779 780 /* IPv4 only */ 781 if (ip->ip_v != IPVERSION) 782 goto swcsum; 783 784 hlen = ip->ip_hl << 2; 785 if (hlen < sizeof(struct ip)) 786 goto swcsum; 787 788 /* 789 * bail if too short, has random trailing garbage, truncated, 790 * fragment, or has ethernet pad. 791 */ 792 if ((ntohs(ip->ip_len) < hlen) || (ntohs(ip->ip_len) != pktlen) 793 || (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 794 goto swcsum; 795 796 switch (ip->ip_p) { 797 case IPPROTO_TCP: 798 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 799 goto swcsum; 800 if (pktlen < (hlen + sizeof(struct tcphdr))) 801 goto swcsum; 802 m0->m_pkthdr.csum_flags = M_CSUM_TCPv4; 803 break; 804 case IPPROTO_UDP: 805 if (! (ifp->if_csum_flags_rx & M_CSUM_UDPv4)) 806 goto swcsum; 807 if (pktlen < (hlen + sizeof(struct udphdr))) 808 goto swcsum; 809 uh = (struct udphdr *)((caddr_t)ip + hlen); 810 /* no checksum */ 811 if (uh->uh_sum == 0) 812 goto swcsum; 813 m0->m_pkthdr.csum_flags = M_CSUM_UDPv4; 814 break; 815 default: 816 goto swcsum; 817 } 818 819 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */ 820 m0->m_pkthdr.csum_data = (~flags) & HME_XD_RXCKSUM; 821 822 /* if the pkt had ip options, we have to deduct them */ 823 if (hlen > sizeof(struct ip)) { 824 uint32_t optsum; 825 826 optsum = 0; 827 temp = hlen - sizeof(struct ip); 828 opts = (uint16_t *) ((caddr_t) ip + sizeof(struct ip)); 829 830 while (temp > 1) { 831 optsum += ntohs(*opts++); 832 temp -= 2; 833 } 834 while (optsum >> 16) 835 optsum = (optsum >> 16) + (optsum & 0xffff); 836 837 /* Deduct the ip opts sum from the hwsum (rfc 1624). */ 838 m0->m_pkthdr.csum_data = ~((~m0->m_pkthdr.csum_data) - 839 ~optsum); 840 841 while (m0->m_pkthdr.csum_data >> 16) 842 m0->m_pkthdr.csum_data = 843 (m0->m_pkthdr.csum_data >> 16) + 844 (m0->m_pkthdr.csum_data & 0xffff); 845 } 846 847 m0->m_pkthdr.csum_flags |= M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 848 } 849 swcsum: 850 m0->m_pkthdr.csum_flags = 0; 851 #endif 852 853 return (m0); 854 855 bad: 856 m_freem(m0); 857 return (0); 858 } 859 860 /* 861 * Pass a packet to the higher levels. 862 */ 863 void 864 hme_read(sc, ix, flags) 865 struct hme_softc *sc; 866 int ix; 867 u_int32_t flags; 868 { 869 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 870 struct mbuf *m; 871 int len; 872 873 len = HME_XD_DECODE_RSIZE(flags); 874 if (len <= sizeof(struct ether_header) || 875 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 876 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 877 ETHERMTU + sizeof(struct ether_header))) { 878 #ifdef HMEDEBUG 879 printf("%s: invalid packet size %d; dropping\n", 880 sc->sc_dev.dv_xname, len); 881 #endif 882 ifp->if_ierrors++; 883 return; 884 } 885 886 /* Pull packet off interface. */ 887 m = hme_get(sc, ix, flags); 888 if (m == 0) { 889 ifp->if_ierrors++; 890 return; 891 } 892 893 ifp->if_ipackets++; 894 895 #if NBPFILTER > 0 896 /* 897 * Check if there's a BPF listener on this interface. 898 * If so, hand off the raw packet to BPF. 899 */ 900 if (ifp->if_bpf) 901 bpf_mtap(ifp->if_bpf, m); 902 #endif 903 904 /* Pass the packet up. */ 905 (*ifp->if_input)(ifp, m); 906 } 907 908 void 909 hme_start(ifp) 910 struct ifnet *ifp; 911 { 912 struct hme_softc *sc = (struct hme_softc *)ifp->if_softc; 913 caddr_t txd = sc->sc_rb.rb_txd; 914 struct mbuf *m; 915 unsigned int txflags; 916 unsigned int ri, len; 917 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 918 919 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 920 return; 921 922 ri = sc->sc_rb.rb_tdhead; 923 924 for (;;) { 925 IFQ_DEQUEUE(&ifp->if_snd, m); 926 if (m == 0) 927 break; 928 929 #if NBPFILTER > 0 930 /* 931 * If BPF is listening on this interface, let it see the 932 * packet before we commit it to the wire. 933 */ 934 if (ifp->if_bpf) 935 bpf_mtap(ifp->if_bpf, m); 936 #endif 937 938 #ifdef INET 939 /* collect bits for h/w csum, before hme_put frees the mbuf */ 940 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) && 941 m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 942 struct ether_header *eh; 943 uint16_t offset, start; 944 945 eh = mtod(m, struct ether_header *); 946 switch (ntohs(eh->ether_type)) { 947 case ETHERTYPE_IP: 948 start = ETHER_HDR_LEN; 949 break; 950 case ETHERTYPE_VLAN: 951 start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 952 break; 953 default: 954 /* unsupported, drop it */ 955 m_free(m); 956 continue; 957 } 958 start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 959 offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data) 960 + start; 961 txflags = HME_XD_TXCKSUM | 962 (offset << HME_XD_TXCSSTUFFSHIFT) | 963 (start << HME_XD_TXCSSTARTSHIFT); 964 } else 965 #endif 966 txflags = 0; 967 968 /* 969 * Copy the mbuf chain into the transmit buffer. 970 */ 971 len = hme_put(sc, ri, m); 972 973 /* 974 * Initialize transmit registers and start transmission 975 */ 976 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 977 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 978 HME_XD_ENCODE_TSIZE(len) | txflags); 979 980 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 981 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 982 HME_ETX_TP_DMAWAKEUP); 983 984 if (++ri == ntbuf) 985 ri = 0; 986 987 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 988 ifp->if_flags |= IFF_OACTIVE; 989 break; 990 } 991 } 992 993 sc->sc_rb.rb_tdhead = ri; 994 } 995 996 /* 997 * Transmit interrupt. 998 */ 999 int 1000 hme_tint(sc) 1001 struct hme_softc *sc; 1002 { 1003 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1004 bus_space_tag_t t = sc->sc_bustag; 1005 bus_space_handle_t mac = sc->sc_mac; 1006 unsigned int ri, txflags; 1007 1008 /* 1009 * Unload collision counters 1010 */ 1011 ifp->if_collisions += 1012 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 1013 bus_space_read_4(t, mac, HME_MACI_FCCNT) + 1014 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 1015 bus_space_read_4(t, mac, HME_MACI_LTCNT); 1016 1017 /* 1018 * then clear the hardware counters. 1019 */ 1020 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 1021 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 1022 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 1023 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 1024 1025 /* Fetch current position in the transmit ring */ 1026 ri = sc->sc_rb.rb_tdtail; 1027 1028 for (;;) { 1029 if (sc->sc_rb.rb_td_nbusy <= 0) 1030 break; 1031 1032 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 1033 1034 if (txflags & HME_XD_OWN) 1035 break; 1036 1037 ifp->if_flags &= ~IFF_OACTIVE; 1038 ifp->if_opackets++; 1039 1040 if (++ri == sc->sc_rb.rb_ntbuf) 1041 ri = 0; 1042 1043 --sc->sc_rb.rb_td_nbusy; 1044 } 1045 1046 /* Update ring */ 1047 sc->sc_rb.rb_tdtail = ri; 1048 1049 hme_start(ifp); 1050 1051 if (sc->sc_rb.rb_td_nbusy == 0) 1052 ifp->if_timer = 0; 1053 1054 return (1); 1055 } 1056 1057 /* 1058 * Receive interrupt. 1059 */ 1060 int 1061 hme_rint(sc) 1062 struct hme_softc *sc; 1063 { 1064 caddr_t xdr = sc->sc_rb.rb_rxd; 1065 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 1066 unsigned int ri; 1067 u_int32_t flags; 1068 1069 ri = sc->sc_rb.rb_rdtail; 1070 1071 /* 1072 * Process all buffers with valid data. 1073 */ 1074 for (;;) { 1075 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 1076 if (flags & HME_XD_OWN) 1077 break; 1078 1079 if (flags & HME_XD_OFL) { 1080 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 1081 sc->sc_dev.dv_xname, ri, flags); 1082 } else 1083 hme_read(sc, ri, flags); 1084 1085 /* This buffer can be used by the hardware again */ 1086 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 1087 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 1088 1089 if (++ri == nrbuf) 1090 ri = 0; 1091 } 1092 1093 sc->sc_rb.rb_rdtail = ri; 1094 1095 return (1); 1096 } 1097 1098 int 1099 hme_eint(sc, status) 1100 struct hme_softc *sc; 1101 u_int status; 1102 { 1103 char bits[128]; 1104 1105 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 1106 bus_space_tag_t t = sc->sc_bustag; 1107 bus_space_handle_t mif = sc->sc_mif; 1108 u_int32_t cf, st, sm; 1109 cf = bus_space_read_4(t, mif, HME_MIFI_CFG); 1110 st = bus_space_read_4(t, mif, HME_MIFI_STAT); 1111 sm = bus_space_read_4(t, mif, HME_MIFI_SM); 1112 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n", 1113 sc->sc_dev.dv_xname, cf, st, sm); 1114 return (1); 1115 } 1116 1117 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1118 bitmask_snprintf(status, HME_SEB_STAT_BITS, bits,sizeof(bits))); 1119 return (1); 1120 } 1121 1122 int 1123 hme_intr(v) 1124 void *v; 1125 { 1126 struct hme_softc *sc = (struct hme_softc *)v; 1127 bus_space_tag_t t = sc->sc_bustag; 1128 bus_space_handle_t seb = sc->sc_seb; 1129 u_int32_t status; 1130 int r = 0; 1131 1132 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 1133 1134 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 1135 r |= hme_eint(sc, status); 1136 1137 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 1138 r |= hme_tint(sc); 1139 1140 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1141 r |= hme_rint(sc); 1142 1143 #if NRND > 0 1144 rnd_add_uint32(&sc->rnd_source, status); 1145 #endif 1146 1147 return (r); 1148 } 1149 1150 1151 void 1152 hme_watchdog(ifp) 1153 struct ifnet *ifp; 1154 { 1155 struct hme_softc *sc = ifp->if_softc; 1156 1157 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1158 ++ifp->if_oerrors; 1159 1160 hme_reset(sc); 1161 } 1162 1163 /* 1164 * Initialize the MII Management Interface 1165 */ 1166 void 1167 hme_mifinit(sc) 1168 struct hme_softc *sc; 1169 { 1170 bus_space_tag_t t = sc->sc_bustag; 1171 bus_space_handle_t mif = sc->sc_mif; 1172 bus_space_handle_t mac = sc->sc_mac; 1173 int instance, phy; 1174 u_int32_t v; 1175 1176 if (sc->sc_media.ifm_cur != NULL) { 1177 instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1178 phy = sc->sc_phys[instance]; 1179 } else 1180 /* No media set yet, pick phy arbitrarily.. */ 1181 phy = HME_PHYAD_EXTERNAL; 1182 1183 /* Configure the MIF in frame mode, no poll, current phy select */ 1184 v = 0; 1185 if (phy == HME_PHYAD_EXTERNAL) 1186 v |= HME_MIF_CFG_PHY; 1187 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1188 1189 /* If an external transceiver is selected, enable its MII drivers */ 1190 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1191 v &= ~HME_MAC_XIF_MIIENABLE; 1192 if (phy == HME_PHYAD_EXTERNAL) 1193 v |= HME_MAC_XIF_MIIENABLE; 1194 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1195 } 1196 1197 /* 1198 * MII interface 1199 */ 1200 static int 1201 hme_mii_readreg(self, phy, reg) 1202 struct device *self; 1203 int phy, reg; 1204 { 1205 struct hme_softc *sc = (void *)self; 1206 bus_space_tag_t t = sc->sc_bustag; 1207 bus_space_handle_t mif = sc->sc_mif; 1208 bus_space_handle_t mac = sc->sc_mac; 1209 u_int32_t v, xif_cfg, mifi_cfg; 1210 int n; 1211 1212 /* We can at most have two PHYs */ 1213 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1214 return (0); 1215 1216 /* Select the desired PHY in the MIF configuration register */ 1217 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1218 v &= ~HME_MIF_CFG_PHY; 1219 if (phy == HME_PHYAD_EXTERNAL) 1220 v |= HME_MIF_CFG_PHY; 1221 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1222 1223 /* Enable MII drivers on external transceiver */ 1224 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1225 if (phy == HME_PHYAD_EXTERNAL) 1226 v |= HME_MAC_XIF_MIIENABLE; 1227 else 1228 v &= ~HME_MAC_XIF_MIIENABLE; 1229 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1230 1231 #if 0 1232 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1233 /* 1234 * Check whether a transceiver is connected by testing 1235 * the MIF configuration register's MDI_X bits. Note that 1236 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1237 */ 1238 mif_mdi_bit = 1 << (8 + (1 - phy)); 1239 delay(100); 1240 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1241 if ((v & mif_mdi_bit) == 0) 1242 return (0); 1243 #endif 1244 1245 /* Construct the frame command */ 1246 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1247 HME_MIF_FO_TAMSB | 1248 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1249 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1250 (reg << HME_MIF_FO_REGAD_SHIFT); 1251 1252 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1253 for (n = 0; n < 100; n++) { 1254 DELAY(1); 1255 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1256 if (v & HME_MIF_FO_TALSB) { 1257 v &= HME_MIF_FO_DATA; 1258 goto out; 1259 } 1260 } 1261 1262 v = 0; 1263 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1264 1265 out: 1266 /* Restore MIFI_CFG register */ 1267 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1268 /* Restore XIF register */ 1269 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1270 return (v); 1271 } 1272 1273 static void 1274 hme_mii_writereg(self, phy, reg, val) 1275 struct device *self; 1276 int phy, reg, val; 1277 { 1278 struct hme_softc *sc = (void *)self; 1279 bus_space_tag_t t = sc->sc_bustag; 1280 bus_space_handle_t mif = sc->sc_mif; 1281 bus_space_handle_t mac = sc->sc_mac; 1282 u_int32_t v, xif_cfg, mifi_cfg; 1283 int n; 1284 1285 /* We can at most have two PHYs */ 1286 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1287 return; 1288 1289 /* Select the desired PHY in the MIF configuration register */ 1290 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1291 v &= ~HME_MIF_CFG_PHY; 1292 if (phy == HME_PHYAD_EXTERNAL) 1293 v |= HME_MIF_CFG_PHY; 1294 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1295 1296 /* Enable MII drivers on external transceiver */ 1297 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1298 if (phy == HME_PHYAD_EXTERNAL) 1299 v |= HME_MAC_XIF_MIIENABLE; 1300 else 1301 v &= ~HME_MAC_XIF_MIIENABLE; 1302 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1303 1304 #if 0 1305 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1306 /* 1307 * Check whether a transceiver is connected by testing 1308 * the MIF configuration register's MDI_X bits. Note that 1309 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1310 */ 1311 mif_mdi_bit = 1 << (8 + (1 - phy)); 1312 delay(100); 1313 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1314 if ((v & mif_mdi_bit) == 0) 1315 return; 1316 #endif 1317 1318 /* Construct the frame command */ 1319 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1320 HME_MIF_FO_TAMSB | 1321 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1322 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1323 (reg << HME_MIF_FO_REGAD_SHIFT) | 1324 (val & HME_MIF_FO_DATA); 1325 1326 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1327 for (n = 0; n < 100; n++) { 1328 DELAY(1); 1329 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1330 if (v & HME_MIF_FO_TALSB) 1331 goto out; 1332 } 1333 1334 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1335 out: 1336 /* Restore MIFI_CFG register */ 1337 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1338 /* Restore XIF register */ 1339 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1340 } 1341 1342 static void 1343 hme_mii_statchg(dev) 1344 struct device *dev; 1345 { 1346 struct hme_softc *sc = (void *)dev; 1347 bus_space_tag_t t = sc->sc_bustag; 1348 bus_space_handle_t mac = sc->sc_mac; 1349 u_int32_t v; 1350 1351 #ifdef HMEDEBUG 1352 if (sc->sc_debug) 1353 printf("hme_mii_statchg: status change\n"); 1354 #endif 1355 1356 /* Set the MAC Full Duplex bit appropriately */ 1357 /* Apparently the hme chip is SIMPLEX if working in full duplex mode, 1358 but not otherwise. */ 1359 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1360 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1361 v |= HME_MAC_TXCFG_FULLDPLX; 1362 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX; 1363 } else { 1364 v &= ~HME_MAC_TXCFG_FULLDPLX; 1365 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX; 1366 } 1367 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags; 1368 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1369 } 1370 1371 int 1372 hme_mediachange(ifp) 1373 struct ifnet *ifp; 1374 { 1375 struct hme_softc *sc = ifp->if_softc; 1376 bus_space_tag_t t = sc->sc_bustag; 1377 bus_space_handle_t mif = sc->sc_mif; 1378 bus_space_handle_t mac = sc->sc_mac; 1379 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1380 int phy = sc->sc_phys[instance]; 1381 u_int32_t v; 1382 1383 #ifdef HMEDEBUG 1384 if (sc->sc_debug) 1385 printf("hme_mediachange: phy = %d\n", phy); 1386 #endif 1387 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1388 return (EINVAL); 1389 1390 /* Select the current PHY in the MIF configuration register */ 1391 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1392 v &= ~HME_MIF_CFG_PHY; 1393 if (phy == HME_PHYAD_EXTERNAL) 1394 v |= HME_MIF_CFG_PHY; 1395 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1396 1397 /* If an external transceiver is selected, enable its MII drivers */ 1398 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1399 v &= ~HME_MAC_XIF_MIIENABLE; 1400 if (phy == HME_PHYAD_EXTERNAL) 1401 v |= HME_MAC_XIF_MIIENABLE; 1402 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1403 1404 return (mii_mediachg(&sc->sc_mii)); 1405 } 1406 1407 void 1408 hme_mediastatus(ifp, ifmr) 1409 struct ifnet *ifp; 1410 struct ifmediareq *ifmr; 1411 { 1412 struct hme_softc *sc = ifp->if_softc; 1413 1414 if ((ifp->if_flags & IFF_UP) == 0) 1415 return; 1416 1417 mii_pollstat(&sc->sc_mii); 1418 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1419 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1420 } 1421 1422 /* 1423 * Process an ioctl request. 1424 */ 1425 int 1426 hme_ioctl(ifp, cmd, data) 1427 struct ifnet *ifp; 1428 u_long cmd; 1429 caddr_t data; 1430 { 1431 struct hme_softc *sc = ifp->if_softc; 1432 struct ifaddr *ifa = (struct ifaddr *)data; 1433 struct ifreq *ifr = (struct ifreq *)data; 1434 int s, error = 0; 1435 1436 s = splnet(); 1437 1438 switch (cmd) { 1439 1440 case SIOCSIFADDR: 1441 switch (ifa->ifa_addr->sa_family) { 1442 #ifdef INET 1443 case AF_INET: 1444 if (ifp->if_flags & IFF_UP) 1445 hme_setladrf(sc); 1446 else { 1447 ifp->if_flags |= IFF_UP; 1448 hme_init(sc); 1449 } 1450 arp_ifinit(ifp, ifa); 1451 break; 1452 #endif 1453 #ifdef NS 1454 case AF_NS: 1455 { 1456 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1457 1458 if (ns_nullhost(*ina)) 1459 ina->x_host = 1460 *(union ns_host *)LLADDR(ifp->if_sadl); 1461 else { 1462 memcpy(LLADDR(ifp->if_sadl), 1463 ina->x_host.c_host, sizeof(sc->sc_enaddr)); 1464 } 1465 /* Set new address. */ 1466 if (ifp->if_flags & IFF_UP) 1467 hme_setladrf(sc); 1468 else { 1469 ifp->if_flags |= IFF_UP; 1470 hme_init(sc); 1471 } 1472 break; 1473 } 1474 #endif 1475 default: 1476 ifp->if_flags |= IFF_UP; 1477 hme_init(sc); 1478 break; 1479 } 1480 break; 1481 1482 case SIOCSIFFLAGS: 1483 #ifdef HMEDEBUG 1484 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1485 #endif 1486 1487 if ((ifp->if_flags & IFF_UP) == 0 && 1488 (ifp->if_flags & IFF_RUNNING) != 0) { 1489 /* 1490 * If interface is marked down and it is running, then 1491 * stop it. 1492 */ 1493 hme_stop(sc); 1494 ifp->if_flags &= ~IFF_RUNNING; 1495 } else if ((ifp->if_flags & IFF_UP) != 0 && 1496 (ifp->if_flags & IFF_RUNNING) == 0) { 1497 /* 1498 * If interface is marked up and it is stopped, then 1499 * start it. 1500 */ 1501 hme_init(sc); 1502 } else if ((ifp->if_flags & IFF_UP) != 0) { 1503 /* 1504 * If setting debug or promiscuous mode, do not reset 1505 * the chip; for everything else, call hme_init() 1506 * which will trigger a reset. 1507 */ 1508 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG) 1509 if (ifp->if_flags != sc->sc_if_flags) { 1510 if ((ifp->if_flags & (~RESETIGN)) 1511 == (sc->sc_if_flags & (~RESETIGN))) 1512 hme_setladrf(sc); 1513 else 1514 hme_init(sc); 1515 } 1516 #undef RESETIGN 1517 } 1518 1519 if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable) 1520 hme_init(sc); 1521 1522 break; 1523 1524 case SIOCADDMULTI: 1525 case SIOCDELMULTI: 1526 error = (cmd == SIOCADDMULTI) ? 1527 ether_addmulti(ifr, &sc->sc_ethercom) : 1528 ether_delmulti(ifr, &sc->sc_ethercom); 1529 1530 if (error == ENETRESET) { 1531 /* 1532 * Multicast list has changed; set the hardware filter 1533 * accordingly. 1534 */ 1535 if (ifp->if_flags & IFF_RUNNING) 1536 hme_setladrf(sc); 1537 error = 0; 1538 } 1539 break; 1540 1541 case SIOCGIFMEDIA: 1542 case SIOCSIFMEDIA: 1543 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1544 break; 1545 1546 default: 1547 error = EINVAL; 1548 break; 1549 } 1550 1551 sc->sc_if_flags = ifp->if_flags; 1552 splx(s); 1553 return (error); 1554 } 1555 1556 void 1557 hme_shutdown(arg) 1558 void *arg; 1559 { 1560 1561 hme_stop((struct hme_softc *)arg); 1562 } 1563 1564 /* 1565 * Set up the logical address filter. 1566 */ 1567 void 1568 hme_setladrf(sc) 1569 struct hme_softc *sc; 1570 { 1571 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1572 struct ether_multi *enm; 1573 struct ether_multistep step; 1574 struct ethercom *ec = &sc->sc_ethercom; 1575 bus_space_tag_t t = sc->sc_bustag; 1576 bus_space_handle_t mac = sc->sc_mac; 1577 u_char *cp; 1578 u_int32_t crc; 1579 u_int32_t hash[4]; 1580 u_int32_t v; 1581 int len; 1582 1583 /* Clear hash table */ 1584 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1585 1586 /* Get current RX configuration */ 1587 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1588 1589 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1590 /* Turn on promiscuous mode; turn off the hash filter */ 1591 v |= HME_MAC_RXCFG_PMISC; 1592 v &= ~HME_MAC_RXCFG_HENABLE; 1593 ifp->if_flags |= IFF_ALLMULTI; 1594 goto chipit; 1595 } 1596 1597 /* Turn off promiscuous mode; turn on the hash filter */ 1598 v &= ~HME_MAC_RXCFG_PMISC; 1599 v |= HME_MAC_RXCFG_HENABLE; 1600 1601 /* 1602 * Set up multicast address filter by passing all multicast addresses 1603 * through a crc generator, and then using the high order 6 bits as an 1604 * index into the 64 bit logical address filter. The high order bit 1605 * selects the word, while the rest of the bits select the bit within 1606 * the word. 1607 */ 1608 1609 ETHER_FIRST_MULTI(step, ec, enm); 1610 while (enm != NULL) { 1611 if (ether_cmp(enm->enm_addrlo, enm->enm_addrhi)) { 1612 /* 1613 * We must listen to a range of multicast addresses. 1614 * For now, just accept all multicasts, rather than 1615 * trying to set only those filter bits needed to match 1616 * the range. (At this time, the only use of address 1617 * ranges is for IP multicast routing, for which the 1618 * range is big enough to require all bits set.) 1619 */ 1620 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1621 ifp->if_flags |= IFF_ALLMULTI; 1622 goto chipit; 1623 } 1624 1625 cp = enm->enm_addrlo; 1626 crc = 0xffffffff; 1627 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1628 int octet = *cp++; 1629 int i; 1630 1631 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1632 for (i = 0; i < 8; i++) { 1633 if ((crc & 1) ^ (octet & 1)) { 1634 crc >>= 1; 1635 crc ^= MC_POLY_LE; 1636 } else { 1637 crc >>= 1; 1638 } 1639 octet >>= 1; 1640 } 1641 } 1642 /* Just want the 6 most significant bits. */ 1643 crc >>= 26; 1644 1645 /* Set the corresponding bit in the filter. */ 1646 hash[crc >> 4] |= 1 << (crc & 0xf); 1647 1648 ETHER_NEXT_MULTI(step, enm); 1649 } 1650 1651 ifp->if_flags &= ~IFF_ALLMULTI; 1652 1653 chipit: 1654 /* Now load the hash table into the chip */ 1655 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1656 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1657 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1658 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1659 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1660 } 1661 1662 /* 1663 * Routines for accessing the transmit and receive buffers. 1664 * The various CPU and adapter configurations supported by this 1665 * driver require three different access methods for buffers 1666 * and descriptors: 1667 * (1) contig (contiguous data; no padding), 1668 * (2) gap2 (two bytes of data followed by two bytes of padding), 1669 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1670 */ 1671 1672 #if 0 1673 /* 1674 * contig: contiguous data with no padding. 1675 * 1676 * Buffers may have any alignment. 1677 */ 1678 1679 void 1680 hme_copytobuf_contig(sc, from, ri, len) 1681 struct hme_softc *sc; 1682 void *from; 1683 int ri, len; 1684 { 1685 volatile caddr_t buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1686 1687 /* 1688 * Just call memcpy() to do the work. 1689 */ 1690 memcpy(buf, from, len); 1691 } 1692 1693 void 1694 hme_copyfrombuf_contig(sc, to, boff, len) 1695 struct hme_softc *sc; 1696 void *to; 1697 int boff, len; 1698 { 1699 volatile caddr_t buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1700 1701 /* 1702 * Just call memcpy() to do the work. 1703 */ 1704 memcpy(to, buf, len); 1705 } 1706 #endif 1707