1 /* $NetBSD: hme.c,v 1.87 2012/02/02 19:43:03 tls Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * HME Ethernet module driver. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.87 2012/02/02 19:43:03 tls Exp $"); 38 39 /* #define HMEDEBUG */ 40 41 #include "opt_inet.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/mbuf.h> 47 #include <sys/syslog.h> 48 #include <sys/socket.h> 49 #include <sys/device.h> 50 #include <sys/malloc.h> 51 #include <sys/ioctl.h> 52 #include <sys/errno.h> 53 #include <sys/rnd.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_ether.h> 58 #include <net/if_media.h> 59 60 #ifdef INET 61 #include <net/if_vlanvar.h> 62 #include <netinet/in.h> 63 #include <netinet/if_inarp.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <netinet/ip.h> 67 #include <netinet/tcp.h> 68 #include <netinet/udp.h> 69 #endif 70 71 72 #include <net/bpf.h> 73 #include <net/bpfdesc.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 78 #include <sys/bus.h> 79 80 #include <dev/ic/hmereg.h> 81 #include <dev/ic/hmevar.h> 82 83 static void hme_start(struct ifnet *); 84 static void hme_stop(struct ifnet *, int); 85 static int hme_ioctl(struct ifnet *, u_long, void *); 86 static void hme_tick(void *); 87 static void hme_watchdog(struct ifnet *); 88 static bool hme_shutdown(device_t, int); 89 static int hme_init(struct ifnet *); 90 static void hme_meminit(struct hme_softc *); 91 static void hme_mifinit(struct hme_softc *); 92 static void hme_reset(struct hme_softc *); 93 static void hme_chipreset(struct hme_softc *); 94 static void hme_setladrf(struct hme_softc *); 95 96 /* MII methods & callbacks */ 97 static int hme_mii_readreg(device_t, int, int); 98 static void hme_mii_writereg(device_t, int, int, int); 99 static void hme_mii_statchg(device_t); 100 101 static int hme_mediachange(struct ifnet *); 102 103 static struct mbuf *hme_get(struct hme_softc *, int, uint32_t); 104 static int hme_put(struct hme_softc *, int, struct mbuf *); 105 static void hme_read(struct hme_softc *, int, uint32_t); 106 static int hme_eint(struct hme_softc *, u_int); 107 static int hme_rint(struct hme_softc *); 108 static int hme_tint(struct hme_softc *); 109 110 #if 0 111 /* Default buffer copy routines */ 112 static void hme_copytobuf_contig(struct hme_softc *, void *, int, int); 113 static void hme_copyfrombuf_contig(struct hme_softc *, void *, int, int); 114 #endif 115 116 void 117 hme_config(struct hme_softc *sc) 118 { 119 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 120 struct mii_data *mii = &sc->sc_mii; 121 struct mii_softc *child; 122 bus_dma_tag_t dmatag = sc->sc_dmatag; 123 bus_dma_segment_t seg; 124 bus_size_t size; 125 int rseg, error; 126 127 /* 128 * HME common initialization. 129 * 130 * hme_softc fields that must be initialized by the front-end: 131 * 132 * the bus tag: 133 * sc_bustag 134 * 135 * the DMA bus tag: 136 * sc_dmatag 137 * 138 * the bus handles: 139 * sc_seb (Shared Ethernet Block registers) 140 * sc_erx (Receiver Unit registers) 141 * sc_etx (Transmitter Unit registers) 142 * sc_mac (MAC registers) 143 * sc_mif (Management Interface registers) 144 * 145 * the maximum bus burst size: 146 * sc_burst 147 * 148 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 149 * rb_membase, rb_dmabase) 150 * 151 * the local Ethernet address: 152 * sc_enaddr 153 * 154 */ 155 156 /* Make sure the chip is stopped. */ 157 hme_chipreset(sc); 158 159 /* 160 * Allocate descriptors and buffers 161 * XXX - do all this differently.. and more configurably, 162 * eg. use things as `dma_load_mbuf()' on transmit, 163 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 164 * all the time) on the receiver side. 165 * 166 * Note: receive buffers must be 64-byte aligned. 167 * Also, apparently, the buffers must extend to a DMA burst 168 * boundary beyond the maximum packet size. 169 */ 170 #define _HME_NDESC 128 171 #define _HME_BUFSZ 1600 172 173 /* Note: the # of descriptors must be a multiple of 16 */ 174 sc->sc_rb.rb_ntbuf = _HME_NDESC; 175 sc->sc_rb.rb_nrbuf = _HME_NDESC; 176 177 /* 178 * Allocate DMA capable memory 179 * Buffer descriptors must be aligned on a 2048 byte boundary; 180 * take this into account when calculating the size. Note that 181 * the maximum number of descriptors (256) occupies 2048 bytes, 182 * so we allocate that much regardless of _HME_NDESC. 183 */ 184 size = 2048 + /* TX descriptors */ 185 2048 + /* RX descriptors */ 186 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 187 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* RX buffers */ 188 189 /* Allocate DMA buffer */ 190 if ((error = bus_dmamem_alloc(dmatag, size, 191 2048, 0, 192 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 193 aprint_error_dev(sc->sc_dev, "DMA buffer alloc error %d\n", 194 error); 195 return; 196 } 197 198 /* Map DMA memory in CPU addressable space */ 199 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 200 &sc->sc_rb.rb_membase, 201 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 202 aprint_error_dev(sc->sc_dev, "DMA buffer map error %d\n", 203 error); 204 bus_dmamap_unload(dmatag, sc->sc_dmamap); 205 bus_dmamem_free(dmatag, &seg, rseg); 206 return; 207 } 208 209 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 210 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 211 aprint_error_dev(sc->sc_dev, "DMA map create error %d\n", 212 error); 213 return; 214 } 215 216 /* Load the buffer */ 217 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 218 sc->sc_rb.rb_membase, size, NULL, 219 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 220 aprint_error_dev(sc->sc_dev, "DMA buffer map load error %d\n", 221 error); 222 bus_dmamem_free(dmatag, &seg, rseg); 223 return; 224 } 225 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 226 227 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 228 ether_sprintf(sc->sc_enaddr)); 229 230 /* Initialize ifnet structure. */ 231 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 232 ifp->if_softc = sc; 233 ifp->if_start = hme_start; 234 ifp->if_stop = hme_stop; 235 ifp->if_ioctl = hme_ioctl; 236 ifp->if_init = hme_init; 237 ifp->if_watchdog = hme_watchdog; 238 ifp->if_flags = 239 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 240 sc->sc_if_flags = ifp->if_flags; 241 ifp->if_capabilities |= 242 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 243 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 244 IFQ_SET_READY(&ifp->if_snd); 245 246 /* Initialize ifmedia structures and MII info */ 247 mii->mii_ifp = ifp; 248 mii->mii_readreg = hme_mii_readreg; 249 mii->mii_writereg = hme_mii_writereg; 250 mii->mii_statchg = hme_mii_statchg; 251 252 sc->sc_ethercom.ec_mii = mii; 253 ifmedia_init(&mii->mii_media, 0, hme_mediachange, ether_mediastatus); 254 255 hme_mifinit(sc); 256 257 /* 258 * Some HME's have an MII connector, as well as RJ45. Try attaching 259 * the RJ45 (internal) PHY first, so that the MII PHY is always 260 * instance 1. 261 */ 262 mii_attach(sc->sc_dev, mii, 0xffffffff, 263 HME_PHYAD_INTERNAL, MII_OFFSET_ANY, MIIF_FORCEANEG); 264 mii_attach(sc->sc_dev, mii, 0xffffffff, 265 HME_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_FORCEANEG); 266 267 child = LIST_FIRST(&mii->mii_phys); 268 if (child == NULL) { 269 /* No PHY attached */ 270 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 271 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 272 } else { 273 /* 274 * Walk along the list of attached MII devices and 275 * establish an `MII instance' to `phy number' 276 * mapping. We'll use this mapping in media change 277 * requests to determine which phy to use to program 278 * the MIF configuration register. 279 */ 280 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 281 /* 282 * Note: we support just two PHYs: the built-in 283 * internal device and an external on the MII 284 * connector. 285 */ 286 if (child->mii_phy > 1 || child->mii_inst > 1) { 287 aprint_error_dev(sc->sc_dev, 288 "cannot accommodate MII device %s" 289 " at phy %d, instance %d\n", 290 device_xname(child->mii_dev), 291 child->mii_phy, child->mii_inst); 292 continue; 293 } 294 295 sc->sc_phys[child->mii_inst] = child->mii_phy; 296 } 297 298 /* 299 * Set the default media to auto negotiation if the phy has 300 * the auto negotiation capability. 301 * XXX; What to do otherwise? 302 */ 303 if (ifmedia_match(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0)) 304 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 305 /* 306 else 307 ifmedia_set(&sc->sc_mii.mii_media, sc->sc_defaultmedia); 308 */ 309 } 310 311 /* claim 802.1q capability */ 312 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 313 314 /* Attach the interface. */ 315 if_attach(ifp); 316 ether_ifattach(ifp, sc->sc_enaddr); 317 318 if (pmf_device_register1(sc->sc_dev, NULL, NULL, hme_shutdown)) 319 pmf_class_network_register(sc->sc_dev, ifp); 320 else 321 aprint_error_dev(sc->sc_dev, 322 "couldn't establish power handler\n"); 323 324 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 325 RND_TYPE_NET, 0); 326 327 callout_init(&sc->sc_tick_ch, 0); 328 } 329 330 void 331 hme_tick(void *arg) 332 { 333 struct hme_softc *sc = arg; 334 int s; 335 336 s = splnet(); 337 mii_tick(&sc->sc_mii); 338 splx(s); 339 340 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 341 } 342 343 void 344 hme_reset(struct hme_softc *sc) 345 { 346 int s; 347 348 s = splnet(); 349 (void)hme_init(&sc->sc_ethercom.ec_if); 350 splx(s); 351 } 352 353 void 354 hme_chipreset(struct hme_softc *sc) 355 { 356 bus_space_tag_t t = sc->sc_bustag; 357 bus_space_handle_t seb = sc->sc_seb; 358 int n; 359 360 /* Mask all interrupts */ 361 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff); 362 363 /* Reset transmitter and receiver */ 364 bus_space_write_4(t, seb, HME_SEBI_RESET, 365 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 366 367 for (n = 0; n < 20; n++) { 368 uint32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 369 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 370 return; 371 DELAY(20); 372 } 373 374 printf("%s: %s: reset failed\n", device_xname(sc->sc_dev), __func__); 375 } 376 377 void 378 hme_stop(struct ifnet *ifp, int disable) 379 { 380 struct hme_softc *sc; 381 382 sc = ifp->if_softc; 383 384 ifp->if_timer = 0; 385 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 386 387 callout_stop(&sc->sc_tick_ch); 388 mii_down(&sc->sc_mii); 389 390 hme_chipreset(sc); 391 } 392 393 void 394 hme_meminit(struct hme_softc *sc) 395 { 396 bus_addr_t txbufdma, rxbufdma; 397 bus_addr_t dma; 398 char *p; 399 unsigned int ntbuf, nrbuf, i; 400 struct hme_ring *hr = &sc->sc_rb; 401 402 p = hr->rb_membase; 403 dma = hr->rb_dmabase; 404 405 ntbuf = hr->rb_ntbuf; 406 nrbuf = hr->rb_nrbuf; 407 408 /* 409 * Allocate transmit descriptors 410 */ 411 hr->rb_txd = p; 412 hr->rb_txddma = dma; 413 p += ntbuf * HME_XD_SIZE; 414 dma += ntbuf * HME_XD_SIZE; 415 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 416 dma = (bus_addr_t)roundup((u_long)dma, 2048); 417 p = (void *)roundup((u_long)p, 2048); 418 419 /* 420 * Allocate receive descriptors 421 */ 422 hr->rb_rxd = p; 423 hr->rb_rxddma = dma; 424 p += nrbuf * HME_XD_SIZE; 425 dma += nrbuf * HME_XD_SIZE; 426 /* Again move forward to the next 2048 byte boundary.*/ 427 dma = (bus_addr_t)roundup((u_long)dma, 2048); 428 p = (void *)roundup((u_long)p, 2048); 429 430 431 /* 432 * Allocate transmit buffers 433 */ 434 hr->rb_txbuf = p; 435 txbufdma = dma; 436 p += ntbuf * _HME_BUFSZ; 437 dma += ntbuf * _HME_BUFSZ; 438 439 /* 440 * Allocate receive buffers 441 */ 442 hr->rb_rxbuf = p; 443 rxbufdma = dma; 444 p += nrbuf * _HME_BUFSZ; 445 dma += nrbuf * _HME_BUFSZ; 446 447 /* 448 * Initialize transmit buffer descriptors 449 */ 450 for (i = 0; i < ntbuf; i++) { 451 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 452 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 453 } 454 455 /* 456 * Initialize receive buffer descriptors 457 */ 458 for (i = 0; i < nrbuf; i++) { 459 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 460 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 461 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 462 } 463 464 hr->rb_tdhead = hr->rb_tdtail = 0; 465 hr->rb_td_nbusy = 0; 466 hr->rb_rdtail = 0; 467 } 468 469 /* 470 * Initialization of interface; set up initialization block 471 * and transmit/receive descriptor rings. 472 */ 473 int 474 hme_init(struct ifnet *ifp) 475 { 476 struct hme_softc *sc = ifp->if_softc; 477 bus_space_tag_t t = sc->sc_bustag; 478 bus_space_handle_t seb = sc->sc_seb; 479 bus_space_handle_t etx = sc->sc_etx; 480 bus_space_handle_t erx = sc->sc_erx; 481 bus_space_handle_t mac = sc->sc_mac; 482 uint8_t *ea; 483 uint32_t v; 484 int rc; 485 486 /* 487 * Initialization sequence. The numbered steps below correspond 488 * to the sequence outlined in section 6.3.5.1 in the Ethernet 489 * Channel Engine manual (part of the PCIO manual). 490 * See also the STP2002-STQ document from Sun Microsystems. 491 */ 492 493 /* step 1 & 2. Reset the Ethernet Channel */ 494 hme_stop(ifp, 0); 495 496 /* Re-initialize the MIF */ 497 hme_mifinit(sc); 498 499 /* Call MI reset function if any */ 500 if (sc->sc_hwreset) 501 (*sc->sc_hwreset)(sc); 502 503 #if 0 504 /* Mask all MIF interrupts, just in case */ 505 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 506 #endif 507 508 /* step 3. Setup data structures in host memory */ 509 hme_meminit(sc); 510 511 /* step 4. TX MAC registers & counters */ 512 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 513 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 514 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 515 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 516 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 517 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 518 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 519 sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable; 520 521 /* Load station MAC address */ 522 ea = sc->sc_enaddr; 523 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 524 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 525 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 526 527 /* 528 * Init seed for backoff 529 * (source suggested by manual: low 10 bits of MAC address) 530 */ 531 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 532 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 533 534 535 /* Note: Accepting power-on default for other MAC registers here.. */ 536 537 538 /* step 5. RX MAC registers & counters */ 539 hme_setladrf(sc); 540 541 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 542 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 543 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 544 545 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 546 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 547 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 548 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 549 550 /* step 8. Global Configuration & Interrupt Mask */ 551 bus_space_write_4(t, seb, HME_SEBI_IMASK, 552 ~( 553 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 554 HME_SEB_STAT_HOSTTOTX | 555 HME_SEB_STAT_RXTOHOST | 556 HME_SEB_STAT_TXALL | 557 HME_SEB_STAT_TXPERR | 558 HME_SEB_STAT_RCNTEXP | 559 HME_SEB_STAT_MIFIRQ | 560 HME_SEB_STAT_ALL_ERRORS )); 561 562 switch (sc->sc_burst) { 563 default: 564 v = 0; 565 break; 566 case 16: 567 v = HME_SEB_CFG_BURST16; 568 break; 569 case 32: 570 v = HME_SEB_CFG_BURST32; 571 break; 572 case 64: 573 v = HME_SEB_CFG_BURST64; 574 break; 575 } 576 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 577 578 /* step 9. ETX Configuration: use mostly default values */ 579 580 /* Enable DMA */ 581 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 582 v |= HME_ETX_CFG_DMAENABLE; 583 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 584 585 /* Transmit Descriptor ring size: in increments of 16 */ 586 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 587 588 589 /* step 10. ERX Configuration */ 590 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 591 592 /* Encode Receive Descriptor ring size: four possible values */ 593 switch (_HME_NDESC /*XXX*/) { 594 case 32: 595 v |= HME_ERX_CFG_RINGSIZE32; 596 break; 597 case 64: 598 v |= HME_ERX_CFG_RINGSIZE64; 599 break; 600 case 128: 601 v |= HME_ERX_CFG_RINGSIZE128; 602 break; 603 case 256: 604 v |= HME_ERX_CFG_RINGSIZE256; 605 break; 606 default: 607 printf("hme: invalid Receive Descriptor ring size\n"); 608 break; 609 } 610 611 /* Enable DMA */ 612 v |= HME_ERX_CFG_DMAENABLE; 613 614 /* set h/w rx checksum start offset (# of half-words) */ 615 #ifdef INET 616 v |= (((ETHER_HDR_LEN + sizeof(struct ip)) / sizeof(uint16_t)) 617 << HME_ERX_CFG_CSUMSHIFT) & 618 HME_ERX_CFG_CSUMSTART; 619 #endif 620 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 621 622 /* step 11. XIF Configuration */ 623 v = bus_space_read_4(t, mac, HME_MACI_XIF); 624 v |= HME_MAC_XIF_OE; 625 bus_space_write_4(t, mac, HME_MACI_XIF, v); 626 627 /* step 12. RX_MAC Configuration Register */ 628 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 629 v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP; 630 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 631 632 /* step 13. TX_MAC Configuration Register */ 633 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 634 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 635 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 636 637 /* step 14. Issue Transmit Pending command */ 638 639 /* Call MI initialization function if any */ 640 if (sc->sc_hwinit) 641 (*sc->sc_hwinit)(sc); 642 643 /* Set the current media. */ 644 if ((rc = hme_mediachange(ifp)) != 0) 645 return rc; 646 647 /* Start the one second timer. */ 648 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 649 650 ifp->if_flags |= IFF_RUNNING; 651 ifp->if_flags &= ~IFF_OACTIVE; 652 sc->sc_if_flags = ifp->if_flags; 653 ifp->if_timer = 0; 654 hme_start(ifp); 655 return 0; 656 } 657 658 /* 659 * Routine to copy from mbuf chain to transmit buffer in 660 * network buffer memory. 661 * Returns the amount of data copied. 662 */ 663 int 664 hme_put(struct hme_softc *sc, int ri, struct mbuf *m) 665 /* ri: Ring index */ 666 { 667 struct mbuf *n; 668 int len, tlen = 0; 669 char *bp; 670 671 bp = (char *)sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 672 for (; m; m = n) { 673 len = m->m_len; 674 if (len == 0) { 675 MFREE(m, n); 676 continue; 677 } 678 memcpy(bp, mtod(m, void *), len); 679 bp += len; 680 tlen += len; 681 MFREE(m, n); 682 } 683 return (tlen); 684 } 685 686 /* 687 * Pull data off an interface. 688 * Len is length of data, with local net header stripped. 689 * We copy the data into mbufs. When full cluster sized units are present 690 * we copy into clusters. 691 */ 692 struct mbuf * 693 hme_get(struct hme_softc *sc, int ri, uint32_t flags) 694 { 695 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 696 struct mbuf *m, *m0, *newm; 697 char *bp; 698 int len, totlen; 699 #ifdef INET 700 int csum_flags; 701 #endif 702 703 totlen = HME_XD_DECODE_RSIZE(flags); 704 MGETHDR(m0, M_DONTWAIT, MT_DATA); 705 if (m0 == 0) 706 return (0); 707 m0->m_pkthdr.rcvif = ifp; 708 m0->m_pkthdr.len = totlen; 709 len = MHLEN; 710 m = m0; 711 712 bp = (char *)sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 713 714 while (totlen > 0) { 715 if (totlen >= MINCLSIZE) { 716 MCLGET(m, M_DONTWAIT); 717 if ((m->m_flags & M_EXT) == 0) 718 goto bad; 719 len = MCLBYTES; 720 } 721 722 if (m == m0) { 723 char *newdata = (char *) 724 ALIGN(m->m_data + sizeof(struct ether_header)) - 725 sizeof(struct ether_header); 726 len -= newdata - m->m_data; 727 m->m_data = newdata; 728 } 729 730 m->m_len = len = min(totlen, len); 731 memcpy(mtod(m, void *), bp, len); 732 bp += len; 733 734 totlen -= len; 735 if (totlen > 0) { 736 MGET(newm, M_DONTWAIT, MT_DATA); 737 if (newm == 0) 738 goto bad; 739 len = MLEN; 740 m = m->m_next = newm; 741 } 742 } 743 744 #ifdef INET 745 /* hardware checksum */ 746 csum_flags = 0; 747 if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 748 struct ether_header *eh; 749 struct ether_vlan_header *evh; 750 struct ip *ip; 751 struct udphdr *uh; 752 uint16_t *opts; 753 int32_t hlen, pktlen; 754 uint32_t csum_data; 755 756 eh = mtod(m0, struct ether_header *); 757 if (ntohs(eh->ether_type) == ETHERTYPE_IP) { 758 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN); 759 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN; 760 } else if (ntohs(eh->ether_type) == ETHERTYPE_VLAN) { 761 evh = (struct ether_vlan_header *)eh; 762 if (ntohs(evh->evl_proto != ETHERTYPE_IP)) 763 goto swcsum; 764 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN + 765 ETHER_VLAN_ENCAP_LEN); 766 pktlen = m0->m_pkthdr.len - 767 ETHER_HDR_LEN - ETHER_VLAN_ENCAP_LEN; 768 } else 769 goto swcsum; 770 771 /* IPv4 only */ 772 if (ip->ip_v != IPVERSION) 773 goto swcsum; 774 775 hlen = ip->ip_hl << 2; 776 if (hlen < sizeof(struct ip)) 777 goto swcsum; 778 779 /* 780 * bail if too short, has random trailing garbage, truncated, 781 * fragment, or has ethernet pad. 782 */ 783 if (ntohs(ip->ip_len) < hlen || 784 ntohs(ip->ip_len) != pktlen || 785 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 786 goto swcsum; 787 788 switch (ip->ip_p) { 789 case IPPROTO_TCP: 790 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0) 791 goto swcsum; 792 if (pktlen < (hlen + sizeof(struct tcphdr))) 793 goto swcsum; 794 csum_flags = 795 M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 796 break; 797 case IPPROTO_UDP: 798 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0) 799 goto swcsum; 800 if (pktlen < (hlen + sizeof(struct udphdr))) 801 goto swcsum; 802 uh = (struct udphdr *)((char *)ip + hlen); 803 /* no checksum */ 804 if (uh->uh_sum == 0) 805 goto swcsum; 806 csum_flags = 807 M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 808 break; 809 default: 810 goto swcsum; 811 } 812 813 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */ 814 csum_data = ~flags & HME_XD_RXCKSUM; 815 816 /* 817 * If data offset is different from RX cksum start offset, 818 * we have to deduct them. 819 */ 820 hlen = ((char *)ip + hlen) - 821 ((char *)eh + ETHER_HDR_LEN + sizeof(struct ip)); 822 if (hlen > 1) { 823 uint32_t optsum; 824 825 optsum = 0; 826 opts = (uint16_t *)((char *)eh + 827 ETHER_HDR_LEN + sizeof(struct ip)); 828 829 while (hlen > 1) { 830 optsum += ntohs(*opts++); 831 hlen -= 2; 832 } 833 while (optsum >> 16) 834 optsum = (optsum >> 16) + (optsum & 0xffff); 835 836 /* Deduct the ip opts sum from the hwsum. */ 837 csum_data += (uint16_t)~optsum; 838 839 while (csum_data >> 16) 840 csum_data = 841 (csum_data >> 16) + (csum_data & 0xffff); 842 } 843 m0->m_pkthdr.csum_data = csum_data; 844 } 845 swcsum: 846 m0->m_pkthdr.csum_flags = csum_flags; 847 #endif 848 849 return (m0); 850 851 bad: 852 m_freem(m0); 853 return (0); 854 } 855 856 /* 857 * Pass a packet to the higher levels. 858 */ 859 void 860 hme_read(struct hme_softc *sc, int ix, uint32_t flags) 861 { 862 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 863 struct mbuf *m; 864 int len; 865 866 len = HME_XD_DECODE_RSIZE(flags); 867 if (len <= sizeof(struct ether_header) || 868 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 869 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 870 ETHERMTU + sizeof(struct ether_header))) { 871 #ifdef HMEDEBUG 872 printf("%s: invalid packet size %d; dropping\n", 873 device_xname(sc->sc_dev), len); 874 #endif 875 ifp->if_ierrors++; 876 return; 877 } 878 879 /* Pull packet off interface. */ 880 m = hme_get(sc, ix, flags); 881 if (m == 0) { 882 ifp->if_ierrors++; 883 return; 884 } 885 886 ifp->if_ipackets++; 887 888 /* 889 * Check if there's a BPF listener on this interface. 890 * If so, hand off the raw packet to BPF. 891 */ 892 bpf_mtap(ifp, m); 893 894 /* Pass the packet up. */ 895 (*ifp->if_input)(ifp, m); 896 } 897 898 void 899 hme_start(struct ifnet *ifp) 900 { 901 struct hme_softc *sc = ifp->if_softc; 902 void *txd = sc->sc_rb.rb_txd; 903 struct mbuf *m; 904 unsigned int txflags; 905 unsigned int ri, len, obusy; 906 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 907 908 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 909 return; 910 911 ri = sc->sc_rb.rb_tdhead; 912 obusy = sc->sc_rb.rb_td_nbusy; 913 914 for (;;) { 915 IFQ_DEQUEUE(&ifp->if_snd, m); 916 if (m == 0) 917 break; 918 919 /* 920 * If BPF is listening on this interface, let it see the 921 * packet before we commit it to the wire. 922 */ 923 bpf_mtap(ifp, m); 924 925 #ifdef INET 926 /* collect bits for h/w csum, before hme_put frees the mbuf */ 927 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) && 928 m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 929 struct ether_header *eh; 930 uint16_t offset, start; 931 932 eh = mtod(m, struct ether_header *); 933 switch (ntohs(eh->ether_type)) { 934 case ETHERTYPE_IP: 935 start = ETHER_HDR_LEN; 936 break; 937 case ETHERTYPE_VLAN: 938 start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 939 break; 940 default: 941 /* unsupported, drop it */ 942 m_free(m); 943 continue; 944 } 945 start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 946 offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data) 947 + start; 948 txflags = HME_XD_TXCKSUM | 949 (offset << HME_XD_TXCSSTUFFSHIFT) | 950 (start << HME_XD_TXCSSTARTSHIFT); 951 } else 952 #endif 953 txflags = 0; 954 955 /* 956 * Copy the mbuf chain into the transmit buffer. 957 */ 958 len = hme_put(sc, ri, m); 959 960 /* 961 * Initialize transmit registers and start transmission 962 */ 963 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 964 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 965 HME_XD_ENCODE_TSIZE(len) | txflags); 966 967 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 968 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 969 HME_ETX_TP_DMAWAKEUP); 970 971 if (++ri == ntbuf) 972 ri = 0; 973 974 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 975 ifp->if_flags |= IFF_OACTIVE; 976 break; 977 } 978 } 979 980 if (obusy != sc->sc_rb.rb_td_nbusy) { 981 sc->sc_rb.rb_tdhead = ri; 982 ifp->if_timer = 5; 983 } 984 } 985 986 /* 987 * Transmit interrupt. 988 */ 989 int 990 hme_tint(struct hme_softc *sc) 991 { 992 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 993 bus_space_tag_t t = sc->sc_bustag; 994 bus_space_handle_t mac = sc->sc_mac; 995 unsigned int ri, txflags; 996 997 /* 998 * Unload collision counters 999 */ 1000 ifp->if_collisions += 1001 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 1002 bus_space_read_4(t, mac, HME_MACI_FCCNT); 1003 ifp->if_oerrors += 1004 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 1005 bus_space_read_4(t, mac, HME_MACI_LTCNT); 1006 1007 /* 1008 * then clear the hardware counters. 1009 */ 1010 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 1011 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 1012 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 1013 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 1014 1015 /* Fetch current position in the transmit ring */ 1016 ri = sc->sc_rb.rb_tdtail; 1017 1018 for (;;) { 1019 if (sc->sc_rb.rb_td_nbusy <= 0) 1020 break; 1021 1022 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 1023 1024 if (txflags & HME_XD_OWN) 1025 break; 1026 1027 ifp->if_flags &= ~IFF_OACTIVE; 1028 ifp->if_opackets++; 1029 1030 if (++ri == sc->sc_rb.rb_ntbuf) 1031 ri = 0; 1032 1033 --sc->sc_rb.rb_td_nbusy; 1034 } 1035 1036 /* Update ring */ 1037 sc->sc_rb.rb_tdtail = ri; 1038 1039 hme_start(ifp); 1040 1041 if (sc->sc_rb.rb_td_nbusy == 0) 1042 ifp->if_timer = 0; 1043 1044 return (1); 1045 } 1046 1047 /* 1048 * Receive interrupt. 1049 */ 1050 int 1051 hme_rint(struct hme_softc *sc) 1052 { 1053 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1054 bus_space_tag_t t = sc->sc_bustag; 1055 bus_space_handle_t mac = sc->sc_mac; 1056 void *xdr = sc->sc_rb.rb_rxd; 1057 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 1058 unsigned int ri; 1059 uint32_t flags; 1060 1061 ri = sc->sc_rb.rb_rdtail; 1062 1063 /* 1064 * Process all buffers with valid data. 1065 */ 1066 for (;;) { 1067 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 1068 if (flags & HME_XD_OWN) 1069 break; 1070 1071 if (flags & HME_XD_OFL) { 1072 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 1073 device_xname(sc->sc_dev), ri, flags); 1074 } else 1075 hme_read(sc, ri, flags); 1076 1077 /* This buffer can be used by the hardware again */ 1078 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 1079 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 1080 1081 if (++ri == nrbuf) 1082 ri = 0; 1083 } 1084 1085 sc->sc_rb.rb_rdtail = ri; 1086 1087 /* Read error counters ... */ 1088 ifp->if_ierrors += 1089 bus_space_read_4(t, mac, HME_MACI_STAT_LCNT) + 1090 bus_space_read_4(t, mac, HME_MACI_STAT_ACNT) + 1091 bus_space_read_4(t, mac, HME_MACI_STAT_CCNT) + 1092 bus_space_read_4(t, mac, HME_MACI_STAT_CVCNT); 1093 1094 /* ... then clear the hardware counters. */ 1095 bus_space_write_4(t, mac, HME_MACI_STAT_LCNT, 0); 1096 bus_space_write_4(t, mac, HME_MACI_STAT_ACNT, 0); 1097 bus_space_write_4(t, mac, HME_MACI_STAT_CCNT, 0); 1098 bus_space_write_4(t, mac, HME_MACI_STAT_CVCNT, 0); 1099 return (1); 1100 } 1101 1102 int 1103 hme_eint(struct hme_softc *sc, u_int status) 1104 { 1105 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1106 char bits[128]; 1107 1108 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 1109 bus_space_tag_t t = sc->sc_bustag; 1110 bus_space_handle_t mif = sc->sc_mif; 1111 uint32_t cf, st, sm; 1112 cf = bus_space_read_4(t, mif, HME_MIFI_CFG); 1113 st = bus_space_read_4(t, mif, HME_MIFI_STAT); 1114 sm = bus_space_read_4(t, mif, HME_MIFI_SM); 1115 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n", 1116 device_xname(sc->sc_dev), cf, st, sm); 1117 return (1); 1118 } 1119 1120 /* Receive error counters rolled over */ 1121 if (status & HME_SEB_STAT_ACNTEXP) 1122 ifp->if_ierrors += 0xff; 1123 if (status & HME_SEB_STAT_CCNTEXP) 1124 ifp->if_ierrors += 0xff; 1125 if (status & HME_SEB_STAT_LCNTEXP) 1126 ifp->if_ierrors += 0xff; 1127 if (status & HME_SEB_STAT_CVCNTEXP) 1128 ifp->if_ierrors += 0xff; 1129 1130 /* RXTERR locks up the interface, so do a reset */ 1131 if (status & HME_SEB_STAT_RXTERR) 1132 hme_reset(sc); 1133 1134 snprintb(bits, sizeof(bits), HME_SEB_STAT_BITS, status); 1135 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1136 1137 return (1); 1138 } 1139 1140 int 1141 hme_intr(void *v) 1142 { 1143 struct hme_softc *sc = v; 1144 bus_space_tag_t t = sc->sc_bustag; 1145 bus_space_handle_t seb = sc->sc_seb; 1146 uint32_t status; 1147 int r = 0; 1148 1149 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 1150 1151 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 1152 r |= hme_eint(sc, status); 1153 1154 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 1155 r |= hme_tint(sc); 1156 1157 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1158 r |= hme_rint(sc); 1159 1160 rnd_add_uint32(&sc->rnd_source, status); 1161 1162 return (r); 1163 } 1164 1165 1166 void 1167 hme_watchdog(struct ifnet *ifp) 1168 { 1169 struct hme_softc *sc = ifp->if_softc; 1170 1171 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1172 ++ifp->if_oerrors; 1173 1174 hme_reset(sc); 1175 } 1176 1177 /* 1178 * Initialize the MII Management Interface 1179 */ 1180 void 1181 hme_mifinit(struct hme_softc *sc) 1182 { 1183 bus_space_tag_t t = sc->sc_bustag; 1184 bus_space_handle_t mif = sc->sc_mif; 1185 bus_space_handle_t mac = sc->sc_mac; 1186 int instance, phy; 1187 uint32_t v; 1188 1189 if (sc->sc_mii.mii_media.ifm_cur != NULL) { 1190 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1191 phy = sc->sc_phys[instance]; 1192 } else 1193 /* No media set yet, pick phy arbitrarily.. */ 1194 phy = HME_PHYAD_EXTERNAL; 1195 1196 /* Configure the MIF in frame mode, no poll, current phy select */ 1197 v = 0; 1198 if (phy == HME_PHYAD_EXTERNAL) 1199 v |= HME_MIF_CFG_PHY; 1200 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1201 1202 /* If an external transceiver is selected, enable its MII drivers */ 1203 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1204 v &= ~HME_MAC_XIF_MIIENABLE; 1205 if (phy == HME_PHYAD_EXTERNAL) 1206 v |= HME_MAC_XIF_MIIENABLE; 1207 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1208 } 1209 1210 /* 1211 * MII interface 1212 */ 1213 static int 1214 hme_mii_readreg(device_t self, int phy, int reg) 1215 { 1216 struct hme_softc *sc = device_private(self); 1217 bus_space_tag_t t = sc->sc_bustag; 1218 bus_space_handle_t mif = sc->sc_mif; 1219 bus_space_handle_t mac = sc->sc_mac; 1220 uint32_t v, xif_cfg, mifi_cfg; 1221 int n; 1222 1223 /* We can at most have two PHYs */ 1224 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1225 return (0); 1226 1227 /* Select the desired PHY in the MIF configuration register */ 1228 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1229 v &= ~HME_MIF_CFG_PHY; 1230 if (phy == HME_PHYAD_EXTERNAL) 1231 v |= HME_MIF_CFG_PHY; 1232 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1233 1234 /* Enable MII drivers on external transceiver */ 1235 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1236 if (phy == HME_PHYAD_EXTERNAL) 1237 v |= HME_MAC_XIF_MIIENABLE; 1238 else 1239 v &= ~HME_MAC_XIF_MIIENABLE; 1240 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1241 1242 #if 0 1243 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1244 /* 1245 * Check whether a transceiver is connected by testing 1246 * the MIF configuration register's MDI_X bits. Note that 1247 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1248 */ 1249 mif_mdi_bit = 1 << (8 + (1 - phy)); 1250 delay(100); 1251 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1252 if ((v & mif_mdi_bit) == 0) 1253 return (0); 1254 #endif 1255 1256 /* Construct the frame command */ 1257 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1258 HME_MIF_FO_TAMSB | 1259 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1260 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1261 (reg << HME_MIF_FO_REGAD_SHIFT); 1262 1263 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1264 for (n = 0; n < 100; n++) { 1265 DELAY(1); 1266 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1267 if (v & HME_MIF_FO_TALSB) { 1268 v &= HME_MIF_FO_DATA; 1269 goto out; 1270 } 1271 } 1272 1273 v = 0; 1274 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1275 1276 out: 1277 /* Restore MIFI_CFG register */ 1278 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1279 /* Restore XIF register */ 1280 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1281 return (v); 1282 } 1283 1284 static void 1285 hme_mii_writereg(device_t self, int phy, int reg, int val) 1286 { 1287 struct hme_softc *sc = device_private(self); 1288 bus_space_tag_t t = sc->sc_bustag; 1289 bus_space_handle_t mif = sc->sc_mif; 1290 bus_space_handle_t mac = sc->sc_mac; 1291 uint32_t v, xif_cfg, mifi_cfg; 1292 int n; 1293 1294 /* We can at most have two PHYs */ 1295 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1296 return; 1297 1298 /* Select the desired PHY in the MIF configuration register */ 1299 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1300 v &= ~HME_MIF_CFG_PHY; 1301 if (phy == HME_PHYAD_EXTERNAL) 1302 v |= HME_MIF_CFG_PHY; 1303 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1304 1305 /* Enable MII drivers on external transceiver */ 1306 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1307 if (phy == HME_PHYAD_EXTERNAL) 1308 v |= HME_MAC_XIF_MIIENABLE; 1309 else 1310 v &= ~HME_MAC_XIF_MIIENABLE; 1311 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1312 1313 #if 0 1314 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1315 /* 1316 * Check whether a transceiver is connected by testing 1317 * the MIF configuration register's MDI_X bits. Note that 1318 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1319 */ 1320 mif_mdi_bit = 1 << (8 + (1 - phy)); 1321 delay(100); 1322 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1323 if ((v & mif_mdi_bit) == 0) 1324 return; 1325 #endif 1326 1327 /* Construct the frame command */ 1328 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1329 HME_MIF_FO_TAMSB | 1330 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1331 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1332 (reg << HME_MIF_FO_REGAD_SHIFT) | 1333 (val & HME_MIF_FO_DATA); 1334 1335 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1336 for (n = 0; n < 100; n++) { 1337 DELAY(1); 1338 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1339 if (v & HME_MIF_FO_TALSB) 1340 goto out; 1341 } 1342 1343 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1344 out: 1345 /* Restore MIFI_CFG register */ 1346 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1347 /* Restore XIF register */ 1348 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1349 } 1350 1351 static void 1352 hme_mii_statchg(device_t dev) 1353 { 1354 struct hme_softc *sc = device_private(dev); 1355 bus_space_tag_t t = sc->sc_bustag; 1356 bus_space_handle_t mac = sc->sc_mac; 1357 uint32_t v; 1358 1359 #ifdef HMEDEBUG 1360 if (sc->sc_debug) 1361 printf("hme_mii_statchg: status change\n"); 1362 #endif 1363 1364 /* Set the MAC Full Duplex bit appropriately */ 1365 /* Apparently the hme chip is SIMPLEX if working in full duplex mode, 1366 but not otherwise. */ 1367 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1368 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1369 v |= HME_MAC_TXCFG_FULLDPLX; 1370 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX; 1371 } else { 1372 v &= ~HME_MAC_TXCFG_FULLDPLX; 1373 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX; 1374 } 1375 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags; 1376 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1377 } 1378 1379 int 1380 hme_mediachange(struct ifnet *ifp) 1381 { 1382 struct hme_softc *sc = ifp->if_softc; 1383 bus_space_tag_t t = sc->sc_bustag; 1384 bus_space_handle_t mif = sc->sc_mif; 1385 bus_space_handle_t mac = sc->sc_mac; 1386 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1387 int phy = sc->sc_phys[instance]; 1388 int rc; 1389 uint32_t v; 1390 1391 #ifdef HMEDEBUG 1392 if (sc->sc_debug) 1393 printf("hme_mediachange: phy = %d\n", phy); 1394 #endif 1395 1396 /* Select the current PHY in the MIF configuration register */ 1397 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1398 v &= ~HME_MIF_CFG_PHY; 1399 if (phy == HME_PHYAD_EXTERNAL) 1400 v |= HME_MIF_CFG_PHY; 1401 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1402 1403 /* If an external transceiver is selected, enable its MII drivers */ 1404 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1405 v &= ~HME_MAC_XIF_MIIENABLE; 1406 if (phy == HME_PHYAD_EXTERNAL) 1407 v |= HME_MAC_XIF_MIIENABLE; 1408 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1409 1410 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 1411 return 0; 1412 return rc; 1413 } 1414 1415 /* 1416 * Process an ioctl request. 1417 */ 1418 int 1419 hme_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1420 { 1421 struct hme_softc *sc = ifp->if_softc; 1422 struct ifaddr *ifa = (struct ifaddr *)data; 1423 int s, error = 0; 1424 1425 s = splnet(); 1426 1427 switch (cmd) { 1428 1429 case SIOCINITIFADDR: 1430 switch (ifa->ifa_addr->sa_family) { 1431 #ifdef INET 1432 case AF_INET: 1433 if (ifp->if_flags & IFF_UP) 1434 hme_setladrf(sc); 1435 else { 1436 ifp->if_flags |= IFF_UP; 1437 error = hme_init(ifp); 1438 } 1439 arp_ifinit(ifp, ifa); 1440 break; 1441 #endif 1442 default: 1443 ifp->if_flags |= IFF_UP; 1444 error = hme_init(ifp); 1445 break; 1446 } 1447 break; 1448 1449 case SIOCSIFFLAGS: 1450 #ifdef HMEDEBUG 1451 { 1452 struct ifreq *ifr = data; 1453 sc->sc_debug = 1454 (ifr->ifr_flags & IFF_DEBUG) != 0 ? 1 : 0; 1455 } 1456 #endif 1457 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1458 break; 1459 1460 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1461 case IFF_RUNNING: 1462 /* 1463 * If interface is marked down and it is running, then 1464 * stop it. 1465 */ 1466 hme_stop(ifp, 0); 1467 ifp->if_flags &= ~IFF_RUNNING; 1468 break; 1469 case IFF_UP: 1470 /* 1471 * If interface is marked up and it is stopped, then 1472 * start it. 1473 */ 1474 error = hme_init(ifp); 1475 break; 1476 case IFF_UP|IFF_RUNNING: 1477 /* 1478 * If setting debug or promiscuous mode, do not reset 1479 * the chip; for everything else, call hme_init() 1480 * which will trigger a reset. 1481 */ 1482 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG) 1483 if (ifp->if_flags != sc->sc_if_flags) { 1484 if ((ifp->if_flags & (~RESETIGN)) 1485 == (sc->sc_if_flags & (~RESETIGN))) 1486 hme_setladrf(sc); 1487 else 1488 error = hme_init(ifp); 1489 } 1490 #undef RESETIGN 1491 break; 1492 case 0: 1493 break; 1494 } 1495 1496 if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable) 1497 error = hme_init(ifp); 1498 1499 break; 1500 1501 default: 1502 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1503 break; 1504 1505 error = 0; 1506 1507 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1508 ; 1509 else if (ifp->if_flags & IFF_RUNNING) { 1510 /* 1511 * Multicast list has changed; set the hardware filter 1512 * accordingly. 1513 */ 1514 hme_setladrf(sc); 1515 } 1516 break; 1517 } 1518 1519 sc->sc_if_flags = ifp->if_flags; 1520 splx(s); 1521 return (error); 1522 } 1523 1524 bool 1525 hme_shutdown(device_t self, int howto) 1526 { 1527 struct hme_softc *sc; 1528 struct ifnet *ifp; 1529 1530 sc = device_private(self); 1531 ifp = &sc->sc_ethercom.ec_if; 1532 hme_stop(ifp, 1); 1533 1534 return true; 1535 } 1536 1537 /* 1538 * Set up the logical address filter. 1539 */ 1540 void 1541 hme_setladrf(struct hme_softc *sc) 1542 { 1543 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1544 struct ether_multi *enm; 1545 struct ether_multistep step; 1546 struct ethercom *ec = &sc->sc_ethercom; 1547 bus_space_tag_t t = sc->sc_bustag; 1548 bus_space_handle_t mac = sc->sc_mac; 1549 uint32_t v; 1550 uint32_t crc; 1551 uint32_t hash[4]; 1552 1553 /* Clear hash table */ 1554 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1555 1556 /* Get current RX configuration */ 1557 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1558 1559 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1560 /* Turn on promiscuous mode; turn off the hash filter */ 1561 v |= HME_MAC_RXCFG_PMISC; 1562 v &= ~HME_MAC_RXCFG_HENABLE; 1563 ifp->if_flags |= IFF_ALLMULTI; 1564 goto chipit; 1565 } 1566 1567 /* Turn off promiscuous mode; turn on the hash filter */ 1568 v &= ~HME_MAC_RXCFG_PMISC; 1569 v |= HME_MAC_RXCFG_HENABLE; 1570 1571 /* 1572 * Set up multicast address filter by passing all multicast addresses 1573 * through a crc generator, and then using the high order 6 bits as an 1574 * index into the 64 bit logical address filter. The high order bit 1575 * selects the word, while the rest of the bits select the bit within 1576 * the word. 1577 */ 1578 1579 ETHER_FIRST_MULTI(step, ec, enm); 1580 while (enm != NULL) { 1581 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1582 /* 1583 * We must listen to a range of multicast addresses. 1584 * For now, just accept all multicasts, rather than 1585 * trying to set only those filter bits needed to match 1586 * the range. (At this time, the only use of address 1587 * ranges is for IP multicast routing, for which the 1588 * range is big enough to require all bits set.) 1589 */ 1590 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1591 ifp->if_flags |= IFF_ALLMULTI; 1592 goto chipit; 1593 } 1594 1595 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1596 1597 /* Just want the 6 most significant bits. */ 1598 crc >>= 26; 1599 1600 /* Set the corresponding bit in the filter. */ 1601 hash[crc >> 4] |= 1 << (crc & 0xf); 1602 1603 ETHER_NEXT_MULTI(step, enm); 1604 } 1605 1606 ifp->if_flags &= ~IFF_ALLMULTI; 1607 1608 chipit: 1609 /* Now load the hash table into the chip */ 1610 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1611 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1612 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1613 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1614 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1615 } 1616 1617 /* 1618 * Routines for accessing the transmit and receive buffers. 1619 * The various CPU and adapter configurations supported by this 1620 * driver require three different access methods for buffers 1621 * and descriptors: 1622 * (1) contig (contiguous data; no padding), 1623 * (2) gap2 (two bytes of data followed by two bytes of padding), 1624 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1625 */ 1626 1627 #if 0 1628 /* 1629 * contig: contiguous data with no padding. 1630 * 1631 * Buffers may have any alignment. 1632 */ 1633 1634 void 1635 hme_copytobuf_contig(struct hme_softc *sc, void *from, int ri, int len) 1636 { 1637 volatile void *buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1638 1639 /* 1640 * Just call memcpy() to do the work. 1641 */ 1642 memcpy(buf, from, len); 1643 } 1644 1645 void 1646 hme_copyfrombuf_contig(struct hme_softc *sc, void *to, int boff, int len) 1647 { 1648 volatile void *buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1649 1650 /* 1651 * Just call memcpy() to do the work. 1652 */ 1653 memcpy(to, buf, len); 1654 } 1655 #endif 1656