1 /* $NetBSD: hme.c,v 1.60 2007/10/19 11:59:52 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * HME Ethernet module driver. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.60 2007/10/19 11:59:52 ad Exp $"); 45 46 /* #define HMEDEBUG */ 47 48 #include "opt_inet.h" 49 #include "bpfilter.h" 50 #include "rnd.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/mbuf.h> 56 #include <sys/syslog.h> 57 #include <sys/socket.h> 58 #include <sys/device.h> 59 #include <sys/malloc.h> 60 #include <sys/ioctl.h> 61 #include <sys/errno.h> 62 #if NRND > 0 63 #include <sys/rnd.h> 64 #endif 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_ether.h> 69 #include <net/if_media.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/if_inarp.h> 74 #include <netinet/in_systm.h> 75 #include <netinet/in_var.h> 76 #include <netinet/ip.h> 77 #include <netinet/tcp.h> 78 #include <netinet/udp.h> 79 #endif 80 81 82 #if NBPFILTER > 0 83 #include <net/bpf.h> 84 #include <net/bpfdesc.h> 85 #endif 86 87 #include <dev/mii/mii.h> 88 #include <dev/mii/miivar.h> 89 90 #include <sys/bus.h> 91 92 #include <dev/ic/hmereg.h> 93 #include <dev/ic/hmevar.h> 94 95 void hme_start(struct ifnet *); 96 void hme_stop(struct hme_softc *,bool); 97 int hme_ioctl(struct ifnet *, u_long, void *); 98 void hme_tick(void *); 99 void hme_watchdog(struct ifnet *); 100 void hme_shutdown(void *); 101 void hme_init(struct hme_softc *); 102 void hme_meminit(struct hme_softc *); 103 void hme_mifinit(struct hme_softc *); 104 void hme_reset(struct hme_softc *); 105 void hme_setladrf(struct hme_softc *); 106 107 /* MII methods & callbacks */ 108 static int hme_mii_readreg(struct device *, int, int); 109 static void hme_mii_writereg(struct device *, int, int, int); 110 static void hme_mii_statchg(struct device *); 111 112 int hme_mediachange(struct ifnet *); 113 void hme_mediastatus(struct ifnet *, struct ifmediareq *); 114 115 struct mbuf *hme_get(struct hme_softc *, int, uint32_t); 116 int hme_put(struct hme_softc *, int, struct mbuf *); 117 void hme_read(struct hme_softc *, int, uint32_t); 118 int hme_eint(struct hme_softc *, u_int); 119 int hme_rint(struct hme_softc *); 120 int hme_tint(struct hme_softc *); 121 122 static int ether_cmp(u_char *, u_char *); 123 124 /* Default buffer copy routines */ 125 void hme_copytobuf_contig(struct hme_softc *, void *, int, int); 126 void hme_copyfrombuf_contig(struct hme_softc *, void *, int, int); 127 void hme_zerobuf_contig(struct hme_softc *, int, int); 128 129 130 void 131 hme_config(sc) 132 struct hme_softc *sc; 133 { 134 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 135 struct mii_data *mii = &sc->sc_mii; 136 struct mii_softc *child; 137 bus_dma_tag_t dmatag = sc->sc_dmatag; 138 bus_dma_segment_t seg; 139 bus_size_t size; 140 int rseg, error; 141 142 /* 143 * HME common initialization. 144 * 145 * hme_softc fields that must be initialized by the front-end: 146 * 147 * the bus tag: 148 * sc_bustag 149 * 150 * the DMA bus tag: 151 * sc_dmatag 152 * 153 * the bus handles: 154 * sc_seb (Shared Ethernet Block registers) 155 * sc_erx (Receiver Unit registers) 156 * sc_etx (Transmitter Unit registers) 157 * sc_mac (MAC registers) 158 * sc_mif (Management Interface registers) 159 * 160 * the maximum bus burst size: 161 * sc_burst 162 * 163 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 164 * rb_membase, rb_dmabase) 165 * 166 * the local Ethernet address: 167 * sc_enaddr 168 * 169 */ 170 171 /* Make sure the chip is stopped. */ 172 hme_stop(sc, true); 173 174 175 /* 176 * Allocate descriptors and buffers 177 * XXX - do all this differently.. and more configurably, 178 * eg. use things as `dma_load_mbuf()' on transmit, 179 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 180 * all the time) on the receiver side. 181 * 182 * Note: receive buffers must be 64-byte aligned. 183 * Also, apparently, the buffers must extend to a DMA burst 184 * boundary beyond the maximum packet size. 185 */ 186 #define _HME_NDESC 128 187 #define _HME_BUFSZ 1600 188 189 /* Note: the # of descriptors must be a multiple of 16 */ 190 sc->sc_rb.rb_ntbuf = _HME_NDESC; 191 sc->sc_rb.rb_nrbuf = _HME_NDESC; 192 193 /* 194 * Allocate DMA capable memory 195 * Buffer descriptors must be aligned on a 2048 byte boundary; 196 * take this into account when calculating the size. Note that 197 * the maximum number of descriptors (256) occupies 2048 bytes, 198 * so we allocate that much regardless of _HME_NDESC. 199 */ 200 size = 2048 + /* TX descriptors */ 201 2048 + /* RX descriptors */ 202 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 203 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* RX buffers */ 204 205 /* Allocate DMA buffer */ 206 if ((error = bus_dmamem_alloc(dmatag, size, 207 2048, 0, 208 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 209 printf("%s: DMA buffer alloc error %d\n", 210 sc->sc_dev.dv_xname, error); 211 return; 212 } 213 214 /* Map DMA memory in CPU addressable space */ 215 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 216 &sc->sc_rb.rb_membase, 217 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 218 printf("%s: DMA buffer map error %d\n", 219 sc->sc_dev.dv_xname, error); 220 bus_dmamap_unload(dmatag, sc->sc_dmamap); 221 bus_dmamem_free(dmatag, &seg, rseg); 222 return; 223 } 224 225 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 226 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 227 printf("%s: DMA map create error %d\n", 228 sc->sc_dev.dv_xname, error); 229 return; 230 } 231 232 /* Load the buffer */ 233 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 234 sc->sc_rb.rb_membase, size, NULL, 235 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 236 printf("%s: DMA buffer map load error %d\n", 237 sc->sc_dev.dv_xname, error); 238 bus_dmamem_free(dmatag, &seg, rseg); 239 return; 240 } 241 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 242 243 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 244 ether_sprintf(sc->sc_enaddr)); 245 246 /* Initialize ifnet structure. */ 247 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 248 ifp->if_softc = sc; 249 ifp->if_start = hme_start; 250 ifp->if_ioctl = hme_ioctl; 251 ifp->if_watchdog = hme_watchdog; 252 ifp->if_flags = 253 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 254 sc->sc_if_flags = ifp->if_flags; 255 ifp->if_capabilities |= 256 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 257 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 258 IFQ_SET_READY(&ifp->if_snd); 259 260 /* Initialize ifmedia structures and MII info */ 261 mii->mii_ifp = ifp; 262 mii->mii_readreg = hme_mii_readreg; 263 mii->mii_writereg = hme_mii_writereg; 264 mii->mii_statchg = hme_mii_statchg; 265 266 ifmedia_init(&mii->mii_media, 0, hme_mediachange, hme_mediastatus); 267 268 hme_mifinit(sc); 269 270 mii_attach(&sc->sc_dev, mii, 0xffffffff, 271 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 272 273 child = LIST_FIRST(&mii->mii_phys); 274 if (child == NULL) { 275 /* No PHY attached */ 276 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 277 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 278 } else { 279 /* 280 * Walk along the list of attached MII devices and 281 * establish an `MII instance' to `phy number' 282 * mapping. We'll use this mapping in media change 283 * requests to determine which phy to use to program 284 * the MIF configuration register. 285 */ 286 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 287 /* 288 * Note: we support just two PHYs: the built-in 289 * internal device and an external on the MII 290 * connector. 291 */ 292 if (child->mii_phy > 1 || child->mii_inst > 1) { 293 printf("%s: cannot accommodate MII device %s" 294 " at phy %d, instance %d\n", 295 sc->sc_dev.dv_xname, 296 child->mii_dev.dv_xname, 297 child->mii_phy, child->mii_inst); 298 continue; 299 } 300 301 sc->sc_phys[child->mii_inst] = child->mii_phy; 302 } 303 304 /* 305 * XXX - we can really do the following ONLY if the 306 * phy indeed has the auto negotiation capability!! 307 */ 308 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 309 } 310 311 /* claim 802.1q capability */ 312 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 313 314 /* Attach the interface. */ 315 if_attach(ifp); 316 ether_ifattach(ifp, sc->sc_enaddr); 317 318 sc->sc_sh = shutdownhook_establish(hme_shutdown, sc); 319 if (sc->sc_sh == NULL) 320 panic("hme_config: can't establish shutdownhook"); 321 322 #if NRND > 0 323 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 324 RND_TYPE_NET, 0); 325 #endif 326 327 callout_init(&sc->sc_tick_ch, 0); 328 } 329 330 void 331 hme_tick(arg) 332 void *arg; 333 { 334 struct hme_softc *sc = arg; 335 int s; 336 337 s = splnet(); 338 mii_tick(&sc->sc_mii); 339 splx(s); 340 341 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 342 } 343 344 void 345 hme_reset(sc) 346 struct hme_softc *sc; 347 { 348 int s; 349 350 s = splnet(); 351 hme_init(sc); 352 splx(s); 353 } 354 355 void 356 hme_stop(struct hme_softc *sc, bool chip_only) 357 { 358 bus_space_tag_t t = sc->sc_bustag; 359 bus_space_handle_t seb = sc->sc_seb; 360 int n; 361 362 if (!chip_only) { 363 callout_stop(&sc->sc_tick_ch); 364 mii_down(&sc->sc_mii); 365 } 366 367 /* Mask all interrupts */ 368 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff); 369 370 /* Reset transmitter and receiver */ 371 bus_space_write_4(t, seb, HME_SEBI_RESET, 372 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 373 374 for (n = 0; n < 20; n++) { 375 u_int32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 376 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 377 return; 378 DELAY(20); 379 } 380 381 printf("%s: hme_stop: reset failed\n", sc->sc_dev.dv_xname); 382 } 383 384 void 385 hme_meminit(sc) 386 struct hme_softc *sc; 387 { 388 bus_addr_t txbufdma, rxbufdma; 389 bus_addr_t dma; 390 char *p; 391 unsigned int ntbuf, nrbuf, i; 392 struct hme_ring *hr = &sc->sc_rb; 393 394 p = hr->rb_membase; 395 dma = hr->rb_dmabase; 396 397 ntbuf = hr->rb_ntbuf; 398 nrbuf = hr->rb_nrbuf; 399 400 /* 401 * Allocate transmit descriptors 402 */ 403 hr->rb_txd = p; 404 hr->rb_txddma = dma; 405 p += ntbuf * HME_XD_SIZE; 406 dma += ntbuf * HME_XD_SIZE; 407 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 408 dma = (bus_addr_t)roundup((u_long)dma, 2048); 409 p = (void *)roundup((u_long)p, 2048); 410 411 /* 412 * Allocate receive descriptors 413 */ 414 hr->rb_rxd = p; 415 hr->rb_rxddma = dma; 416 p += nrbuf * HME_XD_SIZE; 417 dma += nrbuf * HME_XD_SIZE; 418 /* Again move forward to the next 2048 byte boundary.*/ 419 dma = (bus_addr_t)roundup((u_long)dma, 2048); 420 p = (void *)roundup((u_long)p, 2048); 421 422 423 /* 424 * Allocate transmit buffers 425 */ 426 hr->rb_txbuf = p; 427 txbufdma = dma; 428 p += ntbuf * _HME_BUFSZ; 429 dma += ntbuf * _HME_BUFSZ; 430 431 /* 432 * Allocate receive buffers 433 */ 434 hr->rb_rxbuf = p; 435 rxbufdma = dma; 436 p += nrbuf * _HME_BUFSZ; 437 dma += nrbuf * _HME_BUFSZ; 438 439 /* 440 * Initialize transmit buffer descriptors 441 */ 442 for (i = 0; i < ntbuf; i++) { 443 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 444 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 445 } 446 447 /* 448 * Initialize receive buffer descriptors 449 */ 450 for (i = 0; i < nrbuf; i++) { 451 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 452 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 453 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 454 } 455 456 hr->rb_tdhead = hr->rb_tdtail = 0; 457 hr->rb_td_nbusy = 0; 458 hr->rb_rdtail = 0; 459 } 460 461 /* 462 * Initialization of interface; set up initialization block 463 * and transmit/receive descriptor rings. 464 */ 465 void 466 hme_init(sc) 467 struct hme_softc *sc; 468 { 469 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 470 bus_space_tag_t t = sc->sc_bustag; 471 bus_space_handle_t seb = sc->sc_seb; 472 bus_space_handle_t etx = sc->sc_etx; 473 bus_space_handle_t erx = sc->sc_erx; 474 bus_space_handle_t mac = sc->sc_mac; 475 u_int8_t *ea; 476 u_int32_t v; 477 478 /* 479 * Initialization sequence. The numbered steps below correspond 480 * to the sequence outlined in section 6.3.5.1 in the Ethernet 481 * Channel Engine manual (part of the PCIO manual). 482 * See also the STP2002-STQ document from Sun Microsystems. 483 */ 484 485 /* step 1 & 2. Reset the Ethernet Channel */ 486 hme_stop(sc, false); 487 488 /* Re-initialize the MIF */ 489 hme_mifinit(sc); 490 491 /* Call MI reset function if any */ 492 if (sc->sc_hwreset) 493 (*sc->sc_hwreset)(sc); 494 495 #if 0 496 /* Mask all MIF interrupts, just in case */ 497 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 498 #endif 499 500 /* step 3. Setup data structures in host memory */ 501 hme_meminit(sc); 502 503 /* step 4. TX MAC registers & counters */ 504 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 505 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 506 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 507 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 508 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 509 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 510 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 511 sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable; 512 513 /* Load station MAC address */ 514 ea = sc->sc_enaddr; 515 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 516 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 517 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 518 519 /* 520 * Init seed for backoff 521 * (source suggested by manual: low 10 bits of MAC address) 522 */ 523 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 524 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 525 526 527 /* Note: Accepting power-on default for other MAC registers here.. */ 528 529 530 /* step 5. RX MAC registers & counters */ 531 hme_setladrf(sc); 532 533 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 534 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 535 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 536 537 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 538 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 539 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 540 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 541 542 /* step 8. Global Configuration & Interrupt Mask */ 543 bus_space_write_4(t, seb, HME_SEBI_IMASK, 544 ~( 545 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 546 HME_SEB_STAT_HOSTTOTX | 547 HME_SEB_STAT_RXTOHOST | 548 HME_SEB_STAT_TXALL | 549 HME_SEB_STAT_TXPERR | 550 HME_SEB_STAT_RCNTEXP | 551 /*HME_SEB_STAT_MIFIRQ |*/ 552 HME_SEB_STAT_ALL_ERRORS )); 553 554 switch (sc->sc_burst) { 555 default: 556 v = 0; 557 break; 558 case 16: 559 v = HME_SEB_CFG_BURST16; 560 break; 561 case 32: 562 v = HME_SEB_CFG_BURST32; 563 break; 564 case 64: 565 v = HME_SEB_CFG_BURST64; 566 break; 567 } 568 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 569 570 /* step 9. ETX Configuration: use mostly default values */ 571 572 /* Enable DMA */ 573 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 574 v |= HME_ETX_CFG_DMAENABLE; 575 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 576 577 /* Transmit Descriptor ring size: in increments of 16 */ 578 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 579 580 581 /* step 10. ERX Configuration */ 582 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 583 584 /* Encode Receive Descriptor ring size: four possible values */ 585 switch (_HME_NDESC /*XXX*/) { 586 case 32: 587 v |= HME_ERX_CFG_RINGSIZE32; 588 break; 589 case 64: 590 v |= HME_ERX_CFG_RINGSIZE64; 591 break; 592 case 128: 593 v |= HME_ERX_CFG_RINGSIZE128; 594 break; 595 case 256: 596 v |= HME_ERX_CFG_RINGSIZE256; 597 break; 598 default: 599 printf("hme: invalid Receive Descriptor ring size\n"); 600 break; 601 } 602 603 /* Enable DMA */ 604 v |= HME_ERX_CFG_DMAENABLE; 605 606 /* set h/w rx checksum start offset (# of half-words) */ 607 #ifdef INET 608 v |= (((ETHER_HDR_LEN + sizeof(struct ip) + 609 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 610 ETHER_VLAN_ENCAP_LEN : 0)) / 2) << HME_ERX_CFG_CSUMSHIFT) & 611 HME_ERX_CFG_CSUMSTART; 612 #endif 613 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 614 615 /* step 11. XIF Configuration */ 616 v = bus_space_read_4(t, mac, HME_MACI_XIF); 617 v |= HME_MAC_XIF_OE; 618 bus_space_write_4(t, mac, HME_MACI_XIF, v); 619 620 /* step 12. RX_MAC Configuration Register */ 621 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 622 v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP; 623 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 624 625 /* step 13. TX_MAC Configuration Register */ 626 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 627 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 628 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 629 630 /* step 14. Issue Transmit Pending command */ 631 632 /* Call MI initialization function if any */ 633 if (sc->sc_hwinit) 634 (*sc->sc_hwinit)(sc); 635 636 /* Set the current media. */ 637 mii_mediachg(&sc->sc_mii); 638 639 /* Start the one second timer. */ 640 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 641 642 ifp->if_flags |= IFF_RUNNING; 643 ifp->if_flags &= ~IFF_OACTIVE; 644 sc->sc_if_flags = ifp->if_flags; 645 ifp->if_timer = 0; 646 hme_start(ifp); 647 } 648 649 /* 650 * Compare two Ether/802 addresses for equality, inlined and unrolled for 651 * speed. 652 */ 653 static inline int 654 ether_cmp(a, b) 655 u_char *a, *b; 656 { 657 658 if (a[5] != b[5] || a[4] != b[4] || a[3] != b[3] || 659 a[2] != b[2] || a[1] != b[1] || a[0] != b[0]) 660 return (0); 661 return (1); 662 } 663 664 665 /* 666 * Routine to copy from mbuf chain to transmit buffer in 667 * network buffer memory. 668 * Returns the amount of data copied. 669 */ 670 int 671 hme_put(sc, ri, m) 672 struct hme_softc *sc; 673 int ri; /* Ring index */ 674 struct mbuf *m; 675 { 676 struct mbuf *n; 677 int len, tlen = 0; 678 char *bp; 679 680 bp = (char *)sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 681 for (; m; m = n) { 682 len = m->m_len; 683 if (len == 0) { 684 MFREE(m, n); 685 continue; 686 } 687 memcpy(bp, mtod(m, void *), len); 688 bp += len; 689 tlen += len; 690 MFREE(m, n); 691 } 692 return (tlen); 693 } 694 695 /* 696 * Pull data off an interface. 697 * Len is length of data, with local net header stripped. 698 * We copy the data into mbufs. When full cluster sized units are present 699 * we copy into clusters. 700 */ 701 struct mbuf * 702 hme_get(sc, ri, flags) 703 struct hme_softc *sc; 704 int ri; 705 u_int32_t flags; 706 { 707 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 708 struct mbuf *m, *m0, *newm; 709 char *bp; 710 int len, totlen; 711 712 totlen = HME_XD_DECODE_RSIZE(flags); 713 MGETHDR(m0, M_DONTWAIT, MT_DATA); 714 if (m0 == 0) 715 return (0); 716 m0->m_pkthdr.rcvif = ifp; 717 m0->m_pkthdr.len = totlen; 718 len = MHLEN; 719 m = m0; 720 721 bp = (char *)sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 722 723 while (totlen > 0) { 724 if (totlen >= MINCLSIZE) { 725 MCLGET(m, M_DONTWAIT); 726 if ((m->m_flags & M_EXT) == 0) 727 goto bad; 728 len = MCLBYTES; 729 } 730 731 if (m == m0) { 732 char *newdata = (char *) 733 ALIGN(m->m_data + sizeof(struct ether_header)) - 734 sizeof(struct ether_header); 735 len -= newdata - m->m_data; 736 m->m_data = newdata; 737 } 738 739 m->m_len = len = min(totlen, len); 740 memcpy(mtod(m, void *), bp, len); 741 bp += len; 742 743 totlen -= len; 744 if (totlen > 0) { 745 MGET(newm, M_DONTWAIT, MT_DATA); 746 if (newm == 0) 747 goto bad; 748 len = MLEN; 749 m = m->m_next = newm; 750 } 751 } 752 753 #ifdef INET 754 /* hardware checksum */ 755 if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 756 struct ether_header *eh; 757 struct ip *ip; 758 struct udphdr *uh; 759 uint16_t *opts; 760 int32_t hlen, pktlen; 761 uint32_t temp; 762 763 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 764 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN - 765 ETHER_VLAN_ENCAP_LEN; 766 eh = (struct ether_header *) mtod(m0, void *) + 767 ETHER_VLAN_ENCAP_LEN; 768 } else { 769 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN; 770 eh = mtod(m0, struct ether_header *); 771 } 772 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 773 goto swcsum; 774 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 775 776 /* IPv4 only */ 777 if (ip->ip_v != IPVERSION) 778 goto swcsum; 779 780 hlen = ip->ip_hl << 2; 781 if (hlen < sizeof(struct ip)) 782 goto swcsum; 783 784 /* 785 * bail if too short, has random trailing garbage, truncated, 786 * fragment, or has ethernet pad. 787 */ 788 if ((ntohs(ip->ip_len) < hlen) || (ntohs(ip->ip_len) != pktlen) 789 || (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 790 goto swcsum; 791 792 switch (ip->ip_p) { 793 case IPPROTO_TCP: 794 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 795 goto swcsum; 796 if (pktlen < (hlen + sizeof(struct tcphdr))) 797 goto swcsum; 798 m0->m_pkthdr.csum_flags = M_CSUM_TCPv4; 799 break; 800 case IPPROTO_UDP: 801 if (! (ifp->if_csum_flags_rx & M_CSUM_UDPv4)) 802 goto swcsum; 803 if (pktlen < (hlen + sizeof(struct udphdr))) 804 goto swcsum; 805 uh = (struct udphdr *)((char *)ip + hlen); 806 /* no checksum */ 807 if (uh->uh_sum == 0) 808 goto swcsum; 809 m0->m_pkthdr.csum_flags = M_CSUM_UDPv4; 810 break; 811 default: 812 goto swcsum; 813 } 814 815 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */ 816 m0->m_pkthdr.csum_data = (~flags) & HME_XD_RXCKSUM; 817 818 /* if the pkt had ip options, we have to deduct them */ 819 if (hlen > sizeof(struct ip)) { 820 uint32_t optsum; 821 822 optsum = 0; 823 temp = hlen - sizeof(struct ip); 824 opts = (uint16_t *)((char *)ip + sizeof(struct ip)); 825 826 while (temp > 1) { 827 optsum += ntohs(*opts++); 828 temp -= 2; 829 } 830 while (optsum >> 16) 831 optsum = (optsum >> 16) + (optsum & 0xffff); 832 833 /* Deduct the ip opts sum from the hwsum (rfc 1624). */ 834 m0->m_pkthdr.csum_data = ~((~m0->m_pkthdr.csum_data) - 835 ~optsum); 836 837 while (m0->m_pkthdr.csum_data >> 16) 838 m0->m_pkthdr.csum_data = 839 (m0->m_pkthdr.csum_data >> 16) + 840 (m0->m_pkthdr.csum_data & 0xffff); 841 } 842 843 m0->m_pkthdr.csum_flags |= M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 844 } 845 swcsum: 846 m0->m_pkthdr.csum_flags = 0; 847 #endif 848 849 return (m0); 850 851 bad: 852 m_freem(m0); 853 return (0); 854 } 855 856 /* 857 * Pass a packet to the higher levels. 858 */ 859 void 860 hme_read(sc, ix, flags) 861 struct hme_softc *sc; 862 int ix; 863 u_int32_t flags; 864 { 865 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 866 struct mbuf *m; 867 int len; 868 869 len = HME_XD_DECODE_RSIZE(flags); 870 if (len <= sizeof(struct ether_header) || 871 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 872 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 873 ETHERMTU + sizeof(struct ether_header))) { 874 #ifdef HMEDEBUG 875 printf("%s: invalid packet size %d; dropping\n", 876 sc->sc_dev.dv_xname, len); 877 #endif 878 ifp->if_ierrors++; 879 return; 880 } 881 882 /* Pull packet off interface. */ 883 m = hme_get(sc, ix, flags); 884 if (m == 0) { 885 ifp->if_ierrors++; 886 return; 887 } 888 889 ifp->if_ipackets++; 890 891 #if NBPFILTER > 0 892 /* 893 * Check if there's a BPF listener on this interface. 894 * If so, hand off the raw packet to BPF. 895 */ 896 if (ifp->if_bpf) 897 bpf_mtap(ifp->if_bpf, m); 898 #endif 899 900 /* Pass the packet up. */ 901 (*ifp->if_input)(ifp, m); 902 } 903 904 void 905 hme_start(ifp) 906 struct ifnet *ifp; 907 { 908 struct hme_softc *sc = (struct hme_softc *)ifp->if_softc; 909 void *txd = sc->sc_rb.rb_txd; 910 struct mbuf *m; 911 unsigned int txflags; 912 unsigned int ri, len; 913 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 914 915 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 916 return; 917 918 ri = sc->sc_rb.rb_tdhead; 919 920 for (;;) { 921 IFQ_DEQUEUE(&ifp->if_snd, m); 922 if (m == 0) 923 break; 924 925 #if NBPFILTER > 0 926 /* 927 * If BPF is listening on this interface, let it see the 928 * packet before we commit it to the wire. 929 */ 930 if (ifp->if_bpf) 931 bpf_mtap(ifp->if_bpf, m); 932 #endif 933 934 #ifdef INET 935 /* collect bits for h/w csum, before hme_put frees the mbuf */ 936 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) && 937 m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 938 struct ether_header *eh; 939 uint16_t offset, start; 940 941 eh = mtod(m, struct ether_header *); 942 switch (ntohs(eh->ether_type)) { 943 case ETHERTYPE_IP: 944 start = ETHER_HDR_LEN; 945 break; 946 case ETHERTYPE_VLAN: 947 start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 948 break; 949 default: 950 /* unsupported, drop it */ 951 m_free(m); 952 continue; 953 } 954 start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 955 offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data) 956 + start; 957 txflags = HME_XD_TXCKSUM | 958 (offset << HME_XD_TXCSSTUFFSHIFT) | 959 (start << HME_XD_TXCSSTARTSHIFT); 960 } else 961 #endif 962 txflags = 0; 963 964 /* 965 * Copy the mbuf chain into the transmit buffer. 966 */ 967 len = hme_put(sc, ri, m); 968 969 /* 970 * Initialize transmit registers and start transmission 971 */ 972 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 973 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 974 HME_XD_ENCODE_TSIZE(len) | txflags); 975 976 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 977 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 978 HME_ETX_TP_DMAWAKEUP); 979 980 if (++ri == ntbuf) 981 ri = 0; 982 983 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 984 ifp->if_flags |= IFF_OACTIVE; 985 break; 986 } 987 } 988 989 sc->sc_rb.rb_tdhead = ri; 990 } 991 992 /* 993 * Transmit interrupt. 994 */ 995 int 996 hme_tint(sc) 997 struct hme_softc *sc; 998 { 999 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1000 bus_space_tag_t t = sc->sc_bustag; 1001 bus_space_handle_t mac = sc->sc_mac; 1002 unsigned int ri, txflags; 1003 1004 /* 1005 * Unload collision counters 1006 */ 1007 ifp->if_collisions += 1008 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 1009 bus_space_read_4(t, mac, HME_MACI_FCCNT) + 1010 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 1011 bus_space_read_4(t, mac, HME_MACI_LTCNT); 1012 1013 /* 1014 * then clear the hardware counters. 1015 */ 1016 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 1017 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 1018 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 1019 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 1020 1021 /* Fetch current position in the transmit ring */ 1022 ri = sc->sc_rb.rb_tdtail; 1023 1024 for (;;) { 1025 if (sc->sc_rb.rb_td_nbusy <= 0) 1026 break; 1027 1028 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 1029 1030 if (txflags & HME_XD_OWN) 1031 break; 1032 1033 ifp->if_flags &= ~IFF_OACTIVE; 1034 ifp->if_opackets++; 1035 1036 if (++ri == sc->sc_rb.rb_ntbuf) 1037 ri = 0; 1038 1039 --sc->sc_rb.rb_td_nbusy; 1040 } 1041 1042 /* Update ring */ 1043 sc->sc_rb.rb_tdtail = ri; 1044 1045 hme_start(ifp); 1046 1047 if (sc->sc_rb.rb_td_nbusy == 0) 1048 ifp->if_timer = 0; 1049 1050 return (1); 1051 } 1052 1053 /* 1054 * Receive interrupt. 1055 */ 1056 int 1057 hme_rint(sc) 1058 struct hme_softc *sc; 1059 { 1060 void *xdr = sc->sc_rb.rb_rxd; 1061 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 1062 unsigned int ri; 1063 u_int32_t flags; 1064 1065 ri = sc->sc_rb.rb_rdtail; 1066 1067 /* 1068 * Process all buffers with valid data. 1069 */ 1070 for (;;) { 1071 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 1072 if (flags & HME_XD_OWN) 1073 break; 1074 1075 if (flags & HME_XD_OFL) { 1076 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 1077 sc->sc_dev.dv_xname, ri, flags); 1078 } else 1079 hme_read(sc, ri, flags); 1080 1081 /* This buffer can be used by the hardware again */ 1082 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 1083 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 1084 1085 if (++ri == nrbuf) 1086 ri = 0; 1087 } 1088 1089 sc->sc_rb.rb_rdtail = ri; 1090 1091 return (1); 1092 } 1093 1094 int 1095 hme_eint(sc, status) 1096 struct hme_softc *sc; 1097 u_int status; 1098 { 1099 char bits[128]; 1100 1101 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 1102 bus_space_tag_t t = sc->sc_bustag; 1103 bus_space_handle_t mif = sc->sc_mif; 1104 u_int32_t cf, st, sm; 1105 cf = bus_space_read_4(t, mif, HME_MIFI_CFG); 1106 st = bus_space_read_4(t, mif, HME_MIFI_STAT); 1107 sm = bus_space_read_4(t, mif, HME_MIFI_SM); 1108 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n", 1109 sc->sc_dev.dv_xname, cf, st, sm); 1110 return (1); 1111 } 1112 1113 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1114 bitmask_snprintf(status, HME_SEB_STAT_BITS, bits,sizeof(bits))); 1115 return (1); 1116 } 1117 1118 int 1119 hme_intr(v) 1120 void *v; 1121 { 1122 struct hme_softc *sc = (struct hme_softc *)v; 1123 bus_space_tag_t t = sc->sc_bustag; 1124 bus_space_handle_t seb = sc->sc_seb; 1125 u_int32_t status; 1126 int r = 0; 1127 1128 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 1129 1130 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 1131 r |= hme_eint(sc, status); 1132 1133 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 1134 r |= hme_tint(sc); 1135 1136 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1137 r |= hme_rint(sc); 1138 1139 #if NRND > 0 1140 rnd_add_uint32(&sc->rnd_source, status); 1141 #endif 1142 1143 return (r); 1144 } 1145 1146 1147 void 1148 hme_watchdog(ifp) 1149 struct ifnet *ifp; 1150 { 1151 struct hme_softc *sc = ifp->if_softc; 1152 1153 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1154 ++ifp->if_oerrors; 1155 1156 hme_reset(sc); 1157 } 1158 1159 /* 1160 * Initialize the MII Management Interface 1161 */ 1162 void 1163 hme_mifinit(sc) 1164 struct hme_softc *sc; 1165 { 1166 bus_space_tag_t t = sc->sc_bustag; 1167 bus_space_handle_t mif = sc->sc_mif; 1168 bus_space_handle_t mac = sc->sc_mac; 1169 int instance, phy; 1170 u_int32_t v; 1171 1172 if (sc->sc_media.ifm_cur != NULL) { 1173 instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1174 phy = sc->sc_phys[instance]; 1175 } else 1176 /* No media set yet, pick phy arbitrarily.. */ 1177 phy = HME_PHYAD_EXTERNAL; 1178 1179 /* Configure the MIF in frame mode, no poll, current phy select */ 1180 v = 0; 1181 if (phy == HME_PHYAD_EXTERNAL) 1182 v |= HME_MIF_CFG_PHY; 1183 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1184 1185 /* If an external transceiver is selected, enable its MII drivers */ 1186 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1187 v &= ~HME_MAC_XIF_MIIENABLE; 1188 if (phy == HME_PHYAD_EXTERNAL) 1189 v |= HME_MAC_XIF_MIIENABLE; 1190 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1191 } 1192 1193 /* 1194 * MII interface 1195 */ 1196 static int 1197 hme_mii_readreg(self, phy, reg) 1198 struct device *self; 1199 int phy, reg; 1200 { 1201 struct hme_softc *sc = (void *)self; 1202 bus_space_tag_t t = sc->sc_bustag; 1203 bus_space_handle_t mif = sc->sc_mif; 1204 bus_space_handle_t mac = sc->sc_mac; 1205 u_int32_t v, xif_cfg, mifi_cfg; 1206 int n; 1207 1208 /* We can at most have two PHYs */ 1209 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1210 return (0); 1211 1212 /* Select the desired PHY in the MIF configuration register */ 1213 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1214 v &= ~HME_MIF_CFG_PHY; 1215 if (phy == HME_PHYAD_EXTERNAL) 1216 v |= HME_MIF_CFG_PHY; 1217 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1218 1219 /* Enable MII drivers on external transceiver */ 1220 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1221 if (phy == HME_PHYAD_EXTERNAL) 1222 v |= HME_MAC_XIF_MIIENABLE; 1223 else 1224 v &= ~HME_MAC_XIF_MIIENABLE; 1225 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1226 1227 #if 0 1228 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1229 /* 1230 * Check whether a transceiver is connected by testing 1231 * the MIF configuration register's MDI_X bits. Note that 1232 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1233 */ 1234 mif_mdi_bit = 1 << (8 + (1 - phy)); 1235 delay(100); 1236 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1237 if ((v & mif_mdi_bit) == 0) 1238 return (0); 1239 #endif 1240 1241 /* Construct the frame command */ 1242 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1243 HME_MIF_FO_TAMSB | 1244 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1245 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1246 (reg << HME_MIF_FO_REGAD_SHIFT); 1247 1248 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1249 for (n = 0; n < 100; n++) { 1250 DELAY(1); 1251 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1252 if (v & HME_MIF_FO_TALSB) { 1253 v &= HME_MIF_FO_DATA; 1254 goto out; 1255 } 1256 } 1257 1258 v = 0; 1259 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1260 1261 out: 1262 /* Restore MIFI_CFG register */ 1263 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1264 /* Restore XIF register */ 1265 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1266 return (v); 1267 } 1268 1269 static void 1270 hme_mii_writereg(self, phy, reg, val) 1271 struct device *self; 1272 int phy, reg, val; 1273 { 1274 struct hme_softc *sc = (void *)self; 1275 bus_space_tag_t t = sc->sc_bustag; 1276 bus_space_handle_t mif = sc->sc_mif; 1277 bus_space_handle_t mac = sc->sc_mac; 1278 u_int32_t v, xif_cfg, mifi_cfg; 1279 int n; 1280 1281 /* We can at most have two PHYs */ 1282 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1283 return; 1284 1285 /* Select the desired PHY in the MIF configuration register */ 1286 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1287 v &= ~HME_MIF_CFG_PHY; 1288 if (phy == HME_PHYAD_EXTERNAL) 1289 v |= HME_MIF_CFG_PHY; 1290 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1291 1292 /* Enable MII drivers on external transceiver */ 1293 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1294 if (phy == HME_PHYAD_EXTERNAL) 1295 v |= HME_MAC_XIF_MIIENABLE; 1296 else 1297 v &= ~HME_MAC_XIF_MIIENABLE; 1298 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1299 1300 #if 0 1301 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1302 /* 1303 * Check whether a transceiver is connected by testing 1304 * the MIF configuration register's MDI_X bits. Note that 1305 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1306 */ 1307 mif_mdi_bit = 1 << (8 + (1 - phy)); 1308 delay(100); 1309 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1310 if ((v & mif_mdi_bit) == 0) 1311 return; 1312 #endif 1313 1314 /* Construct the frame command */ 1315 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1316 HME_MIF_FO_TAMSB | 1317 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1318 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1319 (reg << HME_MIF_FO_REGAD_SHIFT) | 1320 (val & HME_MIF_FO_DATA); 1321 1322 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1323 for (n = 0; n < 100; n++) { 1324 DELAY(1); 1325 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1326 if (v & HME_MIF_FO_TALSB) 1327 goto out; 1328 } 1329 1330 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1331 out: 1332 /* Restore MIFI_CFG register */ 1333 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1334 /* Restore XIF register */ 1335 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1336 } 1337 1338 static void 1339 hme_mii_statchg(dev) 1340 struct device *dev; 1341 { 1342 struct hme_softc *sc = (void *)dev; 1343 bus_space_tag_t t = sc->sc_bustag; 1344 bus_space_handle_t mac = sc->sc_mac; 1345 u_int32_t v; 1346 1347 #ifdef HMEDEBUG 1348 if (sc->sc_debug) 1349 printf("hme_mii_statchg: status change\n"); 1350 #endif 1351 1352 /* Set the MAC Full Duplex bit appropriately */ 1353 /* Apparently the hme chip is SIMPLEX if working in full duplex mode, 1354 but not otherwise. */ 1355 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1356 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1357 v |= HME_MAC_TXCFG_FULLDPLX; 1358 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX; 1359 } else { 1360 v &= ~HME_MAC_TXCFG_FULLDPLX; 1361 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX; 1362 } 1363 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags; 1364 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1365 } 1366 1367 int 1368 hme_mediachange(ifp) 1369 struct ifnet *ifp; 1370 { 1371 struct hme_softc *sc = ifp->if_softc; 1372 bus_space_tag_t t = sc->sc_bustag; 1373 bus_space_handle_t mif = sc->sc_mif; 1374 bus_space_handle_t mac = sc->sc_mac; 1375 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1376 int phy = sc->sc_phys[instance]; 1377 u_int32_t v; 1378 1379 #ifdef HMEDEBUG 1380 if (sc->sc_debug) 1381 printf("hme_mediachange: phy = %d\n", phy); 1382 #endif 1383 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1384 return (EINVAL); 1385 1386 /* Select the current PHY in the MIF configuration register */ 1387 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1388 v &= ~HME_MIF_CFG_PHY; 1389 if (phy == HME_PHYAD_EXTERNAL) 1390 v |= HME_MIF_CFG_PHY; 1391 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1392 1393 /* If an external transceiver is selected, enable its MII drivers */ 1394 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1395 v &= ~HME_MAC_XIF_MIIENABLE; 1396 if (phy == HME_PHYAD_EXTERNAL) 1397 v |= HME_MAC_XIF_MIIENABLE; 1398 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1399 1400 return (mii_mediachg(&sc->sc_mii)); 1401 } 1402 1403 void 1404 hme_mediastatus(ifp, ifmr) 1405 struct ifnet *ifp; 1406 struct ifmediareq *ifmr; 1407 { 1408 struct hme_softc *sc = ifp->if_softc; 1409 1410 if ((ifp->if_flags & IFF_UP) == 0) 1411 return; 1412 1413 mii_pollstat(&sc->sc_mii); 1414 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1415 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1416 } 1417 1418 /* 1419 * Process an ioctl request. 1420 */ 1421 int 1422 hme_ioctl(ifp, cmd, data) 1423 struct ifnet *ifp; 1424 u_long cmd; 1425 void *data; 1426 { 1427 struct hme_softc *sc = ifp->if_softc; 1428 struct ifaddr *ifa = (struct ifaddr *)data; 1429 struct ifreq *ifr = (struct ifreq *)data; 1430 int s, error = 0; 1431 1432 s = splnet(); 1433 1434 switch (cmd) { 1435 1436 case SIOCSIFADDR: 1437 switch (ifa->ifa_addr->sa_family) { 1438 #ifdef INET 1439 case AF_INET: 1440 if (ifp->if_flags & IFF_UP) 1441 hme_setladrf(sc); 1442 else { 1443 ifp->if_flags |= IFF_UP; 1444 hme_init(sc); 1445 } 1446 arp_ifinit(ifp, ifa); 1447 break; 1448 #endif 1449 default: 1450 ifp->if_flags |= IFF_UP; 1451 hme_init(sc); 1452 break; 1453 } 1454 break; 1455 1456 case SIOCSIFFLAGS: 1457 #ifdef HMEDEBUG 1458 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1459 #endif 1460 1461 if ((ifp->if_flags & IFF_UP) == 0 && 1462 (ifp->if_flags & IFF_RUNNING) != 0) { 1463 /* 1464 * If interface is marked down and it is running, then 1465 * stop it. 1466 */ 1467 hme_stop(sc, false); 1468 ifp->if_flags &= ~IFF_RUNNING; 1469 } else if ((ifp->if_flags & IFF_UP) != 0 && 1470 (ifp->if_flags & IFF_RUNNING) == 0) { 1471 /* 1472 * If interface is marked up and it is stopped, then 1473 * start it. 1474 */ 1475 hme_init(sc); 1476 } else if ((ifp->if_flags & IFF_UP) != 0) { 1477 /* 1478 * If setting debug or promiscuous mode, do not reset 1479 * the chip; for everything else, call hme_init() 1480 * which will trigger a reset. 1481 */ 1482 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG) 1483 if (ifp->if_flags != sc->sc_if_flags) { 1484 if ((ifp->if_flags & (~RESETIGN)) 1485 == (sc->sc_if_flags & (~RESETIGN))) 1486 hme_setladrf(sc); 1487 else 1488 hme_init(sc); 1489 } 1490 #undef RESETIGN 1491 } 1492 1493 if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable) 1494 hme_init(sc); 1495 1496 break; 1497 1498 case SIOCADDMULTI: 1499 case SIOCDELMULTI: 1500 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1501 /* 1502 * Multicast list has changed; set the hardware filter 1503 * accordingly. 1504 */ 1505 if (ifp->if_flags & IFF_RUNNING) 1506 hme_setladrf(sc); 1507 error = 0; 1508 } 1509 break; 1510 1511 case SIOCGIFMEDIA: 1512 case SIOCSIFMEDIA: 1513 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1514 break; 1515 1516 default: 1517 error = EINVAL; 1518 break; 1519 } 1520 1521 sc->sc_if_flags = ifp->if_flags; 1522 splx(s); 1523 return (error); 1524 } 1525 1526 void 1527 hme_shutdown(arg) 1528 void *arg; 1529 { 1530 1531 hme_stop((struct hme_softc *)arg, false); 1532 } 1533 1534 /* 1535 * Set up the logical address filter. 1536 */ 1537 void 1538 hme_setladrf(sc) 1539 struct hme_softc *sc; 1540 { 1541 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1542 struct ether_multi *enm; 1543 struct ether_multistep step; 1544 struct ethercom *ec = &sc->sc_ethercom; 1545 bus_space_tag_t t = sc->sc_bustag; 1546 bus_space_handle_t mac = sc->sc_mac; 1547 u_char *cp; 1548 u_int32_t crc; 1549 u_int32_t hash[4]; 1550 u_int32_t v; 1551 int len; 1552 1553 /* Clear hash table */ 1554 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1555 1556 /* Get current RX configuration */ 1557 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1558 1559 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1560 /* Turn on promiscuous mode; turn off the hash filter */ 1561 v |= HME_MAC_RXCFG_PMISC; 1562 v &= ~HME_MAC_RXCFG_HENABLE; 1563 ifp->if_flags |= IFF_ALLMULTI; 1564 goto chipit; 1565 } 1566 1567 /* Turn off promiscuous mode; turn on the hash filter */ 1568 v &= ~HME_MAC_RXCFG_PMISC; 1569 v |= HME_MAC_RXCFG_HENABLE; 1570 1571 /* 1572 * Set up multicast address filter by passing all multicast addresses 1573 * through a crc generator, and then using the high order 6 bits as an 1574 * index into the 64 bit logical address filter. The high order bit 1575 * selects the word, while the rest of the bits select the bit within 1576 * the word. 1577 */ 1578 1579 ETHER_FIRST_MULTI(step, ec, enm); 1580 while (enm != NULL) { 1581 if (ether_cmp(enm->enm_addrlo, enm->enm_addrhi)) { 1582 /* 1583 * We must listen to a range of multicast addresses. 1584 * For now, just accept all multicasts, rather than 1585 * trying to set only those filter bits needed to match 1586 * the range. (At this time, the only use of address 1587 * ranges is for IP multicast routing, for which the 1588 * range is big enough to require all bits set.) 1589 */ 1590 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1591 ifp->if_flags |= IFF_ALLMULTI; 1592 goto chipit; 1593 } 1594 1595 cp = enm->enm_addrlo; 1596 crc = 0xffffffff; 1597 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1598 int octet = *cp++; 1599 int i; 1600 1601 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1602 for (i = 0; i < 8; i++) { 1603 if ((crc & 1) ^ (octet & 1)) { 1604 crc >>= 1; 1605 crc ^= MC_POLY_LE; 1606 } else { 1607 crc >>= 1; 1608 } 1609 octet >>= 1; 1610 } 1611 } 1612 /* Just want the 6 most significant bits. */ 1613 crc >>= 26; 1614 1615 /* Set the corresponding bit in the filter. */ 1616 hash[crc >> 4] |= 1 << (crc & 0xf); 1617 1618 ETHER_NEXT_MULTI(step, enm); 1619 } 1620 1621 ifp->if_flags &= ~IFF_ALLMULTI; 1622 1623 chipit: 1624 /* Now load the hash table into the chip */ 1625 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1626 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1627 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1628 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1629 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1630 } 1631 1632 /* 1633 * Routines for accessing the transmit and receive buffers. 1634 * The various CPU and adapter configurations supported by this 1635 * driver require three different access methods for buffers 1636 * and descriptors: 1637 * (1) contig (contiguous data; no padding), 1638 * (2) gap2 (two bytes of data followed by two bytes of padding), 1639 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1640 */ 1641 1642 #if 0 1643 /* 1644 * contig: contiguous data with no padding. 1645 * 1646 * Buffers may have any alignment. 1647 */ 1648 1649 void 1650 hme_copytobuf_contig(sc, from, ri, len) 1651 struct hme_softc *sc; 1652 void *from; 1653 int ri, len; 1654 { 1655 volatile void *buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1656 1657 /* 1658 * Just call memcpy() to do the work. 1659 */ 1660 memcpy(buf, from, len); 1661 } 1662 1663 void 1664 hme_copyfrombuf_contig(sc, to, boff, len) 1665 struct hme_softc *sc; 1666 void *to; 1667 int boff, len; 1668 { 1669 volatile void *buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1670 1671 /* 1672 * Just call memcpy() to do the work. 1673 */ 1674 memcpy(to, buf, len); 1675 } 1676 #endif 1677