1 /* $NetBSD: hme.c,v 1.64 2008/04/08 12:07:26 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * HME Ethernet module driver. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.64 2008/04/08 12:07:26 cegger Exp $"); 45 46 /* #define HMEDEBUG */ 47 48 #include "opt_inet.h" 49 #include "bpfilter.h" 50 #include "rnd.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/mbuf.h> 56 #include <sys/syslog.h> 57 #include <sys/socket.h> 58 #include <sys/device.h> 59 #include <sys/malloc.h> 60 #include <sys/ioctl.h> 61 #include <sys/errno.h> 62 #if NRND > 0 63 #include <sys/rnd.h> 64 #endif 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_ether.h> 69 #include <net/if_media.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/if_inarp.h> 74 #include <netinet/in_systm.h> 75 #include <netinet/in_var.h> 76 #include <netinet/ip.h> 77 #include <netinet/tcp.h> 78 #include <netinet/udp.h> 79 #endif 80 81 82 #if NBPFILTER > 0 83 #include <net/bpf.h> 84 #include <net/bpfdesc.h> 85 #endif 86 87 #include <dev/mii/mii.h> 88 #include <dev/mii/miivar.h> 89 90 #include <sys/bus.h> 91 92 #include <dev/ic/hmereg.h> 93 #include <dev/ic/hmevar.h> 94 95 void hme_start(struct ifnet *); 96 void hme_stop(struct hme_softc *,bool); 97 int hme_ioctl(struct ifnet *, u_long, void *); 98 void hme_tick(void *); 99 void hme_watchdog(struct ifnet *); 100 void hme_shutdown(void *); 101 int hme_init(struct hme_softc *); 102 void hme_meminit(struct hme_softc *); 103 void hme_mifinit(struct hme_softc *); 104 void hme_reset(struct hme_softc *); 105 void hme_setladrf(struct hme_softc *); 106 107 /* MII methods & callbacks */ 108 static int hme_mii_readreg(struct device *, int, int); 109 static void hme_mii_writereg(struct device *, int, int, int); 110 static void hme_mii_statchg(struct device *); 111 112 int hme_mediachange(struct ifnet *); 113 114 struct mbuf *hme_get(struct hme_softc *, int, uint32_t); 115 int hme_put(struct hme_softc *, int, struct mbuf *); 116 void hme_read(struct hme_softc *, int, uint32_t); 117 int hme_eint(struct hme_softc *, u_int); 118 int hme_rint(struct hme_softc *); 119 int hme_tint(struct hme_softc *); 120 121 static int ether_cmp(u_char *, u_char *); 122 123 /* Default buffer copy routines */ 124 void hme_copytobuf_contig(struct hme_softc *, void *, int, int); 125 void hme_copyfrombuf_contig(struct hme_softc *, void *, int, int); 126 void hme_zerobuf_contig(struct hme_softc *, int, int); 127 128 129 void 130 hme_config(sc) 131 struct hme_softc *sc; 132 { 133 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 134 struct mii_data *mii = &sc->sc_mii; 135 struct mii_softc *child; 136 bus_dma_tag_t dmatag = sc->sc_dmatag; 137 bus_dma_segment_t seg; 138 bus_size_t size; 139 int rseg, error; 140 141 /* 142 * HME common initialization. 143 * 144 * hme_softc fields that must be initialized by the front-end: 145 * 146 * the bus tag: 147 * sc_bustag 148 * 149 * the DMA bus tag: 150 * sc_dmatag 151 * 152 * the bus handles: 153 * sc_seb (Shared Ethernet Block registers) 154 * sc_erx (Receiver Unit registers) 155 * sc_etx (Transmitter Unit registers) 156 * sc_mac (MAC registers) 157 * sc_mif (Management Interface registers) 158 * 159 * the maximum bus burst size: 160 * sc_burst 161 * 162 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 163 * rb_membase, rb_dmabase) 164 * 165 * the local Ethernet address: 166 * sc_enaddr 167 * 168 */ 169 170 /* Make sure the chip is stopped. */ 171 hme_stop(sc, true); 172 173 174 /* 175 * Allocate descriptors and buffers 176 * XXX - do all this differently.. and more configurably, 177 * eg. use things as `dma_load_mbuf()' on transmit, 178 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 179 * all the time) on the receiver side. 180 * 181 * Note: receive buffers must be 64-byte aligned. 182 * Also, apparently, the buffers must extend to a DMA burst 183 * boundary beyond the maximum packet size. 184 */ 185 #define _HME_NDESC 128 186 #define _HME_BUFSZ 1600 187 188 /* Note: the # of descriptors must be a multiple of 16 */ 189 sc->sc_rb.rb_ntbuf = _HME_NDESC; 190 sc->sc_rb.rb_nrbuf = _HME_NDESC; 191 192 /* 193 * Allocate DMA capable memory 194 * Buffer descriptors must be aligned on a 2048 byte boundary; 195 * take this into account when calculating the size. Note that 196 * the maximum number of descriptors (256) occupies 2048 bytes, 197 * so we allocate that much regardless of _HME_NDESC. 198 */ 199 size = 2048 + /* TX descriptors */ 200 2048 + /* RX descriptors */ 201 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 202 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* RX buffers */ 203 204 /* Allocate DMA buffer */ 205 if ((error = bus_dmamem_alloc(dmatag, size, 206 2048, 0, 207 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 208 aprint_error_dev(&sc->sc_dev, "DMA buffer alloc error %d\n", 209 error); 210 return; 211 } 212 213 /* Map DMA memory in CPU addressable space */ 214 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 215 &sc->sc_rb.rb_membase, 216 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 217 aprint_error_dev(&sc->sc_dev, "DMA buffer map error %d\n", 218 error); 219 bus_dmamap_unload(dmatag, sc->sc_dmamap); 220 bus_dmamem_free(dmatag, &seg, rseg); 221 return; 222 } 223 224 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 225 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 226 aprint_error_dev(&sc->sc_dev, "DMA map create error %d\n", 227 error); 228 return; 229 } 230 231 /* Load the buffer */ 232 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 233 sc->sc_rb.rb_membase, size, NULL, 234 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 235 aprint_error_dev(&sc->sc_dev, "DMA buffer map load error %d\n", 236 error); 237 bus_dmamem_free(dmatag, &seg, rseg); 238 return; 239 } 240 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 241 242 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 243 ether_sprintf(sc->sc_enaddr)); 244 245 /* Initialize ifnet structure. */ 246 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 247 ifp->if_softc = sc; 248 ifp->if_start = hme_start; 249 ifp->if_ioctl = hme_ioctl; 250 ifp->if_watchdog = hme_watchdog; 251 ifp->if_flags = 252 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 253 sc->sc_if_flags = ifp->if_flags; 254 ifp->if_capabilities |= 255 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 256 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 257 IFQ_SET_READY(&ifp->if_snd); 258 259 /* Initialize ifmedia structures and MII info */ 260 mii->mii_ifp = ifp; 261 mii->mii_readreg = hme_mii_readreg; 262 mii->mii_writereg = hme_mii_writereg; 263 mii->mii_statchg = hme_mii_statchg; 264 265 sc->sc_ethercom.ec_mii = mii; 266 ifmedia_init(&mii->mii_media, 0, hme_mediachange, ether_mediastatus); 267 268 hme_mifinit(sc); 269 270 mii_attach(&sc->sc_dev, mii, 0xffffffff, 271 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 272 273 child = LIST_FIRST(&mii->mii_phys); 274 if (child == NULL) { 275 /* No PHY attached */ 276 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 277 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 278 } else { 279 /* 280 * Walk along the list of attached MII devices and 281 * establish an `MII instance' to `phy number' 282 * mapping. We'll use this mapping in media change 283 * requests to determine which phy to use to program 284 * the MIF configuration register. 285 */ 286 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 287 /* 288 * Note: we support just two PHYs: the built-in 289 * internal device and an external on the MII 290 * connector. 291 */ 292 if (child->mii_phy > 1 || child->mii_inst > 1) { 293 aprint_error_dev(&sc->sc_dev, "cannot accommodate MII device %s" 294 " at phy %d, instance %d\n", 295 device_xname(&child->mii_dev), 296 child->mii_phy, child->mii_inst); 297 continue; 298 } 299 300 sc->sc_phys[child->mii_inst] = child->mii_phy; 301 } 302 303 /* 304 * XXX - we can really do the following ONLY if the 305 * phy indeed has the auto negotiation capability!! 306 */ 307 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 308 } 309 310 /* claim 802.1q capability */ 311 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 312 313 /* Attach the interface. */ 314 if_attach(ifp); 315 ether_ifattach(ifp, sc->sc_enaddr); 316 317 sc->sc_sh = shutdownhook_establish(hme_shutdown, sc); 318 if (sc->sc_sh == NULL) 319 panic("hme_config: can't establish shutdownhook"); 320 321 #if NRND > 0 322 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 323 RND_TYPE_NET, 0); 324 #endif 325 326 callout_init(&sc->sc_tick_ch, 0); 327 } 328 329 void 330 hme_tick(arg) 331 void *arg; 332 { 333 struct hme_softc *sc = arg; 334 int s; 335 336 s = splnet(); 337 mii_tick(&sc->sc_mii); 338 splx(s); 339 340 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 341 } 342 343 void 344 hme_reset(sc) 345 struct hme_softc *sc; 346 { 347 int s; 348 349 s = splnet(); 350 (void)hme_init(sc); 351 splx(s); 352 } 353 354 void 355 hme_stop(struct hme_softc *sc, bool chip_only) 356 { 357 bus_space_tag_t t = sc->sc_bustag; 358 bus_space_handle_t seb = sc->sc_seb; 359 int n; 360 361 if (!chip_only) { 362 callout_stop(&sc->sc_tick_ch); 363 mii_down(&sc->sc_mii); 364 } 365 366 /* Mask all interrupts */ 367 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff); 368 369 /* Reset transmitter and receiver */ 370 bus_space_write_4(t, seb, HME_SEBI_RESET, 371 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 372 373 for (n = 0; n < 20; n++) { 374 u_int32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 375 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 376 return; 377 DELAY(20); 378 } 379 380 printf("%s: hme_stop: reset failed\n", device_xname(&sc->sc_dev)); 381 } 382 383 void 384 hme_meminit(sc) 385 struct hme_softc *sc; 386 { 387 bus_addr_t txbufdma, rxbufdma; 388 bus_addr_t dma; 389 char *p; 390 unsigned int ntbuf, nrbuf, i; 391 struct hme_ring *hr = &sc->sc_rb; 392 393 p = hr->rb_membase; 394 dma = hr->rb_dmabase; 395 396 ntbuf = hr->rb_ntbuf; 397 nrbuf = hr->rb_nrbuf; 398 399 /* 400 * Allocate transmit descriptors 401 */ 402 hr->rb_txd = p; 403 hr->rb_txddma = dma; 404 p += ntbuf * HME_XD_SIZE; 405 dma += ntbuf * HME_XD_SIZE; 406 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 407 dma = (bus_addr_t)roundup((u_long)dma, 2048); 408 p = (void *)roundup((u_long)p, 2048); 409 410 /* 411 * Allocate receive descriptors 412 */ 413 hr->rb_rxd = p; 414 hr->rb_rxddma = dma; 415 p += nrbuf * HME_XD_SIZE; 416 dma += nrbuf * HME_XD_SIZE; 417 /* Again move forward to the next 2048 byte boundary.*/ 418 dma = (bus_addr_t)roundup((u_long)dma, 2048); 419 p = (void *)roundup((u_long)p, 2048); 420 421 422 /* 423 * Allocate transmit buffers 424 */ 425 hr->rb_txbuf = p; 426 txbufdma = dma; 427 p += ntbuf * _HME_BUFSZ; 428 dma += ntbuf * _HME_BUFSZ; 429 430 /* 431 * Allocate receive buffers 432 */ 433 hr->rb_rxbuf = p; 434 rxbufdma = dma; 435 p += nrbuf * _HME_BUFSZ; 436 dma += nrbuf * _HME_BUFSZ; 437 438 /* 439 * Initialize transmit buffer descriptors 440 */ 441 for (i = 0; i < ntbuf; i++) { 442 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 443 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 444 } 445 446 /* 447 * Initialize receive buffer descriptors 448 */ 449 for (i = 0; i < nrbuf; i++) { 450 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 451 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 452 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 453 } 454 455 hr->rb_tdhead = hr->rb_tdtail = 0; 456 hr->rb_td_nbusy = 0; 457 hr->rb_rdtail = 0; 458 } 459 460 /* 461 * Initialization of interface; set up initialization block 462 * and transmit/receive descriptor rings. 463 */ 464 int 465 hme_init(sc) 466 struct hme_softc *sc; 467 { 468 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 469 bus_space_tag_t t = sc->sc_bustag; 470 bus_space_handle_t seb = sc->sc_seb; 471 bus_space_handle_t etx = sc->sc_etx; 472 bus_space_handle_t erx = sc->sc_erx; 473 bus_space_handle_t mac = sc->sc_mac; 474 u_int8_t *ea; 475 u_int32_t v; 476 int rc; 477 478 /* 479 * Initialization sequence. The numbered steps below correspond 480 * to the sequence outlined in section 6.3.5.1 in the Ethernet 481 * Channel Engine manual (part of the PCIO manual). 482 * See also the STP2002-STQ document from Sun Microsystems. 483 */ 484 485 /* step 1 & 2. Reset the Ethernet Channel */ 486 hme_stop(sc, false); 487 488 /* Re-initialize the MIF */ 489 hme_mifinit(sc); 490 491 /* Call MI reset function if any */ 492 if (sc->sc_hwreset) 493 (*sc->sc_hwreset)(sc); 494 495 #if 0 496 /* Mask all MIF interrupts, just in case */ 497 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 498 #endif 499 500 /* step 3. Setup data structures in host memory */ 501 hme_meminit(sc); 502 503 /* step 4. TX MAC registers & counters */ 504 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 505 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 506 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 507 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 508 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 509 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 510 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 511 sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable; 512 513 /* Load station MAC address */ 514 ea = sc->sc_enaddr; 515 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 516 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 517 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 518 519 /* 520 * Init seed for backoff 521 * (source suggested by manual: low 10 bits of MAC address) 522 */ 523 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 524 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 525 526 527 /* Note: Accepting power-on default for other MAC registers here.. */ 528 529 530 /* step 5. RX MAC registers & counters */ 531 hme_setladrf(sc); 532 533 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 534 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 535 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 536 537 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 538 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 539 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 540 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 541 542 /* step 8. Global Configuration & Interrupt Mask */ 543 bus_space_write_4(t, seb, HME_SEBI_IMASK, 544 ~( 545 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 546 HME_SEB_STAT_HOSTTOTX | 547 HME_SEB_STAT_RXTOHOST | 548 HME_SEB_STAT_TXALL | 549 HME_SEB_STAT_TXPERR | 550 HME_SEB_STAT_RCNTEXP | 551 /*HME_SEB_STAT_MIFIRQ |*/ 552 HME_SEB_STAT_ALL_ERRORS )); 553 554 switch (sc->sc_burst) { 555 default: 556 v = 0; 557 break; 558 case 16: 559 v = HME_SEB_CFG_BURST16; 560 break; 561 case 32: 562 v = HME_SEB_CFG_BURST32; 563 break; 564 case 64: 565 v = HME_SEB_CFG_BURST64; 566 break; 567 } 568 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 569 570 /* step 9. ETX Configuration: use mostly default values */ 571 572 /* Enable DMA */ 573 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 574 v |= HME_ETX_CFG_DMAENABLE; 575 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 576 577 /* Transmit Descriptor ring size: in increments of 16 */ 578 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 579 580 581 /* step 10. ERX Configuration */ 582 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 583 584 /* Encode Receive Descriptor ring size: four possible values */ 585 switch (_HME_NDESC /*XXX*/) { 586 case 32: 587 v |= HME_ERX_CFG_RINGSIZE32; 588 break; 589 case 64: 590 v |= HME_ERX_CFG_RINGSIZE64; 591 break; 592 case 128: 593 v |= HME_ERX_CFG_RINGSIZE128; 594 break; 595 case 256: 596 v |= HME_ERX_CFG_RINGSIZE256; 597 break; 598 default: 599 printf("hme: invalid Receive Descriptor ring size\n"); 600 break; 601 } 602 603 /* Enable DMA */ 604 v |= HME_ERX_CFG_DMAENABLE; 605 606 /* set h/w rx checksum start offset (# of half-words) */ 607 #ifdef INET 608 v |= (((ETHER_HDR_LEN + sizeof(struct ip) + 609 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 610 ETHER_VLAN_ENCAP_LEN : 0)) / 2) << HME_ERX_CFG_CSUMSHIFT) & 611 HME_ERX_CFG_CSUMSTART; 612 #endif 613 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 614 615 /* step 11. XIF Configuration */ 616 v = bus_space_read_4(t, mac, HME_MACI_XIF); 617 v |= HME_MAC_XIF_OE; 618 bus_space_write_4(t, mac, HME_MACI_XIF, v); 619 620 /* step 12. RX_MAC Configuration Register */ 621 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 622 v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP; 623 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 624 625 /* step 13. TX_MAC Configuration Register */ 626 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 627 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 628 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 629 630 /* step 14. Issue Transmit Pending command */ 631 632 /* Call MI initialization function if any */ 633 if (sc->sc_hwinit) 634 (*sc->sc_hwinit)(sc); 635 636 /* Set the current media. */ 637 if ((rc = hme_mediachange(ifp)) != 0) 638 return rc; 639 640 /* Start the one second timer. */ 641 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 642 643 ifp->if_flags |= IFF_RUNNING; 644 ifp->if_flags &= ~IFF_OACTIVE; 645 sc->sc_if_flags = ifp->if_flags; 646 ifp->if_timer = 0; 647 hme_start(ifp); 648 return 0; 649 } 650 651 /* 652 * Compare two Ether/802 addresses for equality, inlined and unrolled for 653 * speed. 654 */ 655 static inline int 656 ether_cmp(a, b) 657 u_char *a, *b; 658 { 659 660 if (a[5] != b[5] || a[4] != b[4] || a[3] != b[3] || 661 a[2] != b[2] || a[1] != b[1] || a[0] != b[0]) 662 return (0); 663 return (1); 664 } 665 666 667 /* 668 * Routine to copy from mbuf chain to transmit buffer in 669 * network buffer memory. 670 * Returns the amount of data copied. 671 */ 672 int 673 hme_put(sc, ri, m) 674 struct hme_softc *sc; 675 int ri; /* Ring index */ 676 struct mbuf *m; 677 { 678 struct mbuf *n; 679 int len, tlen = 0; 680 char *bp; 681 682 bp = (char *)sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 683 for (; m; m = n) { 684 len = m->m_len; 685 if (len == 0) { 686 MFREE(m, n); 687 continue; 688 } 689 memcpy(bp, mtod(m, void *), len); 690 bp += len; 691 tlen += len; 692 MFREE(m, n); 693 } 694 return (tlen); 695 } 696 697 /* 698 * Pull data off an interface. 699 * Len is length of data, with local net header stripped. 700 * We copy the data into mbufs. When full cluster sized units are present 701 * we copy into clusters. 702 */ 703 struct mbuf * 704 hme_get(sc, ri, flags) 705 struct hme_softc *sc; 706 int ri; 707 u_int32_t flags; 708 { 709 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 710 struct mbuf *m, *m0, *newm; 711 char *bp; 712 int len, totlen; 713 714 totlen = HME_XD_DECODE_RSIZE(flags); 715 MGETHDR(m0, M_DONTWAIT, MT_DATA); 716 if (m0 == 0) 717 return (0); 718 m0->m_pkthdr.rcvif = ifp; 719 m0->m_pkthdr.len = totlen; 720 len = MHLEN; 721 m = m0; 722 723 bp = (char *)sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 724 725 while (totlen > 0) { 726 if (totlen >= MINCLSIZE) { 727 MCLGET(m, M_DONTWAIT); 728 if ((m->m_flags & M_EXT) == 0) 729 goto bad; 730 len = MCLBYTES; 731 } 732 733 if (m == m0) { 734 char *newdata = (char *) 735 ALIGN(m->m_data + sizeof(struct ether_header)) - 736 sizeof(struct ether_header); 737 len -= newdata - m->m_data; 738 m->m_data = newdata; 739 } 740 741 m->m_len = len = min(totlen, len); 742 memcpy(mtod(m, void *), bp, len); 743 bp += len; 744 745 totlen -= len; 746 if (totlen > 0) { 747 MGET(newm, M_DONTWAIT, MT_DATA); 748 if (newm == 0) 749 goto bad; 750 len = MLEN; 751 m = m->m_next = newm; 752 } 753 } 754 755 #ifdef INET 756 /* hardware checksum */ 757 if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 758 struct ether_header *eh; 759 struct ip *ip; 760 struct udphdr *uh; 761 uint16_t *opts; 762 int32_t hlen, pktlen; 763 uint32_t temp; 764 765 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 766 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN - 767 ETHER_VLAN_ENCAP_LEN; 768 eh = (struct ether_header *) mtod(m0, void *) + 769 ETHER_VLAN_ENCAP_LEN; 770 } else { 771 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN; 772 eh = mtod(m0, struct ether_header *); 773 } 774 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 775 goto swcsum; 776 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 777 778 /* IPv4 only */ 779 if (ip->ip_v != IPVERSION) 780 goto swcsum; 781 782 hlen = ip->ip_hl << 2; 783 if (hlen < sizeof(struct ip)) 784 goto swcsum; 785 786 /* 787 * bail if too short, has random trailing garbage, truncated, 788 * fragment, or has ethernet pad. 789 */ 790 if ((ntohs(ip->ip_len) < hlen) || (ntohs(ip->ip_len) != pktlen) 791 || (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 792 goto swcsum; 793 794 switch (ip->ip_p) { 795 case IPPROTO_TCP: 796 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 797 goto swcsum; 798 if (pktlen < (hlen + sizeof(struct tcphdr))) 799 goto swcsum; 800 m0->m_pkthdr.csum_flags = M_CSUM_TCPv4; 801 break; 802 case IPPROTO_UDP: 803 if (! (ifp->if_csum_flags_rx & M_CSUM_UDPv4)) 804 goto swcsum; 805 if (pktlen < (hlen + sizeof(struct udphdr))) 806 goto swcsum; 807 uh = (struct udphdr *)((char *)ip + hlen); 808 /* no checksum */ 809 if (uh->uh_sum == 0) 810 goto swcsum; 811 m0->m_pkthdr.csum_flags = M_CSUM_UDPv4; 812 break; 813 default: 814 goto swcsum; 815 } 816 817 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */ 818 m0->m_pkthdr.csum_data = (~flags) & HME_XD_RXCKSUM; 819 820 /* if the pkt had ip options, we have to deduct them */ 821 if (hlen > sizeof(struct ip)) { 822 uint32_t optsum; 823 824 optsum = 0; 825 temp = hlen - sizeof(struct ip); 826 opts = (uint16_t *)((char *)ip + sizeof(struct ip)); 827 828 while (temp > 1) { 829 optsum += ntohs(*opts++); 830 temp -= 2; 831 } 832 while (optsum >> 16) 833 optsum = (optsum >> 16) + (optsum & 0xffff); 834 835 /* Deduct the ip opts sum from the hwsum (rfc 1624). */ 836 m0->m_pkthdr.csum_data = ~((~m0->m_pkthdr.csum_data) - 837 ~optsum); 838 839 while (m0->m_pkthdr.csum_data >> 16) 840 m0->m_pkthdr.csum_data = 841 (m0->m_pkthdr.csum_data >> 16) + 842 (m0->m_pkthdr.csum_data & 0xffff); 843 } 844 845 m0->m_pkthdr.csum_flags |= M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 846 } 847 swcsum: 848 m0->m_pkthdr.csum_flags = 0; 849 #endif 850 851 return (m0); 852 853 bad: 854 m_freem(m0); 855 return (0); 856 } 857 858 /* 859 * Pass a packet to the higher levels. 860 */ 861 void 862 hme_read(sc, ix, flags) 863 struct hme_softc *sc; 864 int ix; 865 u_int32_t flags; 866 { 867 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 868 struct mbuf *m; 869 int len; 870 871 len = HME_XD_DECODE_RSIZE(flags); 872 if (len <= sizeof(struct ether_header) || 873 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 874 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 875 ETHERMTU + sizeof(struct ether_header))) { 876 #ifdef HMEDEBUG 877 printf("%s: invalid packet size %d; dropping\n", 878 device_xname(&sc->sc_dev), len); 879 #endif 880 ifp->if_ierrors++; 881 return; 882 } 883 884 /* Pull packet off interface. */ 885 m = hme_get(sc, ix, flags); 886 if (m == 0) { 887 ifp->if_ierrors++; 888 return; 889 } 890 891 ifp->if_ipackets++; 892 893 #if NBPFILTER > 0 894 /* 895 * Check if there's a BPF listener on this interface. 896 * If so, hand off the raw packet to BPF. 897 */ 898 if (ifp->if_bpf) 899 bpf_mtap(ifp->if_bpf, m); 900 #endif 901 902 /* Pass the packet up. */ 903 (*ifp->if_input)(ifp, m); 904 } 905 906 void 907 hme_start(ifp) 908 struct ifnet *ifp; 909 { 910 struct hme_softc *sc = (struct hme_softc *)ifp->if_softc; 911 void *txd = sc->sc_rb.rb_txd; 912 struct mbuf *m; 913 unsigned int txflags; 914 unsigned int ri, len; 915 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 916 917 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 918 return; 919 920 ri = sc->sc_rb.rb_tdhead; 921 922 for (;;) { 923 IFQ_DEQUEUE(&ifp->if_snd, m); 924 if (m == 0) 925 break; 926 927 #if NBPFILTER > 0 928 /* 929 * If BPF is listening on this interface, let it see the 930 * packet before we commit it to the wire. 931 */ 932 if (ifp->if_bpf) 933 bpf_mtap(ifp->if_bpf, m); 934 #endif 935 936 #ifdef INET 937 /* collect bits for h/w csum, before hme_put frees the mbuf */ 938 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) && 939 m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 940 struct ether_header *eh; 941 uint16_t offset, start; 942 943 eh = mtod(m, struct ether_header *); 944 switch (ntohs(eh->ether_type)) { 945 case ETHERTYPE_IP: 946 start = ETHER_HDR_LEN; 947 break; 948 case ETHERTYPE_VLAN: 949 start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 950 break; 951 default: 952 /* unsupported, drop it */ 953 m_free(m); 954 continue; 955 } 956 start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 957 offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data) 958 + start; 959 txflags = HME_XD_TXCKSUM | 960 (offset << HME_XD_TXCSSTUFFSHIFT) | 961 (start << HME_XD_TXCSSTARTSHIFT); 962 } else 963 #endif 964 txflags = 0; 965 966 /* 967 * Copy the mbuf chain into the transmit buffer. 968 */ 969 len = hme_put(sc, ri, m); 970 971 /* 972 * Initialize transmit registers and start transmission 973 */ 974 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 975 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 976 HME_XD_ENCODE_TSIZE(len) | txflags); 977 978 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 979 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 980 HME_ETX_TP_DMAWAKEUP); 981 982 if (++ri == ntbuf) 983 ri = 0; 984 985 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 986 ifp->if_flags |= IFF_OACTIVE; 987 break; 988 } 989 } 990 991 sc->sc_rb.rb_tdhead = ri; 992 } 993 994 /* 995 * Transmit interrupt. 996 */ 997 int 998 hme_tint(sc) 999 struct hme_softc *sc; 1000 { 1001 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1002 bus_space_tag_t t = sc->sc_bustag; 1003 bus_space_handle_t mac = sc->sc_mac; 1004 unsigned int ri, txflags; 1005 1006 /* 1007 * Unload collision counters 1008 */ 1009 ifp->if_collisions += 1010 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 1011 bus_space_read_4(t, mac, HME_MACI_FCCNT) + 1012 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 1013 bus_space_read_4(t, mac, HME_MACI_LTCNT); 1014 1015 /* 1016 * then clear the hardware counters. 1017 */ 1018 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 1019 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 1020 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 1021 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 1022 1023 /* Fetch current position in the transmit ring */ 1024 ri = sc->sc_rb.rb_tdtail; 1025 1026 for (;;) { 1027 if (sc->sc_rb.rb_td_nbusy <= 0) 1028 break; 1029 1030 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 1031 1032 if (txflags & HME_XD_OWN) 1033 break; 1034 1035 ifp->if_flags &= ~IFF_OACTIVE; 1036 ifp->if_opackets++; 1037 1038 if (++ri == sc->sc_rb.rb_ntbuf) 1039 ri = 0; 1040 1041 --sc->sc_rb.rb_td_nbusy; 1042 } 1043 1044 /* Update ring */ 1045 sc->sc_rb.rb_tdtail = ri; 1046 1047 hme_start(ifp); 1048 1049 if (sc->sc_rb.rb_td_nbusy == 0) 1050 ifp->if_timer = 0; 1051 1052 return (1); 1053 } 1054 1055 /* 1056 * Receive interrupt. 1057 */ 1058 int 1059 hme_rint(sc) 1060 struct hme_softc *sc; 1061 { 1062 void *xdr = sc->sc_rb.rb_rxd; 1063 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 1064 unsigned int ri; 1065 u_int32_t flags; 1066 1067 ri = sc->sc_rb.rb_rdtail; 1068 1069 /* 1070 * Process all buffers with valid data. 1071 */ 1072 for (;;) { 1073 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 1074 if (flags & HME_XD_OWN) 1075 break; 1076 1077 if (flags & HME_XD_OFL) { 1078 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 1079 device_xname(&sc->sc_dev), ri, flags); 1080 } else 1081 hme_read(sc, ri, flags); 1082 1083 /* This buffer can be used by the hardware again */ 1084 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 1085 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 1086 1087 if (++ri == nrbuf) 1088 ri = 0; 1089 } 1090 1091 sc->sc_rb.rb_rdtail = ri; 1092 1093 return (1); 1094 } 1095 1096 int 1097 hme_eint(sc, status) 1098 struct hme_softc *sc; 1099 u_int status; 1100 { 1101 char bits[128]; 1102 1103 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 1104 bus_space_tag_t t = sc->sc_bustag; 1105 bus_space_handle_t mif = sc->sc_mif; 1106 u_int32_t cf, st, sm; 1107 cf = bus_space_read_4(t, mif, HME_MIFI_CFG); 1108 st = bus_space_read_4(t, mif, HME_MIFI_STAT); 1109 sm = bus_space_read_4(t, mif, HME_MIFI_SM); 1110 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n", 1111 device_xname(&sc->sc_dev), cf, st, sm); 1112 return (1); 1113 } 1114 1115 printf("%s: status=%s\n", device_xname(&sc->sc_dev), 1116 bitmask_snprintf(status, HME_SEB_STAT_BITS, bits,sizeof(bits))); 1117 return (1); 1118 } 1119 1120 int 1121 hme_intr(v) 1122 void *v; 1123 { 1124 struct hme_softc *sc = (struct hme_softc *)v; 1125 bus_space_tag_t t = sc->sc_bustag; 1126 bus_space_handle_t seb = sc->sc_seb; 1127 u_int32_t status; 1128 int r = 0; 1129 1130 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 1131 1132 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 1133 r |= hme_eint(sc, status); 1134 1135 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 1136 r |= hme_tint(sc); 1137 1138 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1139 r |= hme_rint(sc); 1140 1141 #if NRND > 0 1142 rnd_add_uint32(&sc->rnd_source, status); 1143 #endif 1144 1145 return (r); 1146 } 1147 1148 1149 void 1150 hme_watchdog(ifp) 1151 struct ifnet *ifp; 1152 { 1153 struct hme_softc *sc = ifp->if_softc; 1154 1155 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev)); 1156 ++ifp->if_oerrors; 1157 1158 hme_reset(sc); 1159 } 1160 1161 /* 1162 * Initialize the MII Management Interface 1163 */ 1164 void 1165 hme_mifinit(sc) 1166 struct hme_softc *sc; 1167 { 1168 bus_space_tag_t t = sc->sc_bustag; 1169 bus_space_handle_t mif = sc->sc_mif; 1170 bus_space_handle_t mac = sc->sc_mac; 1171 int instance, phy; 1172 u_int32_t v; 1173 1174 if (sc->sc_mii.mii_media.ifm_cur != NULL) { 1175 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1176 phy = sc->sc_phys[instance]; 1177 } else 1178 /* No media set yet, pick phy arbitrarily.. */ 1179 phy = HME_PHYAD_EXTERNAL; 1180 1181 /* Configure the MIF in frame mode, no poll, current phy select */ 1182 v = 0; 1183 if (phy == HME_PHYAD_EXTERNAL) 1184 v |= HME_MIF_CFG_PHY; 1185 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1186 1187 /* If an external transceiver is selected, enable its MII drivers */ 1188 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1189 v &= ~HME_MAC_XIF_MIIENABLE; 1190 if (phy == HME_PHYAD_EXTERNAL) 1191 v |= HME_MAC_XIF_MIIENABLE; 1192 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1193 } 1194 1195 /* 1196 * MII interface 1197 */ 1198 static int 1199 hme_mii_readreg(self, phy, reg) 1200 struct device *self; 1201 int phy, reg; 1202 { 1203 struct hme_softc *sc = (void *)self; 1204 bus_space_tag_t t = sc->sc_bustag; 1205 bus_space_handle_t mif = sc->sc_mif; 1206 bus_space_handle_t mac = sc->sc_mac; 1207 u_int32_t v, xif_cfg, mifi_cfg; 1208 int n; 1209 1210 /* We can at most have two PHYs */ 1211 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1212 return (0); 1213 1214 /* Select the desired PHY in the MIF configuration register */ 1215 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1216 v &= ~HME_MIF_CFG_PHY; 1217 if (phy == HME_PHYAD_EXTERNAL) 1218 v |= HME_MIF_CFG_PHY; 1219 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1220 1221 /* Enable MII drivers on external transceiver */ 1222 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1223 if (phy == HME_PHYAD_EXTERNAL) 1224 v |= HME_MAC_XIF_MIIENABLE; 1225 else 1226 v &= ~HME_MAC_XIF_MIIENABLE; 1227 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1228 1229 #if 0 1230 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1231 /* 1232 * Check whether a transceiver is connected by testing 1233 * the MIF configuration register's MDI_X bits. Note that 1234 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1235 */ 1236 mif_mdi_bit = 1 << (8 + (1 - phy)); 1237 delay(100); 1238 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1239 if ((v & mif_mdi_bit) == 0) 1240 return (0); 1241 #endif 1242 1243 /* Construct the frame command */ 1244 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1245 HME_MIF_FO_TAMSB | 1246 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1247 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1248 (reg << HME_MIF_FO_REGAD_SHIFT); 1249 1250 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1251 for (n = 0; n < 100; n++) { 1252 DELAY(1); 1253 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1254 if (v & HME_MIF_FO_TALSB) { 1255 v &= HME_MIF_FO_DATA; 1256 goto out; 1257 } 1258 } 1259 1260 v = 0; 1261 printf("%s: mii_read timeout\n", device_xname(&sc->sc_dev)); 1262 1263 out: 1264 /* Restore MIFI_CFG register */ 1265 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1266 /* Restore XIF register */ 1267 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1268 return (v); 1269 } 1270 1271 static void 1272 hme_mii_writereg(self, phy, reg, val) 1273 struct device *self; 1274 int phy, reg, val; 1275 { 1276 struct hme_softc *sc = (void *)self; 1277 bus_space_tag_t t = sc->sc_bustag; 1278 bus_space_handle_t mif = sc->sc_mif; 1279 bus_space_handle_t mac = sc->sc_mac; 1280 u_int32_t v, xif_cfg, mifi_cfg; 1281 int n; 1282 1283 /* We can at most have two PHYs */ 1284 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1285 return; 1286 1287 /* Select the desired PHY in the MIF configuration register */ 1288 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1289 v &= ~HME_MIF_CFG_PHY; 1290 if (phy == HME_PHYAD_EXTERNAL) 1291 v |= HME_MIF_CFG_PHY; 1292 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1293 1294 /* Enable MII drivers on external transceiver */ 1295 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1296 if (phy == HME_PHYAD_EXTERNAL) 1297 v |= HME_MAC_XIF_MIIENABLE; 1298 else 1299 v &= ~HME_MAC_XIF_MIIENABLE; 1300 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1301 1302 #if 0 1303 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1304 /* 1305 * Check whether a transceiver is connected by testing 1306 * the MIF configuration register's MDI_X bits. Note that 1307 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1308 */ 1309 mif_mdi_bit = 1 << (8 + (1 - phy)); 1310 delay(100); 1311 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1312 if ((v & mif_mdi_bit) == 0) 1313 return; 1314 #endif 1315 1316 /* Construct the frame command */ 1317 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1318 HME_MIF_FO_TAMSB | 1319 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1320 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1321 (reg << HME_MIF_FO_REGAD_SHIFT) | 1322 (val & HME_MIF_FO_DATA); 1323 1324 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1325 for (n = 0; n < 100; n++) { 1326 DELAY(1); 1327 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1328 if (v & HME_MIF_FO_TALSB) 1329 goto out; 1330 } 1331 1332 printf("%s: mii_write timeout\n", device_xname(&sc->sc_dev)); 1333 out: 1334 /* Restore MIFI_CFG register */ 1335 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1336 /* Restore XIF register */ 1337 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1338 } 1339 1340 static void 1341 hme_mii_statchg(dev) 1342 struct device *dev; 1343 { 1344 struct hme_softc *sc = (void *)dev; 1345 bus_space_tag_t t = sc->sc_bustag; 1346 bus_space_handle_t mac = sc->sc_mac; 1347 u_int32_t v; 1348 1349 #ifdef HMEDEBUG 1350 if (sc->sc_debug) 1351 printf("hme_mii_statchg: status change\n"); 1352 #endif 1353 1354 /* Set the MAC Full Duplex bit appropriately */ 1355 /* Apparently the hme chip is SIMPLEX if working in full duplex mode, 1356 but not otherwise. */ 1357 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1358 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1359 v |= HME_MAC_TXCFG_FULLDPLX; 1360 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX; 1361 } else { 1362 v &= ~HME_MAC_TXCFG_FULLDPLX; 1363 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX; 1364 } 1365 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags; 1366 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1367 } 1368 1369 int 1370 hme_mediachange(ifp) 1371 struct ifnet *ifp; 1372 { 1373 struct hme_softc *sc = ifp->if_softc; 1374 bus_space_tag_t t = sc->sc_bustag; 1375 bus_space_handle_t mif = sc->sc_mif; 1376 bus_space_handle_t mac = sc->sc_mac; 1377 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1378 int phy = sc->sc_phys[instance]; 1379 int rc; 1380 u_int32_t v; 1381 1382 #ifdef HMEDEBUG 1383 if (sc->sc_debug) 1384 printf("hme_mediachange: phy = %d\n", phy); 1385 #endif 1386 1387 /* Select the current PHY in the MIF configuration register */ 1388 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1389 v &= ~HME_MIF_CFG_PHY; 1390 if (phy == HME_PHYAD_EXTERNAL) 1391 v |= HME_MIF_CFG_PHY; 1392 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1393 1394 /* If an external transceiver is selected, enable its MII drivers */ 1395 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1396 v &= ~HME_MAC_XIF_MIIENABLE; 1397 if (phy == HME_PHYAD_EXTERNAL) 1398 v |= HME_MAC_XIF_MIIENABLE; 1399 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1400 1401 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 1402 return 0; 1403 return rc; 1404 } 1405 1406 /* 1407 * Process an ioctl request. 1408 */ 1409 int 1410 hme_ioctl(ifp, cmd, data) 1411 struct ifnet *ifp; 1412 u_long cmd; 1413 void *data; 1414 { 1415 struct hme_softc *sc = ifp->if_softc; 1416 struct ifaddr *ifa = (struct ifaddr *)data; 1417 int s, error = 0; 1418 1419 s = splnet(); 1420 1421 switch (cmd) { 1422 1423 case SIOCSIFADDR: 1424 switch (ifa->ifa_addr->sa_family) { 1425 #ifdef INET 1426 case AF_INET: 1427 if (ifp->if_flags & IFF_UP) 1428 hme_setladrf(sc); 1429 else { 1430 ifp->if_flags |= IFF_UP; 1431 error = hme_init(sc); 1432 } 1433 arp_ifinit(ifp, ifa); 1434 break; 1435 #endif 1436 default: 1437 ifp->if_flags |= IFF_UP; 1438 error = hme_init(sc); 1439 break; 1440 } 1441 break; 1442 1443 case SIOCSIFFLAGS: 1444 #ifdef HMEDEBUG 1445 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1446 #endif 1447 1448 if ((ifp->if_flags & IFF_UP) == 0 && 1449 (ifp->if_flags & IFF_RUNNING) != 0) { 1450 /* 1451 * If interface is marked down and it is running, then 1452 * stop it. 1453 */ 1454 hme_stop(sc, false); 1455 ifp->if_flags &= ~IFF_RUNNING; 1456 } else if ((ifp->if_flags & IFF_UP) != 0 && 1457 (ifp->if_flags & IFF_RUNNING) == 0) { 1458 /* 1459 * If interface is marked up and it is stopped, then 1460 * start it. 1461 */ 1462 error = hme_init(sc); 1463 } else if ((ifp->if_flags & IFF_UP) != 0) { 1464 /* 1465 * If setting debug or promiscuous mode, do not reset 1466 * the chip; for everything else, call hme_init() 1467 * which will trigger a reset. 1468 */ 1469 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG) 1470 if (ifp->if_flags != sc->sc_if_flags) { 1471 if ((ifp->if_flags & (~RESETIGN)) 1472 == (sc->sc_if_flags & (~RESETIGN))) 1473 hme_setladrf(sc); 1474 else 1475 error = hme_init(sc); 1476 } 1477 #undef RESETIGN 1478 } 1479 1480 if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable) 1481 error = hme_init(sc); 1482 1483 break; 1484 1485 default: 1486 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1487 break; 1488 1489 error = 0; 1490 1491 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1492 ; 1493 else if (ifp->if_flags & IFF_RUNNING) { 1494 /* 1495 * Multicast list has changed; set the hardware filter 1496 * accordingly. 1497 */ 1498 hme_setladrf(sc); 1499 } 1500 break; 1501 } 1502 1503 sc->sc_if_flags = ifp->if_flags; 1504 splx(s); 1505 return (error); 1506 } 1507 1508 void 1509 hme_shutdown(arg) 1510 void *arg; 1511 { 1512 1513 hme_stop((struct hme_softc *)arg, false); 1514 } 1515 1516 /* 1517 * Set up the logical address filter. 1518 */ 1519 void 1520 hme_setladrf(sc) 1521 struct hme_softc *sc; 1522 { 1523 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1524 struct ether_multi *enm; 1525 struct ether_multistep step; 1526 struct ethercom *ec = &sc->sc_ethercom; 1527 bus_space_tag_t t = sc->sc_bustag; 1528 bus_space_handle_t mac = sc->sc_mac; 1529 u_char *cp; 1530 u_int32_t crc; 1531 u_int32_t hash[4]; 1532 u_int32_t v; 1533 int len; 1534 1535 /* Clear hash table */ 1536 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1537 1538 /* Get current RX configuration */ 1539 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1540 1541 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1542 /* Turn on promiscuous mode; turn off the hash filter */ 1543 v |= HME_MAC_RXCFG_PMISC; 1544 v &= ~HME_MAC_RXCFG_HENABLE; 1545 ifp->if_flags |= IFF_ALLMULTI; 1546 goto chipit; 1547 } 1548 1549 /* Turn off promiscuous mode; turn on the hash filter */ 1550 v &= ~HME_MAC_RXCFG_PMISC; 1551 v |= HME_MAC_RXCFG_HENABLE; 1552 1553 /* 1554 * Set up multicast address filter by passing all multicast addresses 1555 * through a crc generator, and then using the high order 6 bits as an 1556 * index into the 64 bit logical address filter. The high order bit 1557 * selects the word, while the rest of the bits select the bit within 1558 * the word. 1559 */ 1560 1561 ETHER_FIRST_MULTI(step, ec, enm); 1562 while (enm != NULL) { 1563 if (ether_cmp(enm->enm_addrlo, enm->enm_addrhi)) { 1564 /* 1565 * We must listen to a range of multicast addresses. 1566 * For now, just accept all multicasts, rather than 1567 * trying to set only those filter bits needed to match 1568 * the range. (At this time, the only use of address 1569 * ranges is for IP multicast routing, for which the 1570 * range is big enough to require all bits set.) 1571 */ 1572 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1573 ifp->if_flags |= IFF_ALLMULTI; 1574 goto chipit; 1575 } 1576 1577 cp = enm->enm_addrlo; 1578 crc = 0xffffffff; 1579 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1580 int octet = *cp++; 1581 int i; 1582 1583 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1584 for (i = 0; i < 8; i++) { 1585 if ((crc & 1) ^ (octet & 1)) { 1586 crc >>= 1; 1587 crc ^= MC_POLY_LE; 1588 } else { 1589 crc >>= 1; 1590 } 1591 octet >>= 1; 1592 } 1593 } 1594 /* Just want the 6 most significant bits. */ 1595 crc >>= 26; 1596 1597 /* Set the corresponding bit in the filter. */ 1598 hash[crc >> 4] |= 1 << (crc & 0xf); 1599 1600 ETHER_NEXT_MULTI(step, enm); 1601 } 1602 1603 ifp->if_flags &= ~IFF_ALLMULTI; 1604 1605 chipit: 1606 /* Now load the hash table into the chip */ 1607 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1608 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1609 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1610 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1611 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1612 } 1613 1614 /* 1615 * Routines for accessing the transmit and receive buffers. 1616 * The various CPU and adapter configurations supported by this 1617 * driver require three different access methods for buffers 1618 * and descriptors: 1619 * (1) contig (contiguous data; no padding), 1620 * (2) gap2 (two bytes of data followed by two bytes of padding), 1621 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1622 */ 1623 1624 #if 0 1625 /* 1626 * contig: contiguous data with no padding. 1627 * 1628 * Buffers may have any alignment. 1629 */ 1630 1631 void 1632 hme_copytobuf_contig(sc, from, ri, len) 1633 struct hme_softc *sc; 1634 void *from; 1635 int ri, len; 1636 { 1637 volatile void *buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1638 1639 /* 1640 * Just call memcpy() to do the work. 1641 */ 1642 memcpy(buf, from, len); 1643 } 1644 1645 void 1646 hme_copyfrombuf_contig(sc, to, boff, len) 1647 struct hme_softc *sc; 1648 void *to; 1649 int boff, len; 1650 { 1651 volatile void *buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1652 1653 /* 1654 * Just call memcpy() to do the work. 1655 */ 1656 memcpy(to, buf, len); 1657 } 1658 #endif 1659