1 /* $NetBSD: hme.c,v 1.68 2008/12/16 22:35:31 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * HME Ethernet module driver. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.68 2008/12/16 22:35:31 christos Exp $"); 38 39 /* #define HMEDEBUG */ 40 41 #include "opt_inet.h" 42 #include "bpfilter.h" 43 #include "rnd.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/mbuf.h> 49 #include <sys/syslog.h> 50 #include <sys/socket.h> 51 #include <sys/device.h> 52 #include <sys/malloc.h> 53 #include <sys/ioctl.h> 54 #include <sys/errno.h> 55 #if NRND > 0 56 #include <sys/rnd.h> 57 #endif 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_ether.h> 62 #include <net/if_media.h> 63 64 #ifdef INET 65 #include <netinet/in.h> 66 #include <netinet/if_inarp.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/in_var.h> 69 #include <netinet/ip.h> 70 #include <netinet/tcp.h> 71 #include <netinet/udp.h> 72 #endif 73 74 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #include <net/bpfdesc.h> 78 #endif 79 80 #include <dev/mii/mii.h> 81 #include <dev/mii/miivar.h> 82 83 #include <sys/bus.h> 84 85 #include <dev/ic/hmereg.h> 86 #include <dev/ic/hmevar.h> 87 88 void hme_start(struct ifnet *); 89 void hme_stop(struct hme_softc *,bool); 90 int hme_ioctl(struct ifnet *, u_long, void *); 91 void hme_tick(void *); 92 void hme_watchdog(struct ifnet *); 93 void hme_shutdown(void *); 94 int hme_init(struct hme_softc *); 95 void hme_meminit(struct hme_softc *); 96 void hme_mifinit(struct hme_softc *); 97 void hme_reset(struct hme_softc *); 98 void hme_setladrf(struct hme_softc *); 99 100 /* MII methods & callbacks */ 101 static int hme_mii_readreg(struct device *, int, int); 102 static void hme_mii_writereg(struct device *, int, int, int); 103 static void hme_mii_statchg(struct device *); 104 105 int hme_mediachange(struct ifnet *); 106 107 struct mbuf *hme_get(struct hme_softc *, int, uint32_t); 108 int hme_put(struct hme_softc *, int, struct mbuf *); 109 void hme_read(struct hme_softc *, int, uint32_t); 110 int hme_eint(struct hme_softc *, u_int); 111 int hme_rint(struct hme_softc *); 112 int hme_tint(struct hme_softc *); 113 114 static int ether_cmp(u_char *, u_char *); 115 116 /* Default buffer copy routines */ 117 void hme_copytobuf_contig(struct hme_softc *, void *, int, int); 118 void hme_copyfrombuf_contig(struct hme_softc *, void *, int, int); 119 void hme_zerobuf_contig(struct hme_softc *, int, int); 120 121 122 void 123 hme_config(sc) 124 struct hme_softc *sc; 125 { 126 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 127 struct mii_data *mii = &sc->sc_mii; 128 struct mii_softc *child; 129 bus_dma_tag_t dmatag = sc->sc_dmatag; 130 bus_dma_segment_t seg; 131 bus_size_t size; 132 int rseg, error; 133 134 /* 135 * HME common initialization. 136 * 137 * hme_softc fields that must be initialized by the front-end: 138 * 139 * the bus tag: 140 * sc_bustag 141 * 142 * the DMA bus tag: 143 * sc_dmatag 144 * 145 * the bus handles: 146 * sc_seb (Shared Ethernet Block registers) 147 * sc_erx (Receiver Unit registers) 148 * sc_etx (Transmitter Unit registers) 149 * sc_mac (MAC registers) 150 * sc_mif (Management Interface registers) 151 * 152 * the maximum bus burst size: 153 * sc_burst 154 * 155 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 156 * rb_membase, rb_dmabase) 157 * 158 * the local Ethernet address: 159 * sc_enaddr 160 * 161 */ 162 163 /* Make sure the chip is stopped. */ 164 hme_stop(sc, true); 165 166 167 /* 168 * Allocate descriptors and buffers 169 * XXX - do all this differently.. and more configurably, 170 * eg. use things as `dma_load_mbuf()' on transmit, 171 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 172 * all the time) on the receiver side. 173 * 174 * Note: receive buffers must be 64-byte aligned. 175 * Also, apparently, the buffers must extend to a DMA burst 176 * boundary beyond the maximum packet size. 177 */ 178 #define _HME_NDESC 128 179 #define _HME_BUFSZ 1600 180 181 /* Note: the # of descriptors must be a multiple of 16 */ 182 sc->sc_rb.rb_ntbuf = _HME_NDESC; 183 sc->sc_rb.rb_nrbuf = _HME_NDESC; 184 185 /* 186 * Allocate DMA capable memory 187 * Buffer descriptors must be aligned on a 2048 byte boundary; 188 * take this into account when calculating the size. Note that 189 * the maximum number of descriptors (256) occupies 2048 bytes, 190 * so we allocate that much regardless of _HME_NDESC. 191 */ 192 size = 2048 + /* TX descriptors */ 193 2048 + /* RX descriptors */ 194 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 195 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* RX buffers */ 196 197 /* Allocate DMA buffer */ 198 if ((error = bus_dmamem_alloc(dmatag, size, 199 2048, 0, 200 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 201 aprint_error_dev(&sc->sc_dev, "DMA buffer alloc error %d\n", 202 error); 203 return; 204 } 205 206 /* Map DMA memory in CPU addressable space */ 207 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 208 &sc->sc_rb.rb_membase, 209 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 210 aprint_error_dev(&sc->sc_dev, "DMA buffer map error %d\n", 211 error); 212 bus_dmamap_unload(dmatag, sc->sc_dmamap); 213 bus_dmamem_free(dmatag, &seg, rseg); 214 return; 215 } 216 217 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 218 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 219 aprint_error_dev(&sc->sc_dev, "DMA map create error %d\n", 220 error); 221 return; 222 } 223 224 /* Load the buffer */ 225 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 226 sc->sc_rb.rb_membase, size, NULL, 227 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 228 aprint_error_dev(&sc->sc_dev, "DMA buffer map load error %d\n", 229 error); 230 bus_dmamem_free(dmatag, &seg, rseg); 231 return; 232 } 233 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 234 235 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 236 ether_sprintf(sc->sc_enaddr)); 237 238 /* Initialize ifnet structure. */ 239 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 240 ifp->if_softc = sc; 241 ifp->if_start = hme_start; 242 ifp->if_ioctl = hme_ioctl; 243 ifp->if_watchdog = hme_watchdog; 244 ifp->if_flags = 245 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 246 sc->sc_if_flags = ifp->if_flags; 247 ifp->if_capabilities |= 248 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 249 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 250 IFQ_SET_READY(&ifp->if_snd); 251 252 /* Initialize ifmedia structures and MII info */ 253 mii->mii_ifp = ifp; 254 mii->mii_readreg = hme_mii_readreg; 255 mii->mii_writereg = hme_mii_writereg; 256 mii->mii_statchg = hme_mii_statchg; 257 258 sc->sc_ethercom.ec_mii = mii; 259 ifmedia_init(&mii->mii_media, 0, hme_mediachange, ether_mediastatus); 260 261 hme_mifinit(sc); 262 263 mii_attach(&sc->sc_dev, mii, 0xffffffff, 264 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 265 266 child = LIST_FIRST(&mii->mii_phys); 267 if (child == NULL) { 268 /* No PHY attached */ 269 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 270 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 271 } else { 272 /* 273 * Walk along the list of attached MII devices and 274 * establish an `MII instance' to `phy number' 275 * mapping. We'll use this mapping in media change 276 * requests to determine which phy to use to program 277 * the MIF configuration register. 278 */ 279 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 280 /* 281 * Note: we support just two PHYs: the built-in 282 * internal device and an external on the MII 283 * connector. 284 */ 285 if (child->mii_phy > 1 || child->mii_inst > 1) { 286 aprint_error_dev(&sc->sc_dev, "cannot accommodate MII device %s" 287 " at phy %d, instance %d\n", 288 device_xname(child->mii_dev), 289 child->mii_phy, child->mii_inst); 290 continue; 291 } 292 293 sc->sc_phys[child->mii_inst] = child->mii_phy; 294 } 295 296 /* 297 * XXX - we can really do the following ONLY if the 298 * phy indeed has the auto negotiation capability!! 299 */ 300 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 301 } 302 303 /* claim 802.1q capability */ 304 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 305 306 /* Attach the interface. */ 307 if_attach(ifp); 308 ether_ifattach(ifp, sc->sc_enaddr); 309 310 sc->sc_sh = shutdownhook_establish(hme_shutdown, sc); 311 if (sc->sc_sh == NULL) 312 panic("hme_config: can't establish shutdownhook"); 313 314 #if NRND > 0 315 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 316 RND_TYPE_NET, 0); 317 #endif 318 319 callout_init(&sc->sc_tick_ch, 0); 320 } 321 322 void 323 hme_tick(arg) 324 void *arg; 325 { 326 struct hme_softc *sc = arg; 327 int s; 328 329 s = splnet(); 330 mii_tick(&sc->sc_mii); 331 splx(s); 332 333 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 334 } 335 336 void 337 hme_reset(sc) 338 struct hme_softc *sc; 339 { 340 int s; 341 342 s = splnet(); 343 (void)hme_init(sc); 344 splx(s); 345 } 346 347 void 348 hme_stop(struct hme_softc *sc, bool chip_only) 349 { 350 bus_space_tag_t t = sc->sc_bustag; 351 bus_space_handle_t seb = sc->sc_seb; 352 int n; 353 354 if (!chip_only) { 355 callout_stop(&sc->sc_tick_ch); 356 mii_down(&sc->sc_mii); 357 } 358 359 /* Mask all interrupts */ 360 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff); 361 362 /* Reset transmitter and receiver */ 363 bus_space_write_4(t, seb, HME_SEBI_RESET, 364 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 365 366 for (n = 0; n < 20; n++) { 367 u_int32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 368 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 369 return; 370 DELAY(20); 371 } 372 373 printf("%s: hme_stop: reset failed\n", device_xname(&sc->sc_dev)); 374 } 375 376 void 377 hme_meminit(sc) 378 struct hme_softc *sc; 379 { 380 bus_addr_t txbufdma, rxbufdma; 381 bus_addr_t dma; 382 char *p; 383 unsigned int ntbuf, nrbuf, i; 384 struct hme_ring *hr = &sc->sc_rb; 385 386 p = hr->rb_membase; 387 dma = hr->rb_dmabase; 388 389 ntbuf = hr->rb_ntbuf; 390 nrbuf = hr->rb_nrbuf; 391 392 /* 393 * Allocate transmit descriptors 394 */ 395 hr->rb_txd = p; 396 hr->rb_txddma = dma; 397 p += ntbuf * HME_XD_SIZE; 398 dma += ntbuf * HME_XD_SIZE; 399 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 400 dma = (bus_addr_t)roundup((u_long)dma, 2048); 401 p = (void *)roundup((u_long)p, 2048); 402 403 /* 404 * Allocate receive descriptors 405 */ 406 hr->rb_rxd = p; 407 hr->rb_rxddma = dma; 408 p += nrbuf * HME_XD_SIZE; 409 dma += nrbuf * HME_XD_SIZE; 410 /* Again move forward to the next 2048 byte boundary.*/ 411 dma = (bus_addr_t)roundup((u_long)dma, 2048); 412 p = (void *)roundup((u_long)p, 2048); 413 414 415 /* 416 * Allocate transmit buffers 417 */ 418 hr->rb_txbuf = p; 419 txbufdma = dma; 420 p += ntbuf * _HME_BUFSZ; 421 dma += ntbuf * _HME_BUFSZ; 422 423 /* 424 * Allocate receive buffers 425 */ 426 hr->rb_rxbuf = p; 427 rxbufdma = dma; 428 p += nrbuf * _HME_BUFSZ; 429 dma += nrbuf * _HME_BUFSZ; 430 431 /* 432 * Initialize transmit buffer descriptors 433 */ 434 for (i = 0; i < ntbuf; i++) { 435 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 436 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 437 } 438 439 /* 440 * Initialize receive buffer descriptors 441 */ 442 for (i = 0; i < nrbuf; i++) { 443 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 444 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 445 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 446 } 447 448 hr->rb_tdhead = hr->rb_tdtail = 0; 449 hr->rb_td_nbusy = 0; 450 hr->rb_rdtail = 0; 451 } 452 453 /* 454 * Initialization of interface; set up initialization block 455 * and transmit/receive descriptor rings. 456 */ 457 int 458 hme_init(sc) 459 struct hme_softc *sc; 460 { 461 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 462 bus_space_tag_t t = sc->sc_bustag; 463 bus_space_handle_t seb = sc->sc_seb; 464 bus_space_handle_t etx = sc->sc_etx; 465 bus_space_handle_t erx = sc->sc_erx; 466 bus_space_handle_t mac = sc->sc_mac; 467 u_int8_t *ea; 468 u_int32_t v; 469 int rc; 470 471 /* 472 * Initialization sequence. The numbered steps below correspond 473 * to the sequence outlined in section 6.3.5.1 in the Ethernet 474 * Channel Engine manual (part of the PCIO manual). 475 * See also the STP2002-STQ document from Sun Microsystems. 476 */ 477 478 /* step 1 & 2. Reset the Ethernet Channel */ 479 hme_stop(sc, false); 480 481 /* Re-initialize the MIF */ 482 hme_mifinit(sc); 483 484 /* Call MI reset function if any */ 485 if (sc->sc_hwreset) 486 (*sc->sc_hwreset)(sc); 487 488 #if 0 489 /* Mask all MIF interrupts, just in case */ 490 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 491 #endif 492 493 /* step 3. Setup data structures in host memory */ 494 hme_meminit(sc); 495 496 /* step 4. TX MAC registers & counters */ 497 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 498 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 499 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 500 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 501 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 502 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 503 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 504 sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable; 505 506 /* Load station MAC address */ 507 ea = sc->sc_enaddr; 508 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 509 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 510 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 511 512 /* 513 * Init seed for backoff 514 * (source suggested by manual: low 10 bits of MAC address) 515 */ 516 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 517 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 518 519 520 /* Note: Accepting power-on default for other MAC registers here.. */ 521 522 523 /* step 5. RX MAC registers & counters */ 524 hme_setladrf(sc); 525 526 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 527 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 528 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 529 530 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 531 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 532 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 533 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 534 535 /* step 8. Global Configuration & Interrupt Mask */ 536 bus_space_write_4(t, seb, HME_SEBI_IMASK, 537 ~( 538 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 539 HME_SEB_STAT_HOSTTOTX | 540 HME_SEB_STAT_RXTOHOST | 541 HME_SEB_STAT_TXALL | 542 HME_SEB_STAT_TXPERR | 543 HME_SEB_STAT_RCNTEXP | 544 /*HME_SEB_STAT_MIFIRQ |*/ 545 HME_SEB_STAT_ALL_ERRORS )); 546 547 switch (sc->sc_burst) { 548 default: 549 v = 0; 550 break; 551 case 16: 552 v = HME_SEB_CFG_BURST16; 553 break; 554 case 32: 555 v = HME_SEB_CFG_BURST32; 556 break; 557 case 64: 558 v = HME_SEB_CFG_BURST64; 559 break; 560 } 561 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 562 563 /* step 9. ETX Configuration: use mostly default values */ 564 565 /* Enable DMA */ 566 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 567 v |= HME_ETX_CFG_DMAENABLE; 568 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 569 570 /* Transmit Descriptor ring size: in increments of 16 */ 571 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 572 573 574 /* step 10. ERX Configuration */ 575 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 576 577 /* Encode Receive Descriptor ring size: four possible values */ 578 switch (_HME_NDESC /*XXX*/) { 579 case 32: 580 v |= HME_ERX_CFG_RINGSIZE32; 581 break; 582 case 64: 583 v |= HME_ERX_CFG_RINGSIZE64; 584 break; 585 case 128: 586 v |= HME_ERX_CFG_RINGSIZE128; 587 break; 588 case 256: 589 v |= HME_ERX_CFG_RINGSIZE256; 590 break; 591 default: 592 printf("hme: invalid Receive Descriptor ring size\n"); 593 break; 594 } 595 596 /* Enable DMA */ 597 v |= HME_ERX_CFG_DMAENABLE; 598 599 /* set h/w rx checksum start offset (# of half-words) */ 600 #ifdef INET 601 v |= (((ETHER_HDR_LEN + sizeof(struct ip) + 602 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 603 ETHER_VLAN_ENCAP_LEN : 0)) / 2) << HME_ERX_CFG_CSUMSHIFT) & 604 HME_ERX_CFG_CSUMSTART; 605 #endif 606 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 607 608 /* step 11. XIF Configuration */ 609 v = bus_space_read_4(t, mac, HME_MACI_XIF); 610 v |= HME_MAC_XIF_OE; 611 bus_space_write_4(t, mac, HME_MACI_XIF, v); 612 613 /* step 12. RX_MAC Configuration Register */ 614 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 615 v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP; 616 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 617 618 /* step 13. TX_MAC Configuration Register */ 619 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 620 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 621 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 622 623 /* step 14. Issue Transmit Pending command */ 624 625 /* Call MI initialization function if any */ 626 if (sc->sc_hwinit) 627 (*sc->sc_hwinit)(sc); 628 629 /* Set the current media. */ 630 if ((rc = hme_mediachange(ifp)) != 0) 631 return rc; 632 633 /* Start the one second timer. */ 634 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 635 636 ifp->if_flags |= IFF_RUNNING; 637 ifp->if_flags &= ~IFF_OACTIVE; 638 sc->sc_if_flags = ifp->if_flags; 639 ifp->if_timer = 0; 640 hme_start(ifp); 641 return 0; 642 } 643 644 /* 645 * Compare two Ether/802 addresses for equality, inlined and unrolled for 646 * speed. 647 */ 648 static inline int 649 ether_cmp(a, b) 650 u_char *a, *b; 651 { 652 653 if (a[5] != b[5] || a[4] != b[4] || a[3] != b[3] || 654 a[2] != b[2] || a[1] != b[1] || a[0] != b[0]) 655 return (0); 656 return (1); 657 } 658 659 660 /* 661 * Routine to copy from mbuf chain to transmit buffer in 662 * network buffer memory. 663 * Returns the amount of data copied. 664 */ 665 int 666 hme_put(sc, ri, m) 667 struct hme_softc *sc; 668 int ri; /* Ring index */ 669 struct mbuf *m; 670 { 671 struct mbuf *n; 672 int len, tlen = 0; 673 char *bp; 674 675 bp = (char *)sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 676 for (; m; m = n) { 677 len = m->m_len; 678 if (len == 0) { 679 MFREE(m, n); 680 continue; 681 } 682 memcpy(bp, mtod(m, void *), len); 683 bp += len; 684 tlen += len; 685 MFREE(m, n); 686 } 687 return (tlen); 688 } 689 690 /* 691 * Pull data off an interface. 692 * Len is length of data, with local net header stripped. 693 * We copy the data into mbufs. When full cluster sized units are present 694 * we copy into clusters. 695 */ 696 struct mbuf * 697 hme_get(sc, ri, flags) 698 struct hme_softc *sc; 699 int ri; 700 u_int32_t flags; 701 { 702 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 703 struct mbuf *m, *m0, *newm; 704 char *bp; 705 int len, totlen; 706 707 totlen = HME_XD_DECODE_RSIZE(flags); 708 MGETHDR(m0, M_DONTWAIT, MT_DATA); 709 if (m0 == 0) 710 return (0); 711 m0->m_pkthdr.rcvif = ifp; 712 m0->m_pkthdr.len = totlen; 713 len = MHLEN; 714 m = m0; 715 716 bp = (char *)sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 717 718 while (totlen > 0) { 719 if (totlen >= MINCLSIZE) { 720 MCLGET(m, M_DONTWAIT); 721 if ((m->m_flags & M_EXT) == 0) 722 goto bad; 723 len = MCLBYTES; 724 } 725 726 if (m == m0) { 727 char *newdata = (char *) 728 ALIGN(m->m_data + sizeof(struct ether_header)) - 729 sizeof(struct ether_header); 730 len -= newdata - m->m_data; 731 m->m_data = newdata; 732 } 733 734 m->m_len = len = min(totlen, len); 735 memcpy(mtod(m, void *), bp, len); 736 bp += len; 737 738 totlen -= len; 739 if (totlen > 0) { 740 MGET(newm, M_DONTWAIT, MT_DATA); 741 if (newm == 0) 742 goto bad; 743 len = MLEN; 744 m = m->m_next = newm; 745 } 746 } 747 748 #ifdef INET 749 /* hardware checksum */ 750 if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 751 struct ether_header *eh; 752 struct ip *ip; 753 struct udphdr *uh; 754 uint16_t *opts; 755 int32_t hlen, pktlen; 756 uint32_t temp; 757 758 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 759 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN - 760 ETHER_VLAN_ENCAP_LEN; 761 eh = (struct ether_header *) mtod(m0, void *) + 762 ETHER_VLAN_ENCAP_LEN; 763 } else { 764 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN; 765 eh = mtod(m0, struct ether_header *); 766 } 767 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 768 goto swcsum; 769 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 770 771 /* IPv4 only */ 772 if (ip->ip_v != IPVERSION) 773 goto swcsum; 774 775 hlen = ip->ip_hl << 2; 776 if (hlen < sizeof(struct ip)) 777 goto swcsum; 778 779 /* 780 * bail if too short, has random trailing garbage, truncated, 781 * fragment, or has ethernet pad. 782 */ 783 if ((ntohs(ip->ip_len) < hlen) || (ntohs(ip->ip_len) != pktlen) 784 || (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 785 goto swcsum; 786 787 switch (ip->ip_p) { 788 case IPPROTO_TCP: 789 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 790 goto swcsum; 791 if (pktlen < (hlen + sizeof(struct tcphdr))) 792 goto swcsum; 793 m0->m_pkthdr.csum_flags = M_CSUM_TCPv4; 794 break; 795 case IPPROTO_UDP: 796 if (! (ifp->if_csum_flags_rx & M_CSUM_UDPv4)) 797 goto swcsum; 798 if (pktlen < (hlen + sizeof(struct udphdr))) 799 goto swcsum; 800 uh = (struct udphdr *)((char *)ip + hlen); 801 /* no checksum */ 802 if (uh->uh_sum == 0) 803 goto swcsum; 804 m0->m_pkthdr.csum_flags = M_CSUM_UDPv4; 805 break; 806 default: 807 goto swcsum; 808 } 809 810 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */ 811 m0->m_pkthdr.csum_data = (~flags) & HME_XD_RXCKSUM; 812 813 /* if the pkt had ip options, we have to deduct them */ 814 if (hlen > sizeof(struct ip)) { 815 uint32_t optsum; 816 817 optsum = 0; 818 temp = hlen - sizeof(struct ip); 819 opts = (uint16_t *)((char *)ip + sizeof(struct ip)); 820 821 while (temp > 1) { 822 optsum += ntohs(*opts++); 823 temp -= 2; 824 } 825 while (optsum >> 16) 826 optsum = (optsum >> 16) + (optsum & 0xffff); 827 828 /* Deduct the ip opts sum from the hwsum (rfc 1624). */ 829 m0->m_pkthdr.csum_data = ~((~m0->m_pkthdr.csum_data) - 830 ~optsum); 831 832 while (m0->m_pkthdr.csum_data >> 16) 833 m0->m_pkthdr.csum_data = 834 (m0->m_pkthdr.csum_data >> 16) + 835 (m0->m_pkthdr.csum_data & 0xffff); 836 } 837 838 m0->m_pkthdr.csum_flags |= M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 839 } 840 swcsum: 841 m0->m_pkthdr.csum_flags = 0; 842 #endif 843 844 return (m0); 845 846 bad: 847 m_freem(m0); 848 return (0); 849 } 850 851 /* 852 * Pass a packet to the higher levels. 853 */ 854 void 855 hme_read(sc, ix, flags) 856 struct hme_softc *sc; 857 int ix; 858 u_int32_t flags; 859 { 860 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 861 struct mbuf *m; 862 int len; 863 864 len = HME_XD_DECODE_RSIZE(flags); 865 if (len <= sizeof(struct ether_header) || 866 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 867 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 868 ETHERMTU + sizeof(struct ether_header))) { 869 #ifdef HMEDEBUG 870 printf("%s: invalid packet size %d; dropping\n", 871 device_xname(&sc->sc_dev), len); 872 #endif 873 ifp->if_ierrors++; 874 return; 875 } 876 877 /* Pull packet off interface. */ 878 m = hme_get(sc, ix, flags); 879 if (m == 0) { 880 ifp->if_ierrors++; 881 return; 882 } 883 884 ifp->if_ipackets++; 885 886 #if NBPFILTER > 0 887 /* 888 * Check if there's a BPF listener on this interface. 889 * If so, hand off the raw packet to BPF. 890 */ 891 if (ifp->if_bpf) 892 bpf_mtap(ifp->if_bpf, m); 893 #endif 894 895 /* Pass the packet up. */ 896 (*ifp->if_input)(ifp, m); 897 } 898 899 void 900 hme_start(ifp) 901 struct ifnet *ifp; 902 { 903 struct hme_softc *sc = (struct hme_softc *)ifp->if_softc; 904 void *txd = sc->sc_rb.rb_txd; 905 struct mbuf *m; 906 unsigned int txflags; 907 unsigned int ri, len; 908 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 909 910 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 911 return; 912 913 ri = sc->sc_rb.rb_tdhead; 914 915 for (;;) { 916 IFQ_DEQUEUE(&ifp->if_snd, m); 917 if (m == 0) 918 break; 919 920 #if NBPFILTER > 0 921 /* 922 * If BPF is listening on this interface, let it see the 923 * packet before we commit it to the wire. 924 */ 925 if (ifp->if_bpf) 926 bpf_mtap(ifp->if_bpf, m); 927 #endif 928 929 #ifdef INET 930 /* collect bits for h/w csum, before hme_put frees the mbuf */ 931 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) && 932 m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 933 struct ether_header *eh; 934 uint16_t offset, start; 935 936 eh = mtod(m, struct ether_header *); 937 switch (ntohs(eh->ether_type)) { 938 case ETHERTYPE_IP: 939 start = ETHER_HDR_LEN; 940 break; 941 case ETHERTYPE_VLAN: 942 start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 943 break; 944 default: 945 /* unsupported, drop it */ 946 m_free(m); 947 continue; 948 } 949 start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 950 offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data) 951 + start; 952 txflags = HME_XD_TXCKSUM | 953 (offset << HME_XD_TXCSSTUFFSHIFT) | 954 (start << HME_XD_TXCSSTARTSHIFT); 955 } else 956 #endif 957 txflags = 0; 958 959 /* 960 * Copy the mbuf chain into the transmit buffer. 961 */ 962 len = hme_put(sc, ri, m); 963 964 /* 965 * Initialize transmit registers and start transmission 966 */ 967 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 968 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 969 HME_XD_ENCODE_TSIZE(len) | txflags); 970 971 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 972 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 973 HME_ETX_TP_DMAWAKEUP); 974 975 if (++ri == ntbuf) 976 ri = 0; 977 978 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 979 ifp->if_flags |= IFF_OACTIVE; 980 break; 981 } 982 } 983 984 sc->sc_rb.rb_tdhead = ri; 985 } 986 987 /* 988 * Transmit interrupt. 989 */ 990 int 991 hme_tint(sc) 992 struct hme_softc *sc; 993 { 994 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 995 bus_space_tag_t t = sc->sc_bustag; 996 bus_space_handle_t mac = sc->sc_mac; 997 unsigned int ri, txflags; 998 999 /* 1000 * Unload collision counters 1001 */ 1002 ifp->if_collisions += 1003 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 1004 bus_space_read_4(t, mac, HME_MACI_FCCNT) + 1005 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 1006 bus_space_read_4(t, mac, HME_MACI_LTCNT); 1007 1008 /* 1009 * then clear the hardware counters. 1010 */ 1011 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 1012 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 1013 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 1014 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 1015 1016 /* Fetch current position in the transmit ring */ 1017 ri = sc->sc_rb.rb_tdtail; 1018 1019 for (;;) { 1020 if (sc->sc_rb.rb_td_nbusy <= 0) 1021 break; 1022 1023 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 1024 1025 if (txflags & HME_XD_OWN) 1026 break; 1027 1028 ifp->if_flags &= ~IFF_OACTIVE; 1029 ifp->if_opackets++; 1030 1031 if (++ri == sc->sc_rb.rb_ntbuf) 1032 ri = 0; 1033 1034 --sc->sc_rb.rb_td_nbusy; 1035 } 1036 1037 /* Update ring */ 1038 sc->sc_rb.rb_tdtail = ri; 1039 1040 hme_start(ifp); 1041 1042 if (sc->sc_rb.rb_td_nbusy == 0) 1043 ifp->if_timer = 0; 1044 1045 return (1); 1046 } 1047 1048 /* 1049 * Receive interrupt. 1050 */ 1051 int 1052 hme_rint(sc) 1053 struct hme_softc *sc; 1054 { 1055 void *xdr = sc->sc_rb.rb_rxd; 1056 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 1057 unsigned int ri; 1058 u_int32_t flags; 1059 1060 ri = sc->sc_rb.rb_rdtail; 1061 1062 /* 1063 * Process all buffers with valid data. 1064 */ 1065 for (;;) { 1066 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 1067 if (flags & HME_XD_OWN) 1068 break; 1069 1070 if (flags & HME_XD_OFL) { 1071 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 1072 device_xname(&sc->sc_dev), ri, flags); 1073 } else 1074 hme_read(sc, ri, flags); 1075 1076 /* This buffer can be used by the hardware again */ 1077 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 1078 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 1079 1080 if (++ri == nrbuf) 1081 ri = 0; 1082 } 1083 1084 sc->sc_rb.rb_rdtail = ri; 1085 1086 return (1); 1087 } 1088 1089 int 1090 hme_eint(sc, status) 1091 struct hme_softc *sc; 1092 u_int status; 1093 { 1094 char bits[128]; 1095 1096 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 1097 bus_space_tag_t t = sc->sc_bustag; 1098 bus_space_handle_t mif = sc->sc_mif; 1099 u_int32_t cf, st, sm; 1100 cf = bus_space_read_4(t, mif, HME_MIFI_CFG); 1101 st = bus_space_read_4(t, mif, HME_MIFI_STAT); 1102 sm = bus_space_read_4(t, mif, HME_MIFI_SM); 1103 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n", 1104 device_xname(&sc->sc_dev), cf, st, sm); 1105 return (1); 1106 } 1107 snprintb(bits, sizeof(bits), HME_SEB_STAT_BITS, status); 1108 printf("%s: status=%s\n", device_xname(&sc->sc_dev), bits); 1109 1110 return (1); 1111 } 1112 1113 int 1114 hme_intr(v) 1115 void *v; 1116 { 1117 struct hme_softc *sc = (struct hme_softc *)v; 1118 bus_space_tag_t t = sc->sc_bustag; 1119 bus_space_handle_t seb = sc->sc_seb; 1120 u_int32_t status; 1121 int r = 0; 1122 1123 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 1124 1125 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 1126 r |= hme_eint(sc, status); 1127 1128 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 1129 r |= hme_tint(sc); 1130 1131 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1132 r |= hme_rint(sc); 1133 1134 #if NRND > 0 1135 rnd_add_uint32(&sc->rnd_source, status); 1136 #endif 1137 1138 return (r); 1139 } 1140 1141 1142 void 1143 hme_watchdog(ifp) 1144 struct ifnet *ifp; 1145 { 1146 struct hme_softc *sc = ifp->if_softc; 1147 1148 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev)); 1149 ++ifp->if_oerrors; 1150 1151 hme_reset(sc); 1152 } 1153 1154 /* 1155 * Initialize the MII Management Interface 1156 */ 1157 void 1158 hme_mifinit(sc) 1159 struct hme_softc *sc; 1160 { 1161 bus_space_tag_t t = sc->sc_bustag; 1162 bus_space_handle_t mif = sc->sc_mif; 1163 bus_space_handle_t mac = sc->sc_mac; 1164 int instance, phy; 1165 u_int32_t v; 1166 1167 if (sc->sc_mii.mii_media.ifm_cur != NULL) { 1168 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1169 phy = sc->sc_phys[instance]; 1170 } else 1171 /* No media set yet, pick phy arbitrarily.. */ 1172 phy = HME_PHYAD_EXTERNAL; 1173 1174 /* Configure the MIF in frame mode, no poll, current phy select */ 1175 v = 0; 1176 if (phy == HME_PHYAD_EXTERNAL) 1177 v |= HME_MIF_CFG_PHY; 1178 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1179 1180 /* If an external transceiver is selected, enable its MII drivers */ 1181 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1182 v &= ~HME_MAC_XIF_MIIENABLE; 1183 if (phy == HME_PHYAD_EXTERNAL) 1184 v |= HME_MAC_XIF_MIIENABLE; 1185 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1186 } 1187 1188 /* 1189 * MII interface 1190 */ 1191 static int 1192 hme_mii_readreg(self, phy, reg) 1193 struct device *self; 1194 int phy, reg; 1195 { 1196 struct hme_softc *sc = (void *)self; 1197 bus_space_tag_t t = sc->sc_bustag; 1198 bus_space_handle_t mif = sc->sc_mif; 1199 bus_space_handle_t mac = sc->sc_mac; 1200 u_int32_t v, xif_cfg, mifi_cfg; 1201 int n; 1202 1203 /* We can at most have two PHYs */ 1204 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1205 return (0); 1206 1207 /* Select the desired PHY in the MIF configuration register */ 1208 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1209 v &= ~HME_MIF_CFG_PHY; 1210 if (phy == HME_PHYAD_EXTERNAL) 1211 v |= HME_MIF_CFG_PHY; 1212 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1213 1214 /* Enable MII drivers on external transceiver */ 1215 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1216 if (phy == HME_PHYAD_EXTERNAL) 1217 v |= HME_MAC_XIF_MIIENABLE; 1218 else 1219 v &= ~HME_MAC_XIF_MIIENABLE; 1220 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1221 1222 #if 0 1223 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1224 /* 1225 * Check whether a transceiver is connected by testing 1226 * the MIF configuration register's MDI_X bits. Note that 1227 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1228 */ 1229 mif_mdi_bit = 1 << (8 + (1 - phy)); 1230 delay(100); 1231 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1232 if ((v & mif_mdi_bit) == 0) 1233 return (0); 1234 #endif 1235 1236 /* Construct the frame command */ 1237 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1238 HME_MIF_FO_TAMSB | 1239 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1240 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1241 (reg << HME_MIF_FO_REGAD_SHIFT); 1242 1243 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1244 for (n = 0; n < 100; n++) { 1245 DELAY(1); 1246 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1247 if (v & HME_MIF_FO_TALSB) { 1248 v &= HME_MIF_FO_DATA; 1249 goto out; 1250 } 1251 } 1252 1253 v = 0; 1254 printf("%s: mii_read timeout\n", device_xname(&sc->sc_dev)); 1255 1256 out: 1257 /* Restore MIFI_CFG register */ 1258 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1259 /* Restore XIF register */ 1260 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1261 return (v); 1262 } 1263 1264 static void 1265 hme_mii_writereg(self, phy, reg, val) 1266 struct device *self; 1267 int phy, reg, val; 1268 { 1269 struct hme_softc *sc = (void *)self; 1270 bus_space_tag_t t = sc->sc_bustag; 1271 bus_space_handle_t mif = sc->sc_mif; 1272 bus_space_handle_t mac = sc->sc_mac; 1273 u_int32_t v, xif_cfg, mifi_cfg; 1274 int n; 1275 1276 /* We can at most have two PHYs */ 1277 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1278 return; 1279 1280 /* Select the desired PHY in the MIF configuration register */ 1281 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1282 v &= ~HME_MIF_CFG_PHY; 1283 if (phy == HME_PHYAD_EXTERNAL) 1284 v |= HME_MIF_CFG_PHY; 1285 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1286 1287 /* Enable MII drivers on external transceiver */ 1288 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1289 if (phy == HME_PHYAD_EXTERNAL) 1290 v |= HME_MAC_XIF_MIIENABLE; 1291 else 1292 v &= ~HME_MAC_XIF_MIIENABLE; 1293 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1294 1295 #if 0 1296 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1297 /* 1298 * Check whether a transceiver is connected by testing 1299 * the MIF configuration register's MDI_X bits. Note that 1300 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1301 */ 1302 mif_mdi_bit = 1 << (8 + (1 - phy)); 1303 delay(100); 1304 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1305 if ((v & mif_mdi_bit) == 0) 1306 return; 1307 #endif 1308 1309 /* Construct the frame command */ 1310 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1311 HME_MIF_FO_TAMSB | 1312 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1313 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1314 (reg << HME_MIF_FO_REGAD_SHIFT) | 1315 (val & HME_MIF_FO_DATA); 1316 1317 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1318 for (n = 0; n < 100; n++) { 1319 DELAY(1); 1320 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1321 if (v & HME_MIF_FO_TALSB) 1322 goto out; 1323 } 1324 1325 printf("%s: mii_write timeout\n", device_xname(&sc->sc_dev)); 1326 out: 1327 /* Restore MIFI_CFG register */ 1328 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1329 /* Restore XIF register */ 1330 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1331 } 1332 1333 static void 1334 hme_mii_statchg(dev) 1335 struct device *dev; 1336 { 1337 struct hme_softc *sc = (void *)dev; 1338 bus_space_tag_t t = sc->sc_bustag; 1339 bus_space_handle_t mac = sc->sc_mac; 1340 u_int32_t v; 1341 1342 #ifdef HMEDEBUG 1343 if (sc->sc_debug) 1344 printf("hme_mii_statchg: status change\n"); 1345 #endif 1346 1347 /* Set the MAC Full Duplex bit appropriately */ 1348 /* Apparently the hme chip is SIMPLEX if working in full duplex mode, 1349 but not otherwise. */ 1350 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1351 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1352 v |= HME_MAC_TXCFG_FULLDPLX; 1353 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX; 1354 } else { 1355 v &= ~HME_MAC_TXCFG_FULLDPLX; 1356 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX; 1357 } 1358 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags; 1359 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1360 } 1361 1362 int 1363 hme_mediachange(ifp) 1364 struct ifnet *ifp; 1365 { 1366 struct hme_softc *sc = ifp->if_softc; 1367 bus_space_tag_t t = sc->sc_bustag; 1368 bus_space_handle_t mif = sc->sc_mif; 1369 bus_space_handle_t mac = sc->sc_mac; 1370 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1371 int phy = sc->sc_phys[instance]; 1372 int rc; 1373 u_int32_t v; 1374 1375 #ifdef HMEDEBUG 1376 if (sc->sc_debug) 1377 printf("hme_mediachange: phy = %d\n", phy); 1378 #endif 1379 1380 /* Select the current PHY in the MIF configuration register */ 1381 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1382 v &= ~HME_MIF_CFG_PHY; 1383 if (phy == HME_PHYAD_EXTERNAL) 1384 v |= HME_MIF_CFG_PHY; 1385 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1386 1387 /* If an external transceiver is selected, enable its MII drivers */ 1388 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1389 v &= ~HME_MAC_XIF_MIIENABLE; 1390 if (phy == HME_PHYAD_EXTERNAL) 1391 v |= HME_MAC_XIF_MIIENABLE; 1392 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1393 1394 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 1395 return 0; 1396 return rc; 1397 } 1398 1399 /* 1400 * Process an ioctl request. 1401 */ 1402 int 1403 hme_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1404 { 1405 struct hme_softc *sc = ifp->if_softc; 1406 struct ifaddr *ifa = (struct ifaddr *)data; 1407 int s, error = 0; 1408 1409 s = splnet(); 1410 1411 switch (cmd) { 1412 1413 case SIOCINITIFADDR: 1414 switch (ifa->ifa_addr->sa_family) { 1415 #ifdef INET 1416 case AF_INET: 1417 if (ifp->if_flags & IFF_UP) 1418 hme_setladrf(sc); 1419 else { 1420 ifp->if_flags |= IFF_UP; 1421 error = hme_init(sc); 1422 } 1423 arp_ifinit(ifp, ifa); 1424 break; 1425 #endif 1426 default: 1427 ifp->if_flags |= IFF_UP; 1428 error = hme_init(sc); 1429 break; 1430 } 1431 break; 1432 1433 case SIOCSIFFLAGS: 1434 #ifdef HMEDEBUG 1435 { 1436 struct ifreq *ifr = data; 1437 sc->sc_debug = 1438 (ifr->ifr_flags & IFF_DEBUG) != 0 ? 1 : 0; 1439 } 1440 #endif 1441 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1442 break; 1443 1444 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1445 case IFF_RUNNING: 1446 /* 1447 * If interface is marked down and it is running, then 1448 * stop it. 1449 */ 1450 hme_stop(sc, false); 1451 ifp->if_flags &= ~IFF_RUNNING; 1452 break; 1453 case IFF_UP: 1454 /* 1455 * If interface is marked up and it is stopped, then 1456 * start it. 1457 */ 1458 error = hme_init(sc); 1459 break; 1460 case IFF_UP|IFF_RUNNING: 1461 /* 1462 * If setting debug or promiscuous mode, do not reset 1463 * the chip; for everything else, call hme_init() 1464 * which will trigger a reset. 1465 */ 1466 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG) 1467 if (ifp->if_flags != sc->sc_if_flags) { 1468 if ((ifp->if_flags & (~RESETIGN)) 1469 == (sc->sc_if_flags & (~RESETIGN))) 1470 hme_setladrf(sc); 1471 else 1472 error = hme_init(sc); 1473 } 1474 #undef RESETIGN 1475 break; 1476 case 0: 1477 break; 1478 } 1479 1480 if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable) 1481 error = hme_init(sc); 1482 1483 break; 1484 1485 default: 1486 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1487 break; 1488 1489 error = 0; 1490 1491 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1492 ; 1493 else if (ifp->if_flags & IFF_RUNNING) { 1494 /* 1495 * Multicast list has changed; set the hardware filter 1496 * accordingly. 1497 */ 1498 hme_setladrf(sc); 1499 } 1500 break; 1501 } 1502 1503 sc->sc_if_flags = ifp->if_flags; 1504 splx(s); 1505 return (error); 1506 } 1507 1508 void 1509 hme_shutdown(arg) 1510 void *arg; 1511 { 1512 1513 hme_stop((struct hme_softc *)arg, false); 1514 } 1515 1516 /* 1517 * Set up the logical address filter. 1518 */ 1519 void 1520 hme_setladrf(sc) 1521 struct hme_softc *sc; 1522 { 1523 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1524 struct ether_multi *enm; 1525 struct ether_multistep step; 1526 struct ethercom *ec = &sc->sc_ethercom; 1527 bus_space_tag_t t = sc->sc_bustag; 1528 bus_space_handle_t mac = sc->sc_mac; 1529 u_char *cp; 1530 u_int32_t crc; 1531 u_int32_t hash[4]; 1532 u_int32_t v; 1533 int len; 1534 1535 /* Clear hash table */ 1536 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1537 1538 /* Get current RX configuration */ 1539 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1540 1541 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1542 /* Turn on promiscuous mode; turn off the hash filter */ 1543 v |= HME_MAC_RXCFG_PMISC; 1544 v &= ~HME_MAC_RXCFG_HENABLE; 1545 ifp->if_flags |= IFF_ALLMULTI; 1546 goto chipit; 1547 } 1548 1549 /* Turn off promiscuous mode; turn on the hash filter */ 1550 v &= ~HME_MAC_RXCFG_PMISC; 1551 v |= HME_MAC_RXCFG_HENABLE; 1552 1553 /* 1554 * Set up multicast address filter by passing all multicast addresses 1555 * through a crc generator, and then using the high order 6 bits as an 1556 * index into the 64 bit logical address filter. The high order bit 1557 * selects the word, while the rest of the bits select the bit within 1558 * the word. 1559 */ 1560 1561 ETHER_FIRST_MULTI(step, ec, enm); 1562 while (enm != NULL) { 1563 if (ether_cmp(enm->enm_addrlo, enm->enm_addrhi)) { 1564 /* 1565 * We must listen to a range of multicast addresses. 1566 * For now, just accept all multicasts, rather than 1567 * trying to set only those filter bits needed to match 1568 * the range. (At this time, the only use of address 1569 * ranges is for IP multicast routing, for which the 1570 * range is big enough to require all bits set.) 1571 */ 1572 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1573 ifp->if_flags |= IFF_ALLMULTI; 1574 goto chipit; 1575 } 1576 1577 cp = enm->enm_addrlo; 1578 crc = 0xffffffff; 1579 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1580 int octet = *cp++; 1581 int i; 1582 1583 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1584 for (i = 0; i < 8; i++) { 1585 if ((crc & 1) ^ (octet & 1)) { 1586 crc >>= 1; 1587 crc ^= MC_POLY_LE; 1588 } else { 1589 crc >>= 1; 1590 } 1591 octet >>= 1; 1592 } 1593 } 1594 /* Just want the 6 most significant bits. */ 1595 crc >>= 26; 1596 1597 /* Set the corresponding bit in the filter. */ 1598 hash[crc >> 4] |= 1 << (crc & 0xf); 1599 1600 ETHER_NEXT_MULTI(step, enm); 1601 } 1602 1603 ifp->if_flags &= ~IFF_ALLMULTI; 1604 1605 chipit: 1606 /* Now load the hash table into the chip */ 1607 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1608 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1609 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1610 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1611 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1612 } 1613 1614 /* 1615 * Routines for accessing the transmit and receive buffers. 1616 * The various CPU and adapter configurations supported by this 1617 * driver require three different access methods for buffers 1618 * and descriptors: 1619 * (1) contig (contiguous data; no padding), 1620 * (2) gap2 (two bytes of data followed by two bytes of padding), 1621 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1622 */ 1623 1624 #if 0 1625 /* 1626 * contig: contiguous data with no padding. 1627 * 1628 * Buffers may have any alignment. 1629 */ 1630 1631 void 1632 hme_copytobuf_contig(sc, from, ri, len) 1633 struct hme_softc *sc; 1634 void *from; 1635 int ri, len; 1636 { 1637 volatile void *buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1638 1639 /* 1640 * Just call memcpy() to do the work. 1641 */ 1642 memcpy(buf, from, len); 1643 } 1644 1645 void 1646 hme_copyfrombuf_contig(sc, to, boff, len) 1647 struct hme_softc *sc; 1648 void *to; 1649 int boff, len; 1650 { 1651 volatile void *buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1652 1653 /* 1654 * Just call memcpy() to do the work. 1655 */ 1656 memcpy(to, buf, len); 1657 } 1658 #endif 1659