1 /* $NetBSD: hme.c,v 1.74 2009/03/29 07:33:52 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * HME Ethernet module driver. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.74 2009/03/29 07:33:52 tsutsui Exp $"); 38 39 /* #define HMEDEBUG */ 40 41 #include "opt_inet.h" 42 #include "bpfilter.h" 43 #include "rnd.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/mbuf.h> 49 #include <sys/syslog.h> 50 #include <sys/socket.h> 51 #include <sys/device.h> 52 #include <sys/malloc.h> 53 #include <sys/ioctl.h> 54 #include <sys/errno.h> 55 #if NRND > 0 56 #include <sys/rnd.h> 57 #endif 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_ether.h> 62 #include <net/if_media.h> 63 64 #ifdef INET 65 #include <net/if_vlanvar.h> 66 #include <netinet/in.h> 67 #include <netinet/if_inarp.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/ip.h> 71 #include <netinet/tcp.h> 72 #include <netinet/udp.h> 73 #endif 74 75 76 #if NBPFILTER > 0 77 #include <net/bpf.h> 78 #include <net/bpfdesc.h> 79 #endif 80 81 #include <dev/mii/mii.h> 82 #include <dev/mii/miivar.h> 83 84 #include <sys/bus.h> 85 86 #include <dev/ic/hmereg.h> 87 #include <dev/ic/hmevar.h> 88 89 void hme_start(struct ifnet *); 90 void hme_stop(struct hme_softc *,bool); 91 int hme_ioctl(struct ifnet *, u_long, void *); 92 void hme_tick(void *); 93 void hme_watchdog(struct ifnet *); 94 void hme_shutdown(void *); 95 int hme_init(struct hme_softc *); 96 void hme_meminit(struct hme_softc *); 97 void hme_mifinit(struct hme_softc *); 98 void hme_reset(struct hme_softc *); 99 void hme_setladrf(struct hme_softc *); 100 101 /* MII methods & callbacks */ 102 static int hme_mii_readreg(struct device *, int, int); 103 static void hme_mii_writereg(struct device *, int, int, int); 104 static void hme_mii_statchg(struct device *); 105 106 int hme_mediachange(struct ifnet *); 107 108 struct mbuf *hme_get(struct hme_softc *, int, uint32_t); 109 int hme_put(struct hme_softc *, int, struct mbuf *); 110 void hme_read(struct hme_softc *, int, uint32_t); 111 int hme_eint(struct hme_softc *, u_int); 112 int hme_rint(struct hme_softc *); 113 int hme_tint(struct hme_softc *); 114 115 /* Default buffer copy routines */ 116 void hme_copytobuf_contig(struct hme_softc *, void *, int, int); 117 void hme_copyfrombuf_contig(struct hme_softc *, void *, int, int); 118 void hme_zerobuf_contig(struct hme_softc *, int, int); 119 120 121 void 122 hme_config(struct hme_softc *sc) 123 { 124 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 125 struct mii_data *mii = &sc->sc_mii; 126 struct mii_softc *child; 127 bus_dma_tag_t dmatag = sc->sc_dmatag; 128 bus_dma_segment_t seg; 129 bus_size_t size; 130 int rseg, error; 131 132 /* 133 * HME common initialization. 134 * 135 * hme_softc fields that must be initialized by the front-end: 136 * 137 * the bus tag: 138 * sc_bustag 139 * 140 * the DMA bus tag: 141 * sc_dmatag 142 * 143 * the bus handles: 144 * sc_seb (Shared Ethernet Block registers) 145 * sc_erx (Receiver Unit registers) 146 * sc_etx (Transmitter Unit registers) 147 * sc_mac (MAC registers) 148 * sc_mif (Management Interface registers) 149 * 150 * the maximum bus burst size: 151 * sc_burst 152 * 153 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 154 * rb_membase, rb_dmabase) 155 * 156 * the local Ethernet address: 157 * sc_enaddr 158 * 159 */ 160 161 /* Make sure the chip is stopped. */ 162 hme_stop(sc, true); 163 164 165 /* 166 * Allocate descriptors and buffers 167 * XXX - do all this differently.. and more configurably, 168 * eg. use things as `dma_load_mbuf()' on transmit, 169 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 170 * all the time) on the receiver side. 171 * 172 * Note: receive buffers must be 64-byte aligned. 173 * Also, apparently, the buffers must extend to a DMA burst 174 * boundary beyond the maximum packet size. 175 */ 176 #define _HME_NDESC 128 177 #define _HME_BUFSZ 1600 178 179 /* Note: the # of descriptors must be a multiple of 16 */ 180 sc->sc_rb.rb_ntbuf = _HME_NDESC; 181 sc->sc_rb.rb_nrbuf = _HME_NDESC; 182 183 /* 184 * Allocate DMA capable memory 185 * Buffer descriptors must be aligned on a 2048 byte boundary; 186 * take this into account when calculating the size. Note that 187 * the maximum number of descriptors (256) occupies 2048 bytes, 188 * so we allocate that much regardless of _HME_NDESC. 189 */ 190 size = 2048 + /* TX descriptors */ 191 2048 + /* RX descriptors */ 192 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 193 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* RX buffers */ 194 195 /* Allocate DMA buffer */ 196 if ((error = bus_dmamem_alloc(dmatag, size, 197 2048, 0, 198 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 199 aprint_error_dev(&sc->sc_dev, "DMA buffer alloc error %d\n", 200 error); 201 return; 202 } 203 204 /* Map DMA memory in CPU addressable space */ 205 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 206 &sc->sc_rb.rb_membase, 207 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 208 aprint_error_dev(&sc->sc_dev, "DMA buffer map error %d\n", 209 error); 210 bus_dmamap_unload(dmatag, sc->sc_dmamap); 211 bus_dmamem_free(dmatag, &seg, rseg); 212 return; 213 } 214 215 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 216 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 217 aprint_error_dev(&sc->sc_dev, "DMA map create error %d\n", 218 error); 219 return; 220 } 221 222 /* Load the buffer */ 223 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 224 sc->sc_rb.rb_membase, size, NULL, 225 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 226 aprint_error_dev(&sc->sc_dev, "DMA buffer map load error %d\n", 227 error); 228 bus_dmamem_free(dmatag, &seg, rseg); 229 return; 230 } 231 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 232 233 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 234 ether_sprintf(sc->sc_enaddr)); 235 236 /* Initialize ifnet structure. */ 237 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 238 ifp->if_softc = sc; 239 ifp->if_start = hme_start; 240 ifp->if_ioctl = hme_ioctl; 241 ifp->if_watchdog = hme_watchdog; 242 ifp->if_flags = 243 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 244 sc->sc_if_flags = ifp->if_flags; 245 ifp->if_capabilities |= 246 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 247 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 248 IFQ_SET_READY(&ifp->if_snd); 249 250 /* Initialize ifmedia structures and MII info */ 251 mii->mii_ifp = ifp; 252 mii->mii_readreg = hme_mii_readreg; 253 mii->mii_writereg = hme_mii_writereg; 254 mii->mii_statchg = hme_mii_statchg; 255 256 sc->sc_ethercom.ec_mii = mii; 257 ifmedia_init(&mii->mii_media, 0, hme_mediachange, ether_mediastatus); 258 259 hme_mifinit(sc); 260 261 mii_attach(&sc->sc_dev, mii, 0xffffffff, 262 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 263 264 child = LIST_FIRST(&mii->mii_phys); 265 if (child == NULL) { 266 /* No PHY attached */ 267 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 268 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 269 } else { 270 /* 271 * Walk along the list of attached MII devices and 272 * establish an `MII instance' to `phy number' 273 * mapping. We'll use this mapping in media change 274 * requests to determine which phy to use to program 275 * the MIF configuration register. 276 */ 277 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 278 /* 279 * Note: we support just two PHYs: the built-in 280 * internal device and an external on the MII 281 * connector. 282 */ 283 if (child->mii_phy > 1 || child->mii_inst > 1) { 284 aprint_error_dev(&sc->sc_dev, "cannot accommodate MII device %s" 285 " at phy %d, instance %d\n", 286 device_xname(child->mii_dev), 287 child->mii_phy, child->mii_inst); 288 continue; 289 } 290 291 sc->sc_phys[child->mii_inst] = child->mii_phy; 292 } 293 294 /* 295 * XXX - we can really do the following ONLY if the 296 * phy indeed has the auto negotiation capability!! 297 */ 298 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 299 } 300 301 /* claim 802.1q capability */ 302 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 303 304 /* Attach the interface. */ 305 if_attach(ifp); 306 ether_ifattach(ifp, sc->sc_enaddr); 307 308 sc->sc_sh = shutdownhook_establish(hme_shutdown, sc); 309 if (sc->sc_sh == NULL) 310 panic("hme_config: can't establish shutdownhook"); 311 312 #if NRND > 0 313 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 314 RND_TYPE_NET, 0); 315 #endif 316 317 callout_init(&sc->sc_tick_ch, 0); 318 } 319 320 void 321 hme_tick(void *arg) 322 { 323 struct hme_softc *sc = arg; 324 int s; 325 326 s = splnet(); 327 mii_tick(&sc->sc_mii); 328 splx(s); 329 330 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 331 } 332 333 void 334 hme_reset(struct hme_softc *sc) 335 { 336 int s; 337 338 s = splnet(); 339 (void)hme_init(sc); 340 splx(s); 341 } 342 343 void 344 hme_stop(struct hme_softc *sc, bool chip_only) 345 { 346 bus_space_tag_t t = sc->sc_bustag; 347 bus_space_handle_t seb = sc->sc_seb; 348 int n; 349 350 if (!chip_only) { 351 callout_stop(&sc->sc_tick_ch); 352 mii_down(&sc->sc_mii); 353 } 354 355 /* Mask all interrupts */ 356 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff); 357 358 /* Reset transmitter and receiver */ 359 bus_space_write_4(t, seb, HME_SEBI_RESET, 360 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 361 362 for (n = 0; n < 20; n++) { 363 u_int32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 364 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 365 return; 366 DELAY(20); 367 } 368 369 printf("%s: hme_stop: reset failed\n", device_xname(&sc->sc_dev)); 370 } 371 372 void 373 hme_meminit(struct hme_softc *sc) 374 { 375 bus_addr_t txbufdma, rxbufdma; 376 bus_addr_t dma; 377 char *p; 378 unsigned int ntbuf, nrbuf, i; 379 struct hme_ring *hr = &sc->sc_rb; 380 381 p = hr->rb_membase; 382 dma = hr->rb_dmabase; 383 384 ntbuf = hr->rb_ntbuf; 385 nrbuf = hr->rb_nrbuf; 386 387 /* 388 * Allocate transmit descriptors 389 */ 390 hr->rb_txd = p; 391 hr->rb_txddma = dma; 392 p += ntbuf * HME_XD_SIZE; 393 dma += ntbuf * HME_XD_SIZE; 394 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 395 dma = (bus_addr_t)roundup((u_long)dma, 2048); 396 p = (void *)roundup((u_long)p, 2048); 397 398 /* 399 * Allocate receive descriptors 400 */ 401 hr->rb_rxd = p; 402 hr->rb_rxddma = dma; 403 p += nrbuf * HME_XD_SIZE; 404 dma += nrbuf * HME_XD_SIZE; 405 /* Again move forward to the next 2048 byte boundary.*/ 406 dma = (bus_addr_t)roundup((u_long)dma, 2048); 407 p = (void *)roundup((u_long)p, 2048); 408 409 410 /* 411 * Allocate transmit buffers 412 */ 413 hr->rb_txbuf = p; 414 txbufdma = dma; 415 p += ntbuf * _HME_BUFSZ; 416 dma += ntbuf * _HME_BUFSZ; 417 418 /* 419 * Allocate receive buffers 420 */ 421 hr->rb_rxbuf = p; 422 rxbufdma = dma; 423 p += nrbuf * _HME_BUFSZ; 424 dma += nrbuf * _HME_BUFSZ; 425 426 /* 427 * Initialize transmit buffer descriptors 428 */ 429 for (i = 0; i < ntbuf; i++) { 430 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 431 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 432 } 433 434 /* 435 * Initialize receive buffer descriptors 436 */ 437 for (i = 0; i < nrbuf; i++) { 438 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 439 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 440 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 441 } 442 443 hr->rb_tdhead = hr->rb_tdtail = 0; 444 hr->rb_td_nbusy = 0; 445 hr->rb_rdtail = 0; 446 } 447 448 /* 449 * Initialization of interface; set up initialization block 450 * and transmit/receive descriptor rings. 451 */ 452 int 453 hme_init(struct hme_softc *sc) 454 { 455 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 456 bus_space_tag_t t = sc->sc_bustag; 457 bus_space_handle_t seb = sc->sc_seb; 458 bus_space_handle_t etx = sc->sc_etx; 459 bus_space_handle_t erx = sc->sc_erx; 460 bus_space_handle_t mac = sc->sc_mac; 461 u_int8_t *ea; 462 u_int32_t v; 463 int rc; 464 465 /* 466 * Initialization sequence. The numbered steps below correspond 467 * to the sequence outlined in section 6.3.5.1 in the Ethernet 468 * Channel Engine manual (part of the PCIO manual). 469 * See also the STP2002-STQ document from Sun Microsystems. 470 */ 471 472 /* step 1 & 2. Reset the Ethernet Channel */ 473 hme_stop(sc, false); 474 475 /* Re-initialize the MIF */ 476 hme_mifinit(sc); 477 478 /* Call MI reset function if any */ 479 if (sc->sc_hwreset) 480 (*sc->sc_hwreset)(sc); 481 482 #if 0 483 /* Mask all MIF interrupts, just in case */ 484 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 485 #endif 486 487 /* step 3. Setup data structures in host memory */ 488 hme_meminit(sc); 489 490 /* step 4. TX MAC registers & counters */ 491 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 492 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 493 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 494 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 495 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 496 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 497 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 498 sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable; 499 500 /* Load station MAC address */ 501 ea = sc->sc_enaddr; 502 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 503 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 504 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 505 506 /* 507 * Init seed for backoff 508 * (source suggested by manual: low 10 bits of MAC address) 509 */ 510 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 511 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 512 513 514 /* Note: Accepting power-on default for other MAC registers here.. */ 515 516 517 /* step 5. RX MAC registers & counters */ 518 hme_setladrf(sc); 519 520 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 521 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 522 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 523 524 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 525 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 526 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 527 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 528 529 /* step 8. Global Configuration & Interrupt Mask */ 530 bus_space_write_4(t, seb, HME_SEBI_IMASK, 531 ~( 532 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 533 HME_SEB_STAT_HOSTTOTX | 534 HME_SEB_STAT_RXTOHOST | 535 HME_SEB_STAT_TXALL | 536 HME_SEB_STAT_TXPERR | 537 HME_SEB_STAT_RCNTEXP | 538 /*HME_SEB_STAT_MIFIRQ |*/ 539 HME_SEB_STAT_ALL_ERRORS )); 540 541 switch (sc->sc_burst) { 542 default: 543 v = 0; 544 break; 545 case 16: 546 v = HME_SEB_CFG_BURST16; 547 break; 548 case 32: 549 v = HME_SEB_CFG_BURST32; 550 break; 551 case 64: 552 v = HME_SEB_CFG_BURST64; 553 break; 554 } 555 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 556 557 /* step 9. ETX Configuration: use mostly default values */ 558 559 /* Enable DMA */ 560 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 561 v |= HME_ETX_CFG_DMAENABLE; 562 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 563 564 /* Transmit Descriptor ring size: in increments of 16 */ 565 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 566 567 568 /* step 10. ERX Configuration */ 569 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 570 571 /* Encode Receive Descriptor ring size: four possible values */ 572 switch (_HME_NDESC /*XXX*/) { 573 case 32: 574 v |= HME_ERX_CFG_RINGSIZE32; 575 break; 576 case 64: 577 v |= HME_ERX_CFG_RINGSIZE64; 578 break; 579 case 128: 580 v |= HME_ERX_CFG_RINGSIZE128; 581 break; 582 case 256: 583 v |= HME_ERX_CFG_RINGSIZE256; 584 break; 585 default: 586 printf("hme: invalid Receive Descriptor ring size\n"); 587 break; 588 } 589 590 /* Enable DMA */ 591 v |= HME_ERX_CFG_DMAENABLE; 592 593 /* set h/w rx checksum start offset (# of half-words) */ 594 #ifdef INET 595 v |= (((ETHER_HDR_LEN + sizeof(struct ip)) / sizeof(uint16_t)) 596 << HME_ERX_CFG_CSUMSHIFT) & 597 HME_ERX_CFG_CSUMSTART; 598 #endif 599 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 600 601 /* step 11. XIF Configuration */ 602 v = bus_space_read_4(t, mac, HME_MACI_XIF); 603 v |= HME_MAC_XIF_OE; 604 bus_space_write_4(t, mac, HME_MACI_XIF, v); 605 606 /* step 12. RX_MAC Configuration Register */ 607 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 608 v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP; 609 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 610 611 /* step 13. TX_MAC Configuration Register */ 612 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 613 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 614 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 615 616 /* step 14. Issue Transmit Pending command */ 617 618 /* Call MI initialization function if any */ 619 if (sc->sc_hwinit) 620 (*sc->sc_hwinit)(sc); 621 622 /* Set the current media. */ 623 if ((rc = hme_mediachange(ifp)) != 0) 624 return rc; 625 626 /* Start the one second timer. */ 627 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 628 629 ifp->if_flags |= IFF_RUNNING; 630 ifp->if_flags &= ~IFF_OACTIVE; 631 sc->sc_if_flags = ifp->if_flags; 632 ifp->if_timer = 0; 633 hme_start(ifp); 634 return 0; 635 } 636 637 /* 638 * Routine to copy from mbuf chain to transmit buffer in 639 * network buffer memory. 640 * Returns the amount of data copied. 641 */ 642 int 643 hme_put(struct hme_softc *sc, int ri, struct mbuf *m) 644 /* ri: Ring index */ 645 { 646 struct mbuf *n; 647 int len, tlen = 0; 648 char *bp; 649 650 bp = (char *)sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 651 for (; m; m = n) { 652 len = m->m_len; 653 if (len == 0) { 654 MFREE(m, n); 655 continue; 656 } 657 memcpy(bp, mtod(m, void *), len); 658 bp += len; 659 tlen += len; 660 MFREE(m, n); 661 } 662 return (tlen); 663 } 664 665 /* 666 * Pull data off an interface. 667 * Len is length of data, with local net header stripped. 668 * We copy the data into mbufs. When full cluster sized units are present 669 * we copy into clusters. 670 */ 671 struct mbuf * 672 hme_get(struct hme_softc *sc, int ri, u_int32_t flags) 673 { 674 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 675 struct mbuf *m, *m0, *newm; 676 char *bp; 677 int len, totlen; 678 679 totlen = HME_XD_DECODE_RSIZE(flags); 680 MGETHDR(m0, M_DONTWAIT, MT_DATA); 681 if (m0 == 0) 682 return (0); 683 m0->m_pkthdr.rcvif = ifp; 684 m0->m_pkthdr.len = totlen; 685 len = MHLEN; 686 m = m0; 687 688 bp = (char *)sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 689 690 while (totlen > 0) { 691 if (totlen >= MINCLSIZE) { 692 MCLGET(m, M_DONTWAIT); 693 if ((m->m_flags & M_EXT) == 0) 694 goto bad; 695 len = MCLBYTES; 696 } 697 698 if (m == m0) { 699 char *newdata = (char *) 700 ALIGN(m->m_data + sizeof(struct ether_header)) - 701 sizeof(struct ether_header); 702 len -= newdata - m->m_data; 703 m->m_data = newdata; 704 } 705 706 m->m_len = len = min(totlen, len); 707 memcpy(mtod(m, void *), bp, len); 708 bp += len; 709 710 totlen -= len; 711 if (totlen > 0) { 712 MGET(newm, M_DONTWAIT, MT_DATA); 713 if (newm == 0) 714 goto bad; 715 len = MLEN; 716 m = m->m_next = newm; 717 } 718 } 719 720 #ifdef INET 721 /* hardware checksum */ 722 if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 723 struct ether_header *eh; 724 struct ether_vlan_header *evh; 725 struct ip *ip; 726 struct udphdr *uh; 727 uint16_t *opts; 728 int32_t hlen, pktlen; 729 uint32_t temp; 730 731 eh = mtod(m0, struct ether_header *); 732 if (ntohs(eh->ether_type) == ETHERTYPE_IP) { 733 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN); 734 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN; 735 } else if (ntohs(eh->ether_type) == ETHERTYPE_VLAN) { 736 evh = (struct ether_vlan_header *)eh; 737 if (ntohs(evh->evl_proto != ETHERTYPE_IP)) 738 goto swcsum; 739 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN + 740 ETHER_VLAN_ENCAP_LEN); 741 pktlen = m0->m_pkthdr.len - 742 ETHER_HDR_LEN - ETHER_VLAN_ENCAP_LEN; 743 } else 744 goto swcsum; 745 746 /* IPv4 only */ 747 if (ip->ip_v != IPVERSION) 748 goto swcsum; 749 750 hlen = ip->ip_hl << 2; 751 if (hlen < sizeof(struct ip)) 752 goto swcsum; 753 754 /* 755 * bail if too short, has random trailing garbage, truncated, 756 * fragment, or has ethernet pad. 757 */ 758 if ((ntohs(ip->ip_len) < hlen) || (ntohs(ip->ip_len) != pktlen) 759 || (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 760 goto swcsum; 761 762 switch (ip->ip_p) { 763 case IPPROTO_TCP: 764 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 765 goto swcsum; 766 if (pktlen < (hlen + sizeof(struct tcphdr))) 767 goto swcsum; 768 m0->m_pkthdr.csum_flags = M_CSUM_TCPv4; 769 break; 770 case IPPROTO_UDP: 771 if (! (ifp->if_csum_flags_rx & M_CSUM_UDPv4)) 772 goto swcsum; 773 if (pktlen < (hlen + sizeof(struct udphdr))) 774 goto swcsum; 775 uh = (struct udphdr *)((char *)ip + hlen); 776 /* no checksum */ 777 if (uh->uh_sum == 0) 778 goto swcsum; 779 m0->m_pkthdr.csum_flags = M_CSUM_UDPv4; 780 break; 781 default: 782 goto swcsum; 783 } 784 785 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */ 786 m0->m_pkthdr.csum_data = (~flags) & HME_XD_RXCKSUM; 787 788 /* 789 * If data offset is different from RX cksum start offset, 790 * we have to deduct them. 791 */ 792 temp = ((char *)ip + hlen) - 793 ((char *)eh + ETHER_HDR_LEN + sizeof(struct ip)); 794 if (temp > 1) { 795 uint32_t optsum; 796 797 optsum = 0; 798 opts = (uint16_t *)((char *)eh + 799 ETHER_HDR_LEN + sizeof(struct ip)); 800 801 while (temp > 1) { 802 optsum += ntohs(*opts++); 803 temp -= 2; 804 } 805 while (optsum >> 16) 806 optsum = (optsum >> 16) + (optsum & 0xffff); 807 808 /* Deduct the ip opts sum from the hwsum. */ 809 m0->m_pkthdr.csum_data += (uint16_t)~optsum; 810 811 while (m0->m_pkthdr.csum_data >> 16) 812 m0->m_pkthdr.csum_data = 813 (m0->m_pkthdr.csum_data >> 16) + 814 (m0->m_pkthdr.csum_data & 0xffff); 815 } 816 817 m0->m_pkthdr.csum_flags |= M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 818 } else 819 swcsum: 820 m0->m_pkthdr.csum_flags = 0; 821 #endif 822 823 return (m0); 824 825 bad: 826 m_freem(m0); 827 return (0); 828 } 829 830 /* 831 * Pass a packet to the higher levels. 832 */ 833 void 834 hme_read(struct hme_softc *sc, int ix, u_int32_t flags) 835 { 836 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 837 struct mbuf *m; 838 int len; 839 840 len = HME_XD_DECODE_RSIZE(flags); 841 if (len <= sizeof(struct ether_header) || 842 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 843 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 844 ETHERMTU + sizeof(struct ether_header))) { 845 #ifdef HMEDEBUG 846 printf("%s: invalid packet size %d; dropping\n", 847 device_xname(&sc->sc_dev), len); 848 #endif 849 ifp->if_ierrors++; 850 return; 851 } 852 853 /* Pull packet off interface. */ 854 m = hme_get(sc, ix, flags); 855 if (m == 0) { 856 ifp->if_ierrors++; 857 return; 858 } 859 860 ifp->if_ipackets++; 861 862 #if NBPFILTER > 0 863 /* 864 * Check if there's a BPF listener on this interface. 865 * If so, hand off the raw packet to BPF. 866 */ 867 if (ifp->if_bpf) 868 bpf_mtap(ifp->if_bpf, m); 869 #endif 870 871 /* Pass the packet up. */ 872 (*ifp->if_input)(ifp, m); 873 } 874 875 void 876 hme_start(struct ifnet *ifp) 877 { 878 struct hme_softc *sc = (struct hme_softc *)ifp->if_softc; 879 void *txd = sc->sc_rb.rb_txd; 880 struct mbuf *m; 881 unsigned int txflags; 882 unsigned int ri, len; 883 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 884 885 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 886 return; 887 888 ri = sc->sc_rb.rb_tdhead; 889 890 for (;;) { 891 IFQ_DEQUEUE(&ifp->if_snd, m); 892 if (m == 0) 893 break; 894 895 #if NBPFILTER > 0 896 /* 897 * If BPF is listening on this interface, let it see the 898 * packet before we commit it to the wire. 899 */ 900 if (ifp->if_bpf) 901 bpf_mtap(ifp->if_bpf, m); 902 #endif 903 904 #ifdef INET 905 /* collect bits for h/w csum, before hme_put frees the mbuf */ 906 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) && 907 m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 908 struct ether_header *eh; 909 uint16_t offset, start; 910 911 eh = mtod(m, struct ether_header *); 912 switch (ntohs(eh->ether_type)) { 913 case ETHERTYPE_IP: 914 start = ETHER_HDR_LEN; 915 break; 916 case ETHERTYPE_VLAN: 917 start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 918 break; 919 default: 920 /* unsupported, drop it */ 921 m_free(m); 922 continue; 923 } 924 start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 925 offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data) 926 + start; 927 txflags = HME_XD_TXCKSUM | 928 (offset << HME_XD_TXCSSTUFFSHIFT) | 929 (start << HME_XD_TXCSSTARTSHIFT); 930 } else 931 #endif 932 txflags = 0; 933 934 /* 935 * Copy the mbuf chain into the transmit buffer. 936 */ 937 len = hme_put(sc, ri, m); 938 939 /* 940 * Initialize transmit registers and start transmission 941 */ 942 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 943 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 944 HME_XD_ENCODE_TSIZE(len) | txflags); 945 946 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 947 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 948 HME_ETX_TP_DMAWAKEUP); 949 950 if (++ri == ntbuf) 951 ri = 0; 952 953 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 954 ifp->if_flags |= IFF_OACTIVE; 955 break; 956 } 957 } 958 959 sc->sc_rb.rb_tdhead = ri; 960 } 961 962 /* 963 * Transmit interrupt. 964 */ 965 int 966 hme_tint(struct hme_softc *sc) 967 { 968 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 969 bus_space_tag_t t = sc->sc_bustag; 970 bus_space_handle_t mac = sc->sc_mac; 971 unsigned int ri, txflags; 972 973 /* 974 * Unload collision counters 975 */ 976 ifp->if_collisions += 977 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 978 bus_space_read_4(t, mac, HME_MACI_FCCNT) + 979 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 980 bus_space_read_4(t, mac, HME_MACI_LTCNT); 981 982 /* 983 * then clear the hardware counters. 984 */ 985 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 986 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 987 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 988 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 989 990 /* Fetch current position in the transmit ring */ 991 ri = sc->sc_rb.rb_tdtail; 992 993 for (;;) { 994 if (sc->sc_rb.rb_td_nbusy <= 0) 995 break; 996 997 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 998 999 if (txflags & HME_XD_OWN) 1000 break; 1001 1002 ifp->if_flags &= ~IFF_OACTIVE; 1003 ifp->if_opackets++; 1004 1005 if (++ri == sc->sc_rb.rb_ntbuf) 1006 ri = 0; 1007 1008 --sc->sc_rb.rb_td_nbusy; 1009 } 1010 1011 /* Update ring */ 1012 sc->sc_rb.rb_tdtail = ri; 1013 1014 hme_start(ifp); 1015 1016 if (sc->sc_rb.rb_td_nbusy == 0) 1017 ifp->if_timer = 0; 1018 1019 return (1); 1020 } 1021 1022 /* 1023 * Receive interrupt. 1024 */ 1025 int 1026 hme_rint(struct hme_softc *sc) 1027 { 1028 void *xdr = sc->sc_rb.rb_rxd; 1029 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 1030 unsigned int ri; 1031 u_int32_t flags; 1032 1033 ri = sc->sc_rb.rb_rdtail; 1034 1035 /* 1036 * Process all buffers with valid data. 1037 */ 1038 for (;;) { 1039 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 1040 if (flags & HME_XD_OWN) 1041 break; 1042 1043 if (flags & HME_XD_OFL) { 1044 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 1045 device_xname(&sc->sc_dev), ri, flags); 1046 } else 1047 hme_read(sc, ri, flags); 1048 1049 /* This buffer can be used by the hardware again */ 1050 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 1051 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 1052 1053 if (++ri == nrbuf) 1054 ri = 0; 1055 } 1056 1057 sc->sc_rb.rb_rdtail = ri; 1058 1059 return (1); 1060 } 1061 1062 int 1063 hme_eint(struct hme_softc *sc, u_int status) 1064 { 1065 char bits[128]; 1066 1067 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 1068 bus_space_tag_t t = sc->sc_bustag; 1069 bus_space_handle_t mif = sc->sc_mif; 1070 u_int32_t cf, st, sm; 1071 cf = bus_space_read_4(t, mif, HME_MIFI_CFG); 1072 st = bus_space_read_4(t, mif, HME_MIFI_STAT); 1073 sm = bus_space_read_4(t, mif, HME_MIFI_SM); 1074 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n", 1075 device_xname(&sc->sc_dev), cf, st, sm); 1076 return (1); 1077 } 1078 snprintb(bits, sizeof(bits), HME_SEB_STAT_BITS, status); 1079 printf("%s: status=%s\n", device_xname(&sc->sc_dev), bits); 1080 1081 return (1); 1082 } 1083 1084 int 1085 hme_intr(void *v) 1086 { 1087 struct hme_softc *sc = (struct hme_softc *)v; 1088 bus_space_tag_t t = sc->sc_bustag; 1089 bus_space_handle_t seb = sc->sc_seb; 1090 u_int32_t status; 1091 int r = 0; 1092 1093 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 1094 1095 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 1096 r |= hme_eint(sc, status); 1097 1098 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 1099 r |= hme_tint(sc); 1100 1101 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1102 r |= hme_rint(sc); 1103 1104 #if NRND > 0 1105 rnd_add_uint32(&sc->rnd_source, status); 1106 #endif 1107 1108 return (r); 1109 } 1110 1111 1112 void 1113 hme_watchdog(struct ifnet *ifp) 1114 { 1115 struct hme_softc *sc = ifp->if_softc; 1116 1117 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev)); 1118 ++ifp->if_oerrors; 1119 1120 hme_reset(sc); 1121 } 1122 1123 /* 1124 * Initialize the MII Management Interface 1125 */ 1126 void 1127 hme_mifinit(struct hme_softc *sc) 1128 { 1129 bus_space_tag_t t = sc->sc_bustag; 1130 bus_space_handle_t mif = sc->sc_mif; 1131 bus_space_handle_t mac = sc->sc_mac; 1132 int instance, phy; 1133 u_int32_t v; 1134 1135 if (sc->sc_mii.mii_media.ifm_cur != NULL) { 1136 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1137 phy = sc->sc_phys[instance]; 1138 } else 1139 /* No media set yet, pick phy arbitrarily.. */ 1140 phy = HME_PHYAD_EXTERNAL; 1141 1142 /* Configure the MIF in frame mode, no poll, current phy select */ 1143 v = 0; 1144 if (phy == HME_PHYAD_EXTERNAL) 1145 v |= HME_MIF_CFG_PHY; 1146 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1147 1148 /* If an external transceiver is selected, enable its MII drivers */ 1149 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1150 v &= ~HME_MAC_XIF_MIIENABLE; 1151 if (phy == HME_PHYAD_EXTERNAL) 1152 v |= HME_MAC_XIF_MIIENABLE; 1153 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1154 } 1155 1156 /* 1157 * MII interface 1158 */ 1159 static int 1160 hme_mii_readreg(struct device *self, int phy, int reg) 1161 { 1162 struct hme_softc *sc = (void *)self; 1163 bus_space_tag_t t = sc->sc_bustag; 1164 bus_space_handle_t mif = sc->sc_mif; 1165 bus_space_handle_t mac = sc->sc_mac; 1166 u_int32_t v, xif_cfg, mifi_cfg; 1167 int n; 1168 1169 /* We can at most have two PHYs */ 1170 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1171 return (0); 1172 1173 /* Select the desired PHY in the MIF configuration register */ 1174 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1175 v &= ~HME_MIF_CFG_PHY; 1176 if (phy == HME_PHYAD_EXTERNAL) 1177 v |= HME_MIF_CFG_PHY; 1178 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1179 1180 /* Enable MII drivers on external transceiver */ 1181 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1182 if (phy == HME_PHYAD_EXTERNAL) 1183 v |= HME_MAC_XIF_MIIENABLE; 1184 else 1185 v &= ~HME_MAC_XIF_MIIENABLE; 1186 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1187 1188 #if 0 1189 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1190 /* 1191 * Check whether a transceiver is connected by testing 1192 * the MIF configuration register's MDI_X bits. Note that 1193 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1194 */ 1195 mif_mdi_bit = 1 << (8 + (1 - phy)); 1196 delay(100); 1197 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1198 if ((v & mif_mdi_bit) == 0) 1199 return (0); 1200 #endif 1201 1202 /* Construct the frame command */ 1203 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1204 HME_MIF_FO_TAMSB | 1205 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1206 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1207 (reg << HME_MIF_FO_REGAD_SHIFT); 1208 1209 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1210 for (n = 0; n < 100; n++) { 1211 DELAY(1); 1212 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1213 if (v & HME_MIF_FO_TALSB) { 1214 v &= HME_MIF_FO_DATA; 1215 goto out; 1216 } 1217 } 1218 1219 v = 0; 1220 printf("%s: mii_read timeout\n", device_xname(&sc->sc_dev)); 1221 1222 out: 1223 /* Restore MIFI_CFG register */ 1224 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1225 /* Restore XIF register */ 1226 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1227 return (v); 1228 } 1229 1230 static void 1231 hme_mii_writereg(struct device *self, int phy, int reg, int val) 1232 { 1233 struct hme_softc *sc = (void *)self; 1234 bus_space_tag_t t = sc->sc_bustag; 1235 bus_space_handle_t mif = sc->sc_mif; 1236 bus_space_handle_t mac = sc->sc_mac; 1237 u_int32_t v, xif_cfg, mifi_cfg; 1238 int n; 1239 1240 /* We can at most have two PHYs */ 1241 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1242 return; 1243 1244 /* Select the desired PHY in the MIF configuration register */ 1245 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1246 v &= ~HME_MIF_CFG_PHY; 1247 if (phy == HME_PHYAD_EXTERNAL) 1248 v |= HME_MIF_CFG_PHY; 1249 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1250 1251 /* Enable MII drivers on external transceiver */ 1252 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1253 if (phy == HME_PHYAD_EXTERNAL) 1254 v |= HME_MAC_XIF_MIIENABLE; 1255 else 1256 v &= ~HME_MAC_XIF_MIIENABLE; 1257 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1258 1259 #if 0 1260 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1261 /* 1262 * Check whether a transceiver is connected by testing 1263 * the MIF configuration register's MDI_X bits. Note that 1264 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1265 */ 1266 mif_mdi_bit = 1 << (8 + (1 - phy)); 1267 delay(100); 1268 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1269 if ((v & mif_mdi_bit) == 0) 1270 return; 1271 #endif 1272 1273 /* Construct the frame command */ 1274 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1275 HME_MIF_FO_TAMSB | 1276 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1277 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1278 (reg << HME_MIF_FO_REGAD_SHIFT) | 1279 (val & HME_MIF_FO_DATA); 1280 1281 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1282 for (n = 0; n < 100; n++) { 1283 DELAY(1); 1284 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1285 if (v & HME_MIF_FO_TALSB) 1286 goto out; 1287 } 1288 1289 printf("%s: mii_write timeout\n", device_xname(&sc->sc_dev)); 1290 out: 1291 /* Restore MIFI_CFG register */ 1292 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1293 /* Restore XIF register */ 1294 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1295 } 1296 1297 static void 1298 hme_mii_statchg(struct device *dev) 1299 { 1300 struct hme_softc *sc = (void *)dev; 1301 bus_space_tag_t t = sc->sc_bustag; 1302 bus_space_handle_t mac = sc->sc_mac; 1303 u_int32_t v; 1304 1305 #ifdef HMEDEBUG 1306 if (sc->sc_debug) 1307 printf("hme_mii_statchg: status change\n"); 1308 #endif 1309 1310 /* Set the MAC Full Duplex bit appropriately */ 1311 /* Apparently the hme chip is SIMPLEX if working in full duplex mode, 1312 but not otherwise. */ 1313 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1314 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1315 v |= HME_MAC_TXCFG_FULLDPLX; 1316 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX; 1317 } else { 1318 v &= ~HME_MAC_TXCFG_FULLDPLX; 1319 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX; 1320 } 1321 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags; 1322 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1323 } 1324 1325 int 1326 hme_mediachange(struct ifnet *ifp) 1327 { 1328 struct hme_softc *sc = ifp->if_softc; 1329 bus_space_tag_t t = sc->sc_bustag; 1330 bus_space_handle_t mif = sc->sc_mif; 1331 bus_space_handle_t mac = sc->sc_mac; 1332 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1333 int phy = sc->sc_phys[instance]; 1334 int rc; 1335 u_int32_t v; 1336 1337 #ifdef HMEDEBUG 1338 if (sc->sc_debug) 1339 printf("hme_mediachange: phy = %d\n", phy); 1340 #endif 1341 1342 /* Select the current PHY in the MIF configuration register */ 1343 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1344 v &= ~HME_MIF_CFG_PHY; 1345 if (phy == HME_PHYAD_EXTERNAL) 1346 v |= HME_MIF_CFG_PHY; 1347 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1348 1349 /* If an external transceiver is selected, enable its MII drivers */ 1350 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1351 v &= ~HME_MAC_XIF_MIIENABLE; 1352 if (phy == HME_PHYAD_EXTERNAL) 1353 v |= HME_MAC_XIF_MIIENABLE; 1354 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1355 1356 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 1357 return 0; 1358 return rc; 1359 } 1360 1361 /* 1362 * Process an ioctl request. 1363 */ 1364 int 1365 hme_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1366 { 1367 struct hme_softc *sc = ifp->if_softc; 1368 struct ifaddr *ifa = (struct ifaddr *)data; 1369 int s, error = 0; 1370 1371 s = splnet(); 1372 1373 switch (cmd) { 1374 1375 case SIOCINITIFADDR: 1376 switch (ifa->ifa_addr->sa_family) { 1377 #ifdef INET 1378 case AF_INET: 1379 if (ifp->if_flags & IFF_UP) 1380 hme_setladrf(sc); 1381 else { 1382 ifp->if_flags |= IFF_UP; 1383 error = hme_init(sc); 1384 } 1385 arp_ifinit(ifp, ifa); 1386 break; 1387 #endif 1388 default: 1389 ifp->if_flags |= IFF_UP; 1390 error = hme_init(sc); 1391 break; 1392 } 1393 break; 1394 1395 case SIOCSIFFLAGS: 1396 #ifdef HMEDEBUG 1397 { 1398 struct ifreq *ifr = data; 1399 sc->sc_debug = 1400 (ifr->ifr_flags & IFF_DEBUG) != 0 ? 1 : 0; 1401 } 1402 #endif 1403 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1404 break; 1405 1406 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1407 case IFF_RUNNING: 1408 /* 1409 * If interface is marked down and it is running, then 1410 * stop it. 1411 */ 1412 hme_stop(sc, false); 1413 ifp->if_flags &= ~IFF_RUNNING; 1414 break; 1415 case IFF_UP: 1416 /* 1417 * If interface is marked up and it is stopped, then 1418 * start it. 1419 */ 1420 error = hme_init(sc); 1421 break; 1422 case IFF_UP|IFF_RUNNING: 1423 /* 1424 * If setting debug or promiscuous mode, do not reset 1425 * the chip; for everything else, call hme_init() 1426 * which will trigger a reset. 1427 */ 1428 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG) 1429 if (ifp->if_flags != sc->sc_if_flags) { 1430 if ((ifp->if_flags & (~RESETIGN)) 1431 == (sc->sc_if_flags & (~RESETIGN))) 1432 hme_setladrf(sc); 1433 else 1434 error = hme_init(sc); 1435 } 1436 #undef RESETIGN 1437 break; 1438 case 0: 1439 break; 1440 } 1441 1442 if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable) 1443 error = hme_init(sc); 1444 1445 break; 1446 1447 default: 1448 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1449 break; 1450 1451 error = 0; 1452 1453 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1454 ; 1455 else if (ifp->if_flags & IFF_RUNNING) { 1456 /* 1457 * Multicast list has changed; set the hardware filter 1458 * accordingly. 1459 */ 1460 hme_setladrf(sc); 1461 } 1462 break; 1463 } 1464 1465 sc->sc_if_flags = ifp->if_flags; 1466 splx(s); 1467 return (error); 1468 } 1469 1470 void 1471 hme_shutdown(void *arg) 1472 { 1473 1474 hme_stop((struct hme_softc *)arg, false); 1475 } 1476 1477 /* 1478 * Set up the logical address filter. 1479 */ 1480 void 1481 hme_setladrf(struct hme_softc *sc) 1482 { 1483 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1484 struct ether_multi *enm; 1485 struct ether_multistep step; 1486 struct ethercom *ec = &sc->sc_ethercom; 1487 bus_space_tag_t t = sc->sc_bustag; 1488 bus_space_handle_t mac = sc->sc_mac; 1489 u_char *cp; 1490 u_int32_t crc; 1491 u_int32_t hash[4]; 1492 u_int32_t v; 1493 int len; 1494 1495 /* Clear hash table */ 1496 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1497 1498 /* Get current RX configuration */ 1499 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1500 1501 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1502 /* Turn on promiscuous mode; turn off the hash filter */ 1503 v |= HME_MAC_RXCFG_PMISC; 1504 v &= ~HME_MAC_RXCFG_HENABLE; 1505 ifp->if_flags |= IFF_ALLMULTI; 1506 goto chipit; 1507 } 1508 1509 /* Turn off promiscuous mode; turn on the hash filter */ 1510 v &= ~HME_MAC_RXCFG_PMISC; 1511 v |= HME_MAC_RXCFG_HENABLE; 1512 1513 /* 1514 * Set up multicast address filter by passing all multicast addresses 1515 * through a crc generator, and then using the high order 6 bits as an 1516 * index into the 64 bit logical address filter. The high order bit 1517 * selects the word, while the rest of the bits select the bit within 1518 * the word. 1519 */ 1520 1521 ETHER_FIRST_MULTI(step, ec, enm); 1522 while (enm != NULL) { 1523 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1524 /* 1525 * We must listen to a range of multicast addresses. 1526 * For now, just accept all multicasts, rather than 1527 * trying to set only those filter bits needed to match 1528 * the range. (At this time, the only use of address 1529 * ranges is for IP multicast routing, for which the 1530 * range is big enough to require all bits set.) 1531 */ 1532 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1533 ifp->if_flags |= IFF_ALLMULTI; 1534 goto chipit; 1535 } 1536 1537 cp = enm->enm_addrlo; 1538 crc = 0xffffffff; 1539 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1540 int octet = *cp++; 1541 int i; 1542 1543 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1544 for (i = 0; i < 8; i++) { 1545 if ((crc & 1) ^ (octet & 1)) { 1546 crc >>= 1; 1547 crc ^= MC_POLY_LE; 1548 } else { 1549 crc >>= 1; 1550 } 1551 octet >>= 1; 1552 } 1553 } 1554 /* Just want the 6 most significant bits. */ 1555 crc >>= 26; 1556 1557 /* Set the corresponding bit in the filter. */ 1558 hash[crc >> 4] |= 1 << (crc & 0xf); 1559 1560 ETHER_NEXT_MULTI(step, enm); 1561 } 1562 1563 ifp->if_flags &= ~IFF_ALLMULTI; 1564 1565 chipit: 1566 /* Now load the hash table into the chip */ 1567 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1568 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1569 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1570 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1571 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1572 } 1573 1574 /* 1575 * Routines for accessing the transmit and receive buffers. 1576 * The various CPU and adapter configurations supported by this 1577 * driver require three different access methods for buffers 1578 * and descriptors: 1579 * (1) contig (contiguous data; no padding), 1580 * (2) gap2 (two bytes of data followed by two bytes of padding), 1581 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1582 */ 1583 1584 #if 0 1585 /* 1586 * contig: contiguous data with no padding. 1587 * 1588 * Buffers may have any alignment. 1589 */ 1590 1591 void 1592 hme_copytobuf_contig(struct hme_softc *sc, void *from, int ri, int len) 1593 { 1594 volatile void *buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1595 1596 /* 1597 * Just call memcpy() to do the work. 1598 */ 1599 memcpy(buf, from, len); 1600 } 1601 1602 void 1603 hme_copyfrombuf_contig(struct hme_softc *sc, void *to, int boff, int len) 1604 { 1605 volatile void *buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1606 1607 /* 1608 * Just call memcpy() to do the work. 1609 */ 1610 memcpy(to, buf, len); 1611 } 1612 #endif 1613