1 /* $NetBSD: hme.c,v 1.43 2004/10/30 18:08:37 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * HME Ethernet module driver. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.43 2004/10/30 18:08:37 thorpej Exp $"); 45 46 /* #define HMEDEBUG */ 47 48 #include "opt_inet.h" 49 #include "opt_ns.h" 50 #include "bpfilter.h" 51 #include "rnd.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/mbuf.h> 57 #include <sys/syslog.h> 58 #include <sys/socket.h> 59 #include <sys/device.h> 60 #include <sys/malloc.h> 61 #include <sys/ioctl.h> 62 #include <sys/errno.h> 63 #if NRND > 0 64 #include <sys/rnd.h> 65 #endif 66 67 #include <net/if.h> 68 #include <net/if_dl.h> 69 #include <net/if_ether.h> 70 #include <net/if_media.h> 71 72 #ifdef INET 73 #include <netinet/in.h> 74 #include <netinet/if_inarp.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/in_var.h> 77 #include <netinet/ip.h> 78 #endif 79 80 #ifdef NS 81 #include <netns/ns.h> 82 #include <netns/ns_if.h> 83 #endif 84 85 #if NBPFILTER > 0 86 #include <net/bpf.h> 87 #include <net/bpfdesc.h> 88 #endif 89 90 #include <dev/mii/mii.h> 91 #include <dev/mii/miivar.h> 92 93 #include <machine/bus.h> 94 95 #include <dev/ic/hmereg.h> 96 #include <dev/ic/hmevar.h> 97 98 void hme_start __P((struct ifnet *)); 99 void hme_stop __P((struct hme_softc *)); 100 int hme_ioctl __P((struct ifnet *, u_long, caddr_t)); 101 void hme_tick __P((void *)); 102 void hme_watchdog __P((struct ifnet *)); 103 void hme_shutdown __P((void *)); 104 void hme_init __P((struct hme_softc *)); 105 void hme_meminit __P((struct hme_softc *)); 106 void hme_mifinit __P((struct hme_softc *)); 107 void hme_reset __P((struct hme_softc *)); 108 void hme_setladrf __P((struct hme_softc *)); 109 110 /* MII methods & callbacks */ 111 static int hme_mii_readreg __P((struct device *, int, int)); 112 static void hme_mii_writereg __P((struct device *, int, int, int)); 113 static void hme_mii_statchg __P((struct device *)); 114 115 int hme_mediachange __P((struct ifnet *)); 116 void hme_mediastatus __P((struct ifnet *, struct ifmediareq *)); 117 118 struct mbuf *hme_get __P((struct hme_softc *, int, int)); 119 int hme_put __P((struct hme_softc *, int, struct mbuf *)); 120 void hme_read __P((struct hme_softc *, int, int)); 121 int hme_eint __P((struct hme_softc *, u_int)); 122 int hme_rint __P((struct hme_softc *)); 123 int hme_tint __P((struct hme_softc *)); 124 125 static int ether_cmp __P((u_char *, u_char *)); 126 127 /* Default buffer copy routines */ 128 void hme_copytobuf_contig __P((struct hme_softc *, void *, int, int)); 129 void hme_copyfrombuf_contig __P((struct hme_softc *, void *, int, int)); 130 void hme_zerobuf_contig __P((struct hme_softc *, int, int)); 131 132 133 void 134 hme_config(sc) 135 struct hme_softc *sc; 136 { 137 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 138 struct mii_data *mii = &sc->sc_mii; 139 struct mii_softc *child; 140 bus_dma_tag_t dmatag = sc->sc_dmatag; 141 bus_dma_segment_t seg; 142 bus_size_t size; 143 int rseg, error; 144 145 /* 146 * HME common initialization. 147 * 148 * hme_softc fields that must be initialized by the front-end: 149 * 150 * the bus tag: 151 * sc_bustag 152 * 153 * the DMA bus tag: 154 * sc_dmatag 155 * 156 * the bus handles: 157 * sc_seb (Shared Ethernet Block registers) 158 * sc_erx (Receiver Unit registers) 159 * sc_etx (Transmitter Unit registers) 160 * sc_mac (MAC registers) 161 * sc_mif (Management Interface registers) 162 * 163 * the maximum bus burst size: 164 * sc_burst 165 * 166 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 167 * rb_membase, rb_dmabase) 168 * 169 * the local Ethernet address: 170 * sc_enaddr 171 * 172 */ 173 174 /* Make sure the chip is stopped. */ 175 hme_stop(sc); 176 177 178 /* 179 * Allocate descriptors and buffers 180 * XXX - do all this differently.. and more configurably, 181 * eg. use things as `dma_load_mbuf()' on transmit, 182 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 183 * all the time) on the receiver side. 184 * 185 * Note: receive buffers must be 64-byte aligned. 186 * Also, apparently, the buffers must extend to a DMA burst 187 * boundary beyond the maximum packet size. 188 */ 189 #define _HME_NDESC 128 190 #define _HME_BUFSZ 1600 191 192 /* Note: the # of descriptors must be a multiple of 16 */ 193 sc->sc_rb.rb_ntbuf = _HME_NDESC; 194 sc->sc_rb.rb_nrbuf = _HME_NDESC; 195 196 /* 197 * Allocate DMA capable memory 198 * Buffer descriptors must be aligned on a 2048 byte boundary; 199 * take this into account when calculating the size. Note that 200 * the maximum number of descriptors (256) occupies 2048 bytes, 201 * so we allocate that much regardless of _HME_NDESC. 202 */ 203 size = 2048 + /* TX descriptors */ 204 2048 + /* RX descriptors */ 205 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 206 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* TX buffers */ 207 208 /* Allocate DMA buffer */ 209 if ((error = bus_dmamem_alloc(dmatag, size, 210 2048, 0, 211 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 212 printf("%s: DMA buffer alloc error %d\n", 213 sc->sc_dev.dv_xname, error); 214 return; 215 } 216 217 /* Map DMA memory in CPU addressable space */ 218 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 219 &sc->sc_rb.rb_membase, 220 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 221 printf("%s: DMA buffer map error %d\n", 222 sc->sc_dev.dv_xname, error); 223 bus_dmamap_unload(dmatag, sc->sc_dmamap); 224 bus_dmamem_free(dmatag, &seg, rseg); 225 return; 226 } 227 228 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 229 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 230 printf("%s: DMA map create error %d\n", 231 sc->sc_dev.dv_xname, error); 232 return; 233 } 234 235 /* Load the buffer */ 236 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 237 sc->sc_rb.rb_membase, size, NULL, 238 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 239 printf("%s: DMA buffer map load error %d\n", 240 sc->sc_dev.dv_xname, error); 241 bus_dmamem_free(dmatag, &seg, rseg); 242 return; 243 } 244 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 245 246 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 247 ether_sprintf(sc->sc_enaddr)); 248 249 /* Initialize ifnet structure. */ 250 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 251 ifp->if_softc = sc; 252 ifp->if_start = hme_start; 253 ifp->if_ioctl = hme_ioctl; 254 ifp->if_watchdog = hme_watchdog; 255 ifp->if_flags = 256 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 257 sc->sc_if_flags = ifp->if_flags; 258 IFQ_SET_READY(&ifp->if_snd); 259 260 /* Initialize ifmedia structures and MII info */ 261 mii->mii_ifp = ifp; 262 mii->mii_readreg = hme_mii_readreg; 263 mii->mii_writereg = hme_mii_writereg; 264 mii->mii_statchg = hme_mii_statchg; 265 266 ifmedia_init(&mii->mii_media, 0, hme_mediachange, hme_mediastatus); 267 268 hme_mifinit(sc); 269 270 mii_attach(&sc->sc_dev, mii, 0xffffffff, 271 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 272 273 child = LIST_FIRST(&mii->mii_phys); 274 if (child == NULL) { 275 /* No PHY attached */ 276 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 277 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 278 } else { 279 /* 280 * Walk along the list of attached MII devices and 281 * establish an `MII instance' to `phy number' 282 * mapping. We'll use this mapping in media change 283 * requests to determine which phy to use to program 284 * the MIF configuration register. 285 */ 286 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 287 /* 288 * Note: we support just two PHYs: the built-in 289 * internal device and an external on the MII 290 * connector. 291 */ 292 if (child->mii_phy > 1 || child->mii_inst > 1) { 293 printf("%s: cannot accomodate MII device %s" 294 " at phy %d, instance %d\n", 295 sc->sc_dev.dv_xname, 296 child->mii_dev.dv_xname, 297 child->mii_phy, child->mii_inst); 298 continue; 299 } 300 301 sc->sc_phys[child->mii_inst] = child->mii_phy; 302 } 303 304 /* 305 * XXX - we can really do the following ONLY if the 306 * phy indeed has the auto negotiation capability!! 307 */ 308 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 309 } 310 311 /* claim 802.1q capability */ 312 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 313 314 /* Attach the interface. */ 315 if_attach(ifp); 316 ether_ifattach(ifp, sc->sc_enaddr); 317 318 sc->sc_sh = shutdownhook_establish(hme_shutdown, sc); 319 if (sc->sc_sh == NULL) 320 panic("hme_config: can't establish shutdownhook"); 321 322 #if NRND > 0 323 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 324 RND_TYPE_NET, 0); 325 #endif 326 327 callout_init(&sc->sc_tick_ch); 328 } 329 330 void 331 hme_tick(arg) 332 void *arg; 333 { 334 struct hme_softc *sc = arg; 335 int s; 336 337 s = splnet(); 338 mii_tick(&sc->sc_mii); 339 splx(s); 340 341 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 342 } 343 344 void 345 hme_reset(sc) 346 struct hme_softc *sc; 347 { 348 int s; 349 350 s = splnet(); 351 hme_init(sc); 352 splx(s); 353 } 354 355 void 356 hme_stop(sc) 357 struct hme_softc *sc; 358 { 359 bus_space_tag_t t = sc->sc_bustag; 360 bus_space_handle_t seb = sc->sc_seb; 361 int n; 362 363 callout_stop(&sc->sc_tick_ch); 364 mii_down(&sc->sc_mii); 365 366 /* Mask all interrupts */ 367 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff); 368 369 /* Reset transmitter and receiver */ 370 bus_space_write_4(t, seb, HME_SEBI_RESET, 371 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 372 373 for (n = 0; n < 20; n++) { 374 u_int32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 375 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 376 return; 377 DELAY(20); 378 } 379 380 printf("%s: hme_stop: reset failed\n", sc->sc_dev.dv_xname); 381 } 382 383 void 384 hme_meminit(sc) 385 struct hme_softc *sc; 386 { 387 bus_addr_t txbufdma, rxbufdma; 388 bus_addr_t dma; 389 caddr_t p; 390 unsigned int ntbuf, nrbuf, i; 391 struct hme_ring *hr = &sc->sc_rb; 392 393 p = hr->rb_membase; 394 dma = hr->rb_dmabase; 395 396 ntbuf = hr->rb_ntbuf; 397 nrbuf = hr->rb_nrbuf; 398 399 /* 400 * Allocate transmit descriptors 401 */ 402 hr->rb_txd = p; 403 hr->rb_txddma = dma; 404 p += ntbuf * HME_XD_SIZE; 405 dma += ntbuf * HME_XD_SIZE; 406 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 407 dma = (bus_addr_t)roundup((u_long)dma, 2048); 408 p = (caddr_t)roundup((u_long)p, 2048); 409 410 /* 411 * Allocate receive descriptors 412 */ 413 hr->rb_rxd = p; 414 hr->rb_rxddma = dma; 415 p += nrbuf * HME_XD_SIZE; 416 dma += nrbuf * HME_XD_SIZE; 417 /* Again move forward to the next 2048 byte boundary.*/ 418 dma = (bus_addr_t)roundup((u_long)dma, 2048); 419 p = (caddr_t)roundup((u_long)p, 2048); 420 421 422 /* 423 * Allocate transmit buffers 424 */ 425 hr->rb_txbuf = p; 426 txbufdma = dma; 427 p += ntbuf * _HME_BUFSZ; 428 dma += ntbuf * _HME_BUFSZ; 429 430 /* 431 * Allocate receive buffers 432 */ 433 hr->rb_rxbuf = p; 434 rxbufdma = dma; 435 p += nrbuf * _HME_BUFSZ; 436 dma += nrbuf * _HME_BUFSZ; 437 438 /* 439 * Initialize transmit buffer descriptors 440 */ 441 for (i = 0; i < ntbuf; i++) { 442 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 443 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 444 } 445 446 /* 447 * Initialize receive buffer descriptors 448 */ 449 for (i = 0; i < nrbuf; i++) { 450 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 451 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 452 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 453 } 454 455 hr->rb_tdhead = hr->rb_tdtail = 0; 456 hr->rb_td_nbusy = 0; 457 hr->rb_rdtail = 0; 458 } 459 460 /* 461 * Initialization of interface; set up initialization block 462 * and transmit/receive descriptor rings. 463 */ 464 void 465 hme_init(sc) 466 struct hme_softc *sc; 467 { 468 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 469 bus_space_tag_t t = sc->sc_bustag; 470 bus_space_handle_t seb = sc->sc_seb; 471 bus_space_handle_t etx = sc->sc_etx; 472 bus_space_handle_t erx = sc->sc_erx; 473 bus_space_handle_t mac = sc->sc_mac; 474 u_int8_t *ea; 475 u_int32_t v; 476 477 /* 478 * Initialization sequence. The numbered steps below correspond 479 * to the sequence outlined in section 6.3.5.1 in the Ethernet 480 * Channel Engine manual (part of the PCIO manual). 481 * See also the STP2002-STQ document from Sun Microsystems. 482 */ 483 484 /* step 1 & 2. Reset the Ethernet Channel */ 485 hme_stop(sc); 486 487 /* Re-initialize the MIF */ 488 hme_mifinit(sc); 489 490 /* Call MI reset function if any */ 491 if (sc->sc_hwreset) 492 (*sc->sc_hwreset)(sc); 493 494 #if 0 495 /* Mask all MIF interrupts, just in case */ 496 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 497 #endif 498 499 /* step 3. Setup data structures in host memory */ 500 hme_meminit(sc); 501 502 /* step 4. TX MAC registers & counters */ 503 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 504 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 505 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 506 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 507 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 508 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 509 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : 510 ETHER_MAX_LEN); 511 512 /* Load station MAC address */ 513 ea = sc->sc_enaddr; 514 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 515 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 516 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 517 518 /* 519 * Init seed for backoff 520 * (source suggested by manual: low 10 bits of MAC address) 521 */ 522 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 523 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 524 525 526 /* Note: Accepting power-on default for other MAC registers here.. */ 527 528 529 /* step 5. RX MAC registers & counters */ 530 hme_setladrf(sc); 531 532 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 533 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 534 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 535 536 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 537 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 538 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 539 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : 540 ETHER_MAX_LEN); 541 542 543 /* step 8. Global Configuration & Interrupt Mask */ 544 bus_space_write_4(t, seb, HME_SEBI_IMASK, 545 ~( 546 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 547 HME_SEB_STAT_HOSTTOTX | 548 HME_SEB_STAT_RXTOHOST | 549 HME_SEB_STAT_TXALL | 550 HME_SEB_STAT_TXPERR | 551 HME_SEB_STAT_RCNTEXP | 552 /*HME_SEB_STAT_MIFIRQ |*/ 553 HME_SEB_STAT_ALL_ERRORS )); 554 555 switch (sc->sc_burst) { 556 default: 557 v = 0; 558 break; 559 case 16: 560 v = HME_SEB_CFG_BURST16; 561 break; 562 case 32: 563 v = HME_SEB_CFG_BURST32; 564 break; 565 case 64: 566 v = HME_SEB_CFG_BURST64; 567 break; 568 } 569 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 570 571 /* step 9. ETX Configuration: use mostly default values */ 572 573 /* Enable DMA */ 574 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 575 v |= HME_ETX_CFG_DMAENABLE; 576 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 577 578 /* Transmit Descriptor ring size: in increments of 16 */ 579 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 580 581 582 /* step 10. ERX Configuration */ 583 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 584 585 /* Encode Receive Descriptor ring size: four possible values */ 586 switch (_HME_NDESC /*XXX*/) { 587 case 32: 588 v |= HME_ERX_CFG_RINGSIZE32; 589 break; 590 case 64: 591 v |= HME_ERX_CFG_RINGSIZE64; 592 break; 593 case 128: 594 v |= HME_ERX_CFG_RINGSIZE128; 595 break; 596 case 256: 597 v |= HME_ERX_CFG_RINGSIZE256; 598 break; 599 default: 600 printf("hme: invalid Receive Descriptor ring size\n"); 601 break; 602 } 603 604 /* Enable DMA */ 605 v |= HME_ERX_CFG_DMAENABLE; 606 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 607 608 /* step 11. XIF Configuration */ 609 v = bus_space_read_4(t, mac, HME_MACI_XIF); 610 v |= HME_MAC_XIF_OE; 611 bus_space_write_4(t, mac, HME_MACI_XIF, v); 612 613 /* step 12. RX_MAC Configuration Register */ 614 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 615 v |= HME_MAC_RXCFG_ENABLE; 616 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 617 618 /* step 13. TX_MAC Configuration Register */ 619 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 620 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 621 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 622 623 /* step 14. Issue Transmit Pending command */ 624 625 /* Call MI initialization function if any */ 626 if (sc->sc_hwinit) 627 (*sc->sc_hwinit)(sc); 628 629 /* Set the current media. */ 630 mii_mediachg(&sc->sc_mii); 631 632 /* Start the one second timer. */ 633 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 634 635 ifp->if_flags |= IFF_RUNNING; 636 ifp->if_flags &= ~IFF_OACTIVE; 637 sc->sc_if_flags = ifp->if_flags; 638 ifp->if_timer = 0; 639 hme_start(ifp); 640 } 641 642 /* 643 * Compare two Ether/802 addresses for equality, inlined and unrolled for 644 * speed. 645 */ 646 static __inline__ int 647 ether_cmp(a, b) 648 u_char *a, *b; 649 { 650 651 if (a[5] != b[5] || a[4] != b[4] || a[3] != b[3] || 652 a[2] != b[2] || a[1] != b[1] || a[0] != b[0]) 653 return (0); 654 return (1); 655 } 656 657 658 /* 659 * Routine to copy from mbuf chain to transmit buffer in 660 * network buffer memory. 661 * Returns the amount of data copied. 662 */ 663 int 664 hme_put(sc, ri, m) 665 struct hme_softc *sc; 666 int ri; /* Ring index */ 667 struct mbuf *m; 668 { 669 struct mbuf *n; 670 int len, tlen = 0; 671 caddr_t bp; 672 673 bp = sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 674 for (; m; m = n) { 675 len = m->m_len; 676 if (len == 0) { 677 MFREE(m, n); 678 continue; 679 } 680 memcpy(bp, mtod(m, caddr_t), len); 681 bp += len; 682 tlen += len; 683 MFREE(m, n); 684 } 685 return (tlen); 686 } 687 688 /* 689 * Pull data off an interface. 690 * Len is length of data, with local net header stripped. 691 * We copy the data into mbufs. When full cluster sized units are present 692 * we copy into clusters. 693 */ 694 struct mbuf * 695 hme_get(sc, ri, totlen) 696 struct hme_softc *sc; 697 int ri, totlen; 698 { 699 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 700 struct mbuf *m, *m0, *newm; 701 caddr_t bp; 702 int len; 703 704 MGETHDR(m0, M_DONTWAIT, MT_DATA); 705 if (m0 == 0) 706 return (0); 707 m0->m_pkthdr.rcvif = ifp; 708 m0->m_pkthdr.len = totlen; 709 len = MHLEN; 710 m = m0; 711 712 bp = sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 713 714 while (totlen > 0) { 715 if (totlen >= MINCLSIZE) { 716 MCLGET(m, M_DONTWAIT); 717 if ((m->m_flags & M_EXT) == 0) 718 goto bad; 719 len = MCLBYTES; 720 } 721 722 if (m == m0) { 723 caddr_t newdata = (caddr_t) 724 ALIGN(m->m_data + sizeof(struct ether_header)) - 725 sizeof(struct ether_header); 726 len -= newdata - m->m_data; 727 m->m_data = newdata; 728 } 729 730 m->m_len = len = min(totlen, len); 731 memcpy(mtod(m, caddr_t), bp, len); 732 bp += len; 733 734 totlen -= len; 735 if (totlen > 0) { 736 MGET(newm, M_DONTWAIT, MT_DATA); 737 if (newm == 0) 738 goto bad; 739 len = MLEN; 740 m = m->m_next = newm; 741 } 742 } 743 744 return (m0); 745 746 bad: 747 m_freem(m0); 748 return (0); 749 } 750 751 /* 752 * Pass a packet to the higher levels. 753 */ 754 void 755 hme_read(sc, ix, len) 756 struct hme_softc *sc; 757 int ix, len; 758 { 759 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 760 struct mbuf *m; 761 762 if (len <= sizeof(struct ether_header) || 763 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 764 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 765 ETHERMTU + sizeof(struct ether_header))) { 766 #ifdef HMEDEBUG 767 printf("%s: invalid packet size %d; dropping\n", 768 sc->sc_dev.dv_xname, len); 769 #endif 770 ifp->if_ierrors++; 771 return; 772 } 773 774 /* Pull packet off interface. */ 775 m = hme_get(sc, ix, len); 776 if (m == 0) { 777 ifp->if_ierrors++; 778 return; 779 } 780 781 ifp->if_ipackets++; 782 783 #if NBPFILTER > 0 784 /* 785 * Check if there's a BPF listener on this interface. 786 * If so, hand off the raw packet to BPF. 787 */ 788 if (ifp->if_bpf) 789 bpf_mtap(ifp->if_bpf, m); 790 #endif 791 792 /* Pass the packet up. */ 793 (*ifp->if_input)(ifp, m); 794 } 795 796 void 797 hme_start(ifp) 798 struct ifnet *ifp; 799 { 800 struct hme_softc *sc = (struct hme_softc *)ifp->if_softc; 801 caddr_t txd = sc->sc_rb.rb_txd; 802 struct mbuf *m; 803 unsigned int ri, len; 804 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 805 806 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 807 return; 808 809 ri = sc->sc_rb.rb_tdhead; 810 811 for (;;) { 812 IFQ_DEQUEUE(&ifp->if_snd, m); 813 if (m == 0) 814 break; 815 816 #if NBPFILTER > 0 817 /* 818 * If BPF is listening on this interface, let it see the 819 * packet before we commit it to the wire. 820 */ 821 if (ifp->if_bpf) 822 bpf_mtap(ifp->if_bpf, m); 823 #endif 824 825 /* 826 * Copy the mbuf chain into the transmit buffer. 827 */ 828 len = hme_put(sc, ri, m); 829 830 /* 831 * Initialize transmit registers and start transmission 832 */ 833 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 834 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 835 HME_XD_ENCODE_TSIZE(len)); 836 837 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 838 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 839 HME_ETX_TP_DMAWAKEUP); 840 841 if (++ri == ntbuf) 842 ri = 0; 843 844 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 845 ifp->if_flags |= IFF_OACTIVE; 846 break; 847 } 848 } 849 850 sc->sc_rb.rb_tdhead = ri; 851 } 852 853 /* 854 * Transmit interrupt. 855 */ 856 int 857 hme_tint(sc) 858 struct hme_softc *sc; 859 { 860 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 861 bus_space_tag_t t = sc->sc_bustag; 862 bus_space_handle_t mac = sc->sc_mac; 863 unsigned int ri, txflags; 864 865 /* 866 * Unload collision counters 867 */ 868 ifp->if_collisions += 869 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 870 bus_space_read_4(t, mac, HME_MACI_FCCNT) + 871 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 872 bus_space_read_4(t, mac, HME_MACI_LTCNT); 873 874 /* 875 * then clear the hardware counters. 876 */ 877 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 878 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 879 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 880 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 881 882 /* Fetch current position in the transmit ring */ 883 ri = sc->sc_rb.rb_tdtail; 884 885 for (;;) { 886 if (sc->sc_rb.rb_td_nbusy <= 0) 887 break; 888 889 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 890 891 if (txflags & HME_XD_OWN) 892 break; 893 894 ifp->if_flags &= ~IFF_OACTIVE; 895 ifp->if_opackets++; 896 897 if (++ri == sc->sc_rb.rb_ntbuf) 898 ri = 0; 899 900 --sc->sc_rb.rb_td_nbusy; 901 } 902 903 /* Update ring */ 904 sc->sc_rb.rb_tdtail = ri; 905 906 hme_start(ifp); 907 908 if (sc->sc_rb.rb_td_nbusy == 0) 909 ifp->if_timer = 0; 910 911 return (1); 912 } 913 914 /* 915 * Receive interrupt. 916 */ 917 int 918 hme_rint(sc) 919 struct hme_softc *sc; 920 { 921 caddr_t xdr = sc->sc_rb.rb_rxd; 922 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 923 unsigned int ri, len; 924 u_int32_t flags; 925 926 ri = sc->sc_rb.rb_rdtail; 927 928 /* 929 * Process all buffers with valid data. 930 */ 931 for (;;) { 932 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 933 if (flags & HME_XD_OWN) 934 break; 935 936 if (flags & HME_XD_OFL) { 937 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 938 sc->sc_dev.dv_xname, ri, flags); 939 } else { 940 len = HME_XD_DECODE_RSIZE(flags); 941 hme_read(sc, ri, len); 942 } 943 944 /* This buffer can be used by the hardware again */ 945 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 946 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 947 948 if (++ri == nrbuf) 949 ri = 0; 950 } 951 952 sc->sc_rb.rb_rdtail = ri; 953 954 return (1); 955 } 956 957 int 958 hme_eint(sc, status) 959 struct hme_softc *sc; 960 u_int status; 961 { 962 char bits[128]; 963 964 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 965 bus_space_tag_t t = sc->sc_bustag; 966 bus_space_handle_t mif = sc->sc_mif; 967 u_int32_t cf, st, sm; 968 cf = bus_space_read_4(t, mif, HME_MIFI_CFG); 969 st = bus_space_read_4(t, mif, HME_MIFI_STAT); 970 sm = bus_space_read_4(t, mif, HME_MIFI_SM); 971 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n", 972 sc->sc_dev.dv_xname, cf, st, sm); 973 return (1); 974 } 975 976 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 977 bitmask_snprintf(status, HME_SEB_STAT_BITS, bits,sizeof(bits))); 978 return (1); 979 } 980 981 int 982 hme_intr(v) 983 void *v; 984 { 985 struct hme_softc *sc = (struct hme_softc *)v; 986 bus_space_tag_t t = sc->sc_bustag; 987 bus_space_handle_t seb = sc->sc_seb; 988 u_int32_t status; 989 int r = 0; 990 991 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 992 993 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 994 r |= hme_eint(sc, status); 995 996 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 997 r |= hme_tint(sc); 998 999 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1000 r |= hme_rint(sc); 1001 1002 #if NRND > 0 1003 rnd_add_uint32(&sc->rnd_source, status); 1004 #endif 1005 1006 return (r); 1007 } 1008 1009 1010 void 1011 hme_watchdog(ifp) 1012 struct ifnet *ifp; 1013 { 1014 struct hme_softc *sc = ifp->if_softc; 1015 1016 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1017 ++ifp->if_oerrors; 1018 1019 hme_reset(sc); 1020 } 1021 1022 /* 1023 * Initialize the MII Management Interface 1024 */ 1025 void 1026 hme_mifinit(sc) 1027 struct hme_softc *sc; 1028 { 1029 bus_space_tag_t t = sc->sc_bustag; 1030 bus_space_handle_t mif = sc->sc_mif; 1031 bus_space_handle_t mac = sc->sc_mac; 1032 int instance, phy; 1033 u_int32_t v; 1034 1035 if (sc->sc_media.ifm_cur != NULL) { 1036 instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1037 phy = sc->sc_phys[instance]; 1038 } else 1039 /* No media set yet, pick phy arbitrarily.. */ 1040 phy = HME_PHYAD_EXTERNAL; 1041 1042 /* Configure the MIF in frame mode, no poll, current phy select */ 1043 v = 0; 1044 if (phy == HME_PHYAD_EXTERNAL) 1045 v |= HME_MIF_CFG_PHY; 1046 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1047 1048 /* If an external transceiver is selected, enable its MII drivers */ 1049 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1050 v &= ~HME_MAC_XIF_MIIENABLE; 1051 if (phy == HME_PHYAD_EXTERNAL) 1052 v |= HME_MAC_XIF_MIIENABLE; 1053 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1054 } 1055 1056 /* 1057 * MII interface 1058 */ 1059 static int 1060 hme_mii_readreg(self, phy, reg) 1061 struct device *self; 1062 int phy, reg; 1063 { 1064 struct hme_softc *sc = (void *)self; 1065 bus_space_tag_t t = sc->sc_bustag; 1066 bus_space_handle_t mif = sc->sc_mif; 1067 bus_space_handle_t mac = sc->sc_mac; 1068 u_int32_t v, xif_cfg, mifi_cfg; 1069 int n; 1070 1071 /* We can at most have two PHYs */ 1072 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1073 return (0); 1074 1075 /* Select the desired PHY in the MIF configuration register */ 1076 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1077 v &= ~HME_MIF_CFG_PHY; 1078 if (phy == HME_PHYAD_EXTERNAL) 1079 v |= HME_MIF_CFG_PHY; 1080 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1081 1082 /* Enable MII drivers on external transceiver */ 1083 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1084 if (phy == HME_PHYAD_EXTERNAL) 1085 v |= HME_MAC_XIF_MIIENABLE; 1086 else 1087 v &= ~HME_MAC_XIF_MIIENABLE; 1088 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1089 1090 #if 0 1091 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1092 /* 1093 * Check whether a transceiver is connected by testing 1094 * the MIF configuration register's MDI_X bits. Note that 1095 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1096 */ 1097 mif_mdi_bit = 1 << (8 + (1 - phy)); 1098 delay(100); 1099 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1100 if ((v & mif_mdi_bit) == 0) 1101 return (0); 1102 #endif 1103 1104 /* Construct the frame command */ 1105 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1106 HME_MIF_FO_TAMSB | 1107 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1108 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1109 (reg << HME_MIF_FO_REGAD_SHIFT); 1110 1111 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1112 for (n = 0; n < 100; n++) { 1113 DELAY(1); 1114 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1115 if (v & HME_MIF_FO_TALSB) { 1116 v &= HME_MIF_FO_DATA; 1117 goto out; 1118 } 1119 } 1120 1121 v = 0; 1122 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1123 1124 out: 1125 /* Restore MIFI_CFG register */ 1126 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1127 /* Restore XIF register */ 1128 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1129 return (v); 1130 } 1131 1132 static void 1133 hme_mii_writereg(self, phy, reg, val) 1134 struct device *self; 1135 int phy, reg, val; 1136 { 1137 struct hme_softc *sc = (void *)self; 1138 bus_space_tag_t t = sc->sc_bustag; 1139 bus_space_handle_t mif = sc->sc_mif; 1140 bus_space_handle_t mac = sc->sc_mac; 1141 u_int32_t v, xif_cfg, mifi_cfg; 1142 int n; 1143 1144 /* We can at most have two PHYs */ 1145 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1146 return; 1147 1148 /* Select the desired PHY in the MIF configuration register */ 1149 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1150 v &= ~HME_MIF_CFG_PHY; 1151 if (phy == HME_PHYAD_EXTERNAL) 1152 v |= HME_MIF_CFG_PHY; 1153 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1154 1155 /* Enable MII drivers on external transceiver */ 1156 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1157 if (phy == HME_PHYAD_EXTERNAL) 1158 v |= HME_MAC_XIF_MIIENABLE; 1159 else 1160 v &= ~HME_MAC_XIF_MIIENABLE; 1161 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1162 1163 #if 0 1164 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1165 /* 1166 * Check whether a transceiver is connected by testing 1167 * the MIF configuration register's MDI_X bits. Note that 1168 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1169 */ 1170 mif_mdi_bit = 1 << (8 + (1 - phy)); 1171 delay(100); 1172 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1173 if ((v & mif_mdi_bit) == 0) 1174 return; 1175 #endif 1176 1177 /* Construct the frame command */ 1178 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1179 HME_MIF_FO_TAMSB | 1180 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1181 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1182 (reg << HME_MIF_FO_REGAD_SHIFT) | 1183 (val & HME_MIF_FO_DATA); 1184 1185 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1186 for (n = 0; n < 100; n++) { 1187 DELAY(1); 1188 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1189 if (v & HME_MIF_FO_TALSB) 1190 goto out; 1191 } 1192 1193 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1194 out: 1195 /* Restore MIFI_CFG register */ 1196 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1197 /* Restore XIF register */ 1198 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1199 } 1200 1201 static void 1202 hme_mii_statchg(dev) 1203 struct device *dev; 1204 { 1205 struct hme_softc *sc = (void *)dev; 1206 bus_space_tag_t t = sc->sc_bustag; 1207 bus_space_handle_t mac = sc->sc_mac; 1208 u_int32_t v; 1209 1210 #ifdef HMEDEBUG 1211 if (sc->sc_debug) 1212 printf("hme_mii_statchg: status change\n"); 1213 #endif 1214 1215 /* Set the MAC Full Duplex bit appropriately */ 1216 /* Apparently the hme chip is SIMPLEX if working in full duplex mode, 1217 but not otherwise. */ 1218 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1219 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1220 v |= HME_MAC_TXCFG_FULLDPLX; 1221 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX; 1222 } else { 1223 v &= ~HME_MAC_TXCFG_FULLDPLX; 1224 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX; 1225 } 1226 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags; 1227 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1228 } 1229 1230 int 1231 hme_mediachange(ifp) 1232 struct ifnet *ifp; 1233 { 1234 struct hme_softc *sc = ifp->if_softc; 1235 bus_space_tag_t t = sc->sc_bustag; 1236 bus_space_handle_t mif = sc->sc_mif; 1237 bus_space_handle_t mac = sc->sc_mac; 1238 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1239 int phy = sc->sc_phys[instance]; 1240 u_int32_t v; 1241 1242 #ifdef HMEDEBUG 1243 if (sc->sc_debug) 1244 printf("hme_mediachange: phy = %d\n", phy); 1245 #endif 1246 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1247 return (EINVAL); 1248 1249 /* Select the current PHY in the MIF configuration register */ 1250 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1251 v &= ~HME_MIF_CFG_PHY; 1252 if (phy == HME_PHYAD_EXTERNAL) 1253 v |= HME_MIF_CFG_PHY; 1254 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1255 1256 /* If an external transceiver is selected, enable its MII drivers */ 1257 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1258 v &= ~HME_MAC_XIF_MIIENABLE; 1259 if (phy == HME_PHYAD_EXTERNAL) 1260 v |= HME_MAC_XIF_MIIENABLE; 1261 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1262 1263 return (mii_mediachg(&sc->sc_mii)); 1264 } 1265 1266 void 1267 hme_mediastatus(ifp, ifmr) 1268 struct ifnet *ifp; 1269 struct ifmediareq *ifmr; 1270 { 1271 struct hme_softc *sc = ifp->if_softc; 1272 1273 if ((ifp->if_flags & IFF_UP) == 0) 1274 return; 1275 1276 mii_pollstat(&sc->sc_mii); 1277 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1278 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1279 } 1280 1281 /* 1282 * Process an ioctl request. 1283 */ 1284 int 1285 hme_ioctl(ifp, cmd, data) 1286 struct ifnet *ifp; 1287 u_long cmd; 1288 caddr_t data; 1289 { 1290 struct hme_softc *sc = ifp->if_softc; 1291 struct ifaddr *ifa = (struct ifaddr *)data; 1292 struct ifreq *ifr = (struct ifreq *)data; 1293 int s, error = 0; 1294 1295 s = splnet(); 1296 1297 switch (cmd) { 1298 1299 case SIOCSIFADDR: 1300 switch (ifa->ifa_addr->sa_family) { 1301 #ifdef INET 1302 case AF_INET: 1303 if (ifp->if_flags & IFF_UP) 1304 hme_setladrf(sc); 1305 else { 1306 ifp->if_flags |= IFF_UP; 1307 hme_init(sc); 1308 } 1309 arp_ifinit(ifp, ifa); 1310 break; 1311 #endif 1312 #ifdef NS 1313 case AF_NS: 1314 { 1315 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1316 1317 if (ns_nullhost(*ina)) 1318 ina->x_host = 1319 *(union ns_host *)LLADDR(ifp->if_sadl); 1320 else { 1321 memcpy(LLADDR(ifp->if_sadl), 1322 ina->x_host.c_host, sizeof(sc->sc_enaddr)); 1323 } 1324 /* Set new address. */ 1325 if (ifp->if_flags & IFF_UP) 1326 hme_setladrf(sc); 1327 else { 1328 ifp->if_flags |= IFF_UP; 1329 hme_init(sc); 1330 } 1331 break; 1332 } 1333 #endif 1334 default: 1335 ifp->if_flags |= IFF_UP; 1336 hme_init(sc); 1337 break; 1338 } 1339 break; 1340 1341 case SIOCSIFFLAGS: 1342 if ((ifp->if_flags & IFF_UP) == 0 && 1343 (ifp->if_flags & IFF_RUNNING) != 0) { 1344 /* 1345 * If interface is marked down and it is running, then 1346 * stop it. 1347 */ 1348 hme_stop(sc); 1349 ifp->if_flags &= ~IFF_RUNNING; 1350 } else if ((ifp->if_flags & IFF_UP) != 0 && 1351 (ifp->if_flags & IFF_RUNNING) == 0) { 1352 /* 1353 * If interface is marked up and it is stopped, then 1354 * start it. 1355 */ 1356 hme_init(sc); 1357 } else if ((ifp->if_flags & IFF_UP) != 0) { 1358 /* 1359 * If setting debug or promiscuous mode, do not reset 1360 * the chip; for everything else, call hme_init() 1361 * which will trigger a reset. 1362 */ 1363 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG) 1364 if (ifp->if_flags == sc->sc_if_flags) 1365 break; 1366 if ((ifp->if_flags & (~RESETIGN)) 1367 == (sc->sc_if_flags & (~RESETIGN))) 1368 hme_setladrf(sc); 1369 else 1370 hme_init(sc); 1371 #undef RESETIGN 1372 } 1373 #ifdef HMEDEBUG 1374 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1375 #endif 1376 break; 1377 1378 case SIOCADDMULTI: 1379 case SIOCDELMULTI: 1380 error = (cmd == SIOCADDMULTI) ? 1381 ether_addmulti(ifr, &sc->sc_ethercom) : 1382 ether_delmulti(ifr, &sc->sc_ethercom); 1383 1384 if (error == ENETRESET) { 1385 /* 1386 * Multicast list has changed; set the hardware filter 1387 * accordingly. 1388 */ 1389 if (ifp->if_flags & IFF_RUNNING) 1390 hme_setladrf(sc); 1391 error = 0; 1392 } 1393 break; 1394 1395 case SIOCGIFMEDIA: 1396 case SIOCSIFMEDIA: 1397 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1398 break; 1399 1400 default: 1401 error = EINVAL; 1402 break; 1403 } 1404 1405 sc->sc_if_flags = ifp->if_flags; 1406 splx(s); 1407 return (error); 1408 } 1409 1410 void 1411 hme_shutdown(arg) 1412 void *arg; 1413 { 1414 1415 hme_stop((struct hme_softc *)arg); 1416 } 1417 1418 /* 1419 * Set up the logical address filter. 1420 */ 1421 void 1422 hme_setladrf(sc) 1423 struct hme_softc *sc; 1424 { 1425 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1426 struct ether_multi *enm; 1427 struct ether_multistep step; 1428 struct ethercom *ec = &sc->sc_ethercom; 1429 bus_space_tag_t t = sc->sc_bustag; 1430 bus_space_handle_t mac = sc->sc_mac; 1431 u_char *cp; 1432 u_int32_t crc; 1433 u_int32_t hash[4]; 1434 u_int32_t v; 1435 int len; 1436 1437 /* Clear hash table */ 1438 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1439 1440 /* Get current RX configuration */ 1441 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1442 1443 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1444 /* Turn on promiscuous mode; turn off the hash filter */ 1445 v |= HME_MAC_RXCFG_PMISC; 1446 v &= ~HME_MAC_RXCFG_HENABLE; 1447 ifp->if_flags |= IFF_ALLMULTI; 1448 goto chipit; 1449 } 1450 1451 /* Turn off promiscuous mode; turn on the hash filter */ 1452 v &= ~HME_MAC_RXCFG_PMISC; 1453 v |= HME_MAC_RXCFG_HENABLE; 1454 1455 /* 1456 * Set up multicast address filter by passing all multicast addresses 1457 * through a crc generator, and then using the high order 6 bits as an 1458 * index into the 64 bit logical address filter. The high order bit 1459 * selects the word, while the rest of the bits select the bit within 1460 * the word. 1461 */ 1462 1463 ETHER_FIRST_MULTI(step, ec, enm); 1464 while (enm != NULL) { 1465 if (ether_cmp(enm->enm_addrlo, enm->enm_addrhi)) { 1466 /* 1467 * We must listen to a range of multicast addresses. 1468 * For now, just accept all multicasts, rather than 1469 * trying to set only those filter bits needed to match 1470 * the range. (At this time, the only use of address 1471 * ranges is for IP multicast routing, for which the 1472 * range is big enough to require all bits set.) 1473 */ 1474 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1475 ifp->if_flags |= IFF_ALLMULTI; 1476 goto chipit; 1477 } 1478 1479 cp = enm->enm_addrlo; 1480 crc = 0xffffffff; 1481 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1482 int octet = *cp++; 1483 int i; 1484 1485 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1486 for (i = 0; i < 8; i++) { 1487 if ((crc & 1) ^ (octet & 1)) { 1488 crc >>= 1; 1489 crc ^= MC_POLY_LE; 1490 } else { 1491 crc >>= 1; 1492 } 1493 octet >>= 1; 1494 } 1495 } 1496 /* Just want the 6 most significant bits. */ 1497 crc >>= 26; 1498 1499 /* Set the corresponding bit in the filter. */ 1500 hash[crc >> 4] |= 1 << (crc & 0xf); 1501 1502 ETHER_NEXT_MULTI(step, enm); 1503 } 1504 1505 ifp->if_flags &= ~IFF_ALLMULTI; 1506 1507 chipit: 1508 /* Now load the hash table into the chip */ 1509 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1510 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1511 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1512 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1513 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1514 } 1515 1516 /* 1517 * Routines for accessing the transmit and receive buffers. 1518 * The various CPU and adapter configurations supported by this 1519 * driver require three different access methods for buffers 1520 * and descriptors: 1521 * (1) contig (contiguous data; no padding), 1522 * (2) gap2 (two bytes of data followed by two bytes of padding), 1523 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1524 */ 1525 1526 #if 0 1527 /* 1528 * contig: contiguous data with no padding. 1529 * 1530 * Buffers may have any alignment. 1531 */ 1532 1533 void 1534 hme_copytobuf_contig(sc, from, ri, len) 1535 struct hme_softc *sc; 1536 void *from; 1537 int ri, len; 1538 { 1539 volatile caddr_t buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1540 1541 /* 1542 * Just call memcpy() to do the work. 1543 */ 1544 memcpy(buf, from, len); 1545 } 1546 1547 void 1548 hme_copyfrombuf_contig(sc, to, boff, len) 1549 struct hme_softc *sc; 1550 void *to; 1551 int boff, len; 1552 { 1553 volatile caddr_t buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1554 1555 /* 1556 * Just call memcpy() to do the work. 1557 */ 1558 memcpy(to, buf, len); 1559 } 1560 #endif 1561