1 /* $NetBSD: hme.c,v 1.28 2001/11/26 10:39:29 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * HME Ethernet module driver. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.28 2001/11/26 10:39:29 tron Exp $"); 45 46 #define HMEDEBUG 47 48 #include "opt_inet.h" 49 #include "opt_ns.h" 50 #include "bpfilter.h" 51 #include "rnd.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/mbuf.h> 57 #include <sys/syslog.h> 58 #include <sys/socket.h> 59 #include <sys/device.h> 60 #include <sys/malloc.h> 61 #include <sys/ioctl.h> 62 #include <sys/errno.h> 63 #if NRND > 0 64 #include <sys/rnd.h> 65 #endif 66 67 #include <net/if.h> 68 #include <net/if_dl.h> 69 #include <net/if_ether.h> 70 #include <net/if_media.h> 71 72 #ifdef INET 73 #include <netinet/in.h> 74 #include <netinet/if_inarp.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/in_var.h> 77 #include <netinet/ip.h> 78 #endif 79 80 #ifdef NS 81 #include <netns/ns.h> 82 #include <netns/ns_if.h> 83 #endif 84 85 #if NBPFILTER > 0 86 #include <net/bpf.h> 87 #include <net/bpfdesc.h> 88 #endif 89 90 #include <dev/mii/mii.h> 91 #include <dev/mii/miivar.h> 92 93 #include <machine/bus.h> 94 95 #include <dev/ic/hmereg.h> 96 #include <dev/ic/hmevar.h> 97 98 void hme_start __P((struct ifnet *)); 99 void hme_stop __P((struct hme_softc *)); 100 int hme_ioctl __P((struct ifnet *, u_long, caddr_t)); 101 void hme_tick __P((void *)); 102 void hme_watchdog __P((struct ifnet *)); 103 void hme_shutdown __P((void *)); 104 void hme_init __P((struct hme_softc *)); 105 void hme_meminit __P((struct hme_softc *)); 106 void hme_mifinit __P((struct hme_softc *)); 107 void hme_reset __P((struct hme_softc *)); 108 void hme_setladrf __P((struct hme_softc *)); 109 110 /* MII methods & callbacks */ 111 static int hme_mii_readreg __P((struct device *, int, int)); 112 static void hme_mii_writereg __P((struct device *, int, int, int)); 113 static void hme_mii_statchg __P((struct device *)); 114 115 int hme_mediachange __P((struct ifnet *)); 116 void hme_mediastatus __P((struct ifnet *, struct ifmediareq *)); 117 118 struct mbuf *hme_get __P((struct hme_softc *, int, int)); 119 int hme_put __P((struct hme_softc *, int, struct mbuf *)); 120 void hme_read __P((struct hme_softc *, int, int)); 121 int hme_eint __P((struct hme_softc *, u_int)); 122 int hme_rint __P((struct hme_softc *)); 123 int hme_tint __P((struct hme_softc *)); 124 125 static int ether_cmp __P((u_char *, u_char *)); 126 127 /* Default buffer copy routines */ 128 void hme_copytobuf_contig __P((struct hme_softc *, void *, int, int)); 129 void hme_copyfrombuf_contig __P((struct hme_softc *, void *, int, int)); 130 void hme_zerobuf_contig __P((struct hme_softc *, int, int)); 131 132 133 void 134 hme_config(sc) 135 struct hme_softc *sc; 136 { 137 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 138 struct mii_data *mii = &sc->sc_mii; 139 struct mii_softc *child; 140 bus_dma_tag_t dmatag = sc->sc_dmatag; 141 bus_dma_segment_t seg; 142 bus_size_t size; 143 int rseg, error; 144 145 /* 146 * HME common initialization. 147 * 148 * hme_softc fields that must be initialized by the front-end: 149 * 150 * the bus tag: 151 * sc_bustag 152 * 153 * the dma bus tag: 154 * sc_dmatag 155 * 156 * the bus handles: 157 * sc_seb (Shared Ethernet Block registers) 158 * sc_erx (Receiver Unit registers) 159 * sc_etx (Transmitter Unit registers) 160 * sc_mac (MAC registers) 161 * sc_mif (Managment Interface registers) 162 * 163 * the maximum bus burst size: 164 * sc_burst 165 * 166 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 167 * rb_membase, rb_dmabase) 168 * 169 * the local Ethernet address: 170 * sc_enaddr 171 * 172 */ 173 174 /* Make sure the chip is stopped. */ 175 hme_stop(sc); 176 177 178 /* 179 * Allocate descriptors and buffers 180 * XXX - do all this differently.. and more configurably, 181 * eg. use things as `dma_load_mbuf()' on transmit, 182 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 183 * all the time) on the reveiver side. 184 * 185 * Note: receive buffers must be 64-byte aligned. 186 * Also, apparently, the buffers must extend to a DMA burst 187 * boundary beyond the maximum packet size. 188 */ 189 #define _HME_NDESC 128 190 #define _HME_BUFSZ 1600 191 192 /* Note: the # of descriptors must be a multiple of 16 */ 193 sc->sc_rb.rb_ntbuf = _HME_NDESC; 194 sc->sc_rb.rb_nrbuf = _HME_NDESC; 195 196 /* 197 * Allocate DMA capable memory 198 * Buffer descriptors must be aligned on a 2048 byte boundary; 199 * take this into account when calculating the size. Note that 200 * the maximum number of descriptors (256) occupies 2048 bytes, 201 * so we allocate that much regardless of _HME_NDESC. 202 */ 203 size = 2048 + /* TX descriptors */ 204 2048 + /* RX descriptors */ 205 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 206 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* TX buffers */ 207 208 /* Allocate DMA buffer */ 209 if ((error = bus_dmamem_alloc(dmatag, size, 210 2048, 0, 211 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 212 printf("%s: DMA buffer alloc error %d\n", 213 sc->sc_dev.dv_xname, error); 214 return; 215 } 216 217 /* Map DMA memory in CPU addressable space */ 218 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 219 &sc->sc_rb.rb_membase, 220 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 221 printf("%s: DMA buffer map error %d\n", 222 sc->sc_dev.dv_xname, error); 223 bus_dmamap_unload(dmatag, sc->sc_dmamap); 224 bus_dmamem_free(dmatag, &seg, rseg); 225 return; 226 } 227 228 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 229 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 230 printf("%s: DMA map create error %d\n", 231 sc->sc_dev.dv_xname, error); 232 return; 233 } 234 235 /* Load the buffer */ 236 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 237 sc->sc_rb.rb_membase, size, NULL, 238 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 239 printf("%s: DMA buffer map load error %d\n", 240 sc->sc_dev.dv_xname, error); 241 bus_dmamem_free(dmatag, &seg, rseg); 242 return; 243 } 244 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 245 246 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 247 ether_sprintf(sc->sc_enaddr)); 248 249 /* Initialize ifnet structure. */ 250 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 251 ifp->if_softc = sc; 252 ifp->if_start = hme_start; 253 ifp->if_ioctl = hme_ioctl; 254 ifp->if_watchdog = hme_watchdog; 255 ifp->if_flags = 256 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 257 IFQ_SET_READY(&ifp->if_snd); 258 259 /* Initialize ifmedia structures and MII info */ 260 mii->mii_ifp = ifp; 261 mii->mii_readreg = hme_mii_readreg; 262 mii->mii_writereg = hme_mii_writereg; 263 mii->mii_statchg = hme_mii_statchg; 264 265 ifmedia_init(&mii->mii_media, 0, hme_mediachange, hme_mediastatus); 266 267 hme_mifinit(sc); 268 269 mii_attach(&sc->sc_dev, mii, 0xffffffff, 270 MII_PHY_ANY, MII_OFFSET_ANY, 0); 271 272 child = LIST_FIRST(&mii->mii_phys); 273 if (child == NULL) { 274 /* No PHY attached */ 275 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 276 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 277 } else { 278 /* 279 * Walk along the list of attached MII devices and 280 * establish an `MII instance' to `phy number' 281 * mapping. We'll use this mapping in media change 282 * requests to determine which phy to use to program 283 * the MIF configuration register. 284 */ 285 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 286 /* 287 * Note: we support just two PHYs: the built-in 288 * internal device and an external on the MII 289 * connector. 290 */ 291 if (child->mii_phy > 1 || child->mii_inst > 1) { 292 printf("%s: cannot accomodate MII device %s" 293 " at phy %d, instance %d\n", 294 sc->sc_dev.dv_xname, 295 child->mii_dev.dv_xname, 296 child->mii_phy, child->mii_inst); 297 continue; 298 } 299 300 sc->sc_phys[child->mii_inst] = child->mii_phy; 301 } 302 303 /* 304 * XXX - we can really do the following ONLY if the 305 * phy indeed has the auto negotiation capability!! 306 */ 307 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 308 } 309 310 /* claim 802.1q capability */ 311 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 312 313 /* Attach the interface. */ 314 if_attach(ifp); 315 ether_ifattach(ifp, sc->sc_enaddr); 316 317 sc->sc_sh = shutdownhook_establish(hme_shutdown, sc); 318 if (sc->sc_sh == NULL) 319 panic("hme_config: can't establish shutdownhook"); 320 321 #if 0 322 printf("%s: %d receive buffers, %d transmit buffers\n", 323 sc->sc_dev.dv_xname, sc->sc_nrbuf, sc->sc_ntbuf); 324 sc->sc_rbufaddr = malloc(sc->sc_nrbuf * sizeof(int), M_DEVBUF, 325 M_WAITOK); 326 sc->sc_tbufaddr = malloc(sc->sc_ntbuf * sizeof(int), M_DEVBUF, 327 M_WAITOK); 328 #endif 329 330 #if NRND > 0 331 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 332 RND_TYPE_NET, 0); 333 #endif 334 335 callout_init(&sc->sc_tick_ch); 336 } 337 338 void 339 hme_tick(arg) 340 void *arg; 341 { 342 struct hme_softc *sc = arg; 343 int s; 344 345 s = splnet(); 346 mii_tick(&sc->sc_mii); 347 splx(s); 348 349 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 350 } 351 352 void 353 hme_reset(sc) 354 struct hme_softc *sc; 355 { 356 int s; 357 358 s = splnet(); 359 hme_init(sc); 360 splx(s); 361 } 362 363 void 364 hme_stop(sc) 365 struct hme_softc *sc; 366 { 367 bus_space_tag_t t = sc->sc_bustag; 368 bus_space_handle_t seb = sc->sc_seb; 369 int n; 370 371 callout_stop(&sc->sc_tick_ch); 372 mii_down(&sc->sc_mii); 373 374 /* Reset transmitter and receiver */ 375 bus_space_write_4(t, seb, HME_SEBI_RESET, 376 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 377 378 for (n = 0; n < 20; n++) { 379 u_int32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 380 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 381 return; 382 DELAY(20); 383 } 384 385 printf("%s: hme_stop: reset failed\n", sc->sc_dev.dv_xname); 386 } 387 388 void 389 hme_meminit(sc) 390 struct hme_softc *sc; 391 { 392 bus_addr_t txbufdma, rxbufdma; 393 bus_addr_t dma; 394 caddr_t p; 395 unsigned int ntbuf, nrbuf, i; 396 struct hme_ring *hr = &sc->sc_rb; 397 398 p = hr->rb_membase; 399 dma = hr->rb_dmabase; 400 401 ntbuf = hr->rb_ntbuf; 402 nrbuf = hr->rb_nrbuf; 403 404 /* 405 * Allocate transmit descriptors 406 */ 407 hr->rb_txd = p; 408 hr->rb_txddma = dma; 409 p += ntbuf * HME_XD_SIZE; 410 dma += ntbuf * HME_XD_SIZE; 411 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 412 dma = (bus_addr_t)roundup((u_long)dma, 2048); 413 p = (caddr_t)roundup((u_long)p, 2048); 414 415 /* 416 * Allocate receive descriptors 417 */ 418 hr->rb_rxd = p; 419 hr->rb_rxddma = dma; 420 p += nrbuf * HME_XD_SIZE; 421 dma += nrbuf * HME_XD_SIZE; 422 /* Again move forward to the next 2048 byte boundary.*/ 423 dma = (bus_addr_t)roundup((u_long)dma, 2048); 424 p = (caddr_t)roundup((u_long)p, 2048); 425 426 427 /* 428 * Allocate transmit buffers 429 */ 430 hr->rb_txbuf = p; 431 txbufdma = dma; 432 p += ntbuf * _HME_BUFSZ; 433 dma += ntbuf * _HME_BUFSZ; 434 435 /* 436 * Allocate receive buffers 437 */ 438 hr->rb_rxbuf = p; 439 rxbufdma = dma; 440 p += nrbuf * _HME_BUFSZ; 441 dma += nrbuf * _HME_BUFSZ; 442 443 /* 444 * Initialize transmit buffer descriptors 445 */ 446 for (i = 0; i < ntbuf; i++) { 447 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 448 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 449 } 450 451 /* 452 * Initialize receive buffer descriptors 453 */ 454 for (i = 0; i < nrbuf; i++) { 455 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 456 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 457 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 458 } 459 460 hr->rb_tdhead = hr->rb_tdtail = 0; 461 hr->rb_td_nbusy = 0; 462 hr->rb_rdtail = 0; 463 } 464 465 /* 466 * Initialization of interface; set up initialization block 467 * and transmit/receive descriptor rings. 468 */ 469 void 470 hme_init(sc) 471 struct hme_softc *sc; 472 { 473 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 474 bus_space_tag_t t = sc->sc_bustag; 475 bus_space_handle_t seb = sc->sc_seb; 476 bus_space_handle_t etx = sc->sc_etx; 477 bus_space_handle_t erx = sc->sc_erx; 478 bus_space_handle_t mac = sc->sc_mac; 479 bus_space_handle_t mif = sc->sc_mif; 480 u_int8_t *ea; 481 u_int32_t v; 482 483 /* 484 * Initialization sequence. The numbered steps below correspond 485 * to the sequence outlined in section 6.3.5.1 in the Ethernet 486 * Channel Engine manual (part of the PCIO manual). 487 * See also the STP2002-STQ document from Sun Microsystems. 488 */ 489 490 /* step 1 & 2. Reset the Ethernet Channel */ 491 hme_stop(sc); 492 493 /* Re-initialize the MIF */ 494 hme_mifinit(sc); 495 496 /* Call MI reset function if any */ 497 if (sc->sc_hwreset) 498 (*sc->sc_hwreset)(sc); 499 500 #if 0 501 /* Mask all MIF interrupts, just in case */ 502 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 503 #endif 504 505 /* step 3. Setup data structures in host memory */ 506 hme_meminit(sc); 507 508 /* step 4. TX MAC registers & counters */ 509 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 510 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 511 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 512 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 513 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 514 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 515 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : 516 ETHER_MAX_LEN); 517 518 /* Load station MAC address */ 519 ea = sc->sc_enaddr; 520 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 521 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 522 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 523 524 /* 525 * Init seed for backoff 526 * (source suggested by manual: low 10 bits of MAC address) 527 */ 528 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 529 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 530 531 532 /* Note: Accepting power-on default for other MAC registers here.. */ 533 534 535 /* step 5. RX MAC registers & counters */ 536 hme_setladrf(sc); 537 538 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 539 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 540 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 541 542 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 543 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 544 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 545 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : 546 ETHER_MAX_LEN); 547 548 549 /* step 8. Global Configuration & Interrupt Mask */ 550 bus_space_write_4(t, seb, HME_SEBI_IMASK, 551 ~( 552 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 553 HME_SEB_STAT_HOSTTOTX | 554 HME_SEB_STAT_RXTOHOST | 555 HME_SEB_STAT_TXALL | 556 HME_SEB_STAT_TXPERR | 557 HME_SEB_STAT_RCNTEXP | 558 HME_SEB_STAT_ALL_ERRORS )); 559 560 switch (sc->sc_burst) { 561 default: 562 v = 0; 563 break; 564 case 16: 565 v = HME_SEB_CFG_BURST16; 566 break; 567 case 32: 568 v = HME_SEB_CFG_BURST32; 569 break; 570 case 64: 571 v = HME_SEB_CFG_BURST64; 572 break; 573 } 574 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 575 576 /* step 9. ETX Configuration: use mostly default values */ 577 578 /* Enable DMA */ 579 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 580 v |= HME_ETX_CFG_DMAENABLE; 581 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 582 583 /* Transmit Descriptor ring size: in increments of 16 */ 584 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 585 586 587 /* step 10. ERX Configuration */ 588 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 589 590 /* Encode Receive Descriptor ring size: four possible values */ 591 switch (_HME_NDESC /*XXX*/) { 592 case 32: 593 v |= HME_ERX_CFG_RINGSIZE32; 594 break; 595 case 64: 596 v |= HME_ERX_CFG_RINGSIZE64; 597 break; 598 case 128: 599 v |= HME_ERX_CFG_RINGSIZE128; 600 break; 601 case 256: 602 v |= HME_ERX_CFG_RINGSIZE256; 603 break; 604 default: 605 printf("hme: invalid Receive Descriptor ring size\n"); 606 break; 607 } 608 609 /* Enable DMA */ 610 v |= HME_ERX_CFG_DMAENABLE; 611 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 612 613 /* step 11. XIF Configuration */ 614 v = bus_space_read_4(t, mac, HME_MACI_XIF); 615 v |= HME_MAC_XIF_OE; 616 /* If an external transceiver is connected, enable its MII drivers */ 617 if ((bus_space_read_4(t, mif, HME_MIFI_CFG) & HME_MIF_CFG_MDI1) != 0) 618 v |= HME_MAC_XIF_MIIENABLE; 619 bus_space_write_4(t, mac, HME_MACI_XIF, v); 620 621 622 /* step 12. RX_MAC Configuration Register */ 623 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 624 v |= HME_MAC_RXCFG_ENABLE; 625 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 626 627 /* step 13. TX_MAC Configuration Register */ 628 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 629 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 630 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 631 632 /* step 14. Issue Transmit Pending command */ 633 634 /* Call MI initialization function if any */ 635 if (sc->sc_hwinit) 636 (*sc->sc_hwinit)(sc); 637 638 /* Start the one second timer. */ 639 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 640 641 ifp->if_flags |= IFF_RUNNING; 642 ifp->if_flags &= ~IFF_OACTIVE; 643 ifp->if_timer = 0; 644 hme_start(ifp); 645 } 646 647 /* 648 * Compare two Ether/802 addresses for equality, inlined and unrolled for 649 * speed. 650 */ 651 static __inline__ int 652 ether_cmp(a, b) 653 u_char *a, *b; 654 { 655 656 if (a[5] != b[5] || a[4] != b[4] || a[3] != b[3] || 657 a[2] != b[2] || a[1] != b[1] || a[0] != b[0]) 658 return (0); 659 return (1); 660 } 661 662 663 /* 664 * Routine to copy from mbuf chain to transmit buffer in 665 * network buffer memory. 666 * Returns the amount of data copied. 667 */ 668 int 669 hme_put(sc, ri, m) 670 struct hme_softc *sc; 671 int ri; /* Ring index */ 672 struct mbuf *m; 673 { 674 struct mbuf *n; 675 int len, tlen = 0; 676 caddr_t bp; 677 678 bp = sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 679 for (; m; m = n) { 680 len = m->m_len; 681 if (len == 0) { 682 MFREE(m, n); 683 continue; 684 } 685 memcpy(bp, mtod(m, caddr_t), len); 686 bp += len; 687 tlen += len; 688 MFREE(m, n); 689 } 690 return (tlen); 691 } 692 693 /* 694 * Pull data off an interface. 695 * Len is length of data, with local net header stripped. 696 * We copy the data into mbufs. When full cluster sized units are present 697 * we copy into clusters. 698 */ 699 struct mbuf * 700 hme_get(sc, ri, totlen) 701 struct hme_softc *sc; 702 int ri, totlen; 703 { 704 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 705 struct mbuf *m, *m0, *newm; 706 caddr_t bp; 707 int len; 708 709 MGETHDR(m0, M_DONTWAIT, MT_DATA); 710 if (m0 == 0) 711 return (0); 712 m0->m_pkthdr.rcvif = ifp; 713 m0->m_pkthdr.len = totlen; 714 len = MHLEN; 715 m = m0; 716 717 bp = sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 718 719 while (totlen > 0) { 720 if (totlen >= MINCLSIZE) { 721 MCLGET(m, M_DONTWAIT); 722 if ((m->m_flags & M_EXT) == 0) 723 goto bad; 724 len = MCLBYTES; 725 } 726 727 if (m == m0) { 728 caddr_t newdata = (caddr_t) 729 ALIGN(m->m_data + sizeof(struct ether_header)) - 730 sizeof(struct ether_header); 731 len -= newdata - m->m_data; 732 m->m_data = newdata; 733 } 734 735 m->m_len = len = min(totlen, len); 736 memcpy(mtod(m, caddr_t), bp, len); 737 bp += len; 738 739 totlen -= len; 740 if (totlen > 0) { 741 MGET(newm, M_DONTWAIT, MT_DATA); 742 if (newm == 0) 743 goto bad; 744 len = MLEN; 745 m = m->m_next = newm; 746 } 747 } 748 749 return (m0); 750 751 bad: 752 m_freem(m0); 753 return (0); 754 } 755 756 /* 757 * Pass a packet to the higher levels. 758 */ 759 void 760 hme_read(sc, ix, len) 761 struct hme_softc *sc; 762 int ix, len; 763 { 764 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 765 struct mbuf *m; 766 767 if (len <= sizeof(struct ether_header) || 768 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 769 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 770 ETHERMTU + sizeof(struct ether_header))) { 771 #ifdef HMEDEBUG 772 printf("%s: invalid packet size %d; dropping\n", 773 sc->sc_dev.dv_xname, len); 774 #endif 775 ifp->if_ierrors++; 776 return; 777 } 778 779 /* Pull packet off interface. */ 780 m = hme_get(sc, ix, len); 781 if (m == 0) { 782 ifp->if_ierrors++; 783 return; 784 } 785 786 ifp->if_ipackets++; 787 788 #if NBPFILTER > 0 789 /* 790 * Check if there's a BPF listener on this interface. 791 * If so, hand off the raw packet to BPF. 792 */ 793 if (ifp->if_bpf) 794 bpf_mtap(ifp->if_bpf, m); 795 #endif 796 797 /* Pass the packet up. */ 798 (*ifp->if_input)(ifp, m); 799 } 800 801 void 802 hme_start(ifp) 803 struct ifnet *ifp; 804 { 805 struct hme_softc *sc = (struct hme_softc *)ifp->if_softc; 806 caddr_t txd = sc->sc_rb.rb_txd; 807 struct mbuf *m; 808 unsigned int ri, len; 809 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 810 811 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 812 return; 813 814 ri = sc->sc_rb.rb_tdhead; 815 816 for (;;) { 817 IFQ_DEQUEUE(&ifp->if_snd, m); 818 if (m == 0) 819 break; 820 821 #if NBPFILTER > 0 822 /* 823 * If BPF is listening on this interface, let it see the 824 * packet before we commit it to the wire. 825 */ 826 if (ifp->if_bpf) 827 bpf_mtap(ifp->if_bpf, m); 828 #endif 829 830 /* 831 * Copy the mbuf chain into the transmit buffer. 832 */ 833 len = hme_put(sc, ri, m); 834 835 /* 836 * Initialize transmit registers and start transmission 837 */ 838 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 839 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 840 HME_XD_ENCODE_TSIZE(len)); 841 842 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 843 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 844 HME_ETX_TP_DMAWAKEUP); 845 846 if (++ri == ntbuf) 847 ri = 0; 848 849 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 850 ifp->if_flags |= IFF_OACTIVE; 851 break; 852 } 853 } 854 855 sc->sc_rb.rb_tdhead = ri; 856 } 857 858 /* 859 * Transmit interrupt. 860 */ 861 int 862 hme_tint(sc) 863 struct hme_softc *sc; 864 { 865 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 866 bus_space_tag_t t = sc->sc_bustag; 867 bus_space_handle_t mac = sc->sc_mac; 868 unsigned int ri, txflags; 869 870 /* 871 * Unload collision counters 872 */ 873 ifp->if_collisions += 874 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 875 bus_space_read_4(t, mac, HME_MACI_FCCNT) + 876 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 877 bus_space_read_4(t, mac, HME_MACI_LTCNT); 878 879 /* 880 * then clear the hardware counters. 881 */ 882 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 883 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 884 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 885 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 886 887 /* Fetch current position in the transmit ring */ 888 ri = sc->sc_rb.rb_tdtail; 889 890 for (;;) { 891 if (sc->sc_rb.rb_td_nbusy <= 0) 892 break; 893 894 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 895 896 if (txflags & HME_XD_OWN) 897 break; 898 899 ifp->if_flags &= ~IFF_OACTIVE; 900 ifp->if_opackets++; 901 902 if (++ri == sc->sc_rb.rb_ntbuf) 903 ri = 0; 904 905 --sc->sc_rb.rb_td_nbusy; 906 } 907 908 /* Update ring */ 909 sc->sc_rb.rb_tdtail = ri; 910 911 hme_start(ifp); 912 913 if (sc->sc_rb.rb_td_nbusy == 0) 914 ifp->if_timer = 0; 915 916 return (1); 917 } 918 919 /* 920 * Receive interrupt. 921 */ 922 int 923 hme_rint(sc) 924 struct hme_softc *sc; 925 { 926 caddr_t xdr = sc->sc_rb.rb_rxd; 927 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 928 unsigned int ri, len; 929 u_int32_t flags; 930 931 ri = sc->sc_rb.rb_rdtail; 932 933 /* 934 * Process all buffers with valid data. 935 */ 936 for (;;) { 937 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 938 if (flags & HME_XD_OWN) 939 break; 940 941 if (flags & HME_XD_OFL) { 942 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 943 sc->sc_dev.dv_xname, ri, flags); 944 } else { 945 len = HME_XD_DECODE_RSIZE(flags); 946 hme_read(sc, ri, len); 947 } 948 949 /* This buffer can be used by the hardware again */ 950 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 951 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 952 953 if (++ri == nrbuf) 954 ri = 0; 955 } 956 957 sc->sc_rb.rb_rdtail = ri; 958 959 return (1); 960 } 961 962 int 963 hme_eint(sc, status) 964 struct hme_softc *sc; 965 u_int status; 966 { 967 char bits[128]; 968 969 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 970 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 971 return (1); 972 } 973 974 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 975 bitmask_snprintf(status, HME_SEB_STAT_BITS, bits,sizeof(bits))); 976 return (1); 977 } 978 979 int 980 hme_intr(v) 981 void *v; 982 { 983 struct hme_softc *sc = (struct hme_softc *)v; 984 bus_space_tag_t t = sc->sc_bustag; 985 bus_space_handle_t seb = sc->sc_seb; 986 u_int32_t status; 987 int r = 0; 988 989 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 990 991 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 992 r |= hme_eint(sc, status); 993 994 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 995 r |= hme_tint(sc); 996 997 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 998 r |= hme_rint(sc); 999 1000 return (r); 1001 } 1002 1003 1004 void 1005 hme_watchdog(ifp) 1006 struct ifnet *ifp; 1007 { 1008 struct hme_softc *sc = ifp->if_softc; 1009 1010 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1011 ++ifp->if_oerrors; 1012 1013 hme_reset(sc); 1014 } 1015 1016 /* 1017 * Initialize the MII Management Interface 1018 */ 1019 void 1020 hme_mifinit(sc) 1021 struct hme_softc *sc; 1022 { 1023 bus_space_tag_t t = sc->sc_bustag; 1024 bus_space_handle_t mif = sc->sc_mif; 1025 u_int32_t v; 1026 1027 /* Configure the MIF in frame mode */ 1028 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1029 v &= ~HME_MIF_CFG_BBMODE; 1030 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1031 } 1032 1033 /* 1034 * MII interface 1035 */ 1036 static int 1037 hme_mii_readreg(self, phy, reg) 1038 struct device *self; 1039 int phy, reg; 1040 { 1041 struct hme_softc *sc = (void *)self; 1042 bus_space_tag_t t = sc->sc_bustag; 1043 bus_space_handle_t mif = sc->sc_mif; 1044 int n; 1045 u_int32_t v; 1046 1047 /* Select the desired PHY in the MIF configuration register */ 1048 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1049 /* Clear PHY select bit */ 1050 v &= ~HME_MIF_CFG_PHY; 1051 if (phy == HME_PHYAD_EXTERNAL) 1052 /* Set PHY select bit to get at external device */ 1053 v |= HME_MIF_CFG_PHY; 1054 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1055 1056 /* Construct the frame command */ 1057 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1058 HME_MIF_FO_TAMSB | 1059 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1060 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1061 (reg << HME_MIF_FO_REGAD_SHIFT); 1062 1063 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1064 for (n = 0; n < 100; n++) { 1065 DELAY(1); 1066 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1067 if (v & HME_MIF_FO_TALSB) 1068 return (v & HME_MIF_FO_DATA); 1069 } 1070 1071 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1072 return (0); 1073 } 1074 1075 static void 1076 hme_mii_writereg(self, phy, reg, val) 1077 struct device *self; 1078 int phy, reg, val; 1079 { 1080 struct hme_softc *sc = (void *)self; 1081 bus_space_tag_t t = sc->sc_bustag; 1082 bus_space_handle_t mif = sc->sc_mif; 1083 int n; 1084 u_int32_t v; 1085 1086 /* Select the desired PHY in the MIF configuration register */ 1087 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1088 /* Clear PHY select bit */ 1089 v &= ~HME_MIF_CFG_PHY; 1090 if (phy == HME_PHYAD_EXTERNAL) 1091 /* Set PHY select bit to get at external device */ 1092 v |= HME_MIF_CFG_PHY; 1093 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1094 1095 /* Construct the frame command */ 1096 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1097 HME_MIF_FO_TAMSB | 1098 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1099 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1100 (reg << HME_MIF_FO_REGAD_SHIFT) | 1101 (val & HME_MIF_FO_DATA); 1102 1103 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1104 for (n = 0; n < 100; n++) { 1105 DELAY(1); 1106 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1107 if (v & HME_MIF_FO_TALSB) 1108 return; 1109 } 1110 1111 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1112 } 1113 1114 static void 1115 hme_mii_statchg(dev) 1116 struct device *dev; 1117 { 1118 struct hme_softc *sc = (void *)dev; 1119 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1120 int phy = sc->sc_phys[instance]; 1121 bus_space_tag_t t = sc->sc_bustag; 1122 bus_space_handle_t mif = sc->sc_mif; 1123 bus_space_handle_t mac = sc->sc_mac; 1124 u_int32_t v; 1125 1126 #ifdef HMEDEBUG 1127 if (sc->sc_debug) 1128 printf("hme_mii_statchg: status change: phy = %d\n", phy); 1129 #endif 1130 1131 /* Select the current PHY in the MIF configuration register */ 1132 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1133 v &= ~HME_MIF_CFG_PHY; 1134 if (phy == HME_PHYAD_EXTERNAL) 1135 v |= HME_MIF_CFG_PHY; 1136 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1137 1138 /* Set the MAC Full Duplex bit appropriately */ 1139 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1140 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1141 v |= HME_MAC_TXCFG_FULLDPLX; 1142 else 1143 v &= ~HME_MAC_TXCFG_FULLDPLX; 1144 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1145 1146 /* If an external transceiver is selected, enable its MII drivers */ 1147 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1148 v &= ~HME_MAC_XIF_MIIENABLE; 1149 if (phy == HME_PHYAD_EXTERNAL) 1150 v |= HME_MAC_XIF_MIIENABLE; 1151 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1152 } 1153 1154 int 1155 hme_mediachange(ifp) 1156 struct ifnet *ifp; 1157 { 1158 struct hme_softc *sc = ifp->if_softc; 1159 1160 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1161 return (EINVAL); 1162 1163 return (mii_mediachg(&sc->sc_mii)); 1164 } 1165 1166 void 1167 hme_mediastatus(ifp, ifmr) 1168 struct ifnet *ifp; 1169 struct ifmediareq *ifmr; 1170 { 1171 struct hme_softc *sc = ifp->if_softc; 1172 1173 if ((ifp->if_flags & IFF_UP) == 0) 1174 return; 1175 1176 mii_pollstat(&sc->sc_mii); 1177 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1178 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1179 } 1180 1181 /* 1182 * Process an ioctl request. 1183 */ 1184 int 1185 hme_ioctl(ifp, cmd, data) 1186 struct ifnet *ifp; 1187 u_long cmd; 1188 caddr_t data; 1189 { 1190 struct hme_softc *sc = ifp->if_softc; 1191 struct ifaddr *ifa = (struct ifaddr *)data; 1192 struct ifreq *ifr = (struct ifreq *)data; 1193 int s, error = 0; 1194 1195 s = splnet(); 1196 1197 switch (cmd) { 1198 1199 case SIOCSIFADDR: 1200 ifp->if_flags |= IFF_UP; 1201 1202 switch (ifa->ifa_addr->sa_family) { 1203 #ifdef INET 1204 case AF_INET: 1205 hme_init(sc); 1206 arp_ifinit(ifp, ifa); 1207 break; 1208 #endif 1209 #ifdef NS 1210 case AF_NS: 1211 { 1212 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1213 1214 if (ns_nullhost(*ina)) 1215 ina->x_host = 1216 *(union ns_host *)LLADDR(ifp->if_sadl); 1217 else { 1218 memcpy(LLADDR(ifp->if_sadl), 1219 ina->x_host.c_host, sizeof(sc->sc_enaddr)); 1220 } 1221 /* Set new address. */ 1222 hme_init(sc); 1223 break; 1224 } 1225 #endif 1226 default: 1227 hme_init(sc); 1228 break; 1229 } 1230 break; 1231 1232 case SIOCSIFFLAGS: 1233 if ((ifp->if_flags & IFF_UP) == 0 && 1234 (ifp->if_flags & IFF_RUNNING) != 0) { 1235 /* 1236 * If interface is marked down and it is running, then 1237 * stop it. 1238 */ 1239 hme_stop(sc); 1240 ifp->if_flags &= ~IFF_RUNNING; 1241 } else if ((ifp->if_flags & IFF_UP) != 0 && 1242 (ifp->if_flags & IFF_RUNNING) == 0) { 1243 /* 1244 * If interface is marked up and it is stopped, then 1245 * start it. 1246 */ 1247 hme_init(sc); 1248 } else if ((ifp->if_flags & IFF_UP) != 0) { 1249 /* 1250 * Reset the interface to pick up changes in any other 1251 * flags that affect hardware registers. 1252 */ 1253 /*hme_stop(sc);*/ 1254 hme_init(sc); 1255 } 1256 #ifdef HMEDEBUG 1257 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1258 #endif 1259 break; 1260 1261 case SIOCADDMULTI: 1262 case SIOCDELMULTI: 1263 error = (cmd == SIOCADDMULTI) ? 1264 ether_addmulti(ifr, &sc->sc_ethercom) : 1265 ether_delmulti(ifr, &sc->sc_ethercom); 1266 1267 if (error == ENETRESET) { 1268 /* 1269 * Multicast list has changed; set the hardware filter 1270 * accordingly. 1271 */ 1272 hme_setladrf(sc); 1273 error = 0; 1274 } 1275 break; 1276 1277 case SIOCGIFMEDIA: 1278 case SIOCSIFMEDIA: 1279 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1280 break; 1281 1282 default: 1283 error = EINVAL; 1284 break; 1285 } 1286 1287 splx(s); 1288 return (error); 1289 } 1290 1291 void 1292 hme_shutdown(arg) 1293 void *arg; 1294 { 1295 1296 hme_stop((struct hme_softc *)arg); 1297 } 1298 1299 /* 1300 * Set up the logical address filter. 1301 */ 1302 void 1303 hme_setladrf(sc) 1304 struct hme_softc *sc; 1305 { 1306 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1307 struct ether_multi *enm; 1308 struct ether_multistep step; 1309 struct ethercom *ec = &sc->sc_ethercom; 1310 bus_space_tag_t t = sc->sc_bustag; 1311 bus_space_handle_t mac = sc->sc_mac; 1312 u_char *cp; 1313 u_int32_t crc; 1314 u_int32_t hash[4]; 1315 u_int32_t v; 1316 int len; 1317 1318 /* Clear hash table */ 1319 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1320 1321 /* Get current RX configuration */ 1322 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1323 1324 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1325 /* Turn on promiscuous mode; turn off the hash filter */ 1326 v |= HME_MAC_RXCFG_PMISC; 1327 v &= ~HME_MAC_RXCFG_HENABLE; 1328 ifp->if_flags |= IFF_ALLMULTI; 1329 goto chipit; 1330 } 1331 1332 /* Turn off promiscuous mode; turn on the hash filter */ 1333 v &= ~HME_MAC_RXCFG_PMISC; 1334 v |= HME_MAC_RXCFG_HENABLE; 1335 1336 /* 1337 * Set up multicast address filter by passing all multicast addresses 1338 * through a crc generator, and then using the high order 6 bits as an 1339 * index into the 64 bit logical address filter. The high order bit 1340 * selects the word, while the rest of the bits select the bit within 1341 * the word. 1342 */ 1343 1344 ETHER_FIRST_MULTI(step, ec, enm); 1345 while (enm != NULL) { 1346 if (ether_cmp(enm->enm_addrlo, enm->enm_addrhi)) { 1347 /* 1348 * We must listen to a range of multicast addresses. 1349 * For now, just accept all multicasts, rather than 1350 * trying to set only those filter bits needed to match 1351 * the range. (At this time, the only use of address 1352 * ranges is for IP multicast routing, for which the 1353 * range is big enough to require all bits set.) 1354 */ 1355 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1356 ifp->if_flags |= IFF_ALLMULTI; 1357 goto chipit; 1358 } 1359 1360 cp = enm->enm_addrlo; 1361 crc = 0xffffffff; 1362 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1363 int octet = *cp++; 1364 int i; 1365 1366 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1367 for (i = 0; i < 8; i++) { 1368 if ((crc & 1) ^ (octet & 1)) { 1369 crc >>= 1; 1370 crc ^= MC_POLY_LE; 1371 } else { 1372 crc >>= 1; 1373 } 1374 octet >>= 1; 1375 } 1376 } 1377 /* Just want the 6 most significant bits. */ 1378 crc >>= 26; 1379 1380 /* Set the corresponding bit in the filter. */ 1381 hash[crc >> 4] |= 1 << (crc & 0xf); 1382 1383 ETHER_NEXT_MULTI(step, enm); 1384 } 1385 1386 ifp->if_flags &= ~IFF_ALLMULTI; 1387 1388 chipit: 1389 /* Now load the hash table into the chip */ 1390 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1391 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1392 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1393 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1394 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1395 } 1396 1397 /* 1398 * Routines for accessing the transmit and receive buffers. 1399 * The various CPU and adapter configurations supported by this 1400 * driver require three different access methods for buffers 1401 * and descriptors: 1402 * (1) contig (contiguous data; no padding), 1403 * (2) gap2 (two bytes of data followed by two bytes of padding), 1404 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1405 */ 1406 1407 #if 0 1408 /* 1409 * contig: contiguous data with no padding. 1410 * 1411 * Buffers may have any alignment. 1412 */ 1413 1414 void 1415 hme_copytobuf_contig(sc, from, ri, len) 1416 struct hme_softc *sc; 1417 void *from; 1418 int ri, len; 1419 { 1420 volatile caddr_t buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1421 1422 /* 1423 * Just call memcpy() to do the work. 1424 */ 1425 memcpy(buf, from, len); 1426 } 1427 1428 void 1429 hme_copyfrombuf_contig(sc, to, boff, len) 1430 struct hme_softc *sc; 1431 void *to; 1432 int boff, len; 1433 { 1434 volatile caddr_t buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1435 1436 /* 1437 * Just call memcpy() to do the work. 1438 */ 1439 memcpy(to, buf, len); 1440 } 1441 #endif 1442