1 /* $NetBSD: hme.c,v 1.47 2005/02/21 02:12:48 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * HME Ethernet module driver. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.47 2005/02/21 02:12:48 thorpej Exp $"); 45 46 /* #define HMEDEBUG */ 47 48 #include "opt_inet.h" 49 #include "opt_ns.h" 50 #include "bpfilter.h" 51 #include "rnd.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/mbuf.h> 57 #include <sys/syslog.h> 58 #include <sys/socket.h> 59 #include <sys/device.h> 60 #include <sys/malloc.h> 61 #include <sys/ioctl.h> 62 #include <sys/errno.h> 63 #if NRND > 0 64 #include <sys/rnd.h> 65 #endif 66 67 #include <net/if.h> 68 #include <net/if_dl.h> 69 #include <net/if_ether.h> 70 #include <net/if_media.h> 71 72 #ifdef INET 73 #include <netinet/in.h> 74 #include <netinet/if_inarp.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/in_var.h> 77 #include <netinet/ip.h> 78 #include <netinet/tcp.h> 79 #include <netinet/udp.h> 80 #endif 81 82 #ifdef NS 83 #include <netns/ns.h> 84 #include <netns/ns_if.h> 85 #endif 86 87 #if NBPFILTER > 0 88 #include <net/bpf.h> 89 #include <net/bpfdesc.h> 90 #endif 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 95 #include <machine/bus.h> 96 97 #include <dev/ic/hmereg.h> 98 #include <dev/ic/hmevar.h> 99 100 void hme_start(struct ifnet *); 101 void hme_stop(struct hme_softc *); 102 int hme_ioctl(struct ifnet *, u_long, caddr_t); 103 void hme_tick(void *); 104 void hme_watchdog(struct ifnet *); 105 void hme_shutdown(void *); 106 void hme_init(struct hme_softc *); 107 void hme_meminit(struct hme_softc *); 108 void hme_mifinit(struct hme_softc *); 109 void hme_reset(struct hme_softc *); 110 void hme_setladrf(struct hme_softc *); 111 112 /* MII methods & callbacks */ 113 static int hme_mii_readreg(struct device *, int, int); 114 static void hme_mii_writereg(struct device *, int, int, int); 115 static void hme_mii_statchg(struct device *); 116 117 int hme_mediachange(struct ifnet *); 118 void hme_mediastatus(struct ifnet *, struct ifmediareq *); 119 120 struct mbuf *hme_get(struct hme_softc *, int, uint32_t); 121 int hme_put(struct hme_softc *, int, struct mbuf *); 122 void hme_read(struct hme_softc *, int, uint32_t); 123 int hme_eint(struct hme_softc *, u_int); 124 int hme_rint(struct hme_softc *); 125 int hme_tint(struct hme_softc *); 126 127 static int ether_cmp(u_char *, u_char *); 128 129 /* Default buffer copy routines */ 130 void hme_copytobuf_contig(struct hme_softc *, void *, int, int); 131 void hme_copyfrombuf_contig(struct hme_softc *, void *, int, int); 132 void hme_zerobuf_contig(struct hme_softc *, int, int); 133 134 135 void 136 hme_config(sc) 137 struct hme_softc *sc; 138 { 139 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 140 struct mii_data *mii = &sc->sc_mii; 141 struct mii_softc *child; 142 bus_dma_tag_t dmatag = sc->sc_dmatag; 143 bus_dma_segment_t seg; 144 bus_size_t size; 145 int rseg, error; 146 147 /* 148 * HME common initialization. 149 * 150 * hme_softc fields that must be initialized by the front-end: 151 * 152 * the bus tag: 153 * sc_bustag 154 * 155 * the DMA bus tag: 156 * sc_dmatag 157 * 158 * the bus handles: 159 * sc_seb (Shared Ethernet Block registers) 160 * sc_erx (Receiver Unit registers) 161 * sc_etx (Transmitter Unit registers) 162 * sc_mac (MAC registers) 163 * sc_mif (Management Interface registers) 164 * 165 * the maximum bus burst size: 166 * sc_burst 167 * 168 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 169 * rb_membase, rb_dmabase) 170 * 171 * the local Ethernet address: 172 * sc_enaddr 173 * 174 */ 175 176 /* Make sure the chip is stopped. */ 177 hme_stop(sc); 178 179 180 /* 181 * Allocate descriptors and buffers 182 * XXX - do all this differently.. and more configurably, 183 * eg. use things as `dma_load_mbuf()' on transmit, 184 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 185 * all the time) on the receiver side. 186 * 187 * Note: receive buffers must be 64-byte aligned. 188 * Also, apparently, the buffers must extend to a DMA burst 189 * boundary beyond the maximum packet size. 190 */ 191 #define _HME_NDESC 128 192 #define _HME_BUFSZ 1600 193 194 /* Note: the # of descriptors must be a multiple of 16 */ 195 sc->sc_rb.rb_ntbuf = _HME_NDESC; 196 sc->sc_rb.rb_nrbuf = _HME_NDESC; 197 198 /* 199 * Allocate DMA capable memory 200 * Buffer descriptors must be aligned on a 2048 byte boundary; 201 * take this into account when calculating the size. Note that 202 * the maximum number of descriptors (256) occupies 2048 bytes, 203 * so we allocate that much regardless of _HME_NDESC. 204 */ 205 size = 2048 + /* TX descriptors */ 206 2048 + /* RX descriptors */ 207 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 208 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* RX buffers */ 209 210 /* Allocate DMA buffer */ 211 if ((error = bus_dmamem_alloc(dmatag, size, 212 2048, 0, 213 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 214 printf("%s: DMA buffer alloc error %d\n", 215 sc->sc_dev.dv_xname, error); 216 return; 217 } 218 219 /* Map DMA memory in CPU addressable space */ 220 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 221 &sc->sc_rb.rb_membase, 222 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 223 printf("%s: DMA buffer map error %d\n", 224 sc->sc_dev.dv_xname, error); 225 bus_dmamap_unload(dmatag, sc->sc_dmamap); 226 bus_dmamem_free(dmatag, &seg, rseg); 227 return; 228 } 229 230 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 231 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 232 printf("%s: DMA map create error %d\n", 233 sc->sc_dev.dv_xname, error); 234 return; 235 } 236 237 /* Load the buffer */ 238 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 239 sc->sc_rb.rb_membase, size, NULL, 240 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 241 printf("%s: DMA buffer map load error %d\n", 242 sc->sc_dev.dv_xname, error); 243 bus_dmamem_free(dmatag, &seg, rseg); 244 return; 245 } 246 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 247 248 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 249 ether_sprintf(sc->sc_enaddr)); 250 251 /* Initialize ifnet structure. */ 252 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 253 ifp->if_softc = sc; 254 ifp->if_start = hme_start; 255 ifp->if_ioctl = hme_ioctl; 256 ifp->if_watchdog = hme_watchdog; 257 ifp->if_flags = 258 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 259 sc->sc_if_flags = ifp->if_flags; 260 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 261 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 262 IFQ_SET_READY(&ifp->if_snd); 263 264 /* Initialize ifmedia structures and MII info */ 265 mii->mii_ifp = ifp; 266 mii->mii_readreg = hme_mii_readreg; 267 mii->mii_writereg = hme_mii_writereg; 268 mii->mii_statchg = hme_mii_statchg; 269 270 ifmedia_init(&mii->mii_media, 0, hme_mediachange, hme_mediastatus); 271 272 hme_mifinit(sc); 273 274 mii_attach(&sc->sc_dev, mii, 0xffffffff, 275 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 276 277 child = LIST_FIRST(&mii->mii_phys); 278 if (child == NULL) { 279 /* No PHY attached */ 280 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 281 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 282 } else { 283 /* 284 * Walk along the list of attached MII devices and 285 * establish an `MII instance' to `phy number' 286 * mapping. We'll use this mapping in media change 287 * requests to determine which phy to use to program 288 * the MIF configuration register. 289 */ 290 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 291 /* 292 * Note: we support just two PHYs: the built-in 293 * internal device and an external on the MII 294 * connector. 295 */ 296 if (child->mii_phy > 1 || child->mii_inst > 1) { 297 printf("%s: cannot accomodate MII device %s" 298 " at phy %d, instance %d\n", 299 sc->sc_dev.dv_xname, 300 child->mii_dev.dv_xname, 301 child->mii_phy, child->mii_inst); 302 continue; 303 } 304 305 sc->sc_phys[child->mii_inst] = child->mii_phy; 306 } 307 308 /* 309 * XXX - we can really do the following ONLY if the 310 * phy indeed has the auto negotiation capability!! 311 */ 312 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 313 } 314 315 /* claim 802.1q capability */ 316 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 317 318 /* Attach the interface. */ 319 if_attach(ifp); 320 ether_ifattach(ifp, sc->sc_enaddr); 321 322 sc->sc_sh = shutdownhook_establish(hme_shutdown, sc); 323 if (sc->sc_sh == NULL) 324 panic("hme_config: can't establish shutdownhook"); 325 326 #if NRND > 0 327 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 328 RND_TYPE_NET, 0); 329 #endif 330 331 callout_init(&sc->sc_tick_ch); 332 } 333 334 void 335 hme_tick(arg) 336 void *arg; 337 { 338 struct hme_softc *sc = arg; 339 int s; 340 341 s = splnet(); 342 mii_tick(&sc->sc_mii); 343 splx(s); 344 345 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 346 } 347 348 void 349 hme_reset(sc) 350 struct hme_softc *sc; 351 { 352 int s; 353 354 s = splnet(); 355 hme_init(sc); 356 splx(s); 357 } 358 359 void 360 hme_stop(sc) 361 struct hme_softc *sc; 362 { 363 bus_space_tag_t t = sc->sc_bustag; 364 bus_space_handle_t seb = sc->sc_seb; 365 int n; 366 367 callout_stop(&sc->sc_tick_ch); 368 mii_down(&sc->sc_mii); 369 370 /* Mask all interrupts */ 371 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff); 372 373 /* Reset transmitter and receiver */ 374 bus_space_write_4(t, seb, HME_SEBI_RESET, 375 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 376 377 for (n = 0; n < 20; n++) { 378 u_int32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 379 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 380 return; 381 DELAY(20); 382 } 383 384 printf("%s: hme_stop: reset failed\n", sc->sc_dev.dv_xname); 385 } 386 387 void 388 hme_meminit(sc) 389 struct hme_softc *sc; 390 { 391 bus_addr_t txbufdma, rxbufdma; 392 bus_addr_t dma; 393 caddr_t p; 394 unsigned int ntbuf, nrbuf, i; 395 struct hme_ring *hr = &sc->sc_rb; 396 397 p = hr->rb_membase; 398 dma = hr->rb_dmabase; 399 400 ntbuf = hr->rb_ntbuf; 401 nrbuf = hr->rb_nrbuf; 402 403 /* 404 * Allocate transmit descriptors 405 */ 406 hr->rb_txd = p; 407 hr->rb_txddma = dma; 408 p += ntbuf * HME_XD_SIZE; 409 dma += ntbuf * HME_XD_SIZE; 410 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 411 dma = (bus_addr_t)roundup((u_long)dma, 2048); 412 p = (caddr_t)roundup((u_long)p, 2048); 413 414 /* 415 * Allocate receive descriptors 416 */ 417 hr->rb_rxd = p; 418 hr->rb_rxddma = dma; 419 p += nrbuf * HME_XD_SIZE; 420 dma += nrbuf * HME_XD_SIZE; 421 /* Again move forward to the next 2048 byte boundary.*/ 422 dma = (bus_addr_t)roundup((u_long)dma, 2048); 423 p = (caddr_t)roundup((u_long)p, 2048); 424 425 426 /* 427 * Allocate transmit buffers 428 */ 429 hr->rb_txbuf = p; 430 txbufdma = dma; 431 p += ntbuf * _HME_BUFSZ; 432 dma += ntbuf * _HME_BUFSZ; 433 434 /* 435 * Allocate receive buffers 436 */ 437 hr->rb_rxbuf = p; 438 rxbufdma = dma; 439 p += nrbuf * _HME_BUFSZ; 440 dma += nrbuf * _HME_BUFSZ; 441 442 /* 443 * Initialize transmit buffer descriptors 444 */ 445 for (i = 0; i < ntbuf; i++) { 446 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 447 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 448 } 449 450 /* 451 * Initialize receive buffer descriptors 452 */ 453 for (i = 0; i < nrbuf; i++) { 454 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 455 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 456 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 457 } 458 459 hr->rb_tdhead = hr->rb_tdtail = 0; 460 hr->rb_td_nbusy = 0; 461 hr->rb_rdtail = 0; 462 } 463 464 /* 465 * Initialization of interface; set up initialization block 466 * and transmit/receive descriptor rings. 467 */ 468 void 469 hme_init(sc) 470 struct hme_softc *sc; 471 { 472 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 473 bus_space_tag_t t = sc->sc_bustag; 474 bus_space_handle_t seb = sc->sc_seb; 475 bus_space_handle_t etx = sc->sc_etx; 476 bus_space_handle_t erx = sc->sc_erx; 477 bus_space_handle_t mac = sc->sc_mac; 478 u_int8_t *ea; 479 u_int32_t v; 480 481 /* 482 * Initialization sequence. The numbered steps below correspond 483 * to the sequence outlined in section 6.3.5.1 in the Ethernet 484 * Channel Engine manual (part of the PCIO manual). 485 * See also the STP2002-STQ document from Sun Microsystems. 486 */ 487 488 /* step 1 & 2. Reset the Ethernet Channel */ 489 hme_stop(sc); 490 491 /* Re-initialize the MIF */ 492 hme_mifinit(sc); 493 494 /* Call MI reset function if any */ 495 if (sc->sc_hwreset) 496 (*sc->sc_hwreset)(sc); 497 498 #if 0 499 /* Mask all MIF interrupts, just in case */ 500 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 501 #endif 502 503 /* step 3. Setup data structures in host memory */ 504 hme_meminit(sc); 505 506 /* step 4. TX MAC registers & counters */ 507 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 508 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 509 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 510 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 511 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 512 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 513 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : 514 ETHER_MAX_LEN); 515 sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable; 516 517 /* Load station MAC address */ 518 ea = sc->sc_enaddr; 519 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 520 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 521 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 522 523 /* 524 * Init seed for backoff 525 * (source suggested by manual: low 10 bits of MAC address) 526 */ 527 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 528 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 529 530 531 /* Note: Accepting power-on default for other MAC registers here.. */ 532 533 534 /* step 5. RX MAC registers & counters */ 535 hme_setladrf(sc); 536 537 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 538 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 539 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 540 541 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 542 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 543 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 544 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : 545 ETHER_MAX_LEN); 546 547 548 /* step 8. Global Configuration & Interrupt Mask */ 549 bus_space_write_4(t, seb, HME_SEBI_IMASK, 550 ~( 551 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 552 HME_SEB_STAT_HOSTTOTX | 553 HME_SEB_STAT_RXTOHOST | 554 HME_SEB_STAT_TXALL | 555 HME_SEB_STAT_TXPERR | 556 HME_SEB_STAT_RCNTEXP | 557 /*HME_SEB_STAT_MIFIRQ |*/ 558 HME_SEB_STAT_ALL_ERRORS )); 559 560 switch (sc->sc_burst) { 561 default: 562 v = 0; 563 break; 564 case 16: 565 v = HME_SEB_CFG_BURST16; 566 break; 567 case 32: 568 v = HME_SEB_CFG_BURST32; 569 break; 570 case 64: 571 v = HME_SEB_CFG_BURST64; 572 break; 573 } 574 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 575 576 /* step 9. ETX Configuration: use mostly default values */ 577 578 /* Enable DMA */ 579 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 580 v |= HME_ETX_CFG_DMAENABLE; 581 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 582 583 /* Transmit Descriptor ring size: in increments of 16 */ 584 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 585 586 587 /* step 10. ERX Configuration */ 588 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 589 590 /* Encode Receive Descriptor ring size: four possible values */ 591 switch (_HME_NDESC /*XXX*/) { 592 case 32: 593 v |= HME_ERX_CFG_RINGSIZE32; 594 break; 595 case 64: 596 v |= HME_ERX_CFG_RINGSIZE64; 597 break; 598 case 128: 599 v |= HME_ERX_CFG_RINGSIZE128; 600 break; 601 case 256: 602 v |= HME_ERX_CFG_RINGSIZE256; 603 break; 604 default: 605 printf("hme: invalid Receive Descriptor ring size\n"); 606 break; 607 } 608 609 /* Enable DMA */ 610 v |= HME_ERX_CFG_DMAENABLE; 611 612 /* set h/w rx checksum start offset (# of half-words) */ 613 v |= (((ETHER_HDR_LEN + sizeof(struct ip) + 614 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 615 ETHER_VLAN_ENCAP_LEN : 0)) / 2) << HME_ERX_CFG_CSUMSHIFT) & 616 HME_ERX_CFG_CSUMSTART; 617 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 618 619 /* step 11. XIF Configuration */ 620 v = bus_space_read_4(t, mac, HME_MACI_XIF); 621 v |= HME_MAC_XIF_OE; 622 bus_space_write_4(t, mac, HME_MACI_XIF, v); 623 624 /* step 12. RX_MAC Configuration Register */ 625 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 626 v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP; 627 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 628 629 /* step 13. TX_MAC Configuration Register */ 630 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 631 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 632 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 633 634 /* step 14. Issue Transmit Pending command */ 635 636 /* Call MI initialization function if any */ 637 if (sc->sc_hwinit) 638 (*sc->sc_hwinit)(sc); 639 640 /* Set the current media. */ 641 mii_mediachg(&sc->sc_mii); 642 643 /* Start the one second timer. */ 644 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 645 646 ifp->if_flags |= IFF_RUNNING; 647 ifp->if_flags &= ~IFF_OACTIVE; 648 sc->sc_if_flags = ifp->if_flags; 649 ifp->if_timer = 0; 650 hme_start(ifp); 651 } 652 653 /* 654 * Compare two Ether/802 addresses for equality, inlined and unrolled for 655 * speed. 656 */ 657 static __inline__ int 658 ether_cmp(a, b) 659 u_char *a, *b; 660 { 661 662 if (a[5] != b[5] || a[4] != b[4] || a[3] != b[3] || 663 a[2] != b[2] || a[1] != b[1] || a[0] != b[0]) 664 return (0); 665 return (1); 666 } 667 668 669 /* 670 * Routine to copy from mbuf chain to transmit buffer in 671 * network buffer memory. 672 * Returns the amount of data copied. 673 */ 674 int 675 hme_put(sc, ri, m) 676 struct hme_softc *sc; 677 int ri; /* Ring index */ 678 struct mbuf *m; 679 { 680 struct mbuf *n; 681 int len, tlen = 0; 682 caddr_t bp; 683 684 bp = sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 685 for (; m; m = n) { 686 len = m->m_len; 687 if (len == 0) { 688 MFREE(m, n); 689 continue; 690 } 691 memcpy(bp, mtod(m, caddr_t), len); 692 bp += len; 693 tlen += len; 694 MFREE(m, n); 695 } 696 return (tlen); 697 } 698 699 /* 700 * Pull data off an interface. 701 * Len is length of data, with local net header stripped. 702 * We copy the data into mbufs. When full cluster sized units are present 703 * we copy into clusters. 704 */ 705 struct mbuf * 706 hme_get(sc, ri, flags) 707 struct hme_softc *sc; 708 int ri; 709 u_int32_t flags; 710 { 711 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 712 struct mbuf *m, *m0, *newm; 713 caddr_t bp; 714 int len, totlen; 715 716 totlen = HME_XD_DECODE_RSIZE(flags); 717 MGETHDR(m0, M_DONTWAIT, MT_DATA); 718 if (m0 == 0) 719 return (0); 720 m0->m_pkthdr.rcvif = ifp; 721 m0->m_pkthdr.len = totlen; 722 len = MHLEN; 723 m = m0; 724 725 bp = sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 726 727 while (totlen > 0) { 728 if (totlen >= MINCLSIZE) { 729 MCLGET(m, M_DONTWAIT); 730 if ((m->m_flags & M_EXT) == 0) 731 goto bad; 732 len = MCLBYTES; 733 } 734 735 if (m == m0) { 736 caddr_t newdata = (caddr_t) 737 ALIGN(m->m_data + sizeof(struct ether_header)) - 738 sizeof(struct ether_header); 739 len -= newdata - m->m_data; 740 m->m_data = newdata; 741 } 742 743 m->m_len = len = min(totlen, len); 744 memcpy(mtod(m, caddr_t), bp, len); 745 bp += len; 746 747 totlen -= len; 748 if (totlen > 0) { 749 MGET(newm, M_DONTWAIT, MT_DATA); 750 if (newm == 0) 751 goto bad; 752 len = MLEN; 753 m = m->m_next = newm; 754 } 755 } 756 757 if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_TCPv4)) { 758 struct ether_header *eh; 759 struct ip *ip; 760 struct udphdr *uh; 761 uint16_t *opts; 762 int32_t hlen, pktlen; 763 uint32_t temp; 764 765 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 766 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN - 767 ETHER_VLAN_ENCAP_LEN; 768 eh = (struct ether_header *) mtod(m0, caddr_t) + 769 ETHER_VLAN_ENCAP_LEN; 770 } else { 771 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN; 772 eh = mtod(m0, struct ether_header *); 773 } 774 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 775 goto swcsum; 776 ip = (struct ip *) ((caddr_t) eh + ETHER_HDR_LEN); 777 778 /* IPv4 only */ 779 if (ip->ip_v != IPVERSION) 780 goto swcsum; 781 782 hlen = ip->ip_hl << 2; 783 if (hlen < sizeof(struct ip)) 784 goto swcsum; 785 786 /* too short, truncated, fragment */ 787 if ((ntohs(ip->ip_len) < hlen) || (ntohs(ip->ip_len) > pktlen) 788 || (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 789 goto swcsum; 790 791 switch (ip->ip_p) { 792 case IPPROTO_TCP: 793 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 794 goto swcsum; 795 if (pktlen < (hlen + sizeof(struct tcphdr))) 796 goto swcsum; 797 m0->m_pkthdr.csum_flags = M_CSUM_TCPv4; 798 break; 799 case IPPROTO_UDP: 800 if (! (ifp->if_csum_flags_rx & M_CSUM_UDPv4)) 801 goto swcsum; 802 if (pktlen < (hlen + sizeof(struct udphdr))) 803 goto swcsum; 804 uh = (struct udphdr *)((caddr_t)ip + hlen); 805 /* no checksum */ 806 if (uh->uh_sum == 0) 807 goto swcsum; 808 m0->m_pkthdr.csum_flags = M_CSUM_UDPv4; 809 break; 810 default: 811 goto swcsum; 812 } 813 814 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */ 815 m0->m_pkthdr.csum_data = (~flags) & HME_XD_RXCKSUM; 816 817 /* if the pkt had ip options, we have to deduct them */ 818 if (hlen > sizeof(struct ip)) { 819 uint32_t optsum; 820 821 optsum = 0; 822 temp = hlen - sizeof(struct ip); 823 opts = (uint16_t *) ((caddr_t) ip + sizeof(struct ip)); 824 825 while (temp > 1) { 826 optsum += ntohs(*opts++); 827 temp -= 2; 828 } 829 while (optsum >> 16) 830 optsum = (optsum >> 16) + (optsum & 0xffff); 831 832 /* Deduct the ip opts sum from the hwsum (rfc 1624). */ 833 m0->m_pkthdr.csum_data = ~((~m0->m_pkthdr.csum_data) - 834 ~optsum); 835 836 while (m0->m_pkthdr.csum_data >> 16) 837 m0->m_pkthdr.csum_data = 838 (m0->m_pkthdr.csum_data >> 16) + 839 (m0->m_pkthdr.csum_data & 0xffff); 840 } 841 842 m0->m_pkthdr.csum_flags |= M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 843 } 844 845 swcsum: 846 return (m0); 847 848 bad: 849 m_freem(m0); 850 return (0); 851 } 852 853 /* 854 * Pass a packet to the higher levels. 855 */ 856 void 857 hme_read(sc, ix, flags) 858 struct hme_softc *sc; 859 int ix; 860 u_int32_t flags; 861 { 862 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 863 struct mbuf *m; 864 int len; 865 866 len = HME_XD_DECODE_RSIZE(flags); 867 if (len <= sizeof(struct ether_header) || 868 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 869 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 870 ETHERMTU + sizeof(struct ether_header))) { 871 #ifdef HMEDEBUG 872 printf("%s: invalid packet size %d; dropping\n", 873 sc->sc_dev.dv_xname, len); 874 #endif 875 ifp->if_ierrors++; 876 return; 877 } 878 879 /* Pull packet off interface. */ 880 m = hme_get(sc, ix, flags); 881 if (m == 0) { 882 ifp->if_ierrors++; 883 return; 884 } 885 886 ifp->if_ipackets++; 887 888 #if NBPFILTER > 0 889 /* 890 * Check if there's a BPF listener on this interface. 891 * If so, hand off the raw packet to BPF. 892 */ 893 if (ifp->if_bpf) 894 bpf_mtap(ifp->if_bpf, m); 895 #endif 896 897 /* Pass the packet up. */ 898 (*ifp->if_input)(ifp, m); 899 } 900 901 void 902 hme_start(ifp) 903 struct ifnet *ifp; 904 { 905 struct hme_softc *sc = (struct hme_softc *)ifp->if_softc; 906 caddr_t txd = sc->sc_rb.rb_txd; 907 struct mbuf *m; 908 unsigned int txflags; 909 unsigned int ri, len; 910 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 911 912 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 913 return; 914 915 ri = sc->sc_rb.rb_tdhead; 916 917 for (;;) { 918 IFQ_DEQUEUE(&ifp->if_snd, m); 919 if (m == 0) 920 break; 921 922 #if NBPFILTER > 0 923 /* 924 * If BPF is listening on this interface, let it see the 925 * packet before we commit it to the wire. 926 */ 927 if (ifp->if_bpf) 928 bpf_mtap(ifp->if_bpf, m); 929 #endif 930 931 /* collect bits for h/w csum, before hme_put frees the mbuf */ 932 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) && 933 m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 934 struct ether_header *eh; 935 uint16_t offset, start; 936 937 eh = mtod(m, struct ether_header *); 938 switch (ntohs(eh->ether_type)) { 939 case ETHERTYPE_IP: 940 start = ETHER_HDR_LEN; 941 break; 942 case ETHERTYPE_VLAN: 943 start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 944 break; 945 default: 946 /* unsupported, drop it */ 947 m_free(m); 948 continue; 949 } 950 start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 951 offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data) 952 + start; 953 txflags = HME_XD_TXCKSUM | 954 (offset << HME_XD_TXCSSTUFFSHIFT) | 955 (start << HME_XD_TXCSSTARTSHIFT); 956 } else 957 txflags = 0; 958 959 /* 960 * Copy the mbuf chain into the transmit buffer. 961 */ 962 len = hme_put(sc, ri, m); 963 964 /* 965 * Initialize transmit registers and start transmission 966 */ 967 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 968 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 969 HME_XD_ENCODE_TSIZE(len) | txflags); 970 971 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 972 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 973 HME_ETX_TP_DMAWAKEUP); 974 975 if (++ri == ntbuf) 976 ri = 0; 977 978 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 979 ifp->if_flags |= IFF_OACTIVE; 980 break; 981 } 982 } 983 984 sc->sc_rb.rb_tdhead = ri; 985 } 986 987 /* 988 * Transmit interrupt. 989 */ 990 int 991 hme_tint(sc) 992 struct hme_softc *sc; 993 { 994 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 995 bus_space_tag_t t = sc->sc_bustag; 996 bus_space_handle_t mac = sc->sc_mac; 997 unsigned int ri, txflags; 998 999 /* 1000 * Unload collision counters 1001 */ 1002 ifp->if_collisions += 1003 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 1004 bus_space_read_4(t, mac, HME_MACI_FCCNT) + 1005 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 1006 bus_space_read_4(t, mac, HME_MACI_LTCNT); 1007 1008 /* 1009 * then clear the hardware counters. 1010 */ 1011 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 1012 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 1013 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 1014 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 1015 1016 /* Fetch current position in the transmit ring */ 1017 ri = sc->sc_rb.rb_tdtail; 1018 1019 for (;;) { 1020 if (sc->sc_rb.rb_td_nbusy <= 0) 1021 break; 1022 1023 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 1024 1025 if (txflags & HME_XD_OWN) 1026 break; 1027 1028 ifp->if_flags &= ~IFF_OACTIVE; 1029 ifp->if_opackets++; 1030 1031 if (++ri == sc->sc_rb.rb_ntbuf) 1032 ri = 0; 1033 1034 --sc->sc_rb.rb_td_nbusy; 1035 } 1036 1037 /* Update ring */ 1038 sc->sc_rb.rb_tdtail = ri; 1039 1040 hme_start(ifp); 1041 1042 if (sc->sc_rb.rb_td_nbusy == 0) 1043 ifp->if_timer = 0; 1044 1045 return (1); 1046 } 1047 1048 /* 1049 * Receive interrupt. 1050 */ 1051 int 1052 hme_rint(sc) 1053 struct hme_softc *sc; 1054 { 1055 caddr_t xdr = sc->sc_rb.rb_rxd; 1056 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 1057 unsigned int ri; 1058 u_int32_t flags; 1059 1060 ri = sc->sc_rb.rb_rdtail; 1061 1062 /* 1063 * Process all buffers with valid data. 1064 */ 1065 for (;;) { 1066 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 1067 if (flags & HME_XD_OWN) 1068 break; 1069 1070 if (flags & HME_XD_OFL) { 1071 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 1072 sc->sc_dev.dv_xname, ri, flags); 1073 } else 1074 hme_read(sc, ri, flags); 1075 1076 /* This buffer can be used by the hardware again */ 1077 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 1078 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 1079 1080 if (++ri == nrbuf) 1081 ri = 0; 1082 } 1083 1084 sc->sc_rb.rb_rdtail = ri; 1085 1086 return (1); 1087 } 1088 1089 int 1090 hme_eint(sc, status) 1091 struct hme_softc *sc; 1092 u_int status; 1093 { 1094 char bits[128]; 1095 1096 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 1097 bus_space_tag_t t = sc->sc_bustag; 1098 bus_space_handle_t mif = sc->sc_mif; 1099 u_int32_t cf, st, sm; 1100 cf = bus_space_read_4(t, mif, HME_MIFI_CFG); 1101 st = bus_space_read_4(t, mif, HME_MIFI_STAT); 1102 sm = bus_space_read_4(t, mif, HME_MIFI_SM); 1103 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n", 1104 sc->sc_dev.dv_xname, cf, st, sm); 1105 return (1); 1106 } 1107 1108 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1109 bitmask_snprintf(status, HME_SEB_STAT_BITS, bits,sizeof(bits))); 1110 return (1); 1111 } 1112 1113 int 1114 hme_intr(v) 1115 void *v; 1116 { 1117 struct hme_softc *sc = (struct hme_softc *)v; 1118 bus_space_tag_t t = sc->sc_bustag; 1119 bus_space_handle_t seb = sc->sc_seb; 1120 u_int32_t status; 1121 int r = 0; 1122 1123 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 1124 1125 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 1126 r |= hme_eint(sc, status); 1127 1128 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 1129 r |= hme_tint(sc); 1130 1131 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1132 r |= hme_rint(sc); 1133 1134 #if NRND > 0 1135 rnd_add_uint32(&sc->rnd_source, status); 1136 #endif 1137 1138 return (r); 1139 } 1140 1141 1142 void 1143 hme_watchdog(ifp) 1144 struct ifnet *ifp; 1145 { 1146 struct hme_softc *sc = ifp->if_softc; 1147 1148 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1149 ++ifp->if_oerrors; 1150 1151 hme_reset(sc); 1152 } 1153 1154 /* 1155 * Initialize the MII Management Interface 1156 */ 1157 void 1158 hme_mifinit(sc) 1159 struct hme_softc *sc; 1160 { 1161 bus_space_tag_t t = sc->sc_bustag; 1162 bus_space_handle_t mif = sc->sc_mif; 1163 bus_space_handle_t mac = sc->sc_mac; 1164 int instance, phy; 1165 u_int32_t v; 1166 1167 if (sc->sc_media.ifm_cur != NULL) { 1168 instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1169 phy = sc->sc_phys[instance]; 1170 } else 1171 /* No media set yet, pick phy arbitrarily.. */ 1172 phy = HME_PHYAD_EXTERNAL; 1173 1174 /* Configure the MIF in frame mode, no poll, current phy select */ 1175 v = 0; 1176 if (phy == HME_PHYAD_EXTERNAL) 1177 v |= HME_MIF_CFG_PHY; 1178 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1179 1180 /* If an external transceiver is selected, enable its MII drivers */ 1181 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1182 v &= ~HME_MAC_XIF_MIIENABLE; 1183 if (phy == HME_PHYAD_EXTERNAL) 1184 v |= HME_MAC_XIF_MIIENABLE; 1185 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1186 } 1187 1188 /* 1189 * MII interface 1190 */ 1191 static int 1192 hme_mii_readreg(self, phy, reg) 1193 struct device *self; 1194 int phy, reg; 1195 { 1196 struct hme_softc *sc = (void *)self; 1197 bus_space_tag_t t = sc->sc_bustag; 1198 bus_space_handle_t mif = sc->sc_mif; 1199 bus_space_handle_t mac = sc->sc_mac; 1200 u_int32_t v, xif_cfg, mifi_cfg; 1201 int n; 1202 1203 /* We can at most have two PHYs */ 1204 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1205 return (0); 1206 1207 /* Select the desired PHY in the MIF configuration register */ 1208 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1209 v &= ~HME_MIF_CFG_PHY; 1210 if (phy == HME_PHYAD_EXTERNAL) 1211 v |= HME_MIF_CFG_PHY; 1212 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1213 1214 /* Enable MII drivers on external transceiver */ 1215 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1216 if (phy == HME_PHYAD_EXTERNAL) 1217 v |= HME_MAC_XIF_MIIENABLE; 1218 else 1219 v &= ~HME_MAC_XIF_MIIENABLE; 1220 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1221 1222 #if 0 1223 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1224 /* 1225 * Check whether a transceiver is connected by testing 1226 * the MIF configuration register's MDI_X bits. Note that 1227 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1228 */ 1229 mif_mdi_bit = 1 << (8 + (1 - phy)); 1230 delay(100); 1231 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1232 if ((v & mif_mdi_bit) == 0) 1233 return (0); 1234 #endif 1235 1236 /* Construct the frame command */ 1237 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1238 HME_MIF_FO_TAMSB | 1239 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1240 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1241 (reg << HME_MIF_FO_REGAD_SHIFT); 1242 1243 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1244 for (n = 0; n < 100; n++) { 1245 DELAY(1); 1246 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1247 if (v & HME_MIF_FO_TALSB) { 1248 v &= HME_MIF_FO_DATA; 1249 goto out; 1250 } 1251 } 1252 1253 v = 0; 1254 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1255 1256 out: 1257 /* Restore MIFI_CFG register */ 1258 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1259 /* Restore XIF register */ 1260 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1261 return (v); 1262 } 1263 1264 static void 1265 hme_mii_writereg(self, phy, reg, val) 1266 struct device *self; 1267 int phy, reg, val; 1268 { 1269 struct hme_softc *sc = (void *)self; 1270 bus_space_tag_t t = sc->sc_bustag; 1271 bus_space_handle_t mif = sc->sc_mif; 1272 bus_space_handle_t mac = sc->sc_mac; 1273 u_int32_t v, xif_cfg, mifi_cfg; 1274 int n; 1275 1276 /* We can at most have two PHYs */ 1277 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1278 return; 1279 1280 /* Select the desired PHY in the MIF configuration register */ 1281 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1282 v &= ~HME_MIF_CFG_PHY; 1283 if (phy == HME_PHYAD_EXTERNAL) 1284 v |= HME_MIF_CFG_PHY; 1285 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1286 1287 /* Enable MII drivers on external transceiver */ 1288 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1289 if (phy == HME_PHYAD_EXTERNAL) 1290 v |= HME_MAC_XIF_MIIENABLE; 1291 else 1292 v &= ~HME_MAC_XIF_MIIENABLE; 1293 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1294 1295 #if 0 1296 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1297 /* 1298 * Check whether a transceiver is connected by testing 1299 * the MIF configuration register's MDI_X bits. Note that 1300 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1301 */ 1302 mif_mdi_bit = 1 << (8 + (1 - phy)); 1303 delay(100); 1304 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1305 if ((v & mif_mdi_bit) == 0) 1306 return; 1307 #endif 1308 1309 /* Construct the frame command */ 1310 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1311 HME_MIF_FO_TAMSB | 1312 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1313 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1314 (reg << HME_MIF_FO_REGAD_SHIFT) | 1315 (val & HME_MIF_FO_DATA); 1316 1317 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1318 for (n = 0; n < 100; n++) { 1319 DELAY(1); 1320 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1321 if (v & HME_MIF_FO_TALSB) 1322 goto out; 1323 } 1324 1325 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1326 out: 1327 /* Restore MIFI_CFG register */ 1328 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1329 /* Restore XIF register */ 1330 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1331 } 1332 1333 static void 1334 hme_mii_statchg(dev) 1335 struct device *dev; 1336 { 1337 struct hme_softc *sc = (void *)dev; 1338 bus_space_tag_t t = sc->sc_bustag; 1339 bus_space_handle_t mac = sc->sc_mac; 1340 u_int32_t v; 1341 1342 #ifdef HMEDEBUG 1343 if (sc->sc_debug) 1344 printf("hme_mii_statchg: status change\n"); 1345 #endif 1346 1347 /* Set the MAC Full Duplex bit appropriately */ 1348 /* Apparently the hme chip is SIMPLEX if working in full duplex mode, 1349 but not otherwise. */ 1350 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1351 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1352 v |= HME_MAC_TXCFG_FULLDPLX; 1353 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX; 1354 } else { 1355 v &= ~HME_MAC_TXCFG_FULLDPLX; 1356 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX; 1357 } 1358 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags; 1359 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1360 } 1361 1362 int 1363 hme_mediachange(ifp) 1364 struct ifnet *ifp; 1365 { 1366 struct hme_softc *sc = ifp->if_softc; 1367 bus_space_tag_t t = sc->sc_bustag; 1368 bus_space_handle_t mif = sc->sc_mif; 1369 bus_space_handle_t mac = sc->sc_mac; 1370 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1371 int phy = sc->sc_phys[instance]; 1372 u_int32_t v; 1373 1374 #ifdef HMEDEBUG 1375 if (sc->sc_debug) 1376 printf("hme_mediachange: phy = %d\n", phy); 1377 #endif 1378 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1379 return (EINVAL); 1380 1381 /* Select the current PHY in the MIF configuration register */ 1382 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1383 v &= ~HME_MIF_CFG_PHY; 1384 if (phy == HME_PHYAD_EXTERNAL) 1385 v |= HME_MIF_CFG_PHY; 1386 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1387 1388 /* If an external transceiver is selected, enable its MII drivers */ 1389 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1390 v &= ~HME_MAC_XIF_MIIENABLE; 1391 if (phy == HME_PHYAD_EXTERNAL) 1392 v |= HME_MAC_XIF_MIIENABLE; 1393 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1394 1395 return (mii_mediachg(&sc->sc_mii)); 1396 } 1397 1398 void 1399 hme_mediastatus(ifp, ifmr) 1400 struct ifnet *ifp; 1401 struct ifmediareq *ifmr; 1402 { 1403 struct hme_softc *sc = ifp->if_softc; 1404 1405 if ((ifp->if_flags & IFF_UP) == 0) 1406 return; 1407 1408 mii_pollstat(&sc->sc_mii); 1409 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1410 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1411 } 1412 1413 /* 1414 * Process an ioctl request. 1415 */ 1416 int 1417 hme_ioctl(ifp, cmd, data) 1418 struct ifnet *ifp; 1419 u_long cmd; 1420 caddr_t data; 1421 { 1422 struct hme_softc *sc = ifp->if_softc; 1423 struct ifaddr *ifa = (struct ifaddr *)data; 1424 struct ifreq *ifr = (struct ifreq *)data; 1425 int s, error = 0; 1426 1427 s = splnet(); 1428 1429 switch (cmd) { 1430 1431 case SIOCSIFADDR: 1432 switch (ifa->ifa_addr->sa_family) { 1433 #ifdef INET 1434 case AF_INET: 1435 if (ifp->if_flags & IFF_UP) 1436 hme_setladrf(sc); 1437 else { 1438 ifp->if_flags |= IFF_UP; 1439 hme_init(sc); 1440 } 1441 arp_ifinit(ifp, ifa); 1442 break; 1443 #endif 1444 #ifdef NS 1445 case AF_NS: 1446 { 1447 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1448 1449 if (ns_nullhost(*ina)) 1450 ina->x_host = 1451 *(union ns_host *)LLADDR(ifp->if_sadl); 1452 else { 1453 memcpy(LLADDR(ifp->if_sadl), 1454 ina->x_host.c_host, sizeof(sc->sc_enaddr)); 1455 } 1456 /* Set new address. */ 1457 if (ifp->if_flags & IFF_UP) 1458 hme_setladrf(sc); 1459 else { 1460 ifp->if_flags |= IFF_UP; 1461 hme_init(sc); 1462 } 1463 break; 1464 } 1465 #endif 1466 default: 1467 ifp->if_flags |= IFF_UP; 1468 hme_init(sc); 1469 break; 1470 } 1471 break; 1472 1473 case SIOCSIFFLAGS: 1474 #ifdef HMEDEBUG 1475 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1476 #endif 1477 1478 if ((ifp->if_flags & IFF_UP) == 0 && 1479 (ifp->if_flags & IFF_RUNNING) != 0) { 1480 /* 1481 * If interface is marked down and it is running, then 1482 * stop it. 1483 */ 1484 hme_stop(sc); 1485 ifp->if_flags &= ~IFF_RUNNING; 1486 } else if ((ifp->if_flags & IFF_UP) != 0 && 1487 (ifp->if_flags & IFF_RUNNING) == 0) { 1488 /* 1489 * If interface is marked up and it is stopped, then 1490 * start it. 1491 */ 1492 hme_init(sc); 1493 } else if ((ifp->if_flags & IFF_UP) != 0) { 1494 /* 1495 * If setting debug or promiscuous mode, do not reset 1496 * the chip; for everything else, call hme_init() 1497 * which will trigger a reset. 1498 */ 1499 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG) 1500 if (ifp->if_flags != sc->sc_if_flags) { 1501 if ((ifp->if_flags & (~RESETIGN)) 1502 == (sc->sc_if_flags & (~RESETIGN))) 1503 hme_setladrf(sc); 1504 else 1505 hme_init(sc); 1506 } 1507 #undef RESETIGN 1508 } 1509 1510 if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable) 1511 hme_init(sc); 1512 1513 break; 1514 1515 case SIOCADDMULTI: 1516 case SIOCDELMULTI: 1517 error = (cmd == SIOCADDMULTI) ? 1518 ether_addmulti(ifr, &sc->sc_ethercom) : 1519 ether_delmulti(ifr, &sc->sc_ethercom); 1520 1521 if (error == ENETRESET) { 1522 /* 1523 * Multicast list has changed; set the hardware filter 1524 * accordingly. 1525 */ 1526 if (ifp->if_flags & IFF_RUNNING) 1527 hme_setladrf(sc); 1528 error = 0; 1529 } 1530 break; 1531 1532 case SIOCGIFMEDIA: 1533 case SIOCSIFMEDIA: 1534 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1535 break; 1536 1537 default: 1538 error = EINVAL; 1539 break; 1540 } 1541 1542 sc->sc_if_flags = ifp->if_flags; 1543 splx(s); 1544 return (error); 1545 } 1546 1547 void 1548 hme_shutdown(arg) 1549 void *arg; 1550 { 1551 1552 hme_stop((struct hme_softc *)arg); 1553 } 1554 1555 /* 1556 * Set up the logical address filter. 1557 */ 1558 void 1559 hme_setladrf(sc) 1560 struct hme_softc *sc; 1561 { 1562 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1563 struct ether_multi *enm; 1564 struct ether_multistep step; 1565 struct ethercom *ec = &sc->sc_ethercom; 1566 bus_space_tag_t t = sc->sc_bustag; 1567 bus_space_handle_t mac = sc->sc_mac; 1568 u_char *cp; 1569 u_int32_t crc; 1570 u_int32_t hash[4]; 1571 u_int32_t v; 1572 int len; 1573 1574 /* Clear hash table */ 1575 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1576 1577 /* Get current RX configuration */ 1578 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1579 1580 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1581 /* Turn on promiscuous mode; turn off the hash filter */ 1582 v |= HME_MAC_RXCFG_PMISC; 1583 v &= ~HME_MAC_RXCFG_HENABLE; 1584 ifp->if_flags |= IFF_ALLMULTI; 1585 goto chipit; 1586 } 1587 1588 /* Turn off promiscuous mode; turn on the hash filter */ 1589 v &= ~HME_MAC_RXCFG_PMISC; 1590 v |= HME_MAC_RXCFG_HENABLE; 1591 1592 /* 1593 * Set up multicast address filter by passing all multicast addresses 1594 * through a crc generator, and then using the high order 6 bits as an 1595 * index into the 64 bit logical address filter. The high order bit 1596 * selects the word, while the rest of the bits select the bit within 1597 * the word. 1598 */ 1599 1600 ETHER_FIRST_MULTI(step, ec, enm); 1601 while (enm != NULL) { 1602 if (ether_cmp(enm->enm_addrlo, enm->enm_addrhi)) { 1603 /* 1604 * We must listen to a range of multicast addresses. 1605 * For now, just accept all multicasts, rather than 1606 * trying to set only those filter bits needed to match 1607 * the range. (At this time, the only use of address 1608 * ranges is for IP multicast routing, for which the 1609 * range is big enough to require all bits set.) 1610 */ 1611 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1612 ifp->if_flags |= IFF_ALLMULTI; 1613 goto chipit; 1614 } 1615 1616 cp = enm->enm_addrlo; 1617 crc = 0xffffffff; 1618 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1619 int octet = *cp++; 1620 int i; 1621 1622 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1623 for (i = 0; i < 8; i++) { 1624 if ((crc & 1) ^ (octet & 1)) { 1625 crc >>= 1; 1626 crc ^= MC_POLY_LE; 1627 } else { 1628 crc >>= 1; 1629 } 1630 octet >>= 1; 1631 } 1632 } 1633 /* Just want the 6 most significant bits. */ 1634 crc >>= 26; 1635 1636 /* Set the corresponding bit in the filter. */ 1637 hash[crc >> 4] |= 1 << (crc & 0xf); 1638 1639 ETHER_NEXT_MULTI(step, enm); 1640 } 1641 1642 ifp->if_flags &= ~IFF_ALLMULTI; 1643 1644 chipit: 1645 /* Now load the hash table into the chip */ 1646 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1647 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1648 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1649 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1650 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1651 } 1652 1653 /* 1654 * Routines for accessing the transmit and receive buffers. 1655 * The various CPU and adapter configurations supported by this 1656 * driver require three different access methods for buffers 1657 * and descriptors: 1658 * (1) contig (contiguous data; no padding), 1659 * (2) gap2 (two bytes of data followed by two bytes of padding), 1660 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1661 */ 1662 1663 #if 0 1664 /* 1665 * contig: contiguous data with no padding. 1666 * 1667 * Buffers may have any alignment. 1668 */ 1669 1670 void 1671 hme_copytobuf_contig(sc, from, ri, len) 1672 struct hme_softc *sc; 1673 void *from; 1674 int ri, len; 1675 { 1676 volatile caddr_t buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1677 1678 /* 1679 * Just call memcpy() to do the work. 1680 */ 1681 memcpy(buf, from, len); 1682 } 1683 1684 void 1685 hme_copyfrombuf_contig(sc, to, boff, len) 1686 struct hme_softc *sc; 1687 void *to; 1688 int boff, len; 1689 { 1690 volatile caddr_t buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1691 1692 /* 1693 * Just call memcpy() to do the work. 1694 */ 1695 memcpy(to, buf, len); 1696 } 1697 #endif 1698