1 /* $NetBSD: hme.c,v 1.79 2009/05/17 00:40:43 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * HME Ethernet module driver. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.79 2009/05/17 00:40:43 tsutsui Exp $"); 38 39 /* #define HMEDEBUG */ 40 41 #include "opt_inet.h" 42 #include "bpfilter.h" 43 #include "rnd.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/mbuf.h> 49 #include <sys/syslog.h> 50 #include <sys/socket.h> 51 #include <sys/device.h> 52 #include <sys/malloc.h> 53 #include <sys/ioctl.h> 54 #include <sys/errno.h> 55 #if NRND > 0 56 #include <sys/rnd.h> 57 #endif 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_ether.h> 62 #include <net/if_media.h> 63 64 #ifdef INET 65 #include <net/if_vlanvar.h> 66 #include <netinet/in.h> 67 #include <netinet/if_inarp.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/ip.h> 71 #include <netinet/tcp.h> 72 #include <netinet/udp.h> 73 #endif 74 75 76 #if NBPFILTER > 0 77 #include <net/bpf.h> 78 #include <net/bpfdesc.h> 79 #endif 80 81 #include <dev/mii/mii.h> 82 #include <dev/mii/miivar.h> 83 84 #include <sys/bus.h> 85 86 #include <dev/ic/hmereg.h> 87 #include <dev/ic/hmevar.h> 88 89 void hme_start(struct ifnet *); 90 void hme_stop(struct hme_softc *,bool); 91 int hme_ioctl(struct ifnet *, u_long, void *); 92 void hme_tick(void *); 93 void hme_watchdog(struct ifnet *); 94 void hme_shutdown(void *); 95 int hme_init(struct hme_softc *); 96 void hme_meminit(struct hme_softc *); 97 void hme_mifinit(struct hme_softc *); 98 void hme_reset(struct hme_softc *); 99 void hme_setladrf(struct hme_softc *); 100 101 /* MII methods & callbacks */ 102 static int hme_mii_readreg(device_t, int, int); 103 static void hme_mii_writereg(device_t, int, int, int); 104 static void hme_mii_statchg(device_t); 105 106 int hme_mediachange(struct ifnet *); 107 108 struct mbuf *hme_get(struct hme_softc *, int, uint32_t); 109 int hme_put(struct hme_softc *, int, struct mbuf *); 110 void hme_read(struct hme_softc *, int, uint32_t); 111 int hme_eint(struct hme_softc *, u_int); 112 int hme_rint(struct hme_softc *); 113 int hme_tint(struct hme_softc *); 114 115 /* Default buffer copy routines */ 116 void hme_copytobuf_contig(struct hme_softc *, void *, int, int); 117 void hme_copyfrombuf_contig(struct hme_softc *, void *, int, int); 118 void hme_zerobuf_contig(struct hme_softc *, int, int); 119 120 121 void 122 hme_config(struct hme_softc *sc) 123 { 124 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 125 struct mii_data *mii = &sc->sc_mii; 126 struct mii_softc *child; 127 bus_dma_tag_t dmatag = sc->sc_dmatag; 128 bus_dma_segment_t seg; 129 bus_size_t size; 130 int rseg, error; 131 132 /* 133 * HME common initialization. 134 * 135 * hme_softc fields that must be initialized by the front-end: 136 * 137 * the bus tag: 138 * sc_bustag 139 * 140 * the DMA bus tag: 141 * sc_dmatag 142 * 143 * the bus handles: 144 * sc_seb (Shared Ethernet Block registers) 145 * sc_erx (Receiver Unit registers) 146 * sc_etx (Transmitter Unit registers) 147 * sc_mac (MAC registers) 148 * sc_mif (Management Interface registers) 149 * 150 * the maximum bus burst size: 151 * sc_burst 152 * 153 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 154 * rb_membase, rb_dmabase) 155 * 156 * the local Ethernet address: 157 * sc_enaddr 158 * 159 */ 160 161 /* Make sure the chip is stopped. */ 162 hme_stop(sc, true); 163 164 165 /* 166 * Allocate descriptors and buffers 167 * XXX - do all this differently.. and more configurably, 168 * eg. use things as `dma_load_mbuf()' on transmit, 169 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 170 * all the time) on the receiver side. 171 * 172 * Note: receive buffers must be 64-byte aligned. 173 * Also, apparently, the buffers must extend to a DMA burst 174 * boundary beyond the maximum packet size. 175 */ 176 #define _HME_NDESC 128 177 #define _HME_BUFSZ 1600 178 179 /* Note: the # of descriptors must be a multiple of 16 */ 180 sc->sc_rb.rb_ntbuf = _HME_NDESC; 181 sc->sc_rb.rb_nrbuf = _HME_NDESC; 182 183 /* 184 * Allocate DMA capable memory 185 * Buffer descriptors must be aligned on a 2048 byte boundary; 186 * take this into account when calculating the size. Note that 187 * the maximum number of descriptors (256) occupies 2048 bytes, 188 * so we allocate that much regardless of _HME_NDESC. 189 */ 190 size = 2048 + /* TX descriptors */ 191 2048 + /* RX descriptors */ 192 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 193 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* RX buffers */ 194 195 /* Allocate DMA buffer */ 196 if ((error = bus_dmamem_alloc(dmatag, size, 197 2048, 0, 198 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 199 aprint_error_dev(sc->sc_dev, "DMA buffer alloc error %d\n", 200 error); 201 return; 202 } 203 204 /* Map DMA memory in CPU addressable space */ 205 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 206 &sc->sc_rb.rb_membase, 207 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 208 aprint_error_dev(sc->sc_dev, "DMA buffer map error %d\n", 209 error); 210 bus_dmamap_unload(dmatag, sc->sc_dmamap); 211 bus_dmamem_free(dmatag, &seg, rseg); 212 return; 213 } 214 215 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 216 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 217 aprint_error_dev(sc->sc_dev, "DMA map create error %d\n", 218 error); 219 return; 220 } 221 222 /* Load the buffer */ 223 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 224 sc->sc_rb.rb_membase, size, NULL, 225 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 226 aprint_error_dev(sc->sc_dev, "DMA buffer map load error %d\n", 227 error); 228 bus_dmamem_free(dmatag, &seg, rseg); 229 return; 230 } 231 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 232 233 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 234 ether_sprintf(sc->sc_enaddr)); 235 236 /* Initialize ifnet structure. */ 237 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 238 ifp->if_softc = sc; 239 ifp->if_start = hme_start; 240 ifp->if_ioctl = hme_ioctl; 241 ifp->if_watchdog = hme_watchdog; 242 ifp->if_flags = 243 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 244 sc->sc_if_flags = ifp->if_flags; 245 ifp->if_capabilities |= 246 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 247 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 248 IFQ_SET_READY(&ifp->if_snd); 249 250 /* Initialize ifmedia structures and MII info */ 251 mii->mii_ifp = ifp; 252 mii->mii_readreg = hme_mii_readreg; 253 mii->mii_writereg = hme_mii_writereg; 254 mii->mii_statchg = hme_mii_statchg; 255 256 sc->sc_ethercom.ec_mii = mii; 257 ifmedia_init(&mii->mii_media, 0, hme_mediachange, ether_mediastatus); 258 259 hme_mifinit(sc); 260 261 /* 262 * Some HME's have an MII connector, as well as RJ45. Try attaching 263 * the RJ45 (internal) PHY first, so that the MII PHY is always 264 * instance 1. 265 */ 266 mii_attach(sc->sc_dev, mii, 0xffffffff, 267 HME_PHYAD_INTERNAL, MII_OFFSET_ANY, MIIF_FORCEANEG); 268 mii_attach(sc->sc_dev, mii, 0xffffffff, 269 HME_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_FORCEANEG); 270 271 child = LIST_FIRST(&mii->mii_phys); 272 if (child == NULL) { 273 /* No PHY attached */ 274 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 275 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 276 } else { 277 /* 278 * Walk along the list of attached MII devices and 279 * establish an `MII instance' to `phy number' 280 * mapping. We'll use this mapping in media change 281 * requests to determine which phy to use to program 282 * the MIF configuration register. 283 */ 284 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 285 /* 286 * Note: we support just two PHYs: the built-in 287 * internal device and an external on the MII 288 * connector. 289 */ 290 if (child->mii_phy > 1 || child->mii_inst > 1) { 291 aprint_error_dev(sc->sc_dev, 292 "cannot accommodate MII device %s" 293 " at phy %d, instance %d\n", 294 device_xname(child->mii_dev), 295 child->mii_phy, child->mii_inst); 296 continue; 297 } 298 299 sc->sc_phys[child->mii_inst] = child->mii_phy; 300 } 301 302 /* 303 * Set the default media to auto negotiation if the phy has 304 * the auto negotiation capability. 305 * XXX; What to do otherwise? 306 */ 307 if (ifmedia_match(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0)) 308 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 309 /* 310 else 311 ifmedia_set(&sc->sc_mii.mii_media, sc->sc_defaultmedia); 312 */ 313 } 314 315 /* claim 802.1q capability */ 316 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 317 318 /* Attach the interface. */ 319 if_attach(ifp); 320 ether_ifattach(ifp, sc->sc_enaddr); 321 322 sc->sc_sh = shutdownhook_establish(hme_shutdown, sc); 323 if (sc->sc_sh == NULL) 324 panic("hme_config: can't establish shutdownhook"); 325 326 #if NRND > 0 327 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 328 RND_TYPE_NET, 0); 329 #endif 330 331 callout_init(&sc->sc_tick_ch, 0); 332 } 333 334 void 335 hme_tick(void *arg) 336 { 337 struct hme_softc *sc = arg; 338 int s; 339 340 s = splnet(); 341 mii_tick(&sc->sc_mii); 342 splx(s); 343 344 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 345 } 346 347 void 348 hme_reset(struct hme_softc *sc) 349 { 350 int s; 351 352 s = splnet(); 353 (void)hme_init(sc); 354 splx(s); 355 } 356 357 void 358 hme_stop(struct hme_softc *sc, bool chip_only) 359 { 360 bus_space_tag_t t = sc->sc_bustag; 361 bus_space_handle_t seb = sc->sc_seb; 362 int n; 363 364 if (!chip_only) { 365 callout_stop(&sc->sc_tick_ch); 366 mii_down(&sc->sc_mii); 367 } 368 369 /* Mask all interrupts */ 370 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff); 371 372 /* Reset transmitter and receiver */ 373 bus_space_write_4(t, seb, HME_SEBI_RESET, 374 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 375 376 for (n = 0; n < 20; n++) { 377 uint32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 378 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 379 return; 380 DELAY(20); 381 } 382 383 printf("%s: hme_stop: reset failed\n", device_xname(sc->sc_dev)); 384 } 385 386 void 387 hme_meminit(struct hme_softc *sc) 388 { 389 bus_addr_t txbufdma, rxbufdma; 390 bus_addr_t dma; 391 char *p; 392 unsigned int ntbuf, nrbuf, i; 393 struct hme_ring *hr = &sc->sc_rb; 394 395 p = hr->rb_membase; 396 dma = hr->rb_dmabase; 397 398 ntbuf = hr->rb_ntbuf; 399 nrbuf = hr->rb_nrbuf; 400 401 /* 402 * Allocate transmit descriptors 403 */ 404 hr->rb_txd = p; 405 hr->rb_txddma = dma; 406 p += ntbuf * HME_XD_SIZE; 407 dma += ntbuf * HME_XD_SIZE; 408 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 409 dma = (bus_addr_t)roundup((u_long)dma, 2048); 410 p = (void *)roundup((u_long)p, 2048); 411 412 /* 413 * Allocate receive descriptors 414 */ 415 hr->rb_rxd = p; 416 hr->rb_rxddma = dma; 417 p += nrbuf * HME_XD_SIZE; 418 dma += nrbuf * HME_XD_SIZE; 419 /* Again move forward to the next 2048 byte boundary.*/ 420 dma = (bus_addr_t)roundup((u_long)dma, 2048); 421 p = (void *)roundup((u_long)p, 2048); 422 423 424 /* 425 * Allocate transmit buffers 426 */ 427 hr->rb_txbuf = p; 428 txbufdma = dma; 429 p += ntbuf * _HME_BUFSZ; 430 dma += ntbuf * _HME_BUFSZ; 431 432 /* 433 * Allocate receive buffers 434 */ 435 hr->rb_rxbuf = p; 436 rxbufdma = dma; 437 p += nrbuf * _HME_BUFSZ; 438 dma += nrbuf * _HME_BUFSZ; 439 440 /* 441 * Initialize transmit buffer descriptors 442 */ 443 for (i = 0; i < ntbuf; i++) { 444 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 445 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 446 } 447 448 /* 449 * Initialize receive buffer descriptors 450 */ 451 for (i = 0; i < nrbuf; i++) { 452 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 453 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 454 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 455 } 456 457 hr->rb_tdhead = hr->rb_tdtail = 0; 458 hr->rb_td_nbusy = 0; 459 hr->rb_rdtail = 0; 460 } 461 462 /* 463 * Initialization of interface; set up initialization block 464 * and transmit/receive descriptor rings. 465 */ 466 int 467 hme_init(struct hme_softc *sc) 468 { 469 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 470 bus_space_tag_t t = sc->sc_bustag; 471 bus_space_handle_t seb = sc->sc_seb; 472 bus_space_handle_t etx = sc->sc_etx; 473 bus_space_handle_t erx = sc->sc_erx; 474 bus_space_handle_t mac = sc->sc_mac; 475 uint8_t *ea; 476 uint32_t v; 477 int rc; 478 479 /* 480 * Initialization sequence. The numbered steps below correspond 481 * to the sequence outlined in section 6.3.5.1 in the Ethernet 482 * Channel Engine manual (part of the PCIO manual). 483 * See also the STP2002-STQ document from Sun Microsystems. 484 */ 485 486 /* step 1 & 2. Reset the Ethernet Channel */ 487 hme_stop(sc, false); 488 489 /* Re-initialize the MIF */ 490 hme_mifinit(sc); 491 492 /* Call MI reset function if any */ 493 if (sc->sc_hwreset) 494 (*sc->sc_hwreset)(sc); 495 496 #if 0 497 /* Mask all MIF interrupts, just in case */ 498 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 499 #endif 500 501 /* step 3. Setup data structures in host memory */ 502 hme_meminit(sc); 503 504 /* step 4. TX MAC registers & counters */ 505 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 506 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 507 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 508 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 509 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 510 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 511 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 512 sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable; 513 514 /* Load station MAC address */ 515 ea = sc->sc_enaddr; 516 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 517 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 518 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 519 520 /* 521 * Init seed for backoff 522 * (source suggested by manual: low 10 bits of MAC address) 523 */ 524 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 525 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 526 527 528 /* Note: Accepting power-on default for other MAC registers here.. */ 529 530 531 /* step 5. RX MAC registers & counters */ 532 hme_setladrf(sc); 533 534 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 535 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 536 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 537 538 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 539 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 540 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 541 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 542 543 /* step 8. Global Configuration & Interrupt Mask */ 544 bus_space_write_4(t, seb, HME_SEBI_IMASK, 545 ~( 546 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 547 HME_SEB_STAT_HOSTTOTX | 548 HME_SEB_STAT_RXTOHOST | 549 HME_SEB_STAT_TXALL | 550 HME_SEB_STAT_TXPERR | 551 HME_SEB_STAT_RCNTEXP | 552 HME_SEB_STAT_MIFIRQ | 553 HME_SEB_STAT_ALL_ERRORS )); 554 555 switch (sc->sc_burst) { 556 default: 557 v = 0; 558 break; 559 case 16: 560 v = HME_SEB_CFG_BURST16; 561 break; 562 case 32: 563 v = HME_SEB_CFG_BURST32; 564 break; 565 case 64: 566 v = HME_SEB_CFG_BURST64; 567 break; 568 } 569 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 570 571 /* step 9. ETX Configuration: use mostly default values */ 572 573 /* Enable DMA */ 574 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 575 v |= HME_ETX_CFG_DMAENABLE; 576 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 577 578 /* Transmit Descriptor ring size: in increments of 16 */ 579 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 580 581 582 /* step 10. ERX Configuration */ 583 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 584 585 /* Encode Receive Descriptor ring size: four possible values */ 586 switch (_HME_NDESC /*XXX*/) { 587 case 32: 588 v |= HME_ERX_CFG_RINGSIZE32; 589 break; 590 case 64: 591 v |= HME_ERX_CFG_RINGSIZE64; 592 break; 593 case 128: 594 v |= HME_ERX_CFG_RINGSIZE128; 595 break; 596 case 256: 597 v |= HME_ERX_CFG_RINGSIZE256; 598 break; 599 default: 600 printf("hme: invalid Receive Descriptor ring size\n"); 601 break; 602 } 603 604 /* Enable DMA */ 605 v |= HME_ERX_CFG_DMAENABLE; 606 607 /* set h/w rx checksum start offset (# of half-words) */ 608 #ifdef INET 609 v |= (((ETHER_HDR_LEN + sizeof(struct ip)) / sizeof(uint16_t)) 610 << HME_ERX_CFG_CSUMSHIFT) & 611 HME_ERX_CFG_CSUMSTART; 612 #endif 613 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 614 615 /* step 11. XIF Configuration */ 616 v = bus_space_read_4(t, mac, HME_MACI_XIF); 617 v |= HME_MAC_XIF_OE; 618 bus_space_write_4(t, mac, HME_MACI_XIF, v); 619 620 /* step 12. RX_MAC Configuration Register */ 621 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 622 v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP; 623 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 624 625 /* step 13. TX_MAC Configuration Register */ 626 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 627 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 628 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 629 630 /* step 14. Issue Transmit Pending command */ 631 632 /* Call MI initialization function if any */ 633 if (sc->sc_hwinit) 634 (*sc->sc_hwinit)(sc); 635 636 /* Set the current media. */ 637 if ((rc = hme_mediachange(ifp)) != 0) 638 return rc; 639 640 /* Start the one second timer. */ 641 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 642 643 ifp->if_flags |= IFF_RUNNING; 644 ifp->if_flags &= ~IFF_OACTIVE; 645 sc->sc_if_flags = ifp->if_flags; 646 ifp->if_timer = 0; 647 hme_start(ifp); 648 return 0; 649 } 650 651 /* 652 * Routine to copy from mbuf chain to transmit buffer in 653 * network buffer memory. 654 * Returns the amount of data copied. 655 */ 656 int 657 hme_put(struct hme_softc *sc, int ri, struct mbuf *m) 658 /* ri: Ring index */ 659 { 660 struct mbuf *n; 661 int len, tlen = 0; 662 char *bp; 663 664 bp = (char *)sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 665 for (; m; m = n) { 666 len = m->m_len; 667 if (len == 0) { 668 MFREE(m, n); 669 continue; 670 } 671 memcpy(bp, mtod(m, void *), len); 672 bp += len; 673 tlen += len; 674 MFREE(m, n); 675 } 676 return (tlen); 677 } 678 679 /* 680 * Pull data off an interface. 681 * Len is length of data, with local net header stripped. 682 * We copy the data into mbufs. When full cluster sized units are present 683 * we copy into clusters. 684 */ 685 struct mbuf * 686 hme_get(struct hme_softc *sc, int ri, uint32_t flags) 687 { 688 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 689 struct mbuf *m, *m0, *newm; 690 char *bp; 691 int len, totlen; 692 #ifdef INET 693 int csum_flags; 694 #endif 695 696 totlen = HME_XD_DECODE_RSIZE(flags); 697 MGETHDR(m0, M_DONTWAIT, MT_DATA); 698 if (m0 == 0) 699 return (0); 700 m0->m_pkthdr.rcvif = ifp; 701 m0->m_pkthdr.len = totlen; 702 len = MHLEN; 703 m = m0; 704 705 bp = (char *)sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 706 707 while (totlen > 0) { 708 if (totlen >= MINCLSIZE) { 709 MCLGET(m, M_DONTWAIT); 710 if ((m->m_flags & M_EXT) == 0) 711 goto bad; 712 len = MCLBYTES; 713 } 714 715 if (m == m0) { 716 char *newdata = (char *) 717 ALIGN(m->m_data + sizeof(struct ether_header)) - 718 sizeof(struct ether_header); 719 len -= newdata - m->m_data; 720 m->m_data = newdata; 721 } 722 723 m->m_len = len = min(totlen, len); 724 memcpy(mtod(m, void *), bp, len); 725 bp += len; 726 727 totlen -= len; 728 if (totlen > 0) { 729 MGET(newm, M_DONTWAIT, MT_DATA); 730 if (newm == 0) 731 goto bad; 732 len = MLEN; 733 m = m->m_next = newm; 734 } 735 } 736 737 #ifdef INET 738 /* hardware checksum */ 739 csum_flags = 0; 740 if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 741 struct ether_header *eh; 742 struct ether_vlan_header *evh; 743 struct ip *ip; 744 struct udphdr *uh; 745 uint16_t *opts; 746 int32_t hlen, pktlen; 747 uint32_t csum_data; 748 749 eh = mtod(m0, struct ether_header *); 750 if (ntohs(eh->ether_type) == ETHERTYPE_IP) { 751 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN); 752 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN; 753 } else if (ntohs(eh->ether_type) == ETHERTYPE_VLAN) { 754 evh = (struct ether_vlan_header *)eh; 755 if (ntohs(evh->evl_proto != ETHERTYPE_IP)) 756 goto swcsum; 757 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN + 758 ETHER_VLAN_ENCAP_LEN); 759 pktlen = m0->m_pkthdr.len - 760 ETHER_HDR_LEN - ETHER_VLAN_ENCAP_LEN; 761 } else 762 goto swcsum; 763 764 /* IPv4 only */ 765 if (ip->ip_v != IPVERSION) 766 goto swcsum; 767 768 hlen = ip->ip_hl << 2; 769 if (hlen < sizeof(struct ip)) 770 goto swcsum; 771 772 /* 773 * bail if too short, has random trailing garbage, truncated, 774 * fragment, or has ethernet pad. 775 */ 776 if (ntohs(ip->ip_len) < hlen || 777 ntohs(ip->ip_len) != pktlen || 778 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 779 goto swcsum; 780 781 switch (ip->ip_p) { 782 case IPPROTO_TCP: 783 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0) 784 goto swcsum; 785 if (pktlen < (hlen + sizeof(struct tcphdr))) 786 goto swcsum; 787 csum_flags = 788 M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 789 break; 790 case IPPROTO_UDP: 791 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0) 792 goto swcsum; 793 if (pktlen < (hlen + sizeof(struct udphdr))) 794 goto swcsum; 795 uh = (struct udphdr *)((char *)ip + hlen); 796 /* no checksum */ 797 if (uh->uh_sum == 0) 798 goto swcsum; 799 csum_flags = 800 M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 801 break; 802 default: 803 goto swcsum; 804 } 805 806 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */ 807 csum_data = ~flags & HME_XD_RXCKSUM; 808 809 /* 810 * If data offset is different from RX cksum start offset, 811 * we have to deduct them. 812 */ 813 hlen = ((char *)ip + hlen) - 814 ((char *)eh + ETHER_HDR_LEN + sizeof(struct ip)); 815 if (hlen > 1) { 816 uint32_t optsum; 817 818 optsum = 0; 819 opts = (uint16_t *)((char *)eh + 820 ETHER_HDR_LEN + sizeof(struct ip)); 821 822 while (hlen > 1) { 823 optsum += ntohs(*opts++); 824 hlen -= 2; 825 } 826 while (optsum >> 16) 827 optsum = (optsum >> 16) + (optsum & 0xffff); 828 829 /* Deduct the ip opts sum from the hwsum. */ 830 csum_data += (uint16_t)~optsum; 831 832 while (csum_data >> 16) 833 csum_data = 834 (csum_data >> 16) + (csum_data & 0xffff); 835 } 836 m0->m_pkthdr.csum_data = csum_data; 837 } 838 swcsum: 839 m0->m_pkthdr.csum_flags = csum_flags; 840 #endif 841 842 return (m0); 843 844 bad: 845 m_freem(m0); 846 return (0); 847 } 848 849 /* 850 * Pass a packet to the higher levels. 851 */ 852 void 853 hme_read(struct hme_softc *sc, int ix, uint32_t flags) 854 { 855 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 856 struct mbuf *m; 857 int len; 858 859 len = HME_XD_DECODE_RSIZE(flags); 860 if (len <= sizeof(struct ether_header) || 861 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 862 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 863 ETHERMTU + sizeof(struct ether_header))) { 864 #ifdef HMEDEBUG 865 printf("%s: invalid packet size %d; dropping\n", 866 device_xname(sc->sc_dev), len); 867 #endif 868 ifp->if_ierrors++; 869 return; 870 } 871 872 /* Pull packet off interface. */ 873 m = hme_get(sc, ix, flags); 874 if (m == 0) { 875 ifp->if_ierrors++; 876 return; 877 } 878 879 ifp->if_ipackets++; 880 881 #if NBPFILTER > 0 882 /* 883 * Check if there's a BPF listener on this interface. 884 * If so, hand off the raw packet to BPF. 885 */ 886 if (ifp->if_bpf) 887 bpf_mtap(ifp->if_bpf, m); 888 #endif 889 890 /* Pass the packet up. */ 891 (*ifp->if_input)(ifp, m); 892 } 893 894 void 895 hme_start(struct ifnet *ifp) 896 { 897 struct hme_softc *sc = ifp->if_softc; 898 void *txd = sc->sc_rb.rb_txd; 899 struct mbuf *m; 900 unsigned int txflags; 901 unsigned int ri, len; 902 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 903 904 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 905 return; 906 907 ri = sc->sc_rb.rb_tdhead; 908 909 for (;;) { 910 IFQ_DEQUEUE(&ifp->if_snd, m); 911 if (m == 0) 912 break; 913 914 #if NBPFILTER > 0 915 /* 916 * If BPF is listening on this interface, let it see the 917 * packet before we commit it to the wire. 918 */ 919 if (ifp->if_bpf) 920 bpf_mtap(ifp->if_bpf, m); 921 #endif 922 923 #ifdef INET 924 /* collect bits for h/w csum, before hme_put frees the mbuf */ 925 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) && 926 m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 927 struct ether_header *eh; 928 uint16_t offset, start; 929 930 eh = mtod(m, struct ether_header *); 931 switch (ntohs(eh->ether_type)) { 932 case ETHERTYPE_IP: 933 start = ETHER_HDR_LEN; 934 break; 935 case ETHERTYPE_VLAN: 936 start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 937 break; 938 default: 939 /* unsupported, drop it */ 940 m_free(m); 941 continue; 942 } 943 start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 944 offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data) 945 + start; 946 txflags = HME_XD_TXCKSUM | 947 (offset << HME_XD_TXCSSTUFFSHIFT) | 948 (start << HME_XD_TXCSSTARTSHIFT); 949 } else 950 #endif 951 txflags = 0; 952 953 /* 954 * Copy the mbuf chain into the transmit buffer. 955 */ 956 len = hme_put(sc, ri, m); 957 958 /* 959 * Initialize transmit registers and start transmission 960 */ 961 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 962 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 963 HME_XD_ENCODE_TSIZE(len) | txflags); 964 965 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 966 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 967 HME_ETX_TP_DMAWAKEUP); 968 969 if (++ri == ntbuf) 970 ri = 0; 971 972 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 973 ifp->if_flags |= IFF_OACTIVE; 974 break; 975 } 976 } 977 978 sc->sc_rb.rb_tdhead = ri; 979 } 980 981 /* 982 * Transmit interrupt. 983 */ 984 int 985 hme_tint(struct hme_softc *sc) 986 { 987 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 988 bus_space_tag_t t = sc->sc_bustag; 989 bus_space_handle_t mac = sc->sc_mac; 990 unsigned int ri, txflags; 991 992 /* 993 * Unload collision counters 994 */ 995 ifp->if_collisions += 996 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 997 bus_space_read_4(t, mac, HME_MACI_FCCNT); 998 ifp->if_oerrors += 999 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 1000 bus_space_read_4(t, mac, HME_MACI_LTCNT); 1001 1002 /* 1003 * then clear the hardware counters. 1004 */ 1005 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 1006 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 1007 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 1008 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 1009 1010 /* Fetch current position in the transmit ring */ 1011 ri = sc->sc_rb.rb_tdtail; 1012 1013 for (;;) { 1014 if (sc->sc_rb.rb_td_nbusy <= 0) 1015 break; 1016 1017 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 1018 1019 if (txflags & HME_XD_OWN) 1020 break; 1021 1022 ifp->if_flags &= ~IFF_OACTIVE; 1023 ifp->if_opackets++; 1024 1025 if (++ri == sc->sc_rb.rb_ntbuf) 1026 ri = 0; 1027 1028 --sc->sc_rb.rb_td_nbusy; 1029 } 1030 1031 /* Update ring */ 1032 sc->sc_rb.rb_tdtail = ri; 1033 1034 hme_start(ifp); 1035 1036 if (sc->sc_rb.rb_td_nbusy == 0) 1037 ifp->if_timer = 0; 1038 1039 return (1); 1040 } 1041 1042 /* 1043 * Receive interrupt. 1044 */ 1045 int 1046 hme_rint(struct hme_softc *sc) 1047 { 1048 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1049 bus_space_tag_t t = sc->sc_bustag; 1050 bus_space_handle_t mac = sc->sc_mac; 1051 void *xdr = sc->sc_rb.rb_rxd; 1052 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 1053 unsigned int ri; 1054 uint32_t flags; 1055 1056 ri = sc->sc_rb.rb_rdtail; 1057 1058 /* 1059 * Process all buffers with valid data. 1060 */ 1061 for (;;) { 1062 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 1063 if (flags & HME_XD_OWN) 1064 break; 1065 1066 if (flags & HME_XD_OFL) { 1067 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 1068 device_xname(sc->sc_dev), ri, flags); 1069 } else 1070 hme_read(sc, ri, flags); 1071 1072 /* This buffer can be used by the hardware again */ 1073 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 1074 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 1075 1076 if (++ri == nrbuf) 1077 ri = 0; 1078 } 1079 1080 sc->sc_rb.rb_rdtail = ri; 1081 1082 /* Read error counters ... */ 1083 ifp->if_ierrors += 1084 bus_space_read_4(t, mac, HME_MACI_STAT_LCNT) + 1085 bus_space_read_4(t, mac, HME_MACI_STAT_ACNT) + 1086 bus_space_read_4(t, mac, HME_MACI_STAT_CCNT) + 1087 bus_space_read_4(t, mac, HME_MACI_STAT_CVCNT); 1088 1089 /* ... then clear the hardware counters. */ 1090 bus_space_write_4(t, mac, HME_MACI_STAT_LCNT, 0); 1091 bus_space_write_4(t, mac, HME_MACI_STAT_ACNT, 0); 1092 bus_space_write_4(t, mac, HME_MACI_STAT_CCNT, 0); 1093 bus_space_write_4(t, mac, HME_MACI_STAT_CVCNT, 0); 1094 return (1); 1095 } 1096 1097 int 1098 hme_eint(struct hme_softc *sc, u_int status) 1099 { 1100 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1101 char bits[128]; 1102 1103 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 1104 bus_space_tag_t t = sc->sc_bustag; 1105 bus_space_handle_t mif = sc->sc_mif; 1106 uint32_t cf, st, sm; 1107 cf = bus_space_read_4(t, mif, HME_MIFI_CFG); 1108 st = bus_space_read_4(t, mif, HME_MIFI_STAT); 1109 sm = bus_space_read_4(t, mif, HME_MIFI_SM); 1110 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n", 1111 device_xname(sc->sc_dev), cf, st, sm); 1112 return (1); 1113 } 1114 1115 /* Receive error counters rolled over */ 1116 if (status & HME_SEB_STAT_ACNTEXP) 1117 ifp->if_ierrors += 0xff; 1118 if (status & HME_SEB_STAT_CCNTEXP) 1119 ifp->if_ierrors += 0xff; 1120 if (status & HME_SEB_STAT_LCNTEXP) 1121 ifp->if_ierrors += 0xff; 1122 if (status & HME_SEB_STAT_CVCNTEXP) 1123 ifp->if_ierrors += 0xff; 1124 1125 /* RXTERR locks up the interface, so do a reset */ 1126 if (status & HME_SEB_STAT_RXTERR) 1127 hme_reset(sc); 1128 1129 snprintb(bits, sizeof(bits), HME_SEB_STAT_BITS, status); 1130 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1131 1132 return (1); 1133 } 1134 1135 int 1136 hme_intr(void *v) 1137 { 1138 struct hme_softc *sc = v; 1139 bus_space_tag_t t = sc->sc_bustag; 1140 bus_space_handle_t seb = sc->sc_seb; 1141 uint32_t status; 1142 int r = 0; 1143 1144 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 1145 1146 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 1147 r |= hme_eint(sc, status); 1148 1149 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 1150 r |= hme_tint(sc); 1151 1152 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1153 r |= hme_rint(sc); 1154 1155 #if NRND > 0 1156 rnd_add_uint32(&sc->rnd_source, status); 1157 #endif 1158 1159 return (r); 1160 } 1161 1162 1163 void 1164 hme_watchdog(struct ifnet *ifp) 1165 { 1166 struct hme_softc *sc = ifp->if_softc; 1167 1168 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1169 ++ifp->if_oerrors; 1170 1171 hme_reset(sc); 1172 } 1173 1174 /* 1175 * Initialize the MII Management Interface 1176 */ 1177 void 1178 hme_mifinit(struct hme_softc *sc) 1179 { 1180 bus_space_tag_t t = sc->sc_bustag; 1181 bus_space_handle_t mif = sc->sc_mif; 1182 bus_space_handle_t mac = sc->sc_mac; 1183 int instance, phy; 1184 uint32_t v; 1185 1186 if (sc->sc_mii.mii_media.ifm_cur != NULL) { 1187 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1188 phy = sc->sc_phys[instance]; 1189 } else 1190 /* No media set yet, pick phy arbitrarily.. */ 1191 phy = HME_PHYAD_EXTERNAL; 1192 1193 /* Configure the MIF in frame mode, no poll, current phy select */ 1194 v = 0; 1195 if (phy == HME_PHYAD_EXTERNAL) 1196 v |= HME_MIF_CFG_PHY; 1197 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1198 1199 /* If an external transceiver is selected, enable its MII drivers */ 1200 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1201 v &= ~HME_MAC_XIF_MIIENABLE; 1202 if (phy == HME_PHYAD_EXTERNAL) 1203 v |= HME_MAC_XIF_MIIENABLE; 1204 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1205 } 1206 1207 /* 1208 * MII interface 1209 */ 1210 static int 1211 hme_mii_readreg(device_t self, int phy, int reg) 1212 { 1213 struct hme_softc *sc = device_private(self); 1214 bus_space_tag_t t = sc->sc_bustag; 1215 bus_space_handle_t mif = sc->sc_mif; 1216 bus_space_handle_t mac = sc->sc_mac; 1217 uint32_t v, xif_cfg, mifi_cfg; 1218 int n; 1219 1220 /* We can at most have two PHYs */ 1221 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1222 return (0); 1223 1224 /* Select the desired PHY in the MIF configuration register */ 1225 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1226 v &= ~HME_MIF_CFG_PHY; 1227 if (phy == HME_PHYAD_EXTERNAL) 1228 v |= HME_MIF_CFG_PHY; 1229 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1230 1231 /* Enable MII drivers on external transceiver */ 1232 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1233 if (phy == HME_PHYAD_EXTERNAL) 1234 v |= HME_MAC_XIF_MIIENABLE; 1235 else 1236 v &= ~HME_MAC_XIF_MIIENABLE; 1237 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1238 1239 #if 0 1240 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1241 /* 1242 * Check whether a transceiver is connected by testing 1243 * the MIF configuration register's MDI_X bits. Note that 1244 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1245 */ 1246 mif_mdi_bit = 1 << (8 + (1 - phy)); 1247 delay(100); 1248 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1249 if ((v & mif_mdi_bit) == 0) 1250 return (0); 1251 #endif 1252 1253 /* Construct the frame command */ 1254 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1255 HME_MIF_FO_TAMSB | 1256 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1257 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1258 (reg << HME_MIF_FO_REGAD_SHIFT); 1259 1260 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1261 for (n = 0; n < 100; n++) { 1262 DELAY(1); 1263 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1264 if (v & HME_MIF_FO_TALSB) { 1265 v &= HME_MIF_FO_DATA; 1266 goto out; 1267 } 1268 } 1269 1270 v = 0; 1271 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1272 1273 out: 1274 /* Restore MIFI_CFG register */ 1275 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1276 /* Restore XIF register */ 1277 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1278 return (v); 1279 } 1280 1281 static void 1282 hme_mii_writereg(device_t self, int phy, int reg, int val) 1283 { 1284 struct hme_softc *sc = device_private(self); 1285 bus_space_tag_t t = sc->sc_bustag; 1286 bus_space_handle_t mif = sc->sc_mif; 1287 bus_space_handle_t mac = sc->sc_mac; 1288 uint32_t v, xif_cfg, mifi_cfg; 1289 int n; 1290 1291 /* We can at most have two PHYs */ 1292 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1293 return; 1294 1295 /* Select the desired PHY in the MIF configuration register */ 1296 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1297 v &= ~HME_MIF_CFG_PHY; 1298 if (phy == HME_PHYAD_EXTERNAL) 1299 v |= HME_MIF_CFG_PHY; 1300 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1301 1302 /* Enable MII drivers on external transceiver */ 1303 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1304 if (phy == HME_PHYAD_EXTERNAL) 1305 v |= HME_MAC_XIF_MIIENABLE; 1306 else 1307 v &= ~HME_MAC_XIF_MIIENABLE; 1308 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1309 1310 #if 0 1311 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1312 /* 1313 * Check whether a transceiver is connected by testing 1314 * the MIF configuration register's MDI_X bits. Note that 1315 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1316 */ 1317 mif_mdi_bit = 1 << (8 + (1 - phy)); 1318 delay(100); 1319 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1320 if ((v & mif_mdi_bit) == 0) 1321 return; 1322 #endif 1323 1324 /* Construct the frame command */ 1325 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1326 HME_MIF_FO_TAMSB | 1327 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1328 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1329 (reg << HME_MIF_FO_REGAD_SHIFT) | 1330 (val & HME_MIF_FO_DATA); 1331 1332 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1333 for (n = 0; n < 100; n++) { 1334 DELAY(1); 1335 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1336 if (v & HME_MIF_FO_TALSB) 1337 goto out; 1338 } 1339 1340 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1341 out: 1342 /* Restore MIFI_CFG register */ 1343 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1344 /* Restore XIF register */ 1345 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1346 } 1347 1348 static void 1349 hme_mii_statchg(device_t dev) 1350 { 1351 struct hme_softc *sc = device_private(dev); 1352 bus_space_tag_t t = sc->sc_bustag; 1353 bus_space_handle_t mac = sc->sc_mac; 1354 uint32_t v; 1355 1356 #ifdef HMEDEBUG 1357 if (sc->sc_debug) 1358 printf("hme_mii_statchg: status change\n"); 1359 #endif 1360 1361 /* Set the MAC Full Duplex bit appropriately */ 1362 /* Apparently the hme chip is SIMPLEX if working in full duplex mode, 1363 but not otherwise. */ 1364 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1365 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1366 v |= HME_MAC_TXCFG_FULLDPLX; 1367 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX; 1368 } else { 1369 v &= ~HME_MAC_TXCFG_FULLDPLX; 1370 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX; 1371 } 1372 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags; 1373 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1374 } 1375 1376 int 1377 hme_mediachange(struct ifnet *ifp) 1378 { 1379 struct hme_softc *sc = ifp->if_softc; 1380 bus_space_tag_t t = sc->sc_bustag; 1381 bus_space_handle_t mif = sc->sc_mif; 1382 bus_space_handle_t mac = sc->sc_mac; 1383 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1384 int phy = sc->sc_phys[instance]; 1385 int rc; 1386 uint32_t v; 1387 1388 #ifdef HMEDEBUG 1389 if (sc->sc_debug) 1390 printf("hme_mediachange: phy = %d\n", phy); 1391 #endif 1392 1393 /* Select the current PHY in the MIF configuration register */ 1394 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1395 v &= ~HME_MIF_CFG_PHY; 1396 if (phy == HME_PHYAD_EXTERNAL) 1397 v |= HME_MIF_CFG_PHY; 1398 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1399 1400 /* If an external transceiver is selected, enable its MII drivers */ 1401 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1402 v &= ~HME_MAC_XIF_MIIENABLE; 1403 if (phy == HME_PHYAD_EXTERNAL) 1404 v |= HME_MAC_XIF_MIIENABLE; 1405 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1406 1407 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 1408 return 0; 1409 return rc; 1410 } 1411 1412 /* 1413 * Process an ioctl request. 1414 */ 1415 int 1416 hme_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1417 { 1418 struct hme_softc *sc = ifp->if_softc; 1419 struct ifaddr *ifa = (struct ifaddr *)data; 1420 int s, error = 0; 1421 1422 s = splnet(); 1423 1424 switch (cmd) { 1425 1426 case SIOCINITIFADDR: 1427 switch (ifa->ifa_addr->sa_family) { 1428 #ifdef INET 1429 case AF_INET: 1430 if (ifp->if_flags & IFF_UP) 1431 hme_setladrf(sc); 1432 else { 1433 ifp->if_flags |= IFF_UP; 1434 error = hme_init(sc); 1435 } 1436 arp_ifinit(ifp, ifa); 1437 break; 1438 #endif 1439 default: 1440 ifp->if_flags |= IFF_UP; 1441 error = hme_init(sc); 1442 break; 1443 } 1444 break; 1445 1446 case SIOCSIFFLAGS: 1447 #ifdef HMEDEBUG 1448 { 1449 struct ifreq *ifr = data; 1450 sc->sc_debug = 1451 (ifr->ifr_flags & IFF_DEBUG) != 0 ? 1 : 0; 1452 } 1453 #endif 1454 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1455 break; 1456 1457 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1458 case IFF_RUNNING: 1459 /* 1460 * If interface is marked down and it is running, then 1461 * stop it. 1462 */ 1463 hme_stop(sc, false); 1464 ifp->if_flags &= ~IFF_RUNNING; 1465 break; 1466 case IFF_UP: 1467 /* 1468 * If interface is marked up and it is stopped, then 1469 * start it. 1470 */ 1471 error = hme_init(sc); 1472 break; 1473 case IFF_UP|IFF_RUNNING: 1474 /* 1475 * If setting debug or promiscuous mode, do not reset 1476 * the chip; for everything else, call hme_init() 1477 * which will trigger a reset. 1478 */ 1479 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG) 1480 if (ifp->if_flags != sc->sc_if_flags) { 1481 if ((ifp->if_flags & (~RESETIGN)) 1482 == (sc->sc_if_flags & (~RESETIGN))) 1483 hme_setladrf(sc); 1484 else 1485 error = hme_init(sc); 1486 } 1487 #undef RESETIGN 1488 break; 1489 case 0: 1490 break; 1491 } 1492 1493 if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable) 1494 error = hme_init(sc); 1495 1496 break; 1497 1498 default: 1499 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1500 break; 1501 1502 error = 0; 1503 1504 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1505 ; 1506 else if (ifp->if_flags & IFF_RUNNING) { 1507 /* 1508 * Multicast list has changed; set the hardware filter 1509 * accordingly. 1510 */ 1511 hme_setladrf(sc); 1512 } 1513 break; 1514 } 1515 1516 sc->sc_if_flags = ifp->if_flags; 1517 splx(s); 1518 return (error); 1519 } 1520 1521 void 1522 hme_shutdown(void *arg) 1523 { 1524 struct hme_softc *sc; 1525 1526 sc = arg; 1527 hme_stop(sc, false); 1528 } 1529 1530 /* 1531 * Set up the logical address filter. 1532 */ 1533 void 1534 hme_setladrf(struct hme_softc *sc) 1535 { 1536 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1537 struct ether_multi *enm; 1538 struct ether_multistep step; 1539 struct ethercom *ec = &sc->sc_ethercom; 1540 bus_space_tag_t t = sc->sc_bustag; 1541 bus_space_handle_t mac = sc->sc_mac; 1542 u_char *cp; 1543 uint32_t crc; 1544 uint32_t hash[4]; 1545 uint32_t v; 1546 int len; 1547 1548 /* Clear hash table */ 1549 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1550 1551 /* Get current RX configuration */ 1552 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1553 1554 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1555 /* Turn on promiscuous mode; turn off the hash filter */ 1556 v |= HME_MAC_RXCFG_PMISC; 1557 v &= ~HME_MAC_RXCFG_HENABLE; 1558 ifp->if_flags |= IFF_ALLMULTI; 1559 goto chipit; 1560 } 1561 1562 /* Turn off promiscuous mode; turn on the hash filter */ 1563 v &= ~HME_MAC_RXCFG_PMISC; 1564 v |= HME_MAC_RXCFG_HENABLE; 1565 1566 /* 1567 * Set up multicast address filter by passing all multicast addresses 1568 * through a crc generator, and then using the high order 6 bits as an 1569 * index into the 64 bit logical address filter. The high order bit 1570 * selects the word, while the rest of the bits select the bit within 1571 * the word. 1572 */ 1573 1574 ETHER_FIRST_MULTI(step, ec, enm); 1575 while (enm != NULL) { 1576 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1577 /* 1578 * We must listen to a range of multicast addresses. 1579 * For now, just accept all multicasts, rather than 1580 * trying to set only those filter bits needed to match 1581 * the range. (At this time, the only use of address 1582 * ranges is for IP multicast routing, for which the 1583 * range is big enough to require all bits set.) 1584 */ 1585 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1586 ifp->if_flags |= IFF_ALLMULTI; 1587 goto chipit; 1588 } 1589 1590 cp = enm->enm_addrlo; 1591 crc = 0xffffffff; 1592 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1593 int octet = *cp++; 1594 int i; 1595 1596 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1597 for (i = 0; i < 8; i++) { 1598 if ((crc & 1) ^ (octet & 1)) { 1599 crc >>= 1; 1600 crc ^= MC_POLY_LE; 1601 } else { 1602 crc >>= 1; 1603 } 1604 octet >>= 1; 1605 } 1606 } 1607 /* Just want the 6 most significant bits. */ 1608 crc >>= 26; 1609 1610 /* Set the corresponding bit in the filter. */ 1611 hash[crc >> 4] |= 1 << (crc & 0xf); 1612 1613 ETHER_NEXT_MULTI(step, enm); 1614 } 1615 1616 ifp->if_flags &= ~IFF_ALLMULTI; 1617 1618 chipit: 1619 /* Now load the hash table into the chip */ 1620 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1621 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1622 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1623 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1624 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1625 } 1626 1627 /* 1628 * Routines for accessing the transmit and receive buffers. 1629 * The various CPU and adapter configurations supported by this 1630 * driver require three different access methods for buffers 1631 * and descriptors: 1632 * (1) contig (contiguous data; no padding), 1633 * (2) gap2 (two bytes of data followed by two bytes of padding), 1634 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1635 */ 1636 1637 #if 0 1638 /* 1639 * contig: contiguous data with no padding. 1640 * 1641 * Buffers may have any alignment. 1642 */ 1643 1644 void 1645 hme_copytobuf_contig(struct hme_softc *sc, void *from, int ri, int len) 1646 { 1647 volatile void *buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1648 1649 /* 1650 * Just call memcpy() to do the work. 1651 */ 1652 memcpy(buf, from, len); 1653 } 1654 1655 void 1656 hme_copyfrombuf_contig(struct hme_softc *sc, void *to, int boff, int len) 1657 { 1658 volatile void *buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1659 1660 /* 1661 * Just call memcpy() to do the work. 1662 */ 1663 memcpy(to, buf, len); 1664 } 1665 #endif 1666