1 /* $NetBSD: gemreg.h,v 1.8 2005/12/11 12:21:26 christos Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #ifndef _IF_GEMREG_H 33 #define _IF_GEMREG_H 34 35 /* Register definitions for Sun GEM gigabit ethernet */ 36 37 #define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */ 38 #define GEM_CONFIG 0x0004 /* config reg */ 39 #define GEM_STATUS 0x000c /* status reg */ 40 /* Note: Reading the status reg clears bits 0-6 */ 41 #define GEM_INTMASK 0x0010 42 #define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */ 43 #define GEM_STATUS_ALIAS 0x001c 44 /* This is the same as the GEM_STATUS reg but reading it does not clear bits. */ 45 #define GEM_ERROR_STATUS 0x1000 /* PCI error status R/C */ 46 #define GEM_ERROR_MASK 0x1004 47 #define GEM_BIF_CONFIG 0x1008 /* BIF config reg */ 48 #define GEM_BIF_DIAG 0x100c 49 #define GEM_RESET 0x1010 /* Software reset register */ 50 51 52 /* Bits in GEM_SEB register */ 53 #define GEM_SEB_ARB 0x000000002 /* Arbitration status */ 54 #define GEM_SEB_RXWON 0x000000004 55 56 57 /* Bits in GEM_CONFIG register */ 58 #define GEM_CONFIG_BURST_64 0x000000000 /* 0->infinity, 1->64KB */ 59 #define GEM_CONFIG_BURST_INF 0x000000001 /* 0->infinity, 1->64KB */ 60 #define GEM_CONFIG_TXDMA_LIMIT 0x00000003e 61 #define GEM_CONFIG_RXDMA_LIMIT 0x0000007c0 62 63 #define GEM_CONFIG_TXDMA_LIMIT_SHIFT 1 64 #define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6 65 66 67 /* Top part of GEM_STATUS has TX completion information */ 68 #define GEM_STATUS_TX_COMPL 0xfff800000 /* TX completion reg. */ 69 70 71 /* 72 * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs. 73 * Bits 0-6 auto-clear when read. 74 */ 75 #define GEM_INTR_TX_INTME 0x000000001 /* Frame w/INTME bit set sent */ 76 #define GEM_INTR_TX_EMPTY 0x000000002 /* TX ring empty */ 77 #define GEM_INTR_TX_DONE 0x000000004 /* TX complete */ 78 #define GEM_INTR_RX_DONE 0x000000010 /* Got a packet */ 79 #define GEM_INTR_RX_NOBUF 0x000000020 80 #define GEM_INTR_RX_TAG_ERR 0x000000040 81 #define GEM_INTR_PCS 0x000002000 /* Physical Code Sub-layer */ 82 #define GEM_INTR_TX_MAC 0x000004000 83 #define GEM_INTR_RX_MAC 0x000008000 84 #define GEM_INTR_MAC_CONTROL 0x000010000 /* MAC control interrupt */ 85 #define GEM_INTR_MIF 0x000020000 86 #define GEM_INTR_BERR 0x000040000 /* Bus error interrupt */ 87 #define GEM_INTR_BITS "\177\020" \ 88 "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \ 89 "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \ 90 "b\xdPCS\0b\xeTXMAC\0b\xfRXMAC\0" \ 91 "b\x10MAC_CONTROL\0b\x11MIF\0b\x12IBERR\0\0" 92 93 94 95 /* GEM_ERROR_STATUS and GEM_ERROR_MASK PCI error bits */ 96 #define GEM_ERROR_STAT_BADACK 0x000000001 /* No ACK64# */ 97 #define GEM_ERROR_STAT_DTRTO 0x000000002 /* Delayed xaction timeout */ 98 #define GEM_ERROR_STAT_OTHERS 0x000000004 99 #define GEM_ERROR_BITS "\177\020b\0ACKBAD\0b\1DTRTO\0b\2OTHER\0\0" 100 101 102 /* GEM_BIF_CONFIG register bits */ 103 #define GEM_BIF_CONFIG_SLOWCLK 0x000000001 /* Parity error timing */ 104 #define GEM_BIF_CONFIG_HOST_64 0x000000002 /* 64-bit host */ 105 #define GEM_BIF_CONFIG_B64D_DIS 0x000000004 /* no 64-bit data cycle */ 106 #define GEM_BIF_CONFIG_M66EN 0x000000008 107 #define GEM_BIF_CONFIG_BITS "\177\020b\0SLOWCLK\0b\1HOST64\0" \ 108 "b\2B64DIS\0b\3M66EN\0\0" 109 110 111 /* GEM_RESET register bits -- TX and RX self clear when complete. */ 112 #define GEM_RESET_TX 0x000000001 /* Reset TX half */ 113 #define GEM_RESET_RX 0x000000002 /* Reset RX half */ 114 #define GEM_RESET_RSTOUT 0x000000004 /* Force PCI RSTOUT# */ 115 116 117 /* GEM TX DMA registers */ 118 #define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */ 119 #define GEM_TX_CONFIG 0x2004 120 #define GEM_TX_RING_PTR_LO 0x2008 121 #define GEM_TX_RING_PTR_HI 0x200c 122 123 #define GEM_TX_FIFO_WR_PTR 0x2014 /* FIFO write pointer */ 124 #define GEM_TX_FIFO_SDWR_PTR 0x2018 /* FIFO shadow write pointer */ 125 #define GEM_TX_FIFO_RD_PTR 0x201c /* FIFO read pointer */ 126 #define GEM_TX_FIFO_SDRD_PTR 0x2020 /* FIFO shadow read pointer */ 127 #define GEM_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */ 128 129 #define GEM_TX_STATE_MACHINE 0x2028 /* ETX state machine reg */ 130 #define GEM_TX_DATA_PTR 0x2030 /* ETX state machine reg (64-bit)*/ 131 132 #define GEM_TX_COMPLETION 0x2100 133 #define GEM_TX_FIFO_ADDRESS 0x2104 134 #define GEM_TX_FIFO_TAG 0x2108 135 #define GEM_TX_FIFO_DATA_LO 0x210c 136 #define GEM_TX_FIFO_DATA_HI_T1 0x2110 137 #define GEM_TX_FIFO_DATA_HI_T0 0x2114 138 #define GEM_TX_FIFO_SIZE 0x2118 139 #define GEM_TX_DEBUG 0x3028 140 141 142 /* GEM_TX_CONFIG register bits. */ 143 #define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */ 144 #define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */ 145 #define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */ 146 #define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */ 147 148 #define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */ 149 #define GEM_RING_SZ_64 (1<<1) 150 #define GEM_RING_SZ_128 (2<<1) 151 #define GEM_RING_SZ_256 (3<<1) 152 #define GEM_RING_SZ_512 (4<<1) 153 #define GEM_RING_SZ_1024 (5<<1) 154 #define GEM_RING_SZ_2048 (6<<1) 155 #define GEM_RING_SZ_4096 (7<<1) 156 #define GEM_RING_SZ_8192 (8<<1) 157 158 159 /* GEM_TX_COMPLETION register bits */ 160 #define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */ 161 162 163 /* GEM RX DMA registers */ 164 #define GEM_RX_CONFIG 0x4000 165 #define GEM_RX_RING_PTR_LO 0x4004 /* 64-bits unaligned GAK! */ 166 #define GEM_RX_RING_PTR_HI 0x4008 /* 64-bits unaligned GAK! */ 167 168 #define GEM_RX_FIFO_WR_PTR 0x400c /* FIFO write pointer */ 169 #define GEM_RX_FIFO_SDWR_PTR 0x4010 /* FIFO shadow write pointer */ 170 #define GEM_RX_FIFO_RD_PTR 0x4014 /* FIFO read pointer */ 171 #define GEM_RX_FIFO_PKT_CNT 0x4018 /* FIFO packet counter */ 172 173 #define GEM_RX_STATE_MACHINE 0x401c /* ERX state machine reg */ 174 #define GEM_RX_PAUSE_THRESH 0x4020 175 176 #define GEM_RX_DATA_PTR_LO 0x4024 /* ERX state machine reg */ 177 #define GEM_RX_DATA_PTR_HI 0x4028 /* Damn thing is unaligned */ 178 179 #define GEM_RX_KICK 0x4100 /* Write last valid desc + 1 */ 180 #define GEM_RX_COMPLETION 0x4104 /* First pending desc */ 181 #define GEM_RX_BLANKING 0x4108 /* Interrupt blanking reg */ 182 183 #define GEM_RX_FIFO_ADDRESS 0x410c 184 #define GEM_RX_FIFO_TAG 0x4110 185 #define GEM_RX_FIFO_DATA_LO 0x4114 186 #define GEM_RX_FIFO_DATA_HI_T1 0x4118 187 #define GEM_RX_FIFO_DATA_HI_T0 0x411c 188 #define GEM_RX_FIFO_SIZE 0x4120 189 190 191 /* GEM_RX_CONFIG register bits. */ 192 #define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */ 193 #define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */ 194 #define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */ 195 #define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */ 196 #define GEM_RX_CONFIG_CXM_START 0x000fe000 /* cksum start offset bytes */ 197 #define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */ 198 199 #define GEM_THRSH_64 0 200 #define GEM_THRSH_128 1 201 #define GEM_THRSH_256 2 202 #define GEM_THRSH_512 3 203 #define GEM_THRSH_1024 4 204 #define GEM_THRSH_2048 5 205 206 #define GEM_RX_CONFIG_FIFO_THRS_SHIFT 24 207 #define GEM_RX_CONFIG_FBOFF_SHFT 10 208 #define GEM_RX_CONFIG_CXM_START_SHFT 13 209 210 211 /* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */ 212 #define GEM_RX_PTH_XOFF_THRESH 0x000001ff 213 #define GEM_RX_PTH_XON_THRESH 0x001ff000 214 215 216 /* GEM_RX_BLANKING register bits */ 217 #define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */ 218 #define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */ 219 #define GEM_RX_BLANKING_TIME_SHIFT 12 220 /* One tick is 2048 PCI clocks, or 16us at 66MHz */ 221 222 223 /* GEM_MAC registers */ 224 #define GEM_MAC_TXRESET 0x6000 /* Store 1, cleared when done */ 225 #define GEM_MAC_RXRESET 0x6004 /* ditto */ 226 #define GEM_MAC_SEND_PAUSE_CMD 0x6008 227 #define GEM_MAC_TX_STATUS 0x6010 228 #define GEM_MAC_RX_STATUS 0x6014 229 #define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC control status reg */ 230 #define GEM_MAC_TX_MASK 0x6020 /* TX MAC mask register */ 231 #define GEM_MAC_RX_MASK 0x6024 232 #define GEM_MAC_CONTROL_MASK 0x6028 233 #define GEM_MAC_TX_CONFIG 0x6030 234 #define GEM_MAC_RX_CONFIG 0x6034 235 #define GEM_MAC_CONTROL_CONFIG 0x6038 236 #define GEM_MAC_XIF_CONFIG 0x603c 237 #define GEM_MAC_IPG0 0x6040 /* inter packet gap 0 */ 238 #define GEM_MAC_IPG1 0x6044 /* inter packet gap 1 */ 239 #define GEM_MAC_IPG2 0x6048 /* inter packet gap 2 */ 240 #define GEM_MAC_SLOT_TIME 0x604c /* slot time, bits 0-7 */ 241 #define GEM_MAC_MAC_MIN_FRAME 0x6050 242 #define GEM_MAC_MAC_MAX_FRAME 0x6054 243 #define GEM_MAC_PREAMBLE_LEN 0x6058 244 #define GEM_MAC_JAM_SIZE 0x605c 245 #define GEM_MAC_ATTEMPT_LIMIT 0x6060 246 #define GEM_MAC_CONTROL_TYPE 0x6064 247 248 #define GEM_MAC_ADDR0 0x6080 /* Normal MAC address 0 */ 249 #define GEM_MAC_ADDR1 0x6084 250 #define GEM_MAC_ADDR2 0x6088 251 #define GEM_MAC_ADDR3 0x608c /* Alternate MAC address 0 */ 252 #define GEM_MAC_ADDR4 0x6090 253 #define GEM_MAC_ADDR5 0x6094 254 #define GEM_MAC_ADDR6 0x6098 /* Control MAC address 0 */ 255 #define GEM_MAC_ADDR7 0x609c 256 #define GEM_MAC_ADDR8 0x60a0 257 258 #define GEM_MAC_ADDR_FILTER0 0x60a4 259 #define GEM_MAC_ADDR_FILTER1 0x60a8 260 #define GEM_MAC_ADDR_FILTER2 0x60ac 261 #define GEM_MAC_ADR_FLT_MASK1_2 0x60b0 /* Address filter mask 1,2 */ 262 #define GEM_MAC_ADR_FLT_MASK0 0x60b4 /* Address filter mask 0 reg */ 263 264 #define GEM_MAC_HASH0 0x60c0 /* Hash table 0 */ 265 #define GEM_MAC_HASH1 0x60c4 266 #define GEM_MAC_HASH2 0x60c8 267 #define GEM_MAC_HASH3 0x60cc 268 #define GEM_MAC_HASH4 0x60d0 269 #define GEM_MAC_HASH5 0x60d4 270 #define GEM_MAC_HASH6 0x60d8 271 #define GEM_MAC_HASH7 0x60dc 272 #define GEM_MAC_HASH8 0x60e0 273 #define GEM_MAC_HASH9 0x60e4 274 #define GEM_MAC_HASH10 0x60e8 275 #define GEM_MAC_HASH11 0x60ec 276 #define GEM_MAC_HASH12 0x60f0 277 #define GEM_MAC_HASH13 0x60f4 278 #define GEM_MAC_HASH14 0x60f8 279 #define GEM_MAC_HASH15 0x60fc 280 281 #define GEM_MAC_NORM_COLL_CNT 0x6100 /* Normal collision counter */ 282 #define GEM_MAC_FIRST_COLL_CNT 0x6104 /* 1st successful collision cntr */ 283 #define GEM_MAC_EXCESS_COLL_CNT 0x6108 /* Excess collision counter */ 284 #define GEM_MAC_LATE_COLL_CNT 0x610c /* Late collision counter */ 285 #define GEM_MAC_DEFER_TMR_CNT 0x6110 /* defer timer counter */ 286 #define GEM_MAC_PEAK_ATTEMPTS 0x6114 287 #define GEM_MAC_RX_FRAME_COUNT 0x6118 288 #define GEM_MAC_RX_LEN_ERR_CNT 0x611c 289 #define GEM_MAC_RX_ALIGN_ERR 0x6120 290 #define GEM_MAC_RX_CRC_ERR_CNT 0x6124 291 #define GEM_MAC_RX_CODE_VIOL 0x6128 292 #define GEM_MAC_RANDOM_SEED 0x6130 293 #define GEM_MAC_MAC_STATE 0x6134 /* MAC sstate machine reg */ 294 295 296 /* GEM_MAC_SEND_PAUSE_CMD register bits */ 297 #define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff 298 #define GEM_MAC_PAUSE_CMD_SEND 0x00010000 299 300 301 /* GEM_MAC_TX_STATUS and _MASK register bits */ 302 #define GEM_MAC_TX_XMIT_DONE 0x00000001 303 #define GEM_MAC_TX_UNDERRUN 0x00000002 304 #define GEM_MAC_TX_PKT_TOO_LONG 0x00000004 305 #define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision cnt exp */ 306 #define GEM_MAC_TX_ECC_EXP 0x00000010 307 #define GEM_MAC_TX_LCC_EXP 0x00000020 308 #define GEM_MAC_TX_FCC_EXP 0x00000040 309 #define GEM_MAC_TX_DEFER_EXP 0x00000080 310 #define GEM_MAC_TX_PEAK_EXP 0x00000100 311 312 313 /* GEM_MAC_RX_STATUS and _MASK register bits */ 314 #define GEM_MAC_RX_DONE 0x00000001 315 #define GEM_MAC_RX_OVERFLOW 0x00000002 316 #define GEM_MAC_RX_FRAME_CNT 0x00000004 317 #define GEM_MAC_RX_ALIGN_EXP 0x00000008 318 #define GEM_MAC_RX_CRC_EXP 0x00000010 319 #define GEM_MAC_RX_LEN_EXP 0x00000020 320 #define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation */ 321 322 323 /* GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register bits */ 324 #define GEM_MAC_PAUSED 0x00000001 /* Pause received */ 325 #define GEM_MAC_PAUSE 0x00000002 /* enter pause state */ 326 #define GEM_MAC_RESUME 0x00000004 /* exit pause state */ 327 #define GEM_MAC_PAUSE_TIME 0xffff0000 328 #define GEM_MAC_STATUS_BITS "\177\020b\0PAUSED\0b\1PAUSE\0b\2RESUME\0\0" 329 330 /* GEM_MAC_XIF_CONFIG register bits */ 331 #define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable XIF output drivers */ 332 #define GEM_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable MII loopback mode */ 333 #define GEM_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */ 334 #define GEM_MAC_XIF_GMII_MODE 0x00000008 /* Select GMII/MII mode */ 335 #define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */ 336 #define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */ 337 #define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */ 338 #define GEM_MAC_XIF_BITS "\177\020b\0TXMIIENA\0b\1MIILOOP\0b\2NOECHO" \ 339 "\0b\3GMII\0b\4MIIBUFENA\0b\5LINKLED\0" \ 340 "b\6FDLED\0\0" 341 342 /* GEM_MAC_SLOT_TIME register bits */ 343 #define GEM_MAC_SLOT_INT 0x40 344 #define GEM_MAC_SLOT_EXT 0x200 /* external phy */ 345 #define GEM_MAC_SLOT_BITS "\177\020b\6INTSLOT\0b\x9SLOTEXT\0\0" 346 347 /* GEM_MAC_TX_CONFIG register bits */ 348 #define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */ 349 #define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */ 350 #define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */ 351 #define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend Rx-to-TX IPG */ 352 #define GEM_MAC_TX_NGU 0x00000010 /* Never give up */ 353 #define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */ 354 #define GEM_MAC_TX_NO_BACKOFF 0x00000040 355 #define GEM_MAC_TX_SLOWDOWN 0x00000080 356 #define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */ 357 #define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */ 358 /* Carrier Extension is required for half duplex Gbps operation */ 359 #define GEM_MAC_TX_CONFIG_BITS "\177\020" \ 360 "b\0TXENA\0b\1IGNCAR\0b\2IGNCOLLIS\0" \ 361 "b\3IPG0ENA\0b\4TXNGU\0b\5TXNGULIM\0" \ 362 "b\6NOBKOFF\0b\7SLOWDN\0b\x8NOFCS\0" \ 363 "b\x9TXCARREXT\0\0" 364 365 366 /* GEM_MAC_RX_CONFIG register bits */ 367 #define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */ 368 #define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */ 369 #define GEM_MAC_RX_STRIP_CRC 0x00000004 370 #define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */ 371 #define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */ 372 #define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */ 373 #define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */ 374 #define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error checking */ 375 #define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */ 376 /* 377 * Carrier Extension enables reception of packet bursts generated by 378 * senders with carrier extension enabled. 379 */ 380 #define GEM_MAC_RX_CONFIG_BITS "\177\020" \ 381 "b\0RXENA\0b\1STRPAD\0b\2STRCRC\0" \ 382 "b\3PROMIS\0b\4PROMISCGRP\0b\5HASHFLTR\0" \ 383 "b\6ADDRFLTR\0b\7ERRCHKDIS\0b\x9TXCARREXT\0\0" 384 385 386 /* GEM_MAC_CONTROL_CONFIG bits */ 387 #define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */ 388 #define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */ 389 #define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */ 390 #define GEM_MAC_CC_BITS "\177\020b\0TXPAUSE\0b\1RXPAUSE\0b\2NOPAUSE\0\0" 391 392 393 /* GEM MIF registers */ 394 /* Bit bang registers use low bit only */ 395 #define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */ 396 #define GEM_MIF_BB_DATA 0x6204 /* bit bang data */ 397 #define GEM_MIF_BB_OUTPUT_ENAB 0x6208 398 #define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */ 399 #define GEM_MIF_CONFIG 0x6210 400 #define GEM_MIF_INTERRUPT_MASK 0x6214 401 #define GEM_MIF_BASIC_STATUS 0x6218 402 #define GEM_MIF_STATE_MACHINE 0x621c 403 404 405 /* GEM_MIF_FRAME bits */ 406 #define GEM_MIF_FRAME_DATA 0x0000ffff 407 #define GEM_MIF_FRAME_TA0 0x00010000 /* TA bit, 1 for completion */ 408 #define GEM_MIF_FRAME_TA1 0x00020000 /* TA bits */ 409 #define GEM_MIF_FRAME_REG_ADDR 0x007c0000 410 #define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* phy address, should be 0 */ 411 #define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */ 412 #define GEM_MIF_FRAME_START 0xc0000000 /* START bits */ 413 414 #define GEM_MIF_FRAME_READ 0x60020000 415 #define GEM_MIF_FRAME_WRITE 0x50020000 416 417 #define GEM_MIF_REG_SHIFT 18 418 #define GEM_MIF_PHY_SHIFT 23 419 420 421 /* GEM_MIF_CONFIG register bits */ 422 #define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0=MDIO0 */ 423 #define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */ 424 #define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */ 425 #define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */ 426 #define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 Data/MDIO_0 atached */ 427 #define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 Data/MDIO_1 atached */ 428 #define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */ 429 /* MDI0 is onboard transceiver MID1 is external, PHYAD for both is 0 */ 430 #define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \ 431 "b\x8MDIO0\0b\x9MDIO1\0\0" 432 433 434 /* GEM_MIF_BASIC_STATUS and GEM_MIF_INTERRUPT_MASK bits */ 435 #define GEM_MIF_STATUS 0x0000ffff 436 #define GEM_MIF_BASIC 0xffff0000 437 /* 438 * The Basic part is the last value read in the POLL field of the config 439 * register. 440 * 441 * The status part indicates the bits that have changed. 442 */ 443 444 445 /* The GEM PCS/Serial link registers. */ 446 /* DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. */ 447 #define GEM_MII_CONTROL 0x9000 448 #define GEM_MII_STATUS 0x9004 449 #define GEM_MII_ANAR 0x9008 /* MII advertisement reg */ 450 #define GEM_MII_ANLPAR 0x900c /* Link Partner Ability Reg */ 451 #define GEM_MII_CONFIG 0x9010 452 #define GEM_MII_STATE_MACHINE 0x9014 453 #define GEM_MII_INTERRUP_STATUS 0x9018 /* PCS interrupt state */ 454 #define GEM_MII_DATAPATH_MODE 0x9050 455 #define GEM_MII_SLINK_CONTROL 0x9054 /* Serial link control */ 456 #define GEM_MII_OUTPUT_SELECT 0x9058 457 #define GEM_MII_SLINK_STATUS 0x905c /* serial link status */ 458 459 460 /* GEM_MII_CONTROL bits - PCS "BMCR" (Basic Mode Control Reg) */ 461 #define GEM_MII_CONTROL_RESET 0x00008000 462 #define GEM_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */ 463 #define GEM_MII_CONTROL_1000M 0x00002000 /* speed select, always 0 */ 464 #define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto negotiation enabled */ 465 #define GEM_MII_CONTROL_POWERDN 0x00000800 466 #define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate phy from mii */ 467 #define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto negotiation */ 468 #define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full duplex, always 0 */ 469 #define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */ 470 #define GEM_MII_CONTROL_BITS "\177\020b\7COLTST\0b\x8_FD\0b\x9RAN\0" \ 471 "b\xaISOLATE\0b\xbPWRDWN\0b\xc_ANEG\0" \ 472 "b\xdGIGE\0b\xeLOOP\0b\xfRESET\0\0" 473 474 475 /* GEM_MII_STATUS reg - PCS "BMSR" (Basic Mode Status Reg) */ 476 #define GEM_MII_STATUS_GB_FDX 0x00000400 /* can perform GBit FDX */ 477 #define GEM_MII_STATUS_GB_HDX 0x00000200 /* can perform GBit HDX */ 478 #define GEM_MII_STATUS_UNK 0x00000100 479 #define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto negotiate compete */ 480 #define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */ 481 #define GEM_MII_STATUS_ACFG 0x00000008 /* can auto negotiate */ 482 #define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status */ 483 #define GEM_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */ 484 #define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended register capability */ 485 #define GEM_MII_STATUS_BITS "\177\020b\0EXTCAP\0b\1JABBER\0b\2LINKSTS\0" \ 486 "b\3ACFG\0b\4REMFLT\0b\5ANEGCPT\0b\x9GBHDX\0" \ 487 "b\xaGBFDX\0\0" 488 489 490 /* GEM_MII_ANAR and GEM_MII_ANLPAR reg bits */ 491 #define GEM_MII_ANEG_NP 0x00008000 /* next page bit */ 492 #define GEM_MII_ANEG_ACK 0x00004000 /* ack reception of */ 493 /* Link Partner Capability */ 494 #define GEM_MII_ANEG_RF 0x00003000 /* advertise remote fault cap */ 495 #define GEM_MII_ANEG_ASYM_PAUSE 0x00000100 /* asymmetric pause */ 496 #define GEM_MII_ANEG_SYM_PAUSE 0x00000080 /* symmetric pause */ 497 #define GEM_MII_ANEG_HLF_DUPLX 0x00000040 498 #define GEM_MII_ANEG_FUL_DUPLX 0x00000020 499 #define GEM_MII_ANEG_BITS "\177\020b\5FDX\0b\6HDX\0b\7SYMPAUSE\0" \ 500 "\b\x8_ASYMPAUSE\0\b\xdREMFLT\0\b\xeLPACK\0" \ 501 "\b\xfNPBIT\0\0" 502 503 504 /* GEM_MII_CONFIG reg */ 505 #define GEM_MII_CONFIG_TIMER 0x0000000e /* link monitor timer values */ 506 #define GEM_MII_CONFIG_ANTO 0x00000020 /* 10ms ANEG timer override */ 507 #define GEM_MII_CONFIG_JS 0x00000018 /* Jitter Study, 0 normal 508 * 1 high freq, 2 low freq */ 509 #define GEM_MII_CONFIG_SDL 0x00000004 /* Signal Detect active low */ 510 #define GEM_MII_CONFIG_SDO 0x00000002 /* Signal Detect Override */ 511 #define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS */ 512 #define GEM_MII_CONFIG_BITS "\177\020b\0PCSENA\0\0" 513 514 515 /* 516 * GEM_MII_STATE_MACHINE 517 * XXX These are best guesses from observed behavior. 518 */ 519 #define GEM_MII_FSM_STOP 0x00000000 /* stopped */ 520 #define GEM_MII_FSM_RUN 0x00000001 /* running */ 521 #define GEM_MII_FSM_UNKWN 0x00000100 /* unknown */ 522 #define GEM_MII_FSM_DONE 0x00000101 /* complete */ 523 524 525 /* 526 * GEM_MII_INTERRUP_STATUS reg 527 * No mask register; mask with the global interrupt mask register. 528 */ 529 #define GEM_MII_INTERRUP_LINK 0x00000002 /* PCS link status change */ 530 531 532 /* GEM_MII_DATAPATH_MODE reg */ 533 #define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Serial link */ 534 #define GEM_MII_DATAPATH_SERDES 0x00000002 /* Use PCS via 10bit interfac */ 535 #define GEM_MII_DATAPATH_MII 0x00000004 /* Use {G}MII, not PCS */ 536 #define GEM_MII_DATAPATH_MIIOUT 0x00000008 /* enable serial output on GMII */ 537 #define GEM_MII_DATAPATH_BITS "\177\020" \ 538 "b\0SERIAL\0b\1SERDES\0b\2MII\0b\3MIIOUT\0\0" 539 540 541 /* GEM_MII_SLINK_CONTROL reg */ 542 #define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback at sl, logic 543 * reversed for SERDES */ 544 #define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */ 545 #define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock reference clock */ 546 #define GEM_MII_SLINK_EMPHASIS 0x00000008 /* enable emphasis */ 547 #define GEM_MII_SLINK_SELFTEST 0x000001c0 548 #define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down serial link */ 549 #define GEM_MII_SLINK_CONTROL_BITS \ 550 "\177\020b\0LOOP\0b\1ENASYNC\0b\2LOCKREF" \ 551 "\0b\3EMPHASIS\0b\x9PWRDWN\0\0" 552 553 554 /* GEM_MII_SLINK_STATUS reg */ 555 #define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */ 556 #define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us lockrefn */ 557 #define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */ 558 #define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */ 559 560 561 /* Wired GEM PHY addresses */ 562 #define GEM_PHYAD_INTERNAL 1 563 #define GEM_PHYAD_EXTERNAL 0 564 565 /* 566 * GEM descriptor table structures. 567 */ 568 struct gem_desc { 569 uint64_t gd_flags; 570 uint64_t gd_addr; 571 }; 572 573 /* Transmit flags */ 574 #define GEM_TD_BUFSIZE 0x0000000000007fffLL 575 #define GEM_TD_CXSUM_START 0x00000000001f8000LL /* Cxsum start offset */ 576 #define GEM_TD_CXSUM_STARTSHFT 15 577 #define GEM_TD_CXSUM_STUFF 0x000000001fe00000LL /* Cxsum stuff offset */ 578 #define GEM_TD_CXSUM_STUFFSHFT 21 579 #define GEM_TD_CXSUM_ENABLE 0x0000000020000000LL /* Cxsum generation enable */ 580 #define GEM_TD_END_OF_PACKET 0x0000000040000000LL 581 #define GEM_TD_START_OF_PACKET 0x0000000080000000LL 582 #define GEM_TD_INTERRUPT_ME 0x0000000100000000LL /* Interrupt me now */ 583 #define GEM_TD_NO_CRC 0x0000000200000000LL /* do not insert crc */ 584 /* 585 * Only need to set GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_STUFF, 586 * GEM_TD_CXSUM_START, and GEM_TD_INTERRUPT_ME in 1st descriptor of a group. 587 */ 588 589 /* Receive flags */ 590 #define GEM_RD_CHECKSUM 0x000000000000ffffLL /* is the complement */ 591 #define GEM_RD_BUFSIZE 0x000000007fff0000LL 592 #define GEM_RD_OWN 0x0000000080000000LL /* 1 - owned by h/w */ 593 #define GEM_RD_HASHVAL 0x0ffff00000000000LL 594 #define GEM_RD_HASH_PASS 0x1000000000000000LL /* passed hash filter */ 595 #define GEM_RD_ALTERNATE_MAC 0x2000000000000000LL /* Alternate MAC adrs */ 596 #define GEM_RD_BAD_CRC 0x4000000000000000LL 597 598 #define GEM_RD_BUFSHIFT 16 599 #define GEM_RD_BUFLEN(x) (((x)&GEM_RD_BUFSIZE)>>GEM_RD_BUFSHIFT) 600 601 #endif 602