1 /* $NetBSD: gem.c,v 1.34 2005/02/04 02:10:36 perry Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.34 2005/02/04 02:10:36 perry Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/syslog.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <machine/endian.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/bus.h> 67 #include <machine/intr.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/mii/mii_bitbang.h> 72 73 #include <dev/ic/gemreg.h> 74 #include <dev/ic/gemvar.h> 75 76 #define TRIES 10000 77 78 void gem_start(struct ifnet *); 79 void gem_stop(struct ifnet *, int); 80 int gem_ioctl(struct ifnet *, u_long, caddr_t); 81 void gem_tick(void *); 82 void gem_watchdog(struct ifnet *); 83 void gem_shutdown(void *); 84 int gem_init(struct ifnet *); 85 void gem_init_regs(struct gem_softc *sc); 86 static int gem_ringsize(int sz); 87 int gem_meminit(struct gem_softc *); 88 void gem_mifinit(struct gem_softc *); 89 void gem_reset(struct gem_softc *); 90 int gem_reset_rx(struct gem_softc *sc); 91 int gem_reset_tx(struct gem_softc *sc); 92 int gem_disable_rx(struct gem_softc *sc); 93 int gem_disable_tx(struct gem_softc *sc); 94 void gem_rxdrain(struct gem_softc *sc); 95 int gem_add_rxbuf(struct gem_softc *sc, int idx); 96 void gem_setladrf(struct gem_softc *); 97 98 /* MII methods & callbacks */ 99 static int gem_mii_readreg(struct device *, int, int); 100 static void gem_mii_writereg(struct device *, int, int, int); 101 static void gem_mii_statchg(struct device *); 102 103 int gem_mediachange(struct ifnet *); 104 void gem_mediastatus(struct ifnet *, struct ifmediareq *); 105 106 struct mbuf *gem_get(struct gem_softc *, int, int); 107 int gem_put(struct gem_softc *, int, struct mbuf *); 108 void gem_read(struct gem_softc *, int, int); 109 int gem_eint(struct gem_softc *, u_int); 110 int gem_rint(struct gem_softc *); 111 int gem_tint(struct gem_softc *); 112 void gem_power(int, void *); 113 114 #ifdef GEM_DEBUG 115 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 116 printf x 117 #else 118 #define DPRINTF(sc, x) /* nothing */ 119 #endif 120 121 122 /* 123 * gem_attach: 124 * 125 * Attach a Gem interface to the system. 126 */ 127 void 128 gem_attach(sc, enaddr) 129 struct gem_softc *sc; 130 const uint8_t *enaddr; 131 { 132 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 133 struct mii_data *mii = &sc->sc_mii; 134 struct mii_softc *child; 135 struct ifmedia_entry *ifm; 136 int i, error; 137 u_int32_t v; 138 139 /* Make sure the chip is stopped. */ 140 ifp->if_softc = sc; 141 gem_reset(sc); 142 143 /* 144 * Allocate the control data structures, and create and load the 145 * DMA map for it. 146 */ 147 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 148 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 149 1, &sc->sc_cdnseg, 0)) != 0) { 150 aprint_error( 151 "%s: unable to allocate control data, error = %d\n", 152 sc->sc_dev.dv_xname, error); 153 goto fail_0; 154 } 155 156 /* XXX should map this in with correct endianness */ 157 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 158 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 159 BUS_DMA_COHERENT)) != 0) { 160 aprint_error("%s: unable to map control data, error = %d\n", 161 sc->sc_dev.dv_xname, error); 162 goto fail_1; 163 } 164 165 if ((error = bus_dmamap_create(sc->sc_dmatag, 166 sizeof(struct gem_control_data), 1, 167 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 168 aprint_error("%s: unable to create control data DMA map, " 169 "error = %d\n", sc->sc_dev.dv_xname, error); 170 goto fail_2; 171 } 172 173 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 174 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 175 0)) != 0) { 176 aprint_error( 177 "%s: unable to load control data DMA map, error = %d\n", 178 sc->sc_dev.dv_xname, error); 179 goto fail_3; 180 } 181 182 /* 183 * Initialize the transmit job descriptors. 184 */ 185 SIMPLEQ_INIT(&sc->sc_txfreeq); 186 SIMPLEQ_INIT(&sc->sc_txdirtyq); 187 188 /* 189 * Create the transmit buffer DMA maps. 190 */ 191 for (i = 0; i < GEM_TXQUEUELEN; i++) { 192 struct gem_txsoft *txs; 193 194 txs = &sc->sc_txsoft[i]; 195 txs->txs_mbuf = NULL; 196 if ((error = bus_dmamap_create(sc->sc_dmatag, 197 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 198 ETHER_MAX_LEN_JUMBO, 0, 0, 199 &txs->txs_dmamap)) != 0) { 200 aprint_error("%s: unable to create tx DMA map %d, " 201 "error = %d\n", sc->sc_dev.dv_xname, i, error); 202 goto fail_4; 203 } 204 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 205 } 206 207 /* 208 * Create the receive buffer DMA maps. 209 */ 210 for (i = 0; i < GEM_NRXDESC; i++) { 211 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 212 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 213 aprint_error("%s: unable to create rx DMA map %d, " 214 "error = %d\n", sc->sc_dev.dv_xname, i, error); 215 goto fail_5; 216 } 217 sc->sc_rxsoft[i].rxs_mbuf = NULL; 218 } 219 220 /* 221 * From this point forward, the attachment cannot fail. A failure 222 * before this point releases all resources that may have been 223 * allocated. 224 */ 225 226 /* Announce ourselves. */ 227 aprint_normal("%s: Ethernet address %s", sc->sc_dev.dv_xname, 228 ether_sprintf(enaddr)); 229 230 /* Get RX FIFO size */ 231 sc->sc_rxfifosize = 64 * 232 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 233 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 234 235 /* Get TX FIFO size */ 236 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 237 aprint_normal(", %uKB TX fifo\n", v / 16); 238 239 /* Initialize ifnet structure. */ 240 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 241 ifp->if_softc = sc; 242 ifp->if_flags = 243 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 244 ifp->if_start = gem_start; 245 ifp->if_ioctl = gem_ioctl; 246 ifp->if_watchdog = gem_watchdog; 247 ifp->if_stop = gem_stop; 248 ifp->if_init = gem_init; 249 IFQ_SET_READY(&ifp->if_snd); 250 251 /* Initialize ifmedia structures and MII info */ 252 mii->mii_ifp = ifp; 253 mii->mii_readreg = gem_mii_readreg; 254 mii->mii_writereg = gem_mii_writereg; 255 mii->mii_statchg = gem_mii_statchg; 256 257 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_mediachange, gem_mediastatus); 258 259 gem_mifinit(sc); 260 261 mii_attach(&sc->sc_dev, mii, 0xffffffff, 262 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 263 264 child = LIST_FIRST(&mii->mii_phys); 265 if (child == NULL) { 266 /* No PHY attached */ 267 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 268 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 269 } else { 270 /* 271 * Walk along the list of attached MII devices and 272 * establish an `MII instance' to `phy number' 273 * mapping. We'll use this mapping in media change 274 * requests to determine which phy to use to program 275 * the MIF configuration register. 276 */ 277 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 278 /* 279 * Note: we support just two PHYs: the built-in 280 * internal device and an external on the MII 281 * connector. 282 */ 283 if (child->mii_phy > 1 || child->mii_inst > 1) { 284 aprint_error( 285 "%s: cannot accomodate MII device %s" 286 " at phy %d, instance %d\n", 287 sc->sc_dev.dv_xname, 288 child->mii_dev.dv_xname, 289 child->mii_phy, child->mii_inst); 290 continue; 291 } 292 293 sc->sc_phys[child->mii_inst] = child->mii_phy; 294 } 295 296 /* 297 * Now select and activate the PHY we will use. 298 * 299 * The order of preference is External (MDI1), 300 * Internal (MDI0), Serial Link (no MII). 301 */ 302 if (sc->sc_phys[1]) { 303 #ifdef DEBUG 304 aprint_debug("using external phy\n"); 305 #endif 306 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 307 } else { 308 #ifdef DEBUG 309 aprint_debug("using internal phy\n"); 310 #endif 311 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 312 } 313 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 314 sc->sc_mif_config); 315 316 /* 317 * XXX - we can really do the following ONLY if the 318 * phy indeed has the auto negotiation capability!! 319 */ 320 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 321 } 322 323 /* 324 * If we support GigE media, we support jumbo frames too. 325 * Unless we are Apple. 326 */ 327 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 328 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 329 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 330 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 331 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 332 if (sc->sc_variant != GEM_APPLE_GMAC) 333 sc->sc_ethercom.ec_capabilities 334 |= ETHERCAP_JUMBO_MTU; 335 336 sc->sc_flags |= GEM_GIGABIT; 337 break; 338 } 339 } 340 341 /* claim 802.1q capability */ 342 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 343 344 /* Attach the interface. */ 345 if_attach(ifp); 346 ether_ifattach(ifp, enaddr); 347 348 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 349 if (sc->sc_sh == NULL) 350 panic("gem_config: can't establish shutdownhook"); 351 352 #if NRND > 0 353 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 354 RND_TYPE_NET, 0); 355 #endif 356 357 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 358 NULL, sc->sc_dev.dv_xname, "interrupts"); 359 #ifdef GEM_COUNTERS 360 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 361 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "tx interrupts"); 362 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 363 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "rx interrupts"); 364 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 365 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx ring full"); 366 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 367 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx malloc failure"); 368 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 369 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 0desc"); 370 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 371 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 1desc"); 372 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 373 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 2desc"); 374 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 375 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 3desc"); 376 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 377 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >3desc"); 378 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 379 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >7desc"); 380 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 381 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >15desc"); 382 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 383 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >31desc"); 384 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 385 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >63desc"); 386 #endif 387 388 #if notyet 389 /* 390 * Add a suspend hook to make sure we come back up after a 391 * resume. 392 */ 393 sc->sc_powerhook = powerhook_establish(gem_power, sc); 394 if (sc->sc_powerhook == NULL) 395 aprint_error("%s: WARNING: unable to establish power hook\n", 396 sc->sc_dev.dv_xname); 397 #endif 398 399 callout_init(&sc->sc_tick_ch); 400 return; 401 402 /* 403 * Free any resources we've allocated during the failed attach 404 * attempt. Do this in reverse order and fall through. 405 */ 406 fail_5: 407 for (i = 0; i < GEM_NRXDESC; i++) { 408 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 409 bus_dmamap_destroy(sc->sc_dmatag, 410 sc->sc_rxsoft[i].rxs_dmamap); 411 } 412 fail_4: 413 for (i = 0; i < GEM_TXQUEUELEN; i++) { 414 if (sc->sc_txsoft[i].txs_dmamap != NULL) 415 bus_dmamap_destroy(sc->sc_dmatag, 416 sc->sc_txsoft[i].txs_dmamap); 417 } 418 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 419 fail_3: 420 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 421 fail_2: 422 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 423 sizeof(struct gem_control_data)); 424 fail_1: 425 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 426 fail_0: 427 return; 428 } 429 430 431 void 432 gem_tick(arg) 433 void *arg; 434 { 435 struct gem_softc *sc = arg; 436 int s; 437 438 s = splnet(); 439 mii_tick(&sc->sc_mii); 440 splx(s); 441 442 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 443 444 } 445 446 void 447 gem_reset(sc) 448 struct gem_softc *sc; 449 { 450 bus_space_tag_t t = sc->sc_bustag; 451 bus_space_handle_t h = sc->sc_h; 452 int i; 453 int s; 454 455 s = splnet(); 456 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 457 gem_reset_rx(sc); 458 gem_reset_tx(sc); 459 460 /* Do a full reset */ 461 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 462 for (i=TRIES; i--; delay(100)) 463 if ((bus_space_read_4(t, h, GEM_RESET) & 464 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 465 break; 466 if ((bus_space_read_4(t, h, GEM_RESET) & 467 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 468 printf("%s: cannot reset device\n", 469 sc->sc_dev.dv_xname); 470 } 471 splx(s); 472 } 473 474 475 /* 476 * gem_rxdrain: 477 * 478 * Drain the receive queue. 479 */ 480 void 481 gem_rxdrain(struct gem_softc *sc) 482 { 483 struct gem_rxsoft *rxs; 484 int i; 485 486 for (i = 0; i < GEM_NRXDESC; i++) { 487 rxs = &sc->sc_rxsoft[i]; 488 if (rxs->rxs_mbuf != NULL) { 489 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 490 m_freem(rxs->rxs_mbuf); 491 rxs->rxs_mbuf = NULL; 492 } 493 } 494 } 495 496 /* 497 * Reset the whole thing. 498 */ 499 void 500 gem_stop(struct ifnet *ifp, int disable) 501 { 502 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 503 struct gem_txsoft *txs; 504 505 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 506 507 callout_stop(&sc->sc_tick_ch); 508 mii_down(&sc->sc_mii); 509 510 /* XXX - Should we reset these instead? */ 511 gem_disable_rx(sc); 512 gem_disable_tx(sc); 513 514 /* 515 * Release any queued transmit buffers. 516 */ 517 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 518 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 519 if (txs->txs_mbuf != NULL) { 520 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 521 m_freem(txs->txs_mbuf); 522 txs->txs_mbuf = NULL; 523 } 524 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 525 } 526 527 if (disable) { 528 gem_rxdrain(sc); 529 } 530 531 /* 532 * Mark the interface down and cancel the watchdog timer. 533 */ 534 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 535 ifp->if_timer = 0; 536 } 537 538 539 /* 540 * Reset the receiver 541 */ 542 int 543 gem_reset_rx(struct gem_softc *sc) 544 { 545 bus_space_tag_t t = sc->sc_bustag; 546 bus_space_handle_t h = sc->sc_h; 547 int i; 548 549 550 /* 551 * Resetting while DMA is in progress can cause a bus hang, so we 552 * disable DMA first. 553 */ 554 gem_disable_rx(sc); 555 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 556 /* Wait till it finishes */ 557 for (i=TRIES; i--; delay(100)) 558 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 559 break; 560 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 561 printf("%s: cannot disable read DMA\n", 562 sc->sc_dev.dv_xname); 563 564 /* Wait 5ms extra. */ 565 delay(5000); 566 567 /* Finally, reset the ERX */ 568 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 569 /* Wait till it finishes */ 570 for (i=TRIES; i--; delay(100)) 571 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 572 break; 573 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 574 printf("%s: cannot reset receiver\n", 575 sc->sc_dev.dv_xname); 576 return (1); 577 } 578 return (0); 579 } 580 581 582 /* 583 * Reset the transmitter 584 */ 585 int 586 gem_reset_tx(struct gem_softc *sc) 587 { 588 bus_space_tag_t t = sc->sc_bustag; 589 bus_space_handle_t h = sc->sc_h; 590 int i; 591 592 /* 593 * Resetting while DMA is in progress can cause a bus hang, so we 594 * disable DMA first. 595 */ 596 gem_disable_tx(sc); 597 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 598 /* Wait till it finishes */ 599 for (i=TRIES; i--; delay(100)) 600 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 601 break; 602 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 603 printf("%s: cannot disable read DMA\n", 604 sc->sc_dev.dv_xname); 605 606 /* Wait 5ms extra. */ 607 delay(5000); 608 609 /* Finally, reset the ETX */ 610 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 611 /* Wait till it finishes */ 612 for (i=TRIES; i--; delay(100)) 613 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 614 break; 615 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 616 printf("%s: cannot reset receiver\n", 617 sc->sc_dev.dv_xname); 618 return (1); 619 } 620 return (0); 621 } 622 623 /* 624 * disable receiver. 625 */ 626 int 627 gem_disable_rx(struct gem_softc *sc) 628 { 629 bus_space_tag_t t = sc->sc_bustag; 630 bus_space_handle_t h = sc->sc_h; 631 int i; 632 u_int32_t cfg; 633 634 /* Flip the enable bit */ 635 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 636 cfg &= ~GEM_MAC_RX_ENABLE; 637 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 638 639 /* Wait for it to finish */ 640 for (i=TRIES; i--; delay(100)) 641 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 642 GEM_MAC_RX_ENABLE) == 0) 643 return (0); 644 return (1); 645 } 646 647 /* 648 * disable transmitter. 649 */ 650 int 651 gem_disable_tx(struct gem_softc *sc) 652 { 653 bus_space_tag_t t = sc->sc_bustag; 654 bus_space_handle_t h = sc->sc_h; 655 int i; 656 u_int32_t cfg; 657 658 /* Flip the enable bit */ 659 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 660 cfg &= ~GEM_MAC_TX_ENABLE; 661 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 662 663 /* Wait for it to finish */ 664 for (i=TRIES; i--; delay(100)) 665 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 666 GEM_MAC_TX_ENABLE) == 0) 667 return (0); 668 return (1); 669 } 670 671 /* 672 * Initialize interface. 673 */ 674 int 675 gem_meminit(struct gem_softc *sc) 676 { 677 struct gem_rxsoft *rxs; 678 int i, error; 679 680 /* 681 * Initialize the transmit descriptor ring. 682 */ 683 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 684 for (i = 0; i < GEM_NTXDESC; i++) { 685 sc->sc_txdescs[i].gd_flags = 0; 686 sc->sc_txdescs[i].gd_addr = 0; 687 } 688 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 689 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 690 sc->sc_txfree = GEM_NTXDESC-1; 691 sc->sc_txnext = 0; 692 sc->sc_txwin = 0; 693 694 /* 695 * Initialize the receive descriptor and receive job 696 * descriptor rings. 697 */ 698 for (i = 0; i < GEM_NRXDESC; i++) { 699 rxs = &sc->sc_rxsoft[i]; 700 if (rxs->rxs_mbuf == NULL) { 701 if ((error = gem_add_rxbuf(sc, i)) != 0) { 702 printf("%s: unable to allocate or map rx " 703 "buffer %d, error = %d\n", 704 sc->sc_dev.dv_xname, i, error); 705 /* 706 * XXX Should attempt to run with fewer receive 707 * XXX buffers instead of just failing. 708 */ 709 gem_rxdrain(sc); 710 return (1); 711 } 712 } else 713 GEM_INIT_RXDESC(sc, i); 714 } 715 sc->sc_rxptr = 0; 716 717 return (0); 718 } 719 720 static int 721 gem_ringsize(int sz) 722 { 723 switch (sz) { 724 case 32: 725 return GEM_RING_SZ_32; 726 case 64: 727 return GEM_RING_SZ_64; 728 case 128: 729 return GEM_RING_SZ_128; 730 case 256: 731 return GEM_RING_SZ_256; 732 case 512: 733 return GEM_RING_SZ_512; 734 case 1024: 735 return GEM_RING_SZ_1024; 736 case 2048: 737 return GEM_RING_SZ_2048; 738 case 4096: 739 return GEM_RING_SZ_4096; 740 case 8192: 741 return GEM_RING_SZ_8192; 742 default: 743 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 744 return GEM_RING_SZ_32; 745 } 746 } 747 748 /* 749 * Initialization of interface; set up initialization block 750 * and transmit/receive descriptor rings. 751 */ 752 int 753 gem_init(struct ifnet *ifp) 754 { 755 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 756 bus_space_tag_t t = sc->sc_bustag; 757 bus_space_handle_t h = sc->sc_h; 758 int s; 759 u_int max_frame_size; 760 u_int32_t v; 761 762 s = splnet(); 763 764 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 765 /* 766 * Initialization sequence. The numbered steps below correspond 767 * to the sequence outlined in section 6.3.5.1 in the Ethernet 768 * Channel Engine manual (part of the PCIO manual). 769 * See also the STP2002-STQ document from Sun Microsystems. 770 */ 771 772 /* step 1 & 2. Reset the Ethernet Channel */ 773 gem_stop(ifp, 0); 774 gem_reset(sc); 775 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 776 777 /* Re-initialize the MIF */ 778 gem_mifinit(sc); 779 780 /* Call MI reset function if any */ 781 if (sc->sc_hwreset) 782 (*sc->sc_hwreset)(sc); 783 784 /* step 3. Setup data structures in host memory */ 785 gem_meminit(sc); 786 787 /* step 4. TX MAC registers & counters */ 788 gem_init_regs(sc); 789 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 790 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 791 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 792 max_frame_size += ETHER_VLAN_ENCAP_LEN; 793 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 794 max_frame_size|/* burst size */(0x2000<<16)); 795 796 /* step 5. RX MAC registers & counters */ 797 gem_setladrf(sc); 798 799 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 800 /* NOTE: we use only 32-bit DMA addresses here. */ 801 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 802 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 803 804 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 805 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 806 807 /* step 8. Global Configuration & Interrupt Mask */ 808 bus_space_write_4(t, h, GEM_INTMASK, 809 ~(GEM_INTR_TX_INTME| 810 GEM_INTR_TX_EMPTY| 811 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 812 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 813 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 814 GEM_INTR_BERR)); 815 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 816 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 817 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 818 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 819 820 /* step 9. ETX Configuration: use mostly default values */ 821 822 /* Enable DMA */ 823 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 824 bus_space_write_4(t, h, GEM_TX_CONFIG, 825 v|GEM_TX_CONFIG_TXDMA_EN| 826 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 827 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 828 829 /* step 10. ERX Configuration */ 830 831 /* Encode Receive Descriptor ring size: four possible values */ 832 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 833 834 /* Enable DMA */ 835 bus_space_write_4(t, h, GEM_RX_CONFIG, 836 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 837 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 838 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 839 /* 840 * The following value is for an OFF Threshold of about 3/4 full 841 * and an ON Threshold of 1/4 full. 842 */ 843 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 844 (3 * sc->sc_rxfifosize / 256) | 845 ( (sc->sc_rxfifosize / 256) << 12)); 846 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 847 848 /* step 11. Configure Media */ 849 mii_mediachg(&sc->sc_mii); 850 851 /* XXXX Serial link needs a whole different setup. */ 852 853 854 /* step 12. RX_MAC Configuration Register */ 855 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 856 v |= GEM_MAC_RX_ENABLE; 857 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 858 859 /* step 14. Issue Transmit Pending command */ 860 861 /* Call MI initialization function if any */ 862 if (sc->sc_hwinit) 863 (*sc->sc_hwinit)(sc); 864 865 866 /* step 15. Give the reciever a swift kick */ 867 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 868 869 /* Start the one second timer. */ 870 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 871 872 ifp->if_flags |= IFF_RUNNING; 873 ifp->if_flags &= ~IFF_OACTIVE; 874 ifp->if_timer = 0; 875 splx(s); 876 877 return (0); 878 } 879 880 void 881 gem_init_regs(struct gem_softc *sc) 882 { 883 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 884 bus_space_tag_t t = sc->sc_bustag; 885 bus_space_handle_t h = sc->sc_h; 886 const u_char *laddr = LLADDR(ifp->if_sadl); 887 u_int32_t v; 888 889 /* These regs are not cleared on reset */ 890 if (!sc->sc_inited) { 891 892 /* Wooo. Magic values. */ 893 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 894 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 895 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 896 897 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 898 /* Max frame and max burst size */ 899 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 900 ETHER_MAX_LEN | (0x2000<<16)); 901 902 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 903 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 904 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 905 /* Dunno.... */ 906 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 907 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 908 ((laddr[5]<<8)|laddr[4])&0x3ff); 909 910 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 911 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 912 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 913 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 914 915 /* MAC control addr set to 01:80:c2:00:00:01 */ 916 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 917 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 918 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 919 920 /* MAC filter addr set to 0:0:0:0:0:0 */ 921 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 922 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 923 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 924 925 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 926 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 927 928 sc->sc_inited = 1; 929 } 930 931 /* Counters need to be zeroed */ 932 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 933 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 934 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 935 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 936 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 937 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 938 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 939 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 940 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 941 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 942 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 943 944 /* Un-pause stuff */ 945 #if 0 946 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 947 #else 948 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 949 #endif 950 951 /* 952 * Set the station address. 953 */ 954 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 955 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 956 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 957 958 #if 0 959 if (sc->sc_variant != APPLE_GMAC) 960 return; 961 #endif 962 963 /* 964 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 965 */ 966 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 967 v = GEM_MAC_XIF_TX_MII_ENA; 968 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 969 v |= GEM_MAC_XIF_FDPLX_LED; 970 if (sc->sc_flags & GEM_GIGABIT) 971 v |= GEM_MAC_XIF_GMII_MODE; 972 } 973 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 974 } 975 976 void 977 gem_start(ifp) 978 struct ifnet *ifp; 979 { 980 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 981 struct mbuf *m0, *m; 982 struct gem_txsoft *txs, *last_txs; 983 bus_dmamap_t dmamap; 984 int error, firsttx, nexttx, lasttx = -1, ofree, seg; 985 986 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 987 return; 988 989 /* 990 * Remember the previous number of free descriptors and 991 * the first descriptor we'll use. 992 */ 993 ofree = sc->sc_txfree; 994 firsttx = sc->sc_txnext; 995 996 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 997 sc->sc_dev.dv_xname, ofree, firsttx)); 998 999 /* 1000 * Loop through the send queue, setting up transmit descriptors 1001 * until we drain the queue, or use up all available transmit 1002 * descriptors. 1003 */ 1004 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1005 sc->sc_txfree != 0) { 1006 /* 1007 * Grab a packet off the queue. 1008 */ 1009 IFQ_POLL(&ifp->if_snd, m0); 1010 if (m0 == NULL) 1011 break; 1012 m = NULL; 1013 1014 dmamap = txs->txs_dmamap; 1015 1016 /* 1017 * Load the DMA map. If this fails, the packet either 1018 * didn't fit in the alloted number of segments, or we were 1019 * short on resources. In this case, we'll copy and try 1020 * again. 1021 */ 1022 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1023 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1024 if (m0->m_pkthdr.len > MCLBYTES) { 1025 printf("%s: unable to allocate jumbo Tx " 1026 "cluster\n", sc->sc_dev.dv_xname); 1027 IFQ_DEQUEUE(&ifp->if_snd, m0); 1028 m_freem(m0); 1029 continue; 1030 } 1031 MGETHDR(m, M_DONTWAIT, MT_DATA); 1032 if (m == NULL) { 1033 printf("%s: unable to allocate Tx mbuf\n", 1034 sc->sc_dev.dv_xname); 1035 break; 1036 } 1037 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1038 if (m0->m_pkthdr.len > MHLEN) { 1039 MCLGET(m, M_DONTWAIT); 1040 if ((m->m_flags & M_EXT) == 0) { 1041 printf("%s: unable to allocate Tx " 1042 "cluster\n", sc->sc_dev.dv_xname); 1043 m_freem(m); 1044 break; 1045 } 1046 } 1047 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1048 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1049 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1050 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1051 if (error) { 1052 printf("%s: unable to load Tx buffer, " 1053 "error = %d\n", sc->sc_dev.dv_xname, error); 1054 break; 1055 } 1056 } 1057 1058 /* 1059 * Ensure we have enough descriptors free to describe 1060 * the packet. 1061 */ 1062 if (dmamap->dm_nsegs > sc->sc_txfree) { 1063 /* 1064 * Not enough free descriptors to transmit this 1065 * packet. We haven't committed to anything yet, 1066 * so just unload the DMA map, put the packet 1067 * back on the queue, and punt. Notify the upper 1068 * layer that there are no more slots left. 1069 * 1070 * XXX We could allocate an mbuf and copy, but 1071 * XXX it is worth it? 1072 */ 1073 ifp->if_flags |= IFF_OACTIVE; 1074 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1075 if (m != NULL) 1076 m_freem(m); 1077 break; 1078 } 1079 1080 IFQ_DEQUEUE(&ifp->if_snd, m0); 1081 if (m != NULL) { 1082 m_freem(m0); 1083 m0 = m; 1084 } 1085 1086 /* 1087 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1088 */ 1089 1090 /* Sync the DMA map. */ 1091 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1092 BUS_DMASYNC_PREWRITE); 1093 1094 /* 1095 * Initialize the transmit descriptors. 1096 */ 1097 for (nexttx = sc->sc_txnext, seg = 0; 1098 seg < dmamap->dm_nsegs; 1099 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1100 uint64_t flags; 1101 1102 /* 1103 * If this is the first descriptor we're 1104 * enqueueing, set the start of packet flag, 1105 * and the checksum stuff if we want the hardware 1106 * to do it. 1107 */ 1108 sc->sc_txdescs[nexttx].gd_addr = 1109 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1110 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1111 if (nexttx == firsttx) { 1112 flags |= GEM_TD_START_OF_PACKET; 1113 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1114 sc->sc_txwin = 0; 1115 flags |= GEM_TD_INTERRUPT_ME; 1116 } 1117 } 1118 if (seg == dmamap->dm_nsegs - 1) { 1119 flags |= GEM_TD_END_OF_PACKET; 1120 } 1121 sc->sc_txdescs[nexttx].gd_flags = 1122 GEM_DMA_WRITE(sc, flags); 1123 lasttx = nexttx; 1124 } 1125 1126 KASSERT(lasttx != -1); 1127 1128 #ifdef GEM_DEBUG 1129 if (ifp->if_flags & IFF_DEBUG) { 1130 printf(" gem_start %p transmit chain:\n", txs); 1131 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1132 printf("descriptor %d:\t", seg); 1133 printf("gd_flags: 0x%016llx\t", (long long) 1134 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1135 printf("gd_addr: 0x%016llx\n", (long long) 1136 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1137 if (seg == lasttx) 1138 break; 1139 } 1140 } 1141 #endif 1142 1143 /* Sync the descriptors we're using. */ 1144 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1145 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1146 1147 /* 1148 * Store a pointer to the packet so we can free it later, 1149 * and remember what txdirty will be once the packet is 1150 * done. 1151 */ 1152 txs->txs_mbuf = m0; 1153 txs->txs_firstdesc = sc->sc_txnext; 1154 txs->txs_lastdesc = lasttx; 1155 txs->txs_ndescs = dmamap->dm_nsegs; 1156 1157 /* Advance the tx pointer. */ 1158 sc->sc_txfree -= dmamap->dm_nsegs; 1159 sc->sc_txnext = nexttx; 1160 1161 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1162 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1163 1164 last_txs = txs; 1165 1166 #if NBPFILTER > 0 1167 /* 1168 * Pass the packet to any BPF listeners. 1169 */ 1170 if (ifp->if_bpf) 1171 bpf_mtap(ifp->if_bpf, m0); 1172 #endif /* NBPFILTER > 0 */ 1173 } 1174 1175 if (txs == NULL || sc->sc_txfree == 0) { 1176 /* No more slots left; notify upper layer. */ 1177 ifp->if_flags |= IFF_OACTIVE; 1178 } 1179 1180 if (sc->sc_txfree != ofree) { 1181 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1182 sc->sc_dev.dv_xname, lasttx, firsttx)); 1183 /* 1184 * The entire packet chain is set up. 1185 * Kick the transmitter. 1186 */ 1187 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1188 sc->sc_dev.dv_xname, nexttx)); 1189 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1190 sc->sc_txnext); 1191 1192 /* Set a watchdog timer in case the chip flakes out. */ 1193 ifp->if_timer = 5; 1194 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1195 sc->sc_dev.dv_xname, ifp->if_timer)); 1196 } 1197 } 1198 1199 /* 1200 * Transmit interrupt. 1201 */ 1202 int 1203 gem_tint(sc) 1204 struct gem_softc *sc; 1205 { 1206 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1207 bus_space_tag_t t = sc->sc_bustag; 1208 bus_space_handle_t mac = sc->sc_h; 1209 struct gem_txsoft *txs; 1210 int txlast; 1211 int progress = 0; 1212 1213 1214 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1215 1216 /* 1217 * Unload collision counters 1218 */ 1219 ifp->if_collisions += 1220 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1221 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1222 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1223 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1224 1225 /* 1226 * then clear the hardware counters. 1227 */ 1228 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1229 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1230 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1231 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1232 1233 /* 1234 * Go through our Tx list and free mbufs for those 1235 * frames that have been transmitted. 1236 */ 1237 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1238 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1239 txs->txs_ndescs, 1240 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1241 1242 #ifdef GEM_DEBUG 1243 if (ifp->if_flags & IFF_DEBUG) { 1244 int i; 1245 printf(" txsoft %p transmit chain:\n", txs); 1246 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1247 printf("descriptor %d: ", i); 1248 printf("gd_flags: 0x%016llx\t", (long long) 1249 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1250 printf("gd_addr: 0x%016llx\n", (long long) 1251 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1252 if (i == txs->txs_lastdesc) 1253 break; 1254 } 1255 } 1256 #endif 1257 1258 /* 1259 * In theory, we could harveast some descriptors before 1260 * the ring is empty, but that's a bit complicated. 1261 * 1262 * GEM_TX_COMPLETION points to the last descriptor 1263 * processed +1. 1264 */ 1265 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1266 DPRINTF(sc, 1267 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1268 txs->txs_lastdesc, txlast)); 1269 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1270 if ((txlast >= txs->txs_firstdesc) && 1271 (txlast <= txs->txs_lastdesc)) 1272 break; 1273 } else { 1274 /* Ick -- this command wraps */ 1275 if ((txlast >= txs->txs_firstdesc) || 1276 (txlast <= txs->txs_lastdesc)) 1277 break; 1278 } 1279 1280 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1281 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1282 1283 sc->sc_txfree += txs->txs_ndescs; 1284 1285 if (txs->txs_mbuf == NULL) { 1286 #ifdef DIAGNOSTIC 1287 panic("gem_txintr: null mbuf"); 1288 #endif 1289 } 1290 1291 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1292 0, txs->txs_dmamap->dm_mapsize, 1293 BUS_DMASYNC_POSTWRITE); 1294 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1295 m_freem(txs->txs_mbuf); 1296 txs->txs_mbuf = NULL; 1297 1298 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1299 1300 ifp->if_opackets++; 1301 progress = 1; 1302 } 1303 1304 #if 0 1305 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1306 "GEM_TX_DATA_PTR %llx " 1307 "GEM_TX_COMPLETION %x\n", 1308 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1309 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1310 GEM_TX_DATA_PTR_HI) << 32) | 1311 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1312 GEM_TX_DATA_PTR_LO), 1313 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1314 #endif 1315 1316 if (progress) { 1317 if (sc->sc_txfree == GEM_NTXDESC - 1) 1318 sc->sc_txwin = 0; 1319 1320 ifp->if_flags &= ~IFF_OACTIVE; 1321 gem_start(ifp); 1322 1323 if (SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) 1324 ifp->if_timer = 0; 1325 } 1326 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1327 sc->sc_dev.dv_xname, ifp->if_timer)); 1328 1329 return (1); 1330 } 1331 1332 /* 1333 * Receive interrupt. 1334 */ 1335 int 1336 gem_rint(sc) 1337 struct gem_softc *sc; 1338 { 1339 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1340 bus_space_tag_t t = sc->sc_bustag; 1341 bus_space_handle_t h = sc->sc_h; 1342 struct ether_header *eh; 1343 struct gem_rxsoft *rxs; 1344 struct mbuf *m; 1345 u_int64_t rxstat; 1346 u_int32_t rxcomp; 1347 int i, len, progress = 0; 1348 1349 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1350 1351 /* 1352 * Read the completion register once. This limits 1353 * how long the following loop can execute. 1354 */ 1355 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1356 1357 /* 1358 * XXXX Read the lastrx only once at the top for speed. 1359 */ 1360 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1361 sc->sc_rxptr, rxcomp)); 1362 1363 /* 1364 * Go into the loop at least once. 1365 */ 1366 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1367 i = GEM_NEXTRX(i)) { 1368 rxs = &sc->sc_rxsoft[i]; 1369 1370 GEM_CDRXSYNC(sc, i, 1371 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1372 1373 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1374 1375 if (rxstat & GEM_RD_OWN) { 1376 /* 1377 * We have processed all of the receive buffers. 1378 */ 1379 break; 1380 } 1381 1382 progress++; 1383 ifp->if_ipackets++; 1384 1385 if (rxstat & GEM_RD_BAD_CRC) { 1386 ifp->if_ierrors++; 1387 printf("%s: receive error: CRC error\n", 1388 sc->sc_dev.dv_xname); 1389 GEM_INIT_RXDESC(sc, i); 1390 continue; 1391 } 1392 1393 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1394 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1395 #ifdef GEM_DEBUG 1396 if (ifp->if_flags & IFF_DEBUG) { 1397 printf(" rxsoft %p descriptor %d: ", rxs, i); 1398 printf("gd_flags: 0x%016llx\t", (long long) 1399 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1400 printf("gd_addr: 0x%016llx\n", (long long) 1401 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1402 } 1403 #endif 1404 1405 /* 1406 * No errors; receive the packet. Note the Gem 1407 * includes the CRC with every packet. 1408 */ 1409 len = GEM_RD_BUFLEN(rxstat) - ETHER_CRC_LEN; 1410 1411 /* 1412 * Allocate a new mbuf cluster. If that fails, we are 1413 * out of memory, and must drop the packet and recycle 1414 * the buffer that's already attached to this descriptor. 1415 */ 1416 m = rxs->rxs_mbuf; 1417 if (gem_add_rxbuf(sc, i) != 0) { 1418 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1419 ifp->if_ierrors++; 1420 GEM_INIT_RXDESC(sc, i); 1421 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1422 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1423 continue; 1424 } 1425 m->m_data += 2; /* We're already off by two */ 1426 1427 eh = mtod(m, struct ether_header *); 1428 m->m_pkthdr.rcvif = ifp; 1429 m->m_pkthdr.len = m->m_len = len; 1430 1431 #if NBPFILTER > 0 1432 /* 1433 * Pass this up to any BPF listeners, but only 1434 * pass it up the stack if its for us. 1435 */ 1436 if (ifp->if_bpf) 1437 bpf_mtap(ifp->if_bpf, m); 1438 #endif /* NPBFILTER > 0 */ 1439 1440 /* Pass it on. */ 1441 (*ifp->if_input)(ifp, m); 1442 } 1443 1444 if (progress) { 1445 /* Update the receive pointer. */ 1446 if (i == sc->sc_rxptr) { 1447 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1448 #ifdef GEM_DEBUG 1449 if (ifp->if_flags & IFF_DEBUG) 1450 printf("%s: rint: ring wrap\n", 1451 sc->sc_dev.dv_xname); 1452 #endif 1453 } 1454 sc->sc_rxptr = i; 1455 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1456 } 1457 #ifdef GEM_COUNTERS 1458 if (progress <= 4) { 1459 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1460 } else if (progress < 32) { 1461 if (progress < 16) 1462 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1463 else 1464 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1465 1466 } else { 1467 if (progress < 64) 1468 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1469 else 1470 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1471 } 1472 #endif 1473 1474 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1475 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1476 1477 return (1); 1478 } 1479 1480 1481 /* 1482 * gem_add_rxbuf: 1483 * 1484 * Add a receive buffer to the indicated descriptor. 1485 */ 1486 int 1487 gem_add_rxbuf(struct gem_softc *sc, int idx) 1488 { 1489 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1490 struct mbuf *m; 1491 int error; 1492 1493 MGETHDR(m, M_DONTWAIT, MT_DATA); 1494 if (m == NULL) 1495 return (ENOBUFS); 1496 1497 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1498 MCLGET(m, M_DONTWAIT); 1499 if ((m->m_flags & M_EXT) == 0) { 1500 m_freem(m); 1501 return (ENOBUFS); 1502 } 1503 1504 #ifdef GEM_DEBUG 1505 /* bzero the packet to check DMA */ 1506 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1507 #endif 1508 1509 if (rxs->rxs_mbuf != NULL) 1510 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1511 1512 rxs->rxs_mbuf = m; 1513 1514 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1515 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1516 BUS_DMA_READ|BUS_DMA_NOWAIT); 1517 if (error) { 1518 printf("%s: can't load rx DMA map %d, error = %d\n", 1519 sc->sc_dev.dv_xname, idx, error); 1520 panic("gem_add_rxbuf"); /* XXX */ 1521 } 1522 1523 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1524 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1525 1526 GEM_INIT_RXDESC(sc, idx); 1527 1528 return (0); 1529 } 1530 1531 1532 int 1533 gem_eint(sc, status) 1534 struct gem_softc *sc; 1535 u_int status; 1536 { 1537 char bits[128]; 1538 1539 if ((status & GEM_INTR_MIF) != 0) { 1540 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1541 return (1); 1542 } 1543 1544 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1545 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1546 return (1); 1547 } 1548 1549 1550 int 1551 gem_intr(v) 1552 void *v; 1553 { 1554 struct gem_softc *sc = (struct gem_softc *)v; 1555 bus_space_tag_t t = sc->sc_bustag; 1556 bus_space_handle_t seb = sc->sc_h; 1557 u_int32_t status; 1558 int r = 0; 1559 #ifdef GEM_DEBUG 1560 char bits[128]; 1561 #endif 1562 1563 sc->sc_ev_intr.ev_count++; 1564 1565 status = bus_space_read_4(t, seb, GEM_STATUS); 1566 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 1567 sc->sc_dev.dv_xname, (status >> 19), 1568 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1569 1570 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1571 r |= gem_eint(sc, status); 1572 1573 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 1574 GEM_COUNTER_INCR(sc, sc_ev_txint); 1575 r |= gem_tint(sc); 1576 } 1577 1578 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 1579 GEM_COUNTER_INCR(sc, sc_ev_rxint); 1580 r |= gem_rint(sc); 1581 } 1582 1583 /* We should eventually do more than just print out error stats. */ 1584 if (status & GEM_INTR_TX_MAC) { 1585 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1586 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1587 printf("%s: MAC tx fault, status %x\n", 1588 sc->sc_dev.dv_xname, txstat); 1589 } 1590 if (status & GEM_INTR_RX_MAC) { 1591 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1592 if (rxstat & ~GEM_MAC_RX_DONE) 1593 printf("%s: MAC rx fault, status %x\n", 1594 sc->sc_dev.dv_xname, rxstat); 1595 } 1596 return (r); 1597 } 1598 1599 1600 void 1601 gem_watchdog(ifp) 1602 struct ifnet *ifp; 1603 { 1604 struct gem_softc *sc = ifp->if_softc; 1605 1606 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1607 "GEM_MAC_RX_CONFIG %x\n", 1608 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1609 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1610 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1611 1612 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1613 ++ifp->if_oerrors; 1614 1615 /* Try to get more packets going. */ 1616 gem_start(ifp); 1617 } 1618 1619 /* 1620 * Initialize the MII Management Interface 1621 */ 1622 void 1623 gem_mifinit(sc) 1624 struct gem_softc *sc; 1625 { 1626 bus_space_tag_t t = sc->sc_bustag; 1627 bus_space_handle_t mif = sc->sc_h; 1628 1629 /* Configure the MIF in frame mode */ 1630 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1631 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1632 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1633 } 1634 1635 /* 1636 * MII interface 1637 * 1638 * The GEM MII interface supports at least three different operating modes: 1639 * 1640 * Bitbang mode is implemented using data, clock and output enable registers. 1641 * 1642 * Frame mode is implemented by loading a complete frame into the frame 1643 * register and polling the valid bit for completion. 1644 * 1645 * Polling mode uses the frame register but completion is indicated by 1646 * an interrupt. 1647 * 1648 */ 1649 static int 1650 gem_mii_readreg(self, phy, reg) 1651 struct device *self; 1652 int phy, reg; 1653 { 1654 struct gem_softc *sc = (void *)self; 1655 bus_space_tag_t t = sc->sc_bustag; 1656 bus_space_handle_t mif = sc->sc_h; 1657 int n; 1658 u_int32_t v; 1659 1660 #ifdef GEM_DEBUG1 1661 if (sc->sc_debug) 1662 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1663 #endif 1664 1665 #if 0 1666 /* Select the desired PHY in the MIF configuration register */ 1667 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1668 /* Clear PHY select bit */ 1669 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1670 if (phy == GEM_PHYAD_EXTERNAL) 1671 /* Set PHY select bit to get at external device */ 1672 v |= GEM_MIF_CONFIG_PHY_SEL; 1673 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1674 #endif 1675 1676 /* Construct the frame command */ 1677 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1678 GEM_MIF_FRAME_READ; 1679 1680 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1681 for (n = 0; n < 100; n++) { 1682 DELAY(1); 1683 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1684 if (v & GEM_MIF_FRAME_TA0) 1685 return (v & GEM_MIF_FRAME_DATA); 1686 } 1687 1688 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1689 return (0); 1690 } 1691 1692 static void 1693 gem_mii_writereg(self, phy, reg, val) 1694 struct device *self; 1695 int phy, reg, val; 1696 { 1697 struct gem_softc *sc = (void *)self; 1698 bus_space_tag_t t = sc->sc_bustag; 1699 bus_space_handle_t mif = sc->sc_h; 1700 int n; 1701 u_int32_t v; 1702 1703 #ifdef GEM_DEBUG1 1704 if (sc->sc_debug) 1705 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1706 phy, reg, val); 1707 #endif 1708 1709 #if 0 1710 /* Select the desired PHY in the MIF configuration register */ 1711 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1712 /* Clear PHY select bit */ 1713 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1714 if (phy == GEM_PHYAD_EXTERNAL) 1715 /* Set PHY select bit to get at external device */ 1716 v |= GEM_MIF_CONFIG_PHY_SEL; 1717 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1718 #endif 1719 /* Construct the frame command */ 1720 v = GEM_MIF_FRAME_WRITE | 1721 (phy << GEM_MIF_PHY_SHIFT) | 1722 (reg << GEM_MIF_REG_SHIFT) | 1723 (val & GEM_MIF_FRAME_DATA); 1724 1725 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1726 for (n = 0; n < 100; n++) { 1727 DELAY(1); 1728 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1729 if (v & GEM_MIF_FRAME_TA0) 1730 return; 1731 } 1732 1733 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1734 } 1735 1736 static void 1737 gem_mii_statchg(dev) 1738 struct device *dev; 1739 { 1740 struct gem_softc *sc = (void *)dev; 1741 #ifdef GEM_DEBUG 1742 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1743 #endif 1744 bus_space_tag_t t = sc->sc_bustag; 1745 bus_space_handle_t mac = sc->sc_h; 1746 u_int32_t v; 1747 1748 #ifdef GEM_DEBUG 1749 if (sc->sc_debug) 1750 printf("gem_mii_statchg: status change: phy = %d\n", 1751 sc->sc_phys[instance]); 1752 #endif 1753 1754 1755 /* Set tx full duplex options */ 1756 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1757 delay(10000); /* reg must be cleared and delay before changing. */ 1758 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1759 GEM_MAC_TX_ENABLE; 1760 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1761 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1762 } 1763 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1764 1765 /* XIF Configuration */ 1766 /* We should really calculate all this rather than rely on defaults */ 1767 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1768 v = GEM_MAC_XIF_LINK_LED; 1769 v |= GEM_MAC_XIF_TX_MII_ENA; 1770 1771 /* If an external transceiver is connected, enable its MII drivers */ 1772 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1773 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1774 /* External MII needs echo disable if half duplex. */ 1775 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1776 /* turn on full duplex LED */ 1777 v |= GEM_MAC_XIF_FDPLX_LED; 1778 else 1779 /* half duplex -- disable echo */ 1780 v |= GEM_MAC_XIF_ECHO_DISABL; 1781 1782 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 1783 v |= GEM_MAC_XIF_GMII_MODE; 1784 else 1785 v &= ~GEM_MAC_XIF_GMII_MODE; 1786 } else 1787 /* Internal MII needs buf enable */ 1788 v |= GEM_MAC_XIF_MII_BUF_ENA; 1789 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1790 } 1791 1792 int 1793 gem_mediachange(ifp) 1794 struct ifnet *ifp; 1795 { 1796 struct gem_softc *sc = ifp->if_softc; 1797 1798 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1799 return (EINVAL); 1800 1801 return (mii_mediachg(&sc->sc_mii)); 1802 } 1803 1804 void 1805 gem_mediastatus(ifp, ifmr) 1806 struct ifnet *ifp; 1807 struct ifmediareq *ifmr; 1808 { 1809 struct gem_softc *sc = ifp->if_softc; 1810 1811 if ((ifp->if_flags & IFF_UP) == 0) 1812 return; 1813 1814 mii_pollstat(&sc->sc_mii); 1815 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1816 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1817 } 1818 1819 int gem_ioctldebug = 0; 1820 /* 1821 * Process an ioctl request. 1822 */ 1823 int 1824 gem_ioctl(ifp, cmd, data) 1825 struct ifnet *ifp; 1826 u_long cmd; 1827 caddr_t data; 1828 { 1829 struct gem_softc *sc = ifp->if_softc; 1830 struct ifreq *ifr = (struct ifreq *)data; 1831 int s, error = 0; 1832 1833 s = splnet(); 1834 1835 switch (cmd) { 1836 case SIOCGIFMEDIA: 1837 case SIOCSIFMEDIA: 1838 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1839 break; 1840 1841 default: 1842 error = ether_ioctl(ifp, cmd, data); 1843 if (error == ENETRESET) { 1844 /* 1845 * Multicast list has changed; set the hardware filter 1846 * accordingly. 1847 */ 1848 if (ifp->if_flags & IFF_RUNNING) { 1849 if (gem_ioctldebug) printf("reset1\n"); 1850 gem_init(ifp); 1851 delay(50000); 1852 } 1853 error = 0; 1854 } 1855 break; 1856 } 1857 1858 /* Try to get things going again */ 1859 if (ifp->if_flags & IFF_UP) { 1860 if (gem_ioctldebug) printf("start\n"); 1861 gem_start(ifp); 1862 } 1863 splx(s); 1864 return (error); 1865 } 1866 1867 1868 void 1869 gem_shutdown(arg) 1870 void *arg; 1871 { 1872 struct gem_softc *sc = (struct gem_softc *)arg; 1873 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1874 1875 gem_stop(ifp, 1); 1876 } 1877 1878 /* 1879 * Set up the logical address filter. 1880 */ 1881 void 1882 gem_setladrf(sc) 1883 struct gem_softc *sc; 1884 { 1885 struct ethercom *ec = &sc->sc_ethercom; 1886 struct ifnet *ifp = &ec->ec_if; 1887 struct ether_multi *enm; 1888 struct ether_multistep step; 1889 bus_space_tag_t t = sc->sc_bustag; 1890 bus_space_handle_t h = sc->sc_h; 1891 u_int32_t crc; 1892 u_int32_t hash[16]; 1893 u_int32_t v; 1894 int i; 1895 1896 /* Get current RX configuration */ 1897 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1898 1899 /* 1900 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1901 * and hash filter. Depending on the case, the right bit will be 1902 * enabled. 1903 */ 1904 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 1905 GEM_MAC_RX_PROMISC_GRP); 1906 1907 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1908 /* Turn on promiscuous mode */ 1909 v |= GEM_MAC_RX_PROMISCUOUS; 1910 ifp->if_flags |= IFF_ALLMULTI; 1911 goto chipit; 1912 } 1913 1914 /* 1915 * Set up multicast address filter by passing all multicast addresses 1916 * through a crc generator, and then using the high order 8 bits as an 1917 * index into the 256 bit logical address filter. The high order 4 1918 * bits select the word, while the other 4 bits select the bit within 1919 * the word (where bit 0 is the MSB). 1920 */ 1921 1922 /* Clear hash table */ 1923 memset(hash, 0, sizeof(hash)); 1924 1925 ETHER_FIRST_MULTI(step, ec, enm); 1926 while (enm != NULL) { 1927 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1928 /* 1929 * We must listen to a range of multicast addresses. 1930 * For now, just accept all multicasts, rather than 1931 * trying to set only those filter bits needed to match 1932 * the range. (At this time, the only use of address 1933 * ranges is for IP multicast routing, for which the 1934 * range is big enough to require all bits set.) 1935 * XXX use the addr filter for this 1936 */ 1937 ifp->if_flags |= IFF_ALLMULTI; 1938 v |= GEM_MAC_RX_PROMISC_GRP; 1939 goto chipit; 1940 } 1941 1942 /* Get the LE CRC32 of the address */ 1943 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1944 1945 /* Just want the 8 most significant bits. */ 1946 crc >>= 24; 1947 1948 /* Set the corresponding bit in the filter. */ 1949 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1950 1951 ETHER_NEXT_MULTI(step, enm); 1952 } 1953 1954 v |= GEM_MAC_RX_HASH_FILTER; 1955 ifp->if_flags &= ~IFF_ALLMULTI; 1956 1957 /* Now load the hash table into the chip (if we are using it) */ 1958 for (i = 0; i < 16; i++) { 1959 bus_space_write_4(t, h, 1960 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 1961 hash[i]); 1962 } 1963 1964 chipit: 1965 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1966 } 1967 1968 #if notyet 1969 1970 /* 1971 * gem_power: 1972 * 1973 * Power management (suspend/resume) hook. 1974 */ 1975 void 1976 gem_power(why, arg) 1977 int why; 1978 void *arg; 1979 { 1980 struct gem_softc *sc = arg; 1981 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1982 int s; 1983 1984 s = splnet(); 1985 switch (why) { 1986 case PWR_SUSPEND: 1987 case PWR_STANDBY: 1988 gem_stop(ifp, 1); 1989 if (sc->sc_power != NULL) 1990 (*sc->sc_power)(sc, why); 1991 break; 1992 case PWR_RESUME: 1993 if (ifp->if_flags & IFF_UP) { 1994 if (sc->sc_power != NULL) 1995 (*sc->sc_power)(sc, why); 1996 gem_init(ifp); 1997 } 1998 break; 1999 case PWR_SOFTSUSPEND: 2000 case PWR_SOFTSTANDBY: 2001 case PWR_SOFTRESUME: 2002 break; 2003 } 2004 splx(s); 2005 } 2006 #endif 2007