1 /* $NetBSD: gem.c,v 1.40 2005/05/16 15:56:38 bouyer Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.40 2005/05/16 15:56:38 bouyer Exp $"); 38 39 #include "opt_inet.h" 40 #include "bpfilter.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/syslog.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 54 #include <machine/endian.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #endif 75 76 #include <machine/bus.h> 77 #include <machine/intr.h> 78 79 #include <dev/mii/mii.h> 80 #include <dev/mii/miivar.h> 81 #include <dev/mii/mii_bitbang.h> 82 83 #include <dev/ic/gemreg.h> 84 #include <dev/ic/gemvar.h> 85 86 #define TRIES 10000 87 88 void gem_start(struct ifnet *); 89 void gem_stop(struct ifnet *, int); 90 int gem_ioctl(struct ifnet *, u_long, caddr_t); 91 void gem_tick(void *); 92 void gem_watchdog(struct ifnet *); 93 void gem_shutdown(void *); 94 int gem_init(struct ifnet *); 95 void gem_init_regs(struct gem_softc *sc); 96 static int gem_ringsize(int sz); 97 int gem_meminit(struct gem_softc *); 98 void gem_mifinit(struct gem_softc *); 99 void gem_reset(struct gem_softc *); 100 int gem_reset_rx(struct gem_softc *sc); 101 int gem_reset_tx(struct gem_softc *sc); 102 int gem_disable_rx(struct gem_softc *sc); 103 int gem_disable_tx(struct gem_softc *sc); 104 void gem_rxdrain(struct gem_softc *sc); 105 int gem_add_rxbuf(struct gem_softc *sc, int idx); 106 void gem_setladrf(struct gem_softc *); 107 108 /* MII methods & callbacks */ 109 static int gem_mii_readreg(struct device *, int, int); 110 static void gem_mii_writereg(struct device *, int, int, int); 111 static void gem_mii_statchg(struct device *); 112 113 int gem_mediachange(struct ifnet *); 114 void gem_mediastatus(struct ifnet *, struct ifmediareq *); 115 116 struct mbuf *gem_get(struct gem_softc *, int, int); 117 int gem_put(struct gem_softc *, int, struct mbuf *); 118 void gem_read(struct gem_softc *, int, int); 119 int gem_eint(struct gem_softc *, u_int); 120 int gem_rint(struct gem_softc *); 121 int gem_tint(struct gem_softc *); 122 void gem_power(int, void *); 123 124 #ifdef GEM_DEBUG 125 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 126 printf x 127 #else 128 #define DPRINTF(sc, x) /* nothing */ 129 #endif 130 131 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 132 133 134 /* 135 * gem_attach: 136 * 137 * Attach a Gem interface to the system. 138 */ 139 void 140 gem_attach(sc, enaddr) 141 struct gem_softc *sc; 142 const uint8_t *enaddr; 143 { 144 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 145 struct mii_data *mii = &sc->sc_mii; 146 struct mii_softc *child; 147 struct ifmedia_entry *ifm; 148 int i, error; 149 u_int32_t v; 150 char *nullbuf; 151 152 /* Make sure the chip is stopped. */ 153 ifp->if_softc = sc; 154 gem_reset(sc); 155 156 /* 157 * Allocate the control data structures, and create and load the 158 * DMA map for it. gem_control_data is 9216 bytes, we have space for 159 * the padding buffer in the bus_dmamem_alloc()'d memory. 160 */ 161 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 162 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 163 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 164 aprint_error( 165 "%s: unable to allocate control data, error = %d\n", 166 sc->sc_dev.dv_xname, error); 167 goto fail_0; 168 } 169 170 /* XXX should map this in with correct endianness */ 171 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 172 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 173 BUS_DMA_COHERENT)) != 0) { 174 aprint_error("%s: unable to map control data, error = %d\n", 175 sc->sc_dev.dv_xname, error); 176 goto fail_1; 177 } 178 179 nullbuf = 180 (caddr_t)sc->sc_control_data + sizeof(struct gem_control_data); 181 182 if ((error = bus_dmamap_create(sc->sc_dmatag, 183 sizeof(struct gem_control_data), 1, 184 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 185 aprint_error("%s: unable to create control data DMA map, " 186 "error = %d\n", sc->sc_dev.dv_xname, error); 187 goto fail_2; 188 } 189 190 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 191 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 192 0)) != 0) { 193 aprint_error( 194 "%s: unable to load control data DMA map, error = %d\n", 195 sc->sc_dev.dv_xname, error); 196 goto fail_3; 197 } 198 199 memset(nullbuf, 0, ETHER_MIN_TX); 200 if ((error = bus_dmamap_create(sc->sc_dmatag, 201 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 202 aprint_error("%s: unable to create padding DMA map, " 203 "error = %d\n", sc->sc_dev.dv_xname, error); 204 goto fail_4; 205 } 206 207 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 208 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 209 aprint_error( 210 "%s: unable to load padding DMA map, error = %d\n", 211 sc->sc_dev.dv_xname, error); 212 goto fail_5; 213 } 214 215 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 216 BUS_DMASYNC_PREWRITE); 217 218 /* 219 * Initialize the transmit job descriptors. 220 */ 221 SIMPLEQ_INIT(&sc->sc_txfreeq); 222 SIMPLEQ_INIT(&sc->sc_txdirtyq); 223 224 /* 225 * Create the transmit buffer DMA maps. 226 */ 227 for (i = 0; i < GEM_TXQUEUELEN; i++) { 228 struct gem_txsoft *txs; 229 230 txs = &sc->sc_txsoft[i]; 231 txs->txs_mbuf = NULL; 232 if ((error = bus_dmamap_create(sc->sc_dmatag, 233 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 234 ETHER_MAX_LEN_JUMBO, 0, 0, 235 &txs->txs_dmamap)) != 0) { 236 aprint_error("%s: unable to create tx DMA map %d, " 237 "error = %d\n", sc->sc_dev.dv_xname, i, error); 238 goto fail_6; 239 } 240 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 241 } 242 243 /* 244 * Create the receive buffer DMA maps. 245 */ 246 for (i = 0; i < GEM_NRXDESC; i++) { 247 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 248 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 249 aprint_error("%s: unable to create rx DMA map %d, " 250 "error = %d\n", sc->sc_dev.dv_xname, i, error); 251 goto fail_7; 252 } 253 sc->sc_rxsoft[i].rxs_mbuf = NULL; 254 } 255 256 /* 257 * From this point forward, the attachment cannot fail. A failure 258 * before this point releases all resources that may have been 259 * allocated. 260 */ 261 262 /* Announce ourselves. */ 263 aprint_normal("%s: Ethernet address %s", sc->sc_dev.dv_xname, 264 ether_sprintf(enaddr)); 265 266 /* Get RX FIFO size */ 267 sc->sc_rxfifosize = 64 * 268 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 269 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 270 271 /* Get TX FIFO size */ 272 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 273 aprint_normal(", %uKB TX fifo\n", v / 16); 274 275 /* Initialize ifnet structure. */ 276 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 277 ifp->if_softc = sc; 278 ifp->if_flags = 279 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 280 ifp->if_capabilities |= 281 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 282 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 283 ifp->if_start = gem_start; 284 ifp->if_ioctl = gem_ioctl; 285 ifp->if_watchdog = gem_watchdog; 286 ifp->if_stop = gem_stop; 287 ifp->if_init = gem_init; 288 IFQ_SET_READY(&ifp->if_snd); 289 290 /* Initialize ifmedia structures and MII info */ 291 mii->mii_ifp = ifp; 292 mii->mii_readreg = gem_mii_readreg; 293 mii->mii_writereg = gem_mii_writereg; 294 mii->mii_statchg = gem_mii_statchg; 295 296 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_mediachange, gem_mediastatus); 297 298 gem_mifinit(sc); 299 300 mii_attach(&sc->sc_dev, mii, 0xffffffff, 301 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 302 303 child = LIST_FIRST(&mii->mii_phys); 304 if (child == NULL) { 305 /* No PHY attached */ 306 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 307 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 308 } else { 309 /* 310 * Walk along the list of attached MII devices and 311 * establish an `MII instance' to `phy number' 312 * mapping. We'll use this mapping in media change 313 * requests to determine which phy to use to program 314 * the MIF configuration register. 315 */ 316 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 317 /* 318 * Note: we support just two PHYs: the built-in 319 * internal device and an external on the MII 320 * connector. 321 */ 322 if (child->mii_phy > 1 || child->mii_inst > 1) { 323 aprint_error( 324 "%s: cannot accomodate MII device %s" 325 " at phy %d, instance %d\n", 326 sc->sc_dev.dv_xname, 327 child->mii_dev.dv_xname, 328 child->mii_phy, child->mii_inst); 329 continue; 330 } 331 332 sc->sc_phys[child->mii_inst] = child->mii_phy; 333 } 334 335 /* 336 * Now select and activate the PHY we will use. 337 * 338 * The order of preference is External (MDI1), 339 * Internal (MDI0), Serial Link (no MII). 340 */ 341 if (sc->sc_phys[1]) { 342 #ifdef DEBUG 343 aprint_debug("using external phy\n"); 344 #endif 345 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 346 } else { 347 #ifdef DEBUG 348 aprint_debug("using internal phy\n"); 349 #endif 350 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 351 } 352 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 353 sc->sc_mif_config); 354 355 /* 356 * XXX - we can really do the following ONLY if the 357 * phy indeed has the auto negotiation capability!! 358 */ 359 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 360 } 361 362 /* 363 * If we support GigE media, we support jumbo frames too. 364 * Unless we are Apple. 365 */ 366 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 367 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 368 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 369 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 370 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 371 if (sc->sc_variant != GEM_APPLE_GMAC) 372 sc->sc_ethercom.ec_capabilities 373 |= ETHERCAP_JUMBO_MTU; 374 375 sc->sc_flags |= GEM_GIGABIT; 376 break; 377 } 378 } 379 380 /* claim 802.1q capability */ 381 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 382 383 /* Attach the interface. */ 384 if_attach(ifp); 385 ether_ifattach(ifp, enaddr); 386 387 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 388 if (sc->sc_sh == NULL) 389 panic("gem_config: can't establish shutdownhook"); 390 391 #if NRND > 0 392 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 393 RND_TYPE_NET, 0); 394 #endif 395 396 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 397 NULL, sc->sc_dev.dv_xname, "interrupts"); 398 #ifdef GEM_COUNTERS 399 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 400 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "tx interrupts"); 401 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 402 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "rx interrupts"); 403 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 404 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx ring full"); 405 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 406 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx malloc failure"); 407 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 408 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 0desc"); 409 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 410 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 1desc"); 411 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 412 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 2desc"); 413 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 414 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 3desc"); 415 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 416 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >3desc"); 417 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 418 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >7desc"); 419 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 420 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >15desc"); 421 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 422 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >31desc"); 423 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 424 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >63desc"); 425 #endif 426 427 #if notyet 428 /* 429 * Add a suspend hook to make sure we come back up after a 430 * resume. 431 */ 432 sc->sc_powerhook = powerhook_establish(gem_power, sc); 433 if (sc->sc_powerhook == NULL) 434 aprint_error("%s: WARNING: unable to establish power hook\n", 435 sc->sc_dev.dv_xname); 436 #endif 437 438 callout_init(&sc->sc_tick_ch); 439 return; 440 441 /* 442 * Free any resources we've allocated during the failed attach 443 * attempt. Do this in reverse order and fall through. 444 */ 445 fail_7: 446 for (i = 0; i < GEM_NRXDESC; i++) { 447 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 448 bus_dmamap_destroy(sc->sc_dmatag, 449 sc->sc_rxsoft[i].rxs_dmamap); 450 } 451 fail_6: 452 for (i = 0; i < GEM_TXQUEUELEN; i++) { 453 if (sc->sc_txsoft[i].txs_dmamap != NULL) 454 bus_dmamap_destroy(sc->sc_dmatag, 455 sc->sc_txsoft[i].txs_dmamap); 456 } 457 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 458 fail_5: 459 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 460 fail_4: 461 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)nullbuf, ETHER_MIN_TX); 462 fail_3: 463 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 464 fail_2: 465 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 466 sizeof(struct gem_control_data)); 467 fail_1: 468 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 469 fail_0: 470 return; 471 } 472 473 474 void 475 gem_tick(arg) 476 void *arg; 477 { 478 struct gem_softc *sc = arg; 479 int s; 480 481 s = splnet(); 482 mii_tick(&sc->sc_mii); 483 splx(s); 484 485 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 486 487 } 488 489 void 490 gem_reset(sc) 491 struct gem_softc *sc; 492 { 493 bus_space_tag_t t = sc->sc_bustag; 494 bus_space_handle_t h = sc->sc_h; 495 int i; 496 int s; 497 498 s = splnet(); 499 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 500 gem_reset_rx(sc); 501 gem_reset_tx(sc); 502 503 /* Do a full reset */ 504 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 505 for (i=TRIES; i--; delay(100)) 506 if ((bus_space_read_4(t, h, GEM_RESET) & 507 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 508 break; 509 if ((bus_space_read_4(t, h, GEM_RESET) & 510 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 511 printf("%s: cannot reset device\n", 512 sc->sc_dev.dv_xname); 513 } 514 splx(s); 515 } 516 517 518 /* 519 * gem_rxdrain: 520 * 521 * Drain the receive queue. 522 */ 523 void 524 gem_rxdrain(struct gem_softc *sc) 525 { 526 struct gem_rxsoft *rxs; 527 int i; 528 529 for (i = 0; i < GEM_NRXDESC; i++) { 530 rxs = &sc->sc_rxsoft[i]; 531 if (rxs->rxs_mbuf != NULL) { 532 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 533 m_freem(rxs->rxs_mbuf); 534 rxs->rxs_mbuf = NULL; 535 } 536 } 537 } 538 539 /* 540 * Reset the whole thing. 541 */ 542 void 543 gem_stop(struct ifnet *ifp, int disable) 544 { 545 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 546 struct gem_txsoft *txs; 547 548 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 549 550 callout_stop(&sc->sc_tick_ch); 551 mii_down(&sc->sc_mii); 552 553 /* XXX - Should we reset these instead? */ 554 gem_disable_rx(sc); 555 gem_disable_tx(sc); 556 557 /* 558 * Release any queued transmit buffers. 559 */ 560 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 561 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 562 if (txs->txs_mbuf != NULL) { 563 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 564 m_freem(txs->txs_mbuf); 565 txs->txs_mbuf = NULL; 566 } 567 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 568 } 569 570 if (disable) { 571 gem_rxdrain(sc); 572 } 573 574 /* 575 * Mark the interface down and cancel the watchdog timer. 576 */ 577 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 578 ifp->if_timer = 0; 579 } 580 581 582 /* 583 * Reset the receiver 584 */ 585 int 586 gem_reset_rx(struct gem_softc *sc) 587 { 588 bus_space_tag_t t = sc->sc_bustag; 589 bus_space_handle_t h = sc->sc_h; 590 int i; 591 592 593 /* 594 * Resetting while DMA is in progress can cause a bus hang, so we 595 * disable DMA first. 596 */ 597 gem_disable_rx(sc); 598 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 599 /* Wait till it finishes */ 600 for (i=TRIES; i--; delay(100)) 601 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 602 break; 603 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 604 printf("%s: cannot disable read DMA\n", 605 sc->sc_dev.dv_xname); 606 607 /* Wait 5ms extra. */ 608 delay(5000); 609 610 /* Finally, reset the ERX */ 611 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 612 /* Wait till it finishes */ 613 for (i=TRIES; i--; delay(100)) 614 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 615 break; 616 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 617 printf("%s: cannot reset receiver\n", 618 sc->sc_dev.dv_xname); 619 return (1); 620 } 621 return (0); 622 } 623 624 625 /* 626 * Reset the transmitter 627 */ 628 int 629 gem_reset_tx(struct gem_softc *sc) 630 { 631 bus_space_tag_t t = sc->sc_bustag; 632 bus_space_handle_t h = sc->sc_h; 633 int i; 634 635 /* 636 * Resetting while DMA is in progress can cause a bus hang, so we 637 * disable DMA first. 638 */ 639 gem_disable_tx(sc); 640 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 641 /* Wait till it finishes */ 642 for (i=TRIES; i--; delay(100)) 643 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 644 break; 645 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 646 printf("%s: cannot disable read DMA\n", 647 sc->sc_dev.dv_xname); 648 649 /* Wait 5ms extra. */ 650 delay(5000); 651 652 /* Finally, reset the ETX */ 653 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 654 /* Wait till it finishes */ 655 for (i=TRIES; i--; delay(100)) 656 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 657 break; 658 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 659 printf("%s: cannot reset receiver\n", 660 sc->sc_dev.dv_xname); 661 return (1); 662 } 663 return (0); 664 } 665 666 /* 667 * disable receiver. 668 */ 669 int 670 gem_disable_rx(struct gem_softc *sc) 671 { 672 bus_space_tag_t t = sc->sc_bustag; 673 bus_space_handle_t h = sc->sc_h; 674 int i; 675 u_int32_t cfg; 676 677 /* Flip the enable bit */ 678 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 679 cfg &= ~GEM_MAC_RX_ENABLE; 680 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 681 682 /* Wait for it to finish */ 683 for (i=TRIES; i--; delay(100)) 684 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 685 GEM_MAC_RX_ENABLE) == 0) 686 return (0); 687 return (1); 688 } 689 690 /* 691 * disable transmitter. 692 */ 693 int 694 gem_disable_tx(struct gem_softc *sc) 695 { 696 bus_space_tag_t t = sc->sc_bustag; 697 bus_space_handle_t h = sc->sc_h; 698 int i; 699 u_int32_t cfg; 700 701 /* Flip the enable bit */ 702 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 703 cfg &= ~GEM_MAC_TX_ENABLE; 704 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 705 706 /* Wait for it to finish */ 707 for (i=TRIES; i--; delay(100)) 708 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 709 GEM_MAC_TX_ENABLE) == 0) 710 return (0); 711 return (1); 712 } 713 714 /* 715 * Initialize interface. 716 */ 717 int 718 gem_meminit(struct gem_softc *sc) 719 { 720 struct gem_rxsoft *rxs; 721 int i, error; 722 723 /* 724 * Initialize the transmit descriptor ring. 725 */ 726 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 727 for (i = 0; i < GEM_NTXDESC; i++) { 728 sc->sc_txdescs[i].gd_flags = 0; 729 sc->sc_txdescs[i].gd_addr = 0; 730 } 731 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 732 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 733 sc->sc_txfree = GEM_NTXDESC-1; 734 sc->sc_txnext = 0; 735 sc->sc_txwin = 0; 736 737 /* 738 * Initialize the receive descriptor and receive job 739 * descriptor rings. 740 */ 741 for (i = 0; i < GEM_NRXDESC; i++) { 742 rxs = &sc->sc_rxsoft[i]; 743 if (rxs->rxs_mbuf == NULL) { 744 if ((error = gem_add_rxbuf(sc, i)) != 0) { 745 printf("%s: unable to allocate or map rx " 746 "buffer %d, error = %d\n", 747 sc->sc_dev.dv_xname, i, error); 748 /* 749 * XXX Should attempt to run with fewer receive 750 * XXX buffers instead of just failing. 751 */ 752 gem_rxdrain(sc); 753 return (1); 754 } 755 } else 756 GEM_INIT_RXDESC(sc, i); 757 } 758 sc->sc_rxptr = 0; 759 760 return (0); 761 } 762 763 static int 764 gem_ringsize(int sz) 765 { 766 switch (sz) { 767 case 32: 768 return GEM_RING_SZ_32; 769 case 64: 770 return GEM_RING_SZ_64; 771 case 128: 772 return GEM_RING_SZ_128; 773 case 256: 774 return GEM_RING_SZ_256; 775 case 512: 776 return GEM_RING_SZ_512; 777 case 1024: 778 return GEM_RING_SZ_1024; 779 case 2048: 780 return GEM_RING_SZ_2048; 781 case 4096: 782 return GEM_RING_SZ_4096; 783 case 8192: 784 return GEM_RING_SZ_8192; 785 default: 786 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 787 return GEM_RING_SZ_32; 788 } 789 } 790 791 /* 792 * Initialization of interface; set up initialization block 793 * and transmit/receive descriptor rings. 794 */ 795 int 796 gem_init(struct ifnet *ifp) 797 { 798 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 799 bus_space_tag_t t = sc->sc_bustag; 800 bus_space_handle_t h = sc->sc_h; 801 int s; 802 u_int max_frame_size; 803 u_int32_t v; 804 805 s = splnet(); 806 807 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 808 /* 809 * Initialization sequence. The numbered steps below correspond 810 * to the sequence outlined in section 6.3.5.1 in the Ethernet 811 * Channel Engine manual (part of the PCIO manual). 812 * See also the STP2002-STQ document from Sun Microsystems. 813 */ 814 815 /* step 1 & 2. Reset the Ethernet Channel */ 816 gem_stop(ifp, 0); 817 gem_reset(sc); 818 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 819 820 /* Re-initialize the MIF */ 821 gem_mifinit(sc); 822 823 /* Call MI reset function if any */ 824 if (sc->sc_hwreset) 825 (*sc->sc_hwreset)(sc); 826 827 /* step 3. Setup data structures in host memory */ 828 gem_meminit(sc); 829 830 /* step 4. TX MAC registers & counters */ 831 gem_init_regs(sc); 832 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 833 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 834 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 835 max_frame_size += ETHER_VLAN_ENCAP_LEN; 836 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 837 max_frame_size|/* burst size */(0x2000<<16)); 838 839 /* step 5. RX MAC registers & counters */ 840 gem_setladrf(sc); 841 842 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 843 /* NOTE: we use only 32-bit DMA addresses here. */ 844 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 845 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 846 847 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 848 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 849 850 /* step 8. Global Configuration & Interrupt Mask */ 851 bus_space_write_4(t, h, GEM_INTMASK, 852 ~(GEM_INTR_TX_INTME| 853 GEM_INTR_TX_EMPTY| 854 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 855 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 856 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 857 GEM_INTR_BERR)); 858 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 859 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 860 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 861 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 862 863 /* step 9. ETX Configuration: use mostly default values */ 864 865 /* Enable DMA */ 866 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 867 bus_space_write_4(t, h, GEM_TX_CONFIG, 868 v|GEM_TX_CONFIG_TXDMA_EN| 869 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 870 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 871 872 /* step 10. ERX Configuration */ 873 874 /* Encode Receive Descriptor ring size: four possible values */ 875 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 876 877 /* Set receive h/w checksum offset */ 878 #ifdef INET 879 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 880 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 881 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 882 #endif 883 884 /* Enable DMA */ 885 bus_space_write_4(t, h, GEM_RX_CONFIG, 886 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 887 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN); 888 889 /* 890 * The following value is for an OFF Threshold of about 3/4 full 891 * and an ON Threshold of 1/4 full. 892 */ 893 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 894 (3 * sc->sc_rxfifosize / 256) | 895 ( (sc->sc_rxfifosize / 256) << 12)); 896 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 897 898 /* step 11. Configure Media */ 899 mii_mediachg(&sc->sc_mii); 900 901 /* XXXX Serial link needs a whole different setup. */ 902 903 904 /* step 12. RX_MAC Configuration Register */ 905 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 906 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 907 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 908 909 /* step 14. Issue Transmit Pending command */ 910 911 /* Call MI initialization function if any */ 912 if (sc->sc_hwinit) 913 (*sc->sc_hwinit)(sc); 914 915 916 /* step 15. Give the reciever a swift kick */ 917 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 918 919 /* Start the one second timer. */ 920 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 921 922 ifp->if_flags |= IFF_RUNNING; 923 ifp->if_flags &= ~IFF_OACTIVE; 924 ifp->if_timer = 0; 925 splx(s); 926 927 return (0); 928 } 929 930 void 931 gem_init_regs(struct gem_softc *sc) 932 { 933 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 934 bus_space_tag_t t = sc->sc_bustag; 935 bus_space_handle_t h = sc->sc_h; 936 const u_char *laddr = LLADDR(ifp->if_sadl); 937 u_int32_t v; 938 939 /* These regs are not cleared on reset */ 940 if (!sc->sc_inited) { 941 942 /* Wooo. Magic values. */ 943 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 944 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 945 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 946 947 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 948 /* Max frame and max burst size */ 949 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 950 ETHER_MAX_LEN | (0x2000<<16)); 951 952 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 953 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 954 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 955 /* Dunno.... */ 956 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 957 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 958 ((laddr[5]<<8)|laddr[4])&0x3ff); 959 960 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 961 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 962 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 963 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 964 965 /* MAC control addr set to 01:80:c2:00:00:01 */ 966 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 967 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 968 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 969 970 /* MAC filter addr set to 0:0:0:0:0:0 */ 971 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 972 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 973 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 974 975 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 976 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 977 978 sc->sc_inited = 1; 979 } 980 981 /* Counters need to be zeroed */ 982 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 983 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 984 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 985 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 986 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 987 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 988 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 989 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 990 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 991 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 992 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 993 994 /* Un-pause stuff */ 995 #if 0 996 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 997 #else 998 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 999 #endif 1000 1001 /* 1002 * Set the station address. 1003 */ 1004 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1005 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1006 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1007 1008 #if 0 1009 if (sc->sc_variant != APPLE_GMAC) 1010 return; 1011 #endif 1012 1013 /* 1014 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1015 */ 1016 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1017 v = GEM_MAC_XIF_TX_MII_ENA; 1018 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1019 v |= GEM_MAC_XIF_FDPLX_LED; 1020 if (sc->sc_flags & GEM_GIGABIT) 1021 v |= GEM_MAC_XIF_GMII_MODE; 1022 } 1023 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1024 } 1025 1026 void 1027 gem_start(ifp) 1028 struct ifnet *ifp; 1029 { 1030 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1031 struct mbuf *m0, *m; 1032 struct gem_txsoft *txs, *last_txs; 1033 bus_dmamap_t dmamap; 1034 int error, firsttx, nexttx, lasttx = -1, ofree, seg; 1035 uint64_t flags = 0; 1036 1037 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1038 return; 1039 1040 /* 1041 * Remember the previous number of free descriptors and 1042 * the first descriptor we'll use. 1043 */ 1044 ofree = sc->sc_txfree; 1045 firsttx = sc->sc_txnext; 1046 1047 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1048 sc->sc_dev.dv_xname, ofree, firsttx)); 1049 1050 /* 1051 * Loop through the send queue, setting up transmit descriptors 1052 * until we drain the queue, or use up all available transmit 1053 * descriptors. 1054 */ 1055 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1056 sc->sc_txfree != 0) { 1057 /* 1058 * Grab a packet off the queue. 1059 */ 1060 IFQ_POLL(&ifp->if_snd, m0); 1061 if (m0 == NULL) 1062 break; 1063 m = NULL; 1064 1065 dmamap = txs->txs_dmamap; 1066 1067 /* 1068 * Load the DMA map. If this fails, the packet either 1069 * didn't fit in the alloted number of segments, or we were 1070 * short on resources. In this case, we'll copy and try 1071 * again. 1072 */ 1073 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1074 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1075 (m0->m_pkthdr.len < ETHER_MIN_TX && 1076 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1077 if (m0->m_pkthdr.len > MCLBYTES) { 1078 printf("%s: unable to allocate jumbo Tx " 1079 "cluster\n", sc->sc_dev.dv_xname); 1080 IFQ_DEQUEUE(&ifp->if_snd, m0); 1081 m_freem(m0); 1082 continue; 1083 } 1084 MGETHDR(m, M_DONTWAIT, MT_DATA); 1085 if (m == NULL) { 1086 printf("%s: unable to allocate Tx mbuf\n", 1087 sc->sc_dev.dv_xname); 1088 break; 1089 } 1090 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1091 if (m0->m_pkthdr.len > MHLEN) { 1092 MCLGET(m, M_DONTWAIT); 1093 if ((m->m_flags & M_EXT) == 0) { 1094 printf("%s: unable to allocate Tx " 1095 "cluster\n", sc->sc_dev.dv_xname); 1096 m_freem(m); 1097 break; 1098 } 1099 } 1100 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1101 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1102 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1103 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1104 if (error) { 1105 printf("%s: unable to load Tx buffer, " 1106 "error = %d\n", sc->sc_dev.dv_xname, error); 1107 break; 1108 } 1109 } 1110 1111 /* 1112 * Ensure we have enough descriptors free to describe 1113 * the packet. 1114 */ 1115 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1116 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1117 /* 1118 * Not enough free descriptors to transmit this 1119 * packet. We haven't committed to anything yet, 1120 * so just unload the DMA map, put the packet 1121 * back on the queue, and punt. Notify the upper 1122 * layer that there are no more slots left. 1123 * 1124 * XXX We could allocate an mbuf and copy, but 1125 * XXX it is worth it? 1126 */ 1127 ifp->if_flags |= IFF_OACTIVE; 1128 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1129 if (m != NULL) 1130 m_freem(m); 1131 break; 1132 } 1133 1134 IFQ_DEQUEUE(&ifp->if_snd, m0); 1135 if (m != NULL) { 1136 m_freem(m0); 1137 m0 = m; 1138 } 1139 1140 /* 1141 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1142 */ 1143 1144 /* Sync the DMA map. */ 1145 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1146 BUS_DMASYNC_PREWRITE); 1147 1148 /* 1149 * Initialize the transmit descriptors. 1150 */ 1151 for (nexttx = sc->sc_txnext, seg = 0; 1152 seg < dmamap->dm_nsegs; 1153 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1154 1155 /* 1156 * If this is the first descriptor we're 1157 * enqueueing, set the start of packet flag, 1158 * and the checksum stuff if we want the hardware 1159 * to do it. 1160 */ 1161 sc->sc_txdescs[nexttx].gd_addr = 1162 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1163 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1164 if (nexttx == firsttx) { 1165 flags |= GEM_TD_START_OF_PACKET; 1166 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1167 sc->sc_txwin = 0; 1168 flags |= GEM_TD_INTERRUPT_ME; 1169 } 1170 1171 #ifdef INET 1172 /* h/w checksum */ 1173 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | 1174 M_CSUM_UDPv4) && m0->m_pkthdr.csum_flags & 1175 (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1176 struct ether_header *eh; 1177 uint16_t offset, start; 1178 1179 eh = mtod(m0, struct ether_header *); 1180 switch (ntohs(eh->ether_type)) { 1181 case ETHERTYPE_IP: 1182 start = ETHER_HDR_LEN; 1183 break; 1184 case ETHERTYPE_VLAN: 1185 start = ETHER_HDR_LEN + 1186 ETHER_VLAN_ENCAP_LEN; 1187 break; 1188 default: 1189 /* unsupported, drop it */ 1190 m_free(m0); 1191 continue; 1192 } 1193 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1194 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1195 flags |= (start << 1196 GEM_TD_CXSUM_STARTSHFT) | 1197 (offset << 1198 GEM_TD_CXSUM_STUFFSHFT) | 1199 GEM_TD_CXSUM_ENABLE; 1200 } 1201 #endif 1202 } 1203 if (seg == dmamap->dm_nsegs - 1) { 1204 flags |= GEM_TD_END_OF_PACKET; 1205 } else { 1206 /* last flag set outside of loop */ 1207 sc->sc_txdescs[nexttx].gd_flags = 1208 GEM_DMA_WRITE(sc, flags); 1209 } 1210 lasttx = nexttx; 1211 } 1212 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1213 /* add padding buffer at end of chain */ 1214 flags &= ~GEM_TD_END_OF_PACKET; 1215 sc->sc_txdescs[lasttx].gd_flags = 1216 GEM_DMA_WRITE(sc, flags); 1217 1218 sc->sc_txdescs[nexttx].gd_addr = 1219 GEM_DMA_WRITE(sc, 1220 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1221 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1222 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1223 lasttx = nexttx; 1224 nexttx = GEM_NEXTTX(nexttx); 1225 seg++; 1226 } 1227 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1228 1229 KASSERT(lasttx != -1); 1230 1231 /* 1232 * Store a pointer to the packet so we can free it later, 1233 * and remember what txdirty will be once the packet is 1234 * done. 1235 */ 1236 txs->txs_mbuf = m0; 1237 txs->txs_firstdesc = sc->sc_txnext; 1238 txs->txs_lastdesc = lasttx; 1239 txs->txs_ndescs = seg; 1240 1241 #ifdef GEM_DEBUG 1242 if (ifp->if_flags & IFF_DEBUG) { 1243 printf(" gem_start %p transmit chain:\n", txs); 1244 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1245 printf("descriptor %d:\t", seg); 1246 printf("gd_flags: 0x%016llx\t", (long long) 1247 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1248 printf("gd_addr: 0x%016llx\n", (long long) 1249 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1250 if (seg == lasttx) 1251 break; 1252 } 1253 } 1254 #endif 1255 1256 /* Sync the descriptors we're using. */ 1257 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1258 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1259 1260 /* Advance the tx pointer. */ 1261 sc->sc_txfree -= txs->txs_ndescs; 1262 sc->sc_txnext = nexttx; 1263 1264 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1265 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1266 1267 last_txs = txs; 1268 1269 #if NBPFILTER > 0 1270 /* 1271 * Pass the packet to any BPF listeners. 1272 */ 1273 if (ifp->if_bpf) 1274 bpf_mtap(ifp->if_bpf, m0); 1275 #endif /* NBPFILTER > 0 */ 1276 } 1277 1278 if (txs == NULL || sc->sc_txfree == 0) { 1279 /* No more slots left; notify upper layer. */ 1280 ifp->if_flags |= IFF_OACTIVE; 1281 } 1282 1283 if (sc->sc_txfree != ofree) { 1284 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1285 sc->sc_dev.dv_xname, lasttx, firsttx)); 1286 /* 1287 * The entire packet chain is set up. 1288 * Kick the transmitter. 1289 */ 1290 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1291 sc->sc_dev.dv_xname, nexttx)); 1292 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1293 sc->sc_txnext); 1294 1295 /* Set a watchdog timer in case the chip flakes out. */ 1296 ifp->if_timer = 5; 1297 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1298 sc->sc_dev.dv_xname, ifp->if_timer)); 1299 } 1300 } 1301 1302 /* 1303 * Transmit interrupt. 1304 */ 1305 int 1306 gem_tint(sc) 1307 struct gem_softc *sc; 1308 { 1309 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1310 bus_space_tag_t t = sc->sc_bustag; 1311 bus_space_handle_t mac = sc->sc_h; 1312 struct gem_txsoft *txs; 1313 int txlast; 1314 int progress = 0; 1315 1316 1317 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1318 1319 /* 1320 * Unload collision counters 1321 */ 1322 ifp->if_collisions += 1323 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1324 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1325 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1326 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1327 1328 /* 1329 * then clear the hardware counters. 1330 */ 1331 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1332 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1333 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1334 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1335 1336 /* 1337 * Go through our Tx list and free mbufs for those 1338 * frames that have been transmitted. 1339 */ 1340 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1341 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1342 txs->txs_ndescs, 1343 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1344 1345 #ifdef GEM_DEBUG 1346 if (ifp->if_flags & IFF_DEBUG) { 1347 int i; 1348 printf(" txsoft %p transmit chain:\n", txs); 1349 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1350 printf("descriptor %d: ", i); 1351 printf("gd_flags: 0x%016llx\t", (long long) 1352 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1353 printf("gd_addr: 0x%016llx\n", (long long) 1354 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1355 if (i == txs->txs_lastdesc) 1356 break; 1357 } 1358 } 1359 #endif 1360 1361 /* 1362 * In theory, we could harveast some descriptors before 1363 * the ring is empty, but that's a bit complicated. 1364 * 1365 * GEM_TX_COMPLETION points to the last descriptor 1366 * processed +1. 1367 */ 1368 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1369 DPRINTF(sc, 1370 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1371 txs->txs_lastdesc, txlast)); 1372 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1373 if ((txlast >= txs->txs_firstdesc) && 1374 (txlast <= txs->txs_lastdesc)) 1375 break; 1376 } else { 1377 /* Ick -- this command wraps */ 1378 if ((txlast >= txs->txs_firstdesc) || 1379 (txlast <= txs->txs_lastdesc)) 1380 break; 1381 } 1382 1383 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1384 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1385 1386 sc->sc_txfree += txs->txs_ndescs; 1387 1388 if (txs->txs_mbuf == NULL) { 1389 #ifdef DIAGNOSTIC 1390 panic("gem_txintr: null mbuf"); 1391 #endif 1392 } 1393 1394 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1395 0, txs->txs_dmamap->dm_mapsize, 1396 BUS_DMASYNC_POSTWRITE); 1397 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1398 m_freem(txs->txs_mbuf); 1399 txs->txs_mbuf = NULL; 1400 1401 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1402 1403 ifp->if_opackets++; 1404 progress = 1; 1405 } 1406 1407 #if 0 1408 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1409 "GEM_TX_DATA_PTR %llx " 1410 "GEM_TX_COMPLETION %x\n", 1411 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1412 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1413 GEM_TX_DATA_PTR_HI) << 32) | 1414 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1415 GEM_TX_DATA_PTR_LO), 1416 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1417 #endif 1418 1419 if (progress) { 1420 if (sc->sc_txfree == GEM_NTXDESC - 1) 1421 sc->sc_txwin = 0; 1422 1423 ifp->if_flags &= ~IFF_OACTIVE; 1424 gem_start(ifp); 1425 1426 if (SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) 1427 ifp->if_timer = 0; 1428 } 1429 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1430 sc->sc_dev.dv_xname, ifp->if_timer)); 1431 1432 return (1); 1433 } 1434 1435 /* 1436 * Receive interrupt. 1437 */ 1438 int 1439 gem_rint(sc) 1440 struct gem_softc *sc; 1441 { 1442 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1443 bus_space_tag_t t = sc->sc_bustag; 1444 bus_space_handle_t h = sc->sc_h; 1445 struct gem_rxsoft *rxs; 1446 struct mbuf *m; 1447 u_int64_t rxstat; 1448 u_int32_t rxcomp; 1449 int i, len, progress = 0; 1450 1451 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1452 1453 /* 1454 * Read the completion register once. This limits 1455 * how long the following loop can execute. 1456 */ 1457 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1458 1459 /* 1460 * XXXX Read the lastrx only once at the top for speed. 1461 */ 1462 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1463 sc->sc_rxptr, rxcomp)); 1464 1465 /* 1466 * Go into the loop at least once. 1467 */ 1468 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1469 i = GEM_NEXTRX(i)) { 1470 rxs = &sc->sc_rxsoft[i]; 1471 1472 GEM_CDRXSYNC(sc, i, 1473 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1474 1475 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1476 1477 if (rxstat & GEM_RD_OWN) { 1478 /* 1479 * We have processed all of the receive buffers. 1480 */ 1481 break; 1482 } 1483 1484 progress++; 1485 ifp->if_ipackets++; 1486 1487 if (rxstat & GEM_RD_BAD_CRC) { 1488 ifp->if_ierrors++; 1489 printf("%s: receive error: CRC error\n", 1490 sc->sc_dev.dv_xname); 1491 GEM_INIT_RXDESC(sc, i); 1492 continue; 1493 } 1494 1495 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1496 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1497 #ifdef GEM_DEBUG 1498 if (ifp->if_flags & IFF_DEBUG) { 1499 printf(" rxsoft %p descriptor %d: ", rxs, i); 1500 printf("gd_flags: 0x%016llx\t", (long long) 1501 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1502 printf("gd_addr: 0x%016llx\n", (long long) 1503 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1504 } 1505 #endif 1506 1507 /* No errors; receive the packet. */ 1508 len = GEM_RD_BUFLEN(rxstat); 1509 1510 /* 1511 * Allocate a new mbuf cluster. If that fails, we are 1512 * out of memory, and must drop the packet and recycle 1513 * the buffer that's already attached to this descriptor. 1514 */ 1515 m = rxs->rxs_mbuf; 1516 if (gem_add_rxbuf(sc, i) != 0) { 1517 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1518 ifp->if_ierrors++; 1519 GEM_INIT_RXDESC(sc, i); 1520 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1521 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1522 continue; 1523 } 1524 m->m_data += 2; /* We're already off by two */ 1525 1526 m->m_pkthdr.rcvif = ifp; 1527 m->m_pkthdr.len = m->m_len = len; 1528 1529 #if NBPFILTER > 0 1530 /* 1531 * Pass this up to any BPF listeners, but only 1532 * pass it up the stack if its for us. 1533 */ 1534 if (ifp->if_bpf) 1535 bpf_mtap(ifp->if_bpf, m); 1536 #endif /* NPBFILTER > 0 */ 1537 1538 #ifdef INET 1539 /* hardware checksum */ 1540 if (ifp->if_csum_flags_rx & (M_CSUM_UDPv4 | M_CSUM_TCPv4)) { 1541 struct ether_header *eh; 1542 struct ip *ip; 1543 struct udphdr *uh; 1544 int32_t hlen, pktlen; 1545 1546 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1547 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1548 ETHER_VLAN_ENCAP_LEN; 1549 eh = (struct ether_header *) mtod(m, caddr_t) + 1550 ETHER_VLAN_ENCAP_LEN; 1551 } else { 1552 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1553 eh = mtod(m, struct ether_header *); 1554 } 1555 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1556 goto swcsum; 1557 ip = (struct ip *) ((caddr_t)eh + ETHER_HDR_LEN); 1558 1559 /* IPv4 only */ 1560 if (ip->ip_v != IPVERSION) 1561 goto swcsum; 1562 1563 hlen = ip->ip_hl << 2; 1564 if (hlen < sizeof(struct ip)) 1565 goto swcsum; 1566 1567 /* 1568 * bail if too short, has random trailing garbage, 1569 * truncated, fragment, or has ethernet pad. 1570 */ 1571 if ((ntohs(ip->ip_len) < hlen) || 1572 (ntohs(ip->ip_len) != pktlen) || 1573 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1574 goto swcsum; 1575 1576 switch (ip->ip_p) { 1577 case IPPROTO_TCP: 1578 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1579 goto swcsum; 1580 if (pktlen < (hlen + sizeof(struct tcphdr))) 1581 goto swcsum; 1582 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1583 break; 1584 case IPPROTO_UDP: 1585 if (! (ifp->if_csum_flags_rx & M_CSUM_UDPv4)) 1586 goto swcsum; 1587 if (pktlen < (hlen + sizeof(struct udphdr))) 1588 goto swcsum; 1589 uh = (struct udphdr *)((caddr_t)ip + hlen); 1590 /* no checksum */ 1591 if (uh->uh_sum == 0) 1592 goto swcsum; 1593 m->m_pkthdr.csum_flags = M_CSUM_UDPv4; 1594 break; 1595 default: 1596 goto swcsum; 1597 } 1598 1599 /* the uncomplemented sum is expected */ 1600 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1601 1602 /* if the pkt had ip options, we have to deduct them */ 1603 if (hlen > sizeof(struct ip)) { 1604 uint16_t *opts; 1605 uint32_t optsum, temp; 1606 1607 optsum = 0; 1608 temp = hlen - sizeof(struct ip); 1609 opts = (uint16_t *) ((caddr_t) ip + 1610 sizeof(struct ip)); 1611 1612 while (temp > 1) { 1613 optsum += ntohs(*opts++); 1614 temp -= 2; 1615 } 1616 while (optsum >> 16) 1617 optsum = (optsum >> 16) + 1618 (optsum & 0xffff); 1619 1620 /* Deduct ip opts sum from hwsum (rfc 1624). */ 1621 m->m_pkthdr.csum_data = 1622 ~((~m->m_pkthdr.csum_data) - ~optsum); 1623 1624 while (m->m_pkthdr.csum_data >> 16) 1625 m->m_pkthdr.csum_data = 1626 (m->m_pkthdr.csum_data >> 16) + 1627 (m->m_pkthdr.csum_data & 1628 0xffff); 1629 } 1630 1631 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1632 M_CSUM_NO_PSEUDOHDR; 1633 } else 1634 swcsum: 1635 m->m_pkthdr.csum_flags = 0; 1636 #endif 1637 /* Pass it on. */ 1638 (*ifp->if_input)(ifp, m); 1639 } 1640 1641 if (progress) { 1642 /* Update the receive pointer. */ 1643 if (i == sc->sc_rxptr) { 1644 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1645 #ifdef GEM_DEBUG 1646 if (ifp->if_flags & IFF_DEBUG) 1647 printf("%s: rint: ring wrap\n", 1648 sc->sc_dev.dv_xname); 1649 #endif 1650 } 1651 sc->sc_rxptr = i; 1652 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1653 } 1654 #ifdef GEM_COUNTERS 1655 if (progress <= 4) { 1656 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1657 } else if (progress < 32) { 1658 if (progress < 16) 1659 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1660 else 1661 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1662 1663 } else { 1664 if (progress < 64) 1665 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1666 else 1667 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1668 } 1669 #endif 1670 1671 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1672 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1673 1674 return (1); 1675 } 1676 1677 1678 /* 1679 * gem_add_rxbuf: 1680 * 1681 * Add a receive buffer to the indicated descriptor. 1682 */ 1683 int 1684 gem_add_rxbuf(struct gem_softc *sc, int idx) 1685 { 1686 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1687 struct mbuf *m; 1688 int error; 1689 1690 MGETHDR(m, M_DONTWAIT, MT_DATA); 1691 if (m == NULL) 1692 return (ENOBUFS); 1693 1694 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1695 MCLGET(m, M_DONTWAIT); 1696 if ((m->m_flags & M_EXT) == 0) { 1697 m_freem(m); 1698 return (ENOBUFS); 1699 } 1700 1701 #ifdef GEM_DEBUG 1702 /* bzero the packet to check DMA */ 1703 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1704 #endif 1705 1706 if (rxs->rxs_mbuf != NULL) 1707 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1708 1709 rxs->rxs_mbuf = m; 1710 1711 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1712 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1713 BUS_DMA_READ|BUS_DMA_NOWAIT); 1714 if (error) { 1715 printf("%s: can't load rx DMA map %d, error = %d\n", 1716 sc->sc_dev.dv_xname, idx, error); 1717 panic("gem_add_rxbuf"); /* XXX */ 1718 } 1719 1720 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1721 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1722 1723 GEM_INIT_RXDESC(sc, idx); 1724 1725 return (0); 1726 } 1727 1728 1729 int 1730 gem_eint(sc, status) 1731 struct gem_softc *sc; 1732 u_int status; 1733 { 1734 char bits[128]; 1735 1736 if ((status & GEM_INTR_MIF) != 0) { 1737 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1738 return (1); 1739 } 1740 1741 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1742 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1743 return (1); 1744 } 1745 1746 1747 int 1748 gem_intr(v) 1749 void *v; 1750 { 1751 struct gem_softc *sc = (struct gem_softc *)v; 1752 bus_space_tag_t t = sc->sc_bustag; 1753 bus_space_handle_t seb = sc->sc_h; 1754 u_int32_t status; 1755 int r = 0; 1756 #ifdef GEM_DEBUG 1757 char bits[128]; 1758 #endif 1759 1760 sc->sc_ev_intr.ev_count++; 1761 1762 status = bus_space_read_4(t, seb, GEM_STATUS); 1763 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 1764 sc->sc_dev.dv_xname, (status >> 19), 1765 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1766 1767 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1768 r |= gem_eint(sc, status); 1769 1770 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 1771 GEM_COUNTER_INCR(sc, sc_ev_txint); 1772 r |= gem_tint(sc); 1773 } 1774 1775 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 1776 GEM_COUNTER_INCR(sc, sc_ev_rxint); 1777 r |= gem_rint(sc); 1778 } 1779 1780 /* We should eventually do more than just print out error stats. */ 1781 if (status & GEM_INTR_TX_MAC) { 1782 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1783 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1784 printf("%s: MAC tx fault, status %x\n", 1785 sc->sc_dev.dv_xname, txstat); 1786 } 1787 if (status & GEM_INTR_RX_MAC) { 1788 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1789 if (rxstat & ~GEM_MAC_RX_DONE) 1790 printf("%s: MAC rx fault, status %x\n", 1791 sc->sc_dev.dv_xname, rxstat); 1792 } 1793 return (r); 1794 } 1795 1796 1797 void 1798 gem_watchdog(ifp) 1799 struct ifnet *ifp; 1800 { 1801 struct gem_softc *sc = ifp->if_softc; 1802 1803 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1804 "GEM_MAC_RX_CONFIG %x\n", 1805 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1806 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1807 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1808 1809 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1810 ++ifp->if_oerrors; 1811 1812 /* Try to get more packets going. */ 1813 gem_start(ifp); 1814 } 1815 1816 /* 1817 * Initialize the MII Management Interface 1818 */ 1819 void 1820 gem_mifinit(sc) 1821 struct gem_softc *sc; 1822 { 1823 bus_space_tag_t t = sc->sc_bustag; 1824 bus_space_handle_t mif = sc->sc_h; 1825 1826 /* Configure the MIF in frame mode */ 1827 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1828 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1829 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1830 } 1831 1832 /* 1833 * MII interface 1834 * 1835 * The GEM MII interface supports at least three different operating modes: 1836 * 1837 * Bitbang mode is implemented using data, clock and output enable registers. 1838 * 1839 * Frame mode is implemented by loading a complete frame into the frame 1840 * register and polling the valid bit for completion. 1841 * 1842 * Polling mode uses the frame register but completion is indicated by 1843 * an interrupt. 1844 * 1845 */ 1846 static int 1847 gem_mii_readreg(self, phy, reg) 1848 struct device *self; 1849 int phy, reg; 1850 { 1851 struct gem_softc *sc = (void *)self; 1852 bus_space_tag_t t = sc->sc_bustag; 1853 bus_space_handle_t mif = sc->sc_h; 1854 int n; 1855 u_int32_t v; 1856 1857 #ifdef GEM_DEBUG1 1858 if (sc->sc_debug) 1859 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1860 #endif 1861 1862 #if 0 1863 /* Select the desired PHY in the MIF configuration register */ 1864 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1865 /* Clear PHY select bit */ 1866 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1867 if (phy == GEM_PHYAD_EXTERNAL) 1868 /* Set PHY select bit to get at external device */ 1869 v |= GEM_MIF_CONFIG_PHY_SEL; 1870 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1871 #endif 1872 1873 /* Construct the frame command */ 1874 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1875 GEM_MIF_FRAME_READ; 1876 1877 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1878 for (n = 0; n < 100; n++) { 1879 DELAY(1); 1880 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1881 if (v & GEM_MIF_FRAME_TA0) 1882 return (v & GEM_MIF_FRAME_DATA); 1883 } 1884 1885 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1886 return (0); 1887 } 1888 1889 static void 1890 gem_mii_writereg(self, phy, reg, val) 1891 struct device *self; 1892 int phy, reg, val; 1893 { 1894 struct gem_softc *sc = (void *)self; 1895 bus_space_tag_t t = sc->sc_bustag; 1896 bus_space_handle_t mif = sc->sc_h; 1897 int n; 1898 u_int32_t v; 1899 1900 #ifdef GEM_DEBUG1 1901 if (sc->sc_debug) 1902 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1903 phy, reg, val); 1904 #endif 1905 1906 #if 0 1907 /* Select the desired PHY in the MIF configuration register */ 1908 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1909 /* Clear PHY select bit */ 1910 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1911 if (phy == GEM_PHYAD_EXTERNAL) 1912 /* Set PHY select bit to get at external device */ 1913 v |= GEM_MIF_CONFIG_PHY_SEL; 1914 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1915 #endif 1916 /* Construct the frame command */ 1917 v = GEM_MIF_FRAME_WRITE | 1918 (phy << GEM_MIF_PHY_SHIFT) | 1919 (reg << GEM_MIF_REG_SHIFT) | 1920 (val & GEM_MIF_FRAME_DATA); 1921 1922 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1923 for (n = 0; n < 100; n++) { 1924 DELAY(1); 1925 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1926 if (v & GEM_MIF_FRAME_TA0) 1927 return; 1928 } 1929 1930 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1931 } 1932 1933 static void 1934 gem_mii_statchg(dev) 1935 struct device *dev; 1936 { 1937 struct gem_softc *sc = (void *)dev; 1938 #ifdef GEM_DEBUG 1939 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1940 #endif 1941 bus_space_tag_t t = sc->sc_bustag; 1942 bus_space_handle_t mac = sc->sc_h; 1943 u_int32_t v; 1944 1945 #ifdef GEM_DEBUG 1946 if (sc->sc_debug) 1947 printf("gem_mii_statchg: status change: phy = %d\n", 1948 sc->sc_phys[instance]); 1949 #endif 1950 1951 1952 /* Set tx full duplex options */ 1953 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1954 delay(10000); /* reg must be cleared and delay before changing. */ 1955 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1956 GEM_MAC_TX_ENABLE; 1957 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1958 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1959 } 1960 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1961 1962 /* XIF Configuration */ 1963 /* We should really calculate all this rather than rely on defaults */ 1964 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1965 v = GEM_MAC_XIF_LINK_LED; 1966 v |= GEM_MAC_XIF_TX_MII_ENA; 1967 1968 /* If an external transceiver is connected, enable its MII drivers */ 1969 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1970 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1971 /* External MII needs echo disable if half duplex. */ 1972 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1973 /* turn on full duplex LED */ 1974 v |= GEM_MAC_XIF_FDPLX_LED; 1975 else 1976 /* half duplex -- disable echo */ 1977 v |= GEM_MAC_XIF_ECHO_DISABL; 1978 1979 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 1980 v |= GEM_MAC_XIF_GMII_MODE; 1981 else 1982 v &= ~GEM_MAC_XIF_GMII_MODE; 1983 } else 1984 /* Internal MII needs buf enable */ 1985 v |= GEM_MAC_XIF_MII_BUF_ENA; 1986 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1987 } 1988 1989 int 1990 gem_mediachange(ifp) 1991 struct ifnet *ifp; 1992 { 1993 struct gem_softc *sc = ifp->if_softc; 1994 1995 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1996 return (EINVAL); 1997 1998 return (mii_mediachg(&sc->sc_mii)); 1999 } 2000 2001 void 2002 gem_mediastatus(ifp, ifmr) 2003 struct ifnet *ifp; 2004 struct ifmediareq *ifmr; 2005 { 2006 struct gem_softc *sc = ifp->if_softc; 2007 2008 if ((ifp->if_flags & IFF_UP) == 0) 2009 return; 2010 2011 mii_pollstat(&sc->sc_mii); 2012 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2013 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2014 } 2015 2016 int gem_ioctldebug = 0; 2017 /* 2018 * Process an ioctl request. 2019 */ 2020 int 2021 gem_ioctl(ifp, cmd, data) 2022 struct ifnet *ifp; 2023 u_long cmd; 2024 caddr_t data; 2025 { 2026 struct gem_softc *sc = ifp->if_softc; 2027 struct ifreq *ifr = (struct ifreq *)data; 2028 int s, error = 0; 2029 2030 s = splnet(); 2031 2032 switch (cmd) { 2033 case SIOCGIFMEDIA: 2034 case SIOCSIFMEDIA: 2035 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 2036 break; 2037 2038 default: 2039 error = ether_ioctl(ifp, cmd, data); 2040 if (error == ENETRESET) { 2041 /* 2042 * Multicast list has changed; set the hardware filter 2043 * accordingly. 2044 */ 2045 if (ifp->if_flags & IFF_RUNNING) { 2046 if (gem_ioctldebug) printf("reset1\n"); 2047 gem_init(ifp); 2048 delay(50000); 2049 } 2050 error = 0; 2051 } 2052 break; 2053 } 2054 2055 /* Try to get things going again */ 2056 if (ifp->if_flags & IFF_UP) { 2057 if (gem_ioctldebug) printf("start\n"); 2058 gem_start(ifp); 2059 } 2060 splx(s); 2061 return (error); 2062 } 2063 2064 2065 void 2066 gem_shutdown(arg) 2067 void *arg; 2068 { 2069 struct gem_softc *sc = (struct gem_softc *)arg; 2070 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2071 2072 gem_stop(ifp, 1); 2073 } 2074 2075 /* 2076 * Set up the logical address filter. 2077 */ 2078 void 2079 gem_setladrf(sc) 2080 struct gem_softc *sc; 2081 { 2082 struct ethercom *ec = &sc->sc_ethercom; 2083 struct ifnet *ifp = &ec->ec_if; 2084 struct ether_multi *enm; 2085 struct ether_multistep step; 2086 bus_space_tag_t t = sc->sc_bustag; 2087 bus_space_handle_t h = sc->sc_h; 2088 u_int32_t crc; 2089 u_int32_t hash[16]; 2090 u_int32_t v; 2091 int i; 2092 2093 /* Get current RX configuration */ 2094 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2095 2096 /* 2097 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2098 * and hash filter. Depending on the case, the right bit will be 2099 * enabled. 2100 */ 2101 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2102 GEM_MAC_RX_PROMISC_GRP); 2103 2104 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2105 /* Turn on promiscuous mode */ 2106 v |= GEM_MAC_RX_PROMISCUOUS; 2107 ifp->if_flags |= IFF_ALLMULTI; 2108 goto chipit; 2109 } 2110 2111 /* 2112 * Set up multicast address filter by passing all multicast addresses 2113 * through a crc generator, and then using the high order 8 bits as an 2114 * index into the 256 bit logical address filter. The high order 4 2115 * bits select the word, while the other 4 bits select the bit within 2116 * the word (where bit 0 is the MSB). 2117 */ 2118 2119 /* Clear hash table */ 2120 memset(hash, 0, sizeof(hash)); 2121 2122 ETHER_FIRST_MULTI(step, ec, enm); 2123 while (enm != NULL) { 2124 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2125 /* 2126 * We must listen to a range of multicast addresses. 2127 * For now, just accept all multicasts, rather than 2128 * trying to set only those filter bits needed to match 2129 * the range. (At this time, the only use of address 2130 * ranges is for IP multicast routing, for which the 2131 * range is big enough to require all bits set.) 2132 * XXX use the addr filter for this 2133 */ 2134 ifp->if_flags |= IFF_ALLMULTI; 2135 v |= GEM_MAC_RX_PROMISC_GRP; 2136 goto chipit; 2137 } 2138 2139 /* Get the LE CRC32 of the address */ 2140 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2141 2142 /* Just want the 8 most significant bits. */ 2143 crc >>= 24; 2144 2145 /* Set the corresponding bit in the filter. */ 2146 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2147 2148 ETHER_NEXT_MULTI(step, enm); 2149 } 2150 2151 v |= GEM_MAC_RX_HASH_FILTER; 2152 ifp->if_flags &= ~IFF_ALLMULTI; 2153 2154 /* Now load the hash table into the chip (if we are using it) */ 2155 for (i = 0; i < 16; i++) { 2156 bus_space_write_4(t, h, 2157 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2158 hash[i]); 2159 } 2160 2161 chipit: 2162 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2163 } 2164 2165 #if notyet 2166 2167 /* 2168 * gem_power: 2169 * 2170 * Power management (suspend/resume) hook. 2171 */ 2172 void 2173 gem_power(why, arg) 2174 int why; 2175 void *arg; 2176 { 2177 struct gem_softc *sc = arg; 2178 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2179 int s; 2180 2181 s = splnet(); 2182 switch (why) { 2183 case PWR_SUSPEND: 2184 case PWR_STANDBY: 2185 gem_stop(ifp, 1); 2186 if (sc->sc_power != NULL) 2187 (*sc->sc_power)(sc, why); 2188 break; 2189 case PWR_RESUME: 2190 if (ifp->if_flags & IFF_UP) { 2191 if (sc->sc_power != NULL) 2192 (*sc->sc_power)(sc, why); 2193 gem_init(ifp); 2194 } 2195 break; 2196 case PWR_SOFTSUSPEND: 2197 case PWR_SOFTSTANDBY: 2198 case PWR_SOFTRESUME: 2199 break; 2200 } 2201 splx(s); 2202 } 2203 #endif 2204