1 /* $NetBSD: gem.c,v 1.46 2006/05/26 12:52:45 blymn Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.46 2006/05/26 12:52:45 blymn Exp $"); 38 39 #include "opt_inet.h" 40 #include "bpfilter.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/syslog.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 54 #include <machine/endian.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #endif 75 76 #include <machine/bus.h> 77 #include <machine/intr.h> 78 79 #include <dev/mii/mii.h> 80 #include <dev/mii/miivar.h> 81 #include <dev/mii/mii_bitbang.h> 82 83 #include <dev/ic/gemreg.h> 84 #include <dev/ic/gemvar.h> 85 86 #define TRIES 10000 87 88 static void gem_start(struct ifnet *); 89 static void gem_stop(struct ifnet *, int); 90 int gem_ioctl(struct ifnet *, u_long, caddr_t); 91 void gem_tick(void *); 92 void gem_watchdog(struct ifnet *); 93 void gem_shutdown(void *); 94 int gem_init(struct ifnet *); 95 void gem_init_regs(struct gem_softc *sc); 96 static int gem_ringsize(int sz); 97 static int gem_meminit(struct gem_softc *); 98 void gem_mifinit(struct gem_softc *); 99 static int gem_bitwait(struct gem_softc *sc, int, u_int32_t, u_int32_t); 100 void gem_reset(struct gem_softc *); 101 int gem_reset_rx(struct gem_softc *sc); 102 int gem_reset_tx(struct gem_softc *sc); 103 int gem_disable_rx(struct gem_softc *sc); 104 int gem_disable_tx(struct gem_softc *sc); 105 static void gem_rxdrain(struct gem_softc *sc); 106 int gem_add_rxbuf(struct gem_softc *sc, int idx); 107 void gem_setladrf(struct gem_softc *); 108 109 /* MII methods & callbacks */ 110 static int gem_mii_readreg(struct device *, int, int); 111 static void gem_mii_writereg(struct device *, int, int, int); 112 static void gem_mii_statchg(struct device *); 113 114 int gem_mediachange(struct ifnet *); 115 void gem_mediastatus(struct ifnet *, struct ifmediareq *); 116 117 struct mbuf *gem_get(struct gem_softc *, int, int); 118 int gem_put(struct gem_softc *, int, struct mbuf *); 119 void gem_read(struct gem_softc *, int, int); 120 int gem_eint(struct gem_softc *, u_int); 121 int gem_rint(struct gem_softc *); 122 int gem_tint(struct gem_softc *); 123 void gem_power(int, void *); 124 125 #ifdef GEM_DEBUG 126 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 127 printf x 128 #else 129 #define DPRINTF(sc, x) /* nothing */ 130 #endif 131 132 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 133 134 135 /* 136 * gem_attach: 137 * 138 * Attach a Gem interface to the system. 139 */ 140 void 141 gem_attach(sc, enaddr) 142 struct gem_softc *sc; 143 const uint8_t *enaddr; 144 { 145 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 146 struct mii_data *mii = &sc->sc_mii; 147 struct mii_softc *child; 148 struct ifmedia_entry *ifm; 149 int i, error; 150 u_int32_t v; 151 char *nullbuf; 152 153 /* Make sure the chip is stopped. */ 154 ifp->if_softc = sc; 155 gem_reset(sc); 156 157 /* 158 * Allocate the control data structures, and create and load the 159 * DMA map for it. gem_control_data is 9216 bytes, we have space for 160 * the padding buffer in the bus_dmamem_alloc()'d memory. 161 */ 162 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 163 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 164 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 165 aprint_error( 166 "%s: unable to allocate control data, error = %d\n", 167 sc->sc_dev.dv_xname, error); 168 goto fail_0; 169 } 170 171 /* XXX should map this in with correct endianness */ 172 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 173 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 174 BUS_DMA_COHERENT)) != 0) { 175 aprint_error("%s: unable to map control data, error = %d\n", 176 sc->sc_dev.dv_xname, error); 177 goto fail_1; 178 } 179 180 nullbuf = 181 (caddr_t)sc->sc_control_data + sizeof(struct gem_control_data); 182 183 if ((error = bus_dmamap_create(sc->sc_dmatag, 184 sizeof(struct gem_control_data), 1, 185 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 186 aprint_error("%s: unable to create control data DMA map, " 187 "error = %d\n", sc->sc_dev.dv_xname, error); 188 goto fail_2; 189 } 190 191 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 192 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 193 0)) != 0) { 194 aprint_error( 195 "%s: unable to load control data DMA map, error = %d\n", 196 sc->sc_dev.dv_xname, error); 197 goto fail_3; 198 } 199 200 memset(nullbuf, 0, ETHER_MIN_TX); 201 if ((error = bus_dmamap_create(sc->sc_dmatag, 202 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 203 aprint_error("%s: unable to create padding DMA map, " 204 "error = %d\n", sc->sc_dev.dv_xname, error); 205 goto fail_4; 206 } 207 208 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 209 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 210 aprint_error( 211 "%s: unable to load padding DMA map, error = %d\n", 212 sc->sc_dev.dv_xname, error); 213 goto fail_5; 214 } 215 216 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 217 BUS_DMASYNC_PREWRITE); 218 219 /* 220 * Initialize the transmit job descriptors. 221 */ 222 SIMPLEQ_INIT(&sc->sc_txfreeq); 223 SIMPLEQ_INIT(&sc->sc_txdirtyq); 224 225 /* 226 * Create the transmit buffer DMA maps. 227 */ 228 for (i = 0; i < GEM_TXQUEUELEN; i++) { 229 struct gem_txsoft *txs; 230 231 txs = &sc->sc_txsoft[i]; 232 txs->txs_mbuf = NULL; 233 if ((error = bus_dmamap_create(sc->sc_dmatag, 234 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 235 ETHER_MAX_LEN_JUMBO, 0, 0, 236 &txs->txs_dmamap)) != 0) { 237 aprint_error("%s: unable to create tx DMA map %d, " 238 "error = %d\n", sc->sc_dev.dv_xname, i, error); 239 goto fail_6; 240 } 241 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 242 } 243 244 /* 245 * Create the receive buffer DMA maps. 246 */ 247 for (i = 0; i < GEM_NRXDESC; i++) { 248 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 249 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 250 aprint_error("%s: unable to create rx DMA map %d, " 251 "error = %d\n", sc->sc_dev.dv_xname, i, error); 252 goto fail_7; 253 } 254 sc->sc_rxsoft[i].rxs_mbuf = NULL; 255 } 256 257 /* 258 * From this point forward, the attachment cannot fail. A failure 259 * before this point releases all resources that may have been 260 * allocated. 261 */ 262 263 /* Announce ourselves. */ 264 aprint_normal("%s: Ethernet address %s", sc->sc_dev.dv_xname, 265 ether_sprintf(enaddr)); 266 267 /* Get RX FIFO size */ 268 sc->sc_rxfifosize = 64 * 269 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 270 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 271 272 /* Get TX FIFO size */ 273 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 274 aprint_normal(", %uKB TX fifo\n", v / 16); 275 276 /* Initialize ifnet structure. */ 277 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 278 ifp->if_softc = sc; 279 ifp->if_flags = 280 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 281 sc->sc_if_flags = ifp->if_flags; 282 ifp->if_capabilities |= 283 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 284 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 285 ifp->if_start = gem_start; 286 ifp->if_ioctl = gem_ioctl; 287 ifp->if_watchdog = gem_watchdog; 288 ifp->if_stop = gem_stop; 289 ifp->if_init = gem_init; 290 IFQ_SET_READY(&ifp->if_snd); 291 292 /* Initialize ifmedia structures and MII info */ 293 mii->mii_ifp = ifp; 294 mii->mii_readreg = gem_mii_readreg; 295 mii->mii_writereg = gem_mii_writereg; 296 mii->mii_statchg = gem_mii_statchg; 297 298 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_mediachange, gem_mediastatus); 299 300 gem_mifinit(sc); 301 302 mii_attach(&sc->sc_dev, mii, 0xffffffff, 303 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 304 305 child = LIST_FIRST(&mii->mii_phys); 306 if (child == NULL) { 307 /* No PHY attached */ 308 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 309 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 310 } else { 311 /* 312 * Walk along the list of attached MII devices and 313 * establish an `MII instance' to `phy number' 314 * mapping. We'll use this mapping in media change 315 * requests to determine which phy to use to program 316 * the MIF configuration register. 317 */ 318 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 319 /* 320 * Note: we support just two PHYs: the built-in 321 * internal device and an external on the MII 322 * connector. 323 */ 324 if (child->mii_phy > 1 || child->mii_inst > 1) { 325 aprint_error( 326 "%s: cannot accomodate MII device %s" 327 " at phy %d, instance %d\n", 328 sc->sc_dev.dv_xname, 329 child->mii_dev.dv_xname, 330 child->mii_phy, child->mii_inst); 331 continue; 332 } 333 334 sc->sc_phys[child->mii_inst] = child->mii_phy; 335 } 336 337 /* 338 * Now select and activate the PHY we will use. 339 * 340 * The order of preference is External (MDI1), 341 * Internal (MDI0), Serial Link (no MII). 342 */ 343 if (sc->sc_phys[1]) { 344 #ifdef GEM_DEBUG 345 aprint_debug("using external phy\n"); 346 #endif 347 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 348 } else { 349 #ifdef GEM_DEBUG 350 aprint_debug("using internal phy\n"); 351 #endif 352 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 353 } 354 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 355 sc->sc_mif_config); 356 357 /* 358 * XXX - we can really do the following ONLY if the 359 * phy indeed has the auto negotiation capability!! 360 */ 361 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 362 } 363 364 /* 365 * If we support GigE media, we support jumbo frames too. 366 * Unless we are Apple. 367 */ 368 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 369 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 370 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 371 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 372 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 373 if (sc->sc_variant != GEM_APPLE_GMAC) 374 sc->sc_ethercom.ec_capabilities 375 |= ETHERCAP_JUMBO_MTU; 376 377 sc->sc_flags |= GEM_GIGABIT; 378 break; 379 } 380 } 381 382 /* claim 802.1q capability */ 383 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 384 385 /* Attach the interface. */ 386 if_attach(ifp); 387 ether_ifattach(ifp, enaddr); 388 389 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 390 if (sc->sc_sh == NULL) 391 panic("gem_config: can't establish shutdownhook"); 392 393 #if NRND > 0 394 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 395 RND_TYPE_NET, 0); 396 #endif 397 398 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 399 NULL, sc->sc_dev.dv_xname, "interrupts"); 400 #ifdef GEM_COUNTERS 401 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 402 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "tx interrupts"); 403 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 404 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "rx interrupts"); 405 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 406 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx ring full"); 407 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 408 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx malloc failure"); 409 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 410 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 0desc"); 411 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 412 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 1desc"); 413 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 414 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 2desc"); 415 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 416 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 3desc"); 417 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 418 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >3desc"); 419 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 420 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >7desc"); 421 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 422 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >15desc"); 423 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 424 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >31desc"); 425 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 426 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >63desc"); 427 #endif 428 429 #if notyet 430 /* 431 * Add a suspend hook to make sure we come back up after a 432 * resume. 433 */ 434 sc->sc_powerhook = powerhook_establish(gem_power, sc); 435 if (sc->sc_powerhook == NULL) 436 aprint_error("%s: WARNING: unable to establish power hook\n", 437 sc->sc_dev.dv_xname); 438 #endif 439 440 callout_init(&sc->sc_tick_ch); 441 return; 442 443 /* 444 * Free any resources we've allocated during the failed attach 445 * attempt. Do this in reverse order and fall through. 446 */ 447 fail_7: 448 for (i = 0; i < GEM_NRXDESC; i++) { 449 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 450 bus_dmamap_destroy(sc->sc_dmatag, 451 sc->sc_rxsoft[i].rxs_dmamap); 452 } 453 fail_6: 454 for (i = 0; i < GEM_TXQUEUELEN; i++) { 455 if (sc->sc_txsoft[i].txs_dmamap != NULL) 456 bus_dmamap_destroy(sc->sc_dmatag, 457 sc->sc_txsoft[i].txs_dmamap); 458 } 459 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 460 fail_5: 461 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 462 fail_4: 463 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)nullbuf, ETHER_MIN_TX); 464 fail_3: 465 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 466 fail_2: 467 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 468 sizeof(struct gem_control_data)); 469 fail_1: 470 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 471 fail_0: 472 return; 473 } 474 475 476 void 477 gem_tick(arg) 478 void *arg; 479 { 480 struct gem_softc *sc = arg; 481 int s; 482 483 s = splnet(); 484 mii_tick(&sc->sc_mii); 485 splx(s); 486 487 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 488 489 } 490 491 static int 492 gem_bitwait(sc, r, clr, set) 493 struct gem_softc *sc; 494 int r; 495 u_int32_t clr; 496 u_int32_t set; 497 { 498 int i; 499 u_int32_t reg; 500 501 for (i = TRIES; i--; DELAY(100)) { 502 reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r); 503 if ((r & clr) == 0 && (r & set) == set) 504 return (1); 505 } 506 return (0); 507 } 508 509 void 510 gem_reset(sc) 511 struct gem_softc *sc; 512 { 513 bus_space_tag_t t = sc->sc_bustag; 514 bus_space_handle_t h = sc->sc_h; 515 int s; 516 517 s = splnet(); 518 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 519 gem_reset_rx(sc); 520 gem_reset_tx(sc); 521 522 /* Do a full reset */ 523 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 524 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 525 printf("%s: cannot reset device\n", sc->sc_dev.dv_xname); 526 splx(s); 527 } 528 529 530 /* 531 * gem_rxdrain: 532 * 533 * Drain the receive queue. 534 */ 535 static void 536 gem_rxdrain(struct gem_softc *sc) 537 { 538 struct gem_rxsoft *rxs; 539 int i; 540 541 for (i = 0; i < GEM_NRXDESC; i++) { 542 rxs = &sc->sc_rxsoft[i]; 543 if (rxs->rxs_mbuf != NULL) { 544 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 545 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 546 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 547 m_freem(rxs->rxs_mbuf); 548 rxs->rxs_mbuf = NULL; 549 } 550 } 551 } 552 553 /* 554 * Reset the whole thing. 555 */ 556 static void 557 gem_stop(struct ifnet *ifp, int disable) 558 { 559 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 560 struct gem_txsoft *txs; 561 562 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 563 564 callout_stop(&sc->sc_tick_ch); 565 mii_down(&sc->sc_mii); 566 567 /* XXX - Should we reset these instead? */ 568 gem_disable_rx(sc); 569 gem_disable_tx(sc); 570 571 /* 572 * Release any queued transmit buffers. 573 */ 574 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 575 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 576 if (txs->txs_mbuf != NULL) { 577 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 578 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 579 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 580 m_freem(txs->txs_mbuf); 581 txs->txs_mbuf = NULL; 582 } 583 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 584 } 585 586 if (disable) { 587 gem_rxdrain(sc); 588 } 589 590 /* 591 * Mark the interface down and cancel the watchdog timer. 592 */ 593 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 594 sc->sc_if_flags = ifp->if_flags; 595 ifp->if_timer = 0; 596 } 597 598 599 /* 600 * Reset the receiver 601 */ 602 int 603 gem_reset_rx(struct gem_softc *sc) 604 { 605 bus_space_tag_t t = sc->sc_bustag; 606 bus_space_handle_t h = sc->sc_h; 607 608 /* 609 * Resetting while DMA is in progress can cause a bus hang, so we 610 * disable DMA first. 611 */ 612 gem_disable_rx(sc); 613 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 614 /* Wait till it finishes */ 615 if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0)) 616 printf("%s: cannot disable read dma\n", sc->sc_dev.dv_xname); 617 /* Wait 5ms extra. */ 618 delay(5000); 619 620 /* Finally, reset the ERX */ 621 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 622 /* Wait till it finishes */ 623 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 624 printf("%s: cannot reset receiver\n", sc->sc_dev.dv_xname); 625 return (1); 626 } 627 return (0); 628 } 629 630 631 /* 632 * Reset the transmitter 633 */ 634 int 635 gem_reset_tx(struct gem_softc *sc) 636 { 637 bus_space_tag_t t = sc->sc_bustag; 638 bus_space_handle_t h = sc->sc_h; 639 640 /* 641 * Resetting while DMA is in progress can cause a bus hang, so we 642 * disable DMA first. 643 */ 644 gem_disable_tx(sc); 645 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 646 /* Wait till it finishes */ 647 if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0)) 648 printf("%s: cannot disable read dma\n", sc->sc_dev.dv_xname); 649 /* Wait 5ms extra. */ 650 delay(5000); 651 652 /* Finally, reset the ETX */ 653 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 654 /* Wait till it finishes */ 655 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 656 printf("%s: cannot reset receiver\n", 657 sc->sc_dev.dv_xname); 658 return (1); 659 } 660 return (0); 661 } 662 663 /* 664 * disable receiver. 665 */ 666 int 667 gem_disable_rx(struct gem_softc *sc) 668 { 669 bus_space_tag_t t = sc->sc_bustag; 670 bus_space_handle_t h = sc->sc_h; 671 u_int32_t cfg; 672 673 /* Flip the enable bit */ 674 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 675 cfg &= ~GEM_MAC_RX_ENABLE; 676 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 677 678 /* Wait for it to finish */ 679 return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 680 } 681 682 /* 683 * disable transmitter. 684 */ 685 int 686 gem_disable_tx(struct gem_softc *sc) 687 { 688 bus_space_tag_t t = sc->sc_bustag; 689 bus_space_handle_t h = sc->sc_h; 690 u_int32_t cfg; 691 692 /* Flip the enable bit */ 693 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 694 cfg &= ~GEM_MAC_TX_ENABLE; 695 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 696 697 /* Wait for it to finish */ 698 return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 699 } 700 701 /* 702 * Initialize interface. 703 */ 704 int 705 gem_meminit(struct gem_softc *sc) 706 { 707 struct gem_rxsoft *rxs; 708 int i, error; 709 710 /* 711 * Initialize the transmit descriptor ring. 712 */ 713 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 714 for (i = 0; i < GEM_NTXDESC; i++) { 715 sc->sc_txdescs[i].gd_flags = 0; 716 sc->sc_txdescs[i].gd_addr = 0; 717 } 718 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 719 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 720 sc->sc_txfree = GEM_NTXDESC-1; 721 sc->sc_txnext = 0; 722 sc->sc_txwin = 0; 723 724 /* 725 * Initialize the receive descriptor and receive job 726 * descriptor rings. 727 */ 728 for (i = 0; i < GEM_NRXDESC; i++) { 729 rxs = &sc->sc_rxsoft[i]; 730 if (rxs->rxs_mbuf == NULL) { 731 if ((error = gem_add_rxbuf(sc, i)) != 0) { 732 printf("%s: unable to allocate or map rx " 733 "buffer %d, error = %d\n", 734 sc->sc_dev.dv_xname, i, error); 735 /* 736 * XXX Should attempt to run with fewer receive 737 * XXX buffers instead of just failing. 738 */ 739 gem_rxdrain(sc); 740 return (1); 741 } 742 } else 743 GEM_INIT_RXDESC(sc, i); 744 } 745 sc->sc_rxptr = 0; 746 747 return (0); 748 } 749 750 static int 751 gem_ringsize(int sz) 752 { 753 switch (sz) { 754 case 32: 755 return GEM_RING_SZ_32; 756 case 64: 757 return GEM_RING_SZ_64; 758 case 128: 759 return GEM_RING_SZ_128; 760 case 256: 761 return GEM_RING_SZ_256; 762 case 512: 763 return GEM_RING_SZ_512; 764 case 1024: 765 return GEM_RING_SZ_1024; 766 case 2048: 767 return GEM_RING_SZ_2048; 768 case 4096: 769 return GEM_RING_SZ_4096; 770 case 8192: 771 return GEM_RING_SZ_8192; 772 default: 773 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 774 return GEM_RING_SZ_32; 775 } 776 } 777 778 /* 779 * Initialization of interface; set up initialization block 780 * and transmit/receive descriptor rings. 781 */ 782 int 783 gem_init(struct ifnet *ifp) 784 { 785 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 786 bus_space_tag_t t = sc->sc_bustag; 787 bus_space_handle_t h = sc->sc_h; 788 int s; 789 u_int max_frame_size; 790 u_int32_t v; 791 792 s = splnet(); 793 794 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 795 /* 796 * Initialization sequence. The numbered steps below correspond 797 * to the sequence outlined in section 6.3.5.1 in the Ethernet 798 * Channel Engine manual (part of the PCIO manual). 799 * See also the STP2002-STQ document from Sun Microsystems. 800 */ 801 802 /* step 1 & 2. Reset the Ethernet Channel */ 803 gem_stop(ifp, 0); 804 gem_reset(sc); 805 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 806 807 /* Re-initialize the MIF */ 808 gem_mifinit(sc); 809 810 /* Call MI reset function if any */ 811 if (sc->sc_hwreset) 812 (*sc->sc_hwreset)(sc); 813 814 /* step 3. Setup data structures in host memory */ 815 gem_meminit(sc); 816 817 /* step 4. TX MAC registers & counters */ 818 gem_init_regs(sc); 819 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 820 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 821 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 822 max_frame_size += ETHER_VLAN_ENCAP_LEN; 823 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 824 max_frame_size|/* burst size */(0x2000<<16)); 825 826 /* step 5. RX MAC registers & counters */ 827 gem_setladrf(sc); 828 829 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 830 /* NOTE: we use only 32-bit DMA addresses here. */ 831 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 832 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 833 834 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 835 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 836 837 /* step 8. Global Configuration & Interrupt Mask */ 838 bus_space_write_4(t, h, GEM_INTMASK, 839 ~(GEM_INTR_TX_INTME| 840 GEM_INTR_TX_EMPTY| 841 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 842 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 843 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 844 GEM_INTR_BERR)); 845 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 846 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 847 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 848 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 849 850 /* step 9. ETX Configuration: use mostly default values */ 851 852 /* Enable DMA */ 853 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 854 bus_space_write_4(t, h, GEM_TX_CONFIG, 855 v|GEM_TX_CONFIG_TXDMA_EN| 856 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 857 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 858 859 /* step 10. ERX Configuration */ 860 861 /* Encode Receive Descriptor ring size: four possible values */ 862 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 863 864 /* Set receive h/w checksum offset */ 865 #ifdef INET 866 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 867 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 868 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 869 #endif 870 871 /* Enable DMA */ 872 bus_space_write_4(t, h, GEM_RX_CONFIG, 873 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 874 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN); 875 876 /* 877 * The following value is for an OFF Threshold of about 3/4 full 878 * and an ON Threshold of 1/4 full. 879 */ 880 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 881 (3 * sc->sc_rxfifosize / 256) | 882 ( (sc->sc_rxfifosize / 256) << 12)); 883 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 884 885 /* step 11. Configure Media */ 886 mii_mediachg(&sc->sc_mii); 887 888 /* XXXX Serial link needs a whole different setup. */ 889 890 891 /* step 12. RX_MAC Configuration Register */ 892 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 893 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 894 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 895 896 /* step 14. Issue Transmit Pending command */ 897 898 /* Call MI initialization function if any */ 899 if (sc->sc_hwinit) 900 (*sc->sc_hwinit)(sc); 901 902 903 /* step 15. Give the reciever a swift kick */ 904 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 905 906 /* Start the one second timer. */ 907 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 908 909 ifp->if_flags |= IFF_RUNNING; 910 ifp->if_flags &= ~IFF_OACTIVE; 911 ifp->if_timer = 0; 912 sc->sc_if_flags = ifp->if_flags; 913 splx(s); 914 915 return (0); 916 } 917 918 void 919 gem_init_regs(struct gem_softc *sc) 920 { 921 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 922 bus_space_tag_t t = sc->sc_bustag; 923 bus_space_handle_t h = sc->sc_h; 924 const u_char *laddr = LLADDR(ifp->if_sadl); 925 u_int32_t v; 926 927 /* These regs are not cleared on reset */ 928 if (!sc->sc_inited) { 929 930 /* Wooo. Magic values. */ 931 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 932 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 933 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 934 935 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 936 /* Max frame and max burst size */ 937 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 938 ETHER_MAX_LEN | (0x2000<<16)); 939 940 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 941 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 942 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 943 /* Dunno.... */ 944 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 945 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 946 ((laddr[5]<<8)|laddr[4])&0x3ff); 947 948 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 949 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 950 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 951 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 952 953 /* MAC control addr set to 01:80:c2:00:00:01 */ 954 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 955 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 956 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 957 958 /* MAC filter addr set to 0:0:0:0:0:0 */ 959 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 960 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 961 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 962 963 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 964 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 965 966 sc->sc_inited = 1; 967 } 968 969 /* Counters need to be zeroed */ 970 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 971 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 972 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 973 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 974 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 975 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 976 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 977 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 978 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 979 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 980 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 981 982 /* Un-pause stuff */ 983 #if 0 984 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 985 #else 986 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 987 #endif 988 989 /* 990 * Set the station address. 991 */ 992 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 993 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 994 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 995 996 #if 0 997 if (sc->sc_variant != APPLE_GMAC) 998 return; 999 #endif 1000 1001 /* 1002 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1003 */ 1004 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1005 v = GEM_MAC_XIF_TX_MII_ENA; 1006 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1007 v |= GEM_MAC_XIF_FDPLX_LED; 1008 if (sc->sc_flags & GEM_GIGABIT) 1009 v |= GEM_MAC_XIF_GMII_MODE; 1010 } 1011 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1012 } 1013 1014 static void 1015 gem_start(ifp) 1016 struct ifnet *ifp; 1017 { 1018 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1019 struct mbuf *m0, *m; 1020 struct gem_txsoft *txs, *last_txs; 1021 bus_dmamap_t dmamap; 1022 int error, firsttx, nexttx, lasttx = -1, ofree, seg; 1023 uint64_t flags = 0; 1024 1025 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1026 return; 1027 1028 /* 1029 * Remember the previous number of free descriptors and 1030 * the first descriptor we'll use. 1031 */ 1032 ofree = sc->sc_txfree; 1033 firsttx = sc->sc_txnext; 1034 1035 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1036 sc->sc_dev.dv_xname, ofree, firsttx)); 1037 1038 /* 1039 * Loop through the send queue, setting up transmit descriptors 1040 * until we drain the queue, or use up all available transmit 1041 * descriptors. 1042 */ 1043 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1044 sc->sc_txfree != 0) { 1045 /* 1046 * Grab a packet off the queue. 1047 */ 1048 IFQ_POLL(&ifp->if_snd, m0); 1049 if (m0 == NULL) 1050 break; 1051 m = NULL; 1052 1053 dmamap = txs->txs_dmamap; 1054 1055 /* 1056 * Load the DMA map. If this fails, the packet either 1057 * didn't fit in the alloted number of segments, or we were 1058 * short on resources. In this case, we'll copy and try 1059 * again. 1060 */ 1061 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1062 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1063 (m0->m_pkthdr.len < ETHER_MIN_TX && 1064 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1065 if (m0->m_pkthdr.len > MCLBYTES) { 1066 printf("%s: unable to allocate jumbo Tx " 1067 "cluster\n", sc->sc_dev.dv_xname); 1068 IFQ_DEQUEUE(&ifp->if_snd, m0); 1069 m_freem(m0); 1070 continue; 1071 } 1072 MGETHDR(m, M_DONTWAIT, MT_DATA); 1073 if (m == NULL) { 1074 printf("%s: unable to allocate Tx mbuf\n", 1075 sc->sc_dev.dv_xname); 1076 break; 1077 } 1078 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1079 if (m0->m_pkthdr.len > MHLEN) { 1080 MCLGET(m, M_DONTWAIT); 1081 if ((m->m_flags & M_EXT) == 0) { 1082 printf("%s: unable to allocate Tx " 1083 "cluster\n", sc->sc_dev.dv_xname); 1084 m_freem(m); 1085 break; 1086 } 1087 } 1088 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1089 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1090 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1091 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1092 if (error) { 1093 printf("%s: unable to load Tx buffer, " 1094 "error = %d\n", sc->sc_dev.dv_xname, error); 1095 break; 1096 } 1097 } 1098 1099 /* 1100 * Ensure we have enough descriptors free to describe 1101 * the packet. 1102 */ 1103 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1104 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1105 /* 1106 * Not enough free descriptors to transmit this 1107 * packet. We haven't committed to anything yet, 1108 * so just unload the DMA map, put the packet 1109 * back on the queue, and punt. Notify the upper 1110 * layer that there are no more slots left. 1111 * 1112 * XXX We could allocate an mbuf and copy, but 1113 * XXX it is worth it? 1114 */ 1115 ifp->if_flags |= IFF_OACTIVE; 1116 sc->sc_if_flags = ifp->if_flags; 1117 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1118 if (m != NULL) 1119 m_freem(m); 1120 break; 1121 } 1122 1123 IFQ_DEQUEUE(&ifp->if_snd, m0); 1124 if (m != NULL) { 1125 m_freem(m0); 1126 m0 = m; 1127 } 1128 1129 /* 1130 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1131 */ 1132 1133 /* Sync the DMA map. */ 1134 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1135 BUS_DMASYNC_PREWRITE); 1136 1137 /* 1138 * Initialize the transmit descriptors. 1139 */ 1140 for (nexttx = sc->sc_txnext, seg = 0; 1141 seg < dmamap->dm_nsegs; 1142 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1143 1144 /* 1145 * If this is the first descriptor we're 1146 * enqueueing, set the start of packet flag, 1147 * and the checksum stuff if we want the hardware 1148 * to do it. 1149 */ 1150 sc->sc_txdescs[nexttx].gd_addr = 1151 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1152 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1153 if (nexttx == firsttx) { 1154 flags |= GEM_TD_START_OF_PACKET; 1155 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1156 sc->sc_txwin = 0; 1157 flags |= GEM_TD_INTERRUPT_ME; 1158 } 1159 1160 #ifdef INET 1161 /* h/w checksum */ 1162 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | 1163 M_CSUM_UDPv4) && m0->m_pkthdr.csum_flags & 1164 (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1165 struct ether_header *eh; 1166 uint16_t offset, start; 1167 1168 eh = mtod(m0, struct ether_header *); 1169 switch (ntohs(eh->ether_type)) { 1170 case ETHERTYPE_IP: 1171 start = ETHER_HDR_LEN; 1172 break; 1173 case ETHERTYPE_VLAN: 1174 start = ETHER_HDR_LEN + 1175 ETHER_VLAN_ENCAP_LEN; 1176 break; 1177 default: 1178 /* unsupported, drop it */ 1179 m_free(m0); 1180 continue; 1181 } 1182 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1183 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1184 flags |= (start << 1185 GEM_TD_CXSUM_STARTSHFT) | 1186 (offset << 1187 GEM_TD_CXSUM_STUFFSHFT) | 1188 GEM_TD_CXSUM_ENABLE; 1189 } 1190 #endif 1191 } 1192 if (seg == dmamap->dm_nsegs - 1) { 1193 flags |= GEM_TD_END_OF_PACKET; 1194 } else { 1195 /* last flag set outside of loop */ 1196 sc->sc_txdescs[nexttx].gd_flags = 1197 GEM_DMA_WRITE(sc, flags); 1198 } 1199 lasttx = nexttx; 1200 } 1201 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1202 /* add padding buffer at end of chain */ 1203 flags &= ~GEM_TD_END_OF_PACKET; 1204 sc->sc_txdescs[lasttx].gd_flags = 1205 GEM_DMA_WRITE(sc, flags); 1206 1207 sc->sc_txdescs[nexttx].gd_addr = 1208 GEM_DMA_WRITE(sc, 1209 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1210 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1211 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1212 lasttx = nexttx; 1213 nexttx = GEM_NEXTTX(nexttx); 1214 seg++; 1215 } 1216 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1217 1218 KASSERT(lasttx != -1); 1219 1220 /* 1221 * Store a pointer to the packet so we can free it later, 1222 * and remember what txdirty will be once the packet is 1223 * done. 1224 */ 1225 txs->txs_mbuf = m0; 1226 txs->txs_firstdesc = sc->sc_txnext; 1227 txs->txs_lastdesc = lasttx; 1228 txs->txs_ndescs = seg; 1229 1230 #ifdef GEM_DEBUG 1231 if (ifp->if_flags & IFF_DEBUG) { 1232 printf(" gem_start %p transmit chain:\n", txs); 1233 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1234 printf("descriptor %d:\t", seg); 1235 printf("gd_flags: 0x%016llx\t", (long long) 1236 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1237 printf("gd_addr: 0x%016llx\n", (long long) 1238 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1239 if (seg == lasttx) 1240 break; 1241 } 1242 } 1243 #endif 1244 1245 /* Sync the descriptors we're using. */ 1246 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1247 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1248 1249 /* Advance the tx pointer. */ 1250 sc->sc_txfree -= txs->txs_ndescs; 1251 sc->sc_txnext = nexttx; 1252 1253 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1254 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1255 1256 last_txs = txs; 1257 1258 #if NBPFILTER > 0 1259 /* 1260 * Pass the packet to any BPF listeners. 1261 */ 1262 if (ifp->if_bpf) 1263 bpf_mtap(ifp->if_bpf, m0); 1264 #endif /* NBPFILTER > 0 */ 1265 } 1266 1267 if (txs == NULL || sc->sc_txfree == 0) { 1268 /* No more slots left; notify upper layer. */ 1269 ifp->if_flags |= IFF_OACTIVE; 1270 sc->sc_if_flags = ifp->if_flags; 1271 } 1272 1273 if (sc->sc_txfree != ofree) { 1274 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1275 sc->sc_dev.dv_xname, lasttx, firsttx)); 1276 /* 1277 * The entire packet chain is set up. 1278 * Kick the transmitter. 1279 */ 1280 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1281 sc->sc_dev.dv_xname, nexttx)); 1282 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1283 sc->sc_txnext); 1284 1285 /* Set a watchdog timer in case the chip flakes out. */ 1286 ifp->if_timer = 5; 1287 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1288 sc->sc_dev.dv_xname, ifp->if_timer)); 1289 } 1290 } 1291 1292 /* 1293 * Transmit interrupt. 1294 */ 1295 int 1296 gem_tint(sc) 1297 struct gem_softc *sc; 1298 { 1299 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1300 bus_space_tag_t t = sc->sc_bustag; 1301 bus_space_handle_t mac = sc->sc_h; 1302 struct gem_txsoft *txs; 1303 int txlast; 1304 int progress = 0; 1305 1306 1307 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1308 1309 /* 1310 * Unload collision counters 1311 */ 1312 ifp->if_collisions += 1313 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1314 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1315 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1316 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1317 1318 /* 1319 * then clear the hardware counters. 1320 */ 1321 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1322 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1323 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1324 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1325 1326 /* 1327 * Go through our Tx list and free mbufs for those 1328 * frames that have been transmitted. 1329 */ 1330 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1331 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1332 txs->txs_ndescs, 1333 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1334 1335 #ifdef GEM_DEBUG 1336 if (ifp->if_flags & IFF_DEBUG) { 1337 int i; 1338 printf(" txsoft %p transmit chain:\n", txs); 1339 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1340 printf("descriptor %d: ", i); 1341 printf("gd_flags: 0x%016llx\t", (long long) 1342 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1343 printf("gd_addr: 0x%016llx\n", (long long) 1344 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1345 if (i == txs->txs_lastdesc) 1346 break; 1347 } 1348 } 1349 #endif 1350 1351 /* 1352 * In theory, we could harveast some descriptors before 1353 * the ring is empty, but that's a bit complicated. 1354 * 1355 * GEM_TX_COMPLETION points to the last descriptor 1356 * processed +1. 1357 */ 1358 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1359 DPRINTF(sc, 1360 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1361 txs->txs_lastdesc, txlast)); 1362 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1363 if ((txlast >= txs->txs_firstdesc) && 1364 (txlast <= txs->txs_lastdesc)) 1365 break; 1366 } else { 1367 /* Ick -- this command wraps */ 1368 if ((txlast >= txs->txs_firstdesc) || 1369 (txlast <= txs->txs_lastdesc)) 1370 break; 1371 } 1372 1373 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1374 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1375 1376 sc->sc_txfree += txs->txs_ndescs; 1377 1378 if (txs->txs_mbuf == NULL) { 1379 #ifdef DIAGNOSTIC 1380 panic("gem_txintr: null mbuf"); 1381 #endif 1382 } 1383 1384 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1385 0, txs->txs_dmamap->dm_mapsize, 1386 BUS_DMASYNC_POSTWRITE); 1387 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1388 m_freem(txs->txs_mbuf); 1389 txs->txs_mbuf = NULL; 1390 1391 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1392 1393 ifp->if_opackets++; 1394 progress = 1; 1395 } 1396 1397 #if 0 1398 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1399 "GEM_TX_DATA_PTR %llx " 1400 "GEM_TX_COMPLETION %x\n", 1401 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1402 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1403 GEM_TX_DATA_PTR_HI) << 32) | 1404 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1405 GEM_TX_DATA_PTR_LO), 1406 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1407 #endif 1408 1409 if (progress) { 1410 if (sc->sc_txfree == GEM_NTXDESC - 1) 1411 sc->sc_txwin = 0; 1412 1413 ifp->if_flags &= ~IFF_OACTIVE; 1414 sc->sc_if_flags = ifp->if_flags; 1415 gem_start(ifp); 1416 1417 if (SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) 1418 ifp->if_timer = 0; 1419 } 1420 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1421 sc->sc_dev.dv_xname, ifp->if_timer)); 1422 1423 return (1); 1424 } 1425 1426 /* 1427 * Receive interrupt. 1428 */ 1429 int 1430 gem_rint(sc) 1431 struct gem_softc *sc; 1432 { 1433 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1434 bus_space_tag_t t = sc->sc_bustag; 1435 bus_space_handle_t h = sc->sc_h; 1436 struct gem_rxsoft *rxs; 1437 struct mbuf *m; 1438 u_int64_t rxstat; 1439 u_int32_t rxcomp; 1440 int i, len, progress = 0; 1441 1442 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1443 1444 /* 1445 * Read the completion register once. This limits 1446 * how long the following loop can execute. 1447 */ 1448 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1449 1450 /* 1451 * XXXX Read the lastrx only once at the top for speed. 1452 */ 1453 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1454 sc->sc_rxptr, rxcomp)); 1455 1456 /* 1457 * Go into the loop at least once. 1458 */ 1459 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1460 i = GEM_NEXTRX(i)) { 1461 rxs = &sc->sc_rxsoft[i]; 1462 1463 GEM_CDRXSYNC(sc, i, 1464 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1465 1466 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1467 1468 if (rxstat & GEM_RD_OWN) { 1469 /* 1470 * We have processed all of the receive buffers. 1471 */ 1472 break; 1473 } 1474 1475 progress++; 1476 ifp->if_ipackets++; 1477 1478 if (rxstat & GEM_RD_BAD_CRC) { 1479 ifp->if_ierrors++; 1480 printf("%s: receive error: CRC error\n", 1481 sc->sc_dev.dv_xname); 1482 GEM_INIT_RXDESC(sc, i); 1483 continue; 1484 } 1485 1486 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1487 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1488 #ifdef GEM_DEBUG 1489 if (ifp->if_flags & IFF_DEBUG) { 1490 printf(" rxsoft %p descriptor %d: ", rxs, i); 1491 printf("gd_flags: 0x%016llx\t", (long long) 1492 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1493 printf("gd_addr: 0x%016llx\n", (long long) 1494 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1495 } 1496 #endif 1497 1498 /* No errors; receive the packet. */ 1499 len = GEM_RD_BUFLEN(rxstat); 1500 1501 /* 1502 * Allocate a new mbuf cluster. If that fails, we are 1503 * out of memory, and must drop the packet and recycle 1504 * the buffer that's already attached to this descriptor. 1505 */ 1506 m = rxs->rxs_mbuf; 1507 if (gem_add_rxbuf(sc, i) != 0) { 1508 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1509 ifp->if_ierrors++; 1510 GEM_INIT_RXDESC(sc, i); 1511 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1512 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1513 continue; 1514 } 1515 m->m_data += 2; /* We're already off by two */ 1516 1517 m->m_pkthdr.rcvif = ifp; 1518 m->m_pkthdr.len = m->m_len = len; 1519 1520 #if NBPFILTER > 0 1521 /* 1522 * Pass this up to any BPF listeners, but only 1523 * pass it up the stack if its for us. 1524 */ 1525 if (ifp->if_bpf) 1526 bpf_mtap(ifp->if_bpf, m); 1527 #endif /* NPBFILTER > 0 */ 1528 1529 #ifdef INET 1530 /* hardware checksum */ 1531 if (ifp->if_csum_flags_rx & (M_CSUM_UDPv4 | M_CSUM_TCPv4)) { 1532 struct ether_header *eh; 1533 struct ip *ip; 1534 struct udphdr *uh; 1535 int32_t hlen, pktlen; 1536 1537 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1538 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1539 ETHER_VLAN_ENCAP_LEN; 1540 eh = (struct ether_header *) mtod(m, caddr_t) + 1541 ETHER_VLAN_ENCAP_LEN; 1542 } else { 1543 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1544 eh = mtod(m, struct ether_header *); 1545 } 1546 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1547 goto swcsum; 1548 ip = (struct ip *) ((caddr_t)eh + ETHER_HDR_LEN); 1549 1550 /* IPv4 only */ 1551 if (ip->ip_v != IPVERSION) 1552 goto swcsum; 1553 1554 hlen = ip->ip_hl << 2; 1555 if (hlen < sizeof(struct ip)) 1556 goto swcsum; 1557 1558 /* 1559 * bail if too short, has random trailing garbage, 1560 * truncated, fragment, or has ethernet pad. 1561 */ 1562 if ((ntohs(ip->ip_len) < hlen) || 1563 (ntohs(ip->ip_len) != pktlen) || 1564 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1565 goto swcsum; 1566 1567 switch (ip->ip_p) { 1568 case IPPROTO_TCP: 1569 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1570 goto swcsum; 1571 if (pktlen < (hlen + sizeof(struct tcphdr))) 1572 goto swcsum; 1573 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1574 break; 1575 case IPPROTO_UDP: 1576 if (! (ifp->if_csum_flags_rx & M_CSUM_UDPv4)) 1577 goto swcsum; 1578 if (pktlen < (hlen + sizeof(struct udphdr))) 1579 goto swcsum; 1580 uh = (struct udphdr *)((caddr_t)ip + hlen); 1581 /* no checksum */ 1582 if (uh->uh_sum == 0) 1583 goto swcsum; 1584 m->m_pkthdr.csum_flags = M_CSUM_UDPv4; 1585 break; 1586 default: 1587 goto swcsum; 1588 } 1589 1590 /* the uncomplemented sum is expected */ 1591 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1592 1593 /* if the pkt had ip options, we have to deduct them */ 1594 if (hlen > sizeof(struct ip)) { 1595 uint16_t *opts; 1596 uint32_t optsum, temp; 1597 1598 optsum = 0; 1599 temp = hlen - sizeof(struct ip); 1600 opts = (uint16_t *) ((caddr_t) ip + 1601 sizeof(struct ip)); 1602 1603 while (temp > 1) { 1604 optsum += ntohs(*opts++); 1605 temp -= 2; 1606 } 1607 while (optsum >> 16) 1608 optsum = (optsum >> 16) + 1609 (optsum & 0xffff); 1610 1611 /* Deduct ip opts sum from hwsum (rfc 1624). */ 1612 m->m_pkthdr.csum_data = 1613 ~((~m->m_pkthdr.csum_data) - ~optsum); 1614 1615 while (m->m_pkthdr.csum_data >> 16) 1616 m->m_pkthdr.csum_data = 1617 (m->m_pkthdr.csum_data >> 16) + 1618 (m->m_pkthdr.csum_data & 1619 0xffff); 1620 } 1621 1622 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1623 M_CSUM_NO_PSEUDOHDR; 1624 } else 1625 swcsum: 1626 m->m_pkthdr.csum_flags = 0; 1627 #endif 1628 /* Pass it on. */ 1629 (*ifp->if_input)(ifp, m); 1630 } 1631 1632 if (progress) { 1633 /* Update the receive pointer. */ 1634 if (i == sc->sc_rxptr) { 1635 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1636 #ifdef GEM_DEBUG 1637 if (ifp->if_flags & IFF_DEBUG) 1638 printf("%s: rint: ring wrap\n", 1639 sc->sc_dev.dv_xname); 1640 #endif 1641 } 1642 sc->sc_rxptr = i; 1643 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1644 } 1645 #ifdef GEM_COUNTERS 1646 if (progress <= 4) { 1647 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1648 } else if (progress < 32) { 1649 if (progress < 16) 1650 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1651 else 1652 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1653 1654 } else { 1655 if (progress < 64) 1656 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1657 else 1658 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1659 } 1660 #endif 1661 1662 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1663 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1664 1665 return (1); 1666 } 1667 1668 1669 /* 1670 * gem_add_rxbuf: 1671 * 1672 * Add a receive buffer to the indicated descriptor. 1673 */ 1674 int 1675 gem_add_rxbuf(struct gem_softc *sc, int idx) 1676 { 1677 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1678 struct mbuf *m; 1679 int error; 1680 1681 MGETHDR(m, M_DONTWAIT, MT_DATA); 1682 if (m == NULL) 1683 return (ENOBUFS); 1684 1685 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1686 MCLGET(m, M_DONTWAIT); 1687 if ((m->m_flags & M_EXT) == 0) { 1688 m_freem(m); 1689 return (ENOBUFS); 1690 } 1691 1692 #ifdef GEM_DEBUG 1693 /* bzero the packet to check DMA */ 1694 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1695 #endif 1696 1697 if (rxs->rxs_mbuf != NULL) 1698 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1699 1700 rxs->rxs_mbuf = m; 1701 1702 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1703 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1704 BUS_DMA_READ|BUS_DMA_NOWAIT); 1705 if (error) { 1706 printf("%s: can't load rx DMA map %d, error = %d\n", 1707 sc->sc_dev.dv_xname, idx, error); 1708 panic("gem_add_rxbuf"); /* XXX */ 1709 } 1710 1711 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1712 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1713 1714 GEM_INIT_RXDESC(sc, idx); 1715 1716 return (0); 1717 } 1718 1719 1720 int 1721 gem_eint(sc, status) 1722 struct gem_softc *sc; 1723 u_int status; 1724 { 1725 char bits[128]; 1726 1727 if ((status & GEM_INTR_MIF) != 0) { 1728 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1729 return (1); 1730 } 1731 1732 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1733 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1734 return (1); 1735 } 1736 1737 1738 int 1739 gem_intr(v) 1740 void *v; 1741 { 1742 struct gem_softc *sc = (struct gem_softc *)v; 1743 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1744 bus_space_tag_t t = sc->sc_bustag; 1745 bus_space_handle_t seb = sc->sc_h; 1746 u_int32_t status; 1747 int r = 0; 1748 #ifdef GEM_DEBUG 1749 char bits[128]; 1750 #endif 1751 1752 sc->sc_ev_intr.ev_count++; 1753 1754 status = bus_space_read_4(t, seb, GEM_STATUS); 1755 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 1756 sc->sc_dev.dv_xname, (status >> 19), 1757 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1758 1759 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1760 r |= gem_eint(sc, status); 1761 1762 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 1763 GEM_COUNTER_INCR(sc, sc_ev_txint); 1764 r |= gem_tint(sc); 1765 } 1766 1767 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 1768 GEM_COUNTER_INCR(sc, sc_ev_rxint); 1769 r |= gem_rint(sc); 1770 } 1771 1772 /* We should eventually do more than just print out error stats. */ 1773 if (status & GEM_INTR_TX_MAC) { 1774 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1775 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1776 printf("%s: MAC tx fault, status %x\n", 1777 sc->sc_dev.dv_xname, txstat); 1778 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 1779 gem_init(ifp); 1780 } 1781 if (status & GEM_INTR_RX_MAC) { 1782 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1783 if (rxstat & ~GEM_MAC_RX_DONE) 1784 printf("%s: MAC rx fault, status %x\n", 1785 sc->sc_dev.dv_xname, rxstat); 1786 /* 1787 * On some chip revisions GEM_MAC_RX_OVERFLOW happen often 1788 * due to a silicon bug so handle them silently. 1789 */ 1790 if (rxstat & GEM_MAC_RX_OVERFLOW) 1791 gem_init(ifp); 1792 else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 1793 printf("%s: MAC rx fault, status %x\n", 1794 sc->sc_dev.dv_xname, rxstat); 1795 } 1796 #if NRND > 0 1797 rnd_add_uint32(&sc->rnd_source, status); 1798 #endif 1799 return (r); 1800 } 1801 1802 1803 void 1804 gem_watchdog(ifp) 1805 struct ifnet *ifp; 1806 { 1807 struct gem_softc *sc = ifp->if_softc; 1808 1809 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1810 "GEM_MAC_RX_CONFIG %x\n", 1811 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1812 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1813 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1814 1815 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1816 ++ifp->if_oerrors; 1817 1818 /* Try to get more packets going. */ 1819 gem_start(ifp); 1820 } 1821 1822 /* 1823 * Initialize the MII Management Interface 1824 */ 1825 void 1826 gem_mifinit(sc) 1827 struct gem_softc *sc; 1828 { 1829 bus_space_tag_t t = sc->sc_bustag; 1830 bus_space_handle_t mif = sc->sc_h; 1831 1832 /* Configure the MIF in frame mode */ 1833 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1834 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1835 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1836 } 1837 1838 /* 1839 * MII interface 1840 * 1841 * The GEM MII interface supports at least three different operating modes: 1842 * 1843 * Bitbang mode is implemented using data, clock and output enable registers. 1844 * 1845 * Frame mode is implemented by loading a complete frame into the frame 1846 * register and polling the valid bit for completion. 1847 * 1848 * Polling mode uses the frame register but completion is indicated by 1849 * an interrupt. 1850 * 1851 */ 1852 static int 1853 gem_mii_readreg(self, phy, reg) 1854 struct device *self; 1855 int phy, reg; 1856 { 1857 struct gem_softc *sc = (void *)self; 1858 bus_space_tag_t t = sc->sc_bustag; 1859 bus_space_handle_t mif = sc->sc_h; 1860 int n; 1861 u_int32_t v; 1862 1863 #ifdef GEM_DEBUG1 1864 if (sc->sc_debug) 1865 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1866 #endif 1867 1868 #if 0 1869 /* Select the desired PHY in the MIF configuration register */ 1870 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1871 /* Clear PHY select bit */ 1872 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1873 if (phy == GEM_PHYAD_EXTERNAL) 1874 /* Set PHY select bit to get at external device */ 1875 v |= GEM_MIF_CONFIG_PHY_SEL; 1876 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1877 #endif 1878 1879 /* Construct the frame command */ 1880 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1881 GEM_MIF_FRAME_READ; 1882 1883 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1884 for (n = 0; n < 100; n++) { 1885 DELAY(1); 1886 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1887 if (v & GEM_MIF_FRAME_TA0) 1888 return (v & GEM_MIF_FRAME_DATA); 1889 } 1890 1891 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1892 return (0); 1893 } 1894 1895 static void 1896 gem_mii_writereg(self, phy, reg, val) 1897 struct device *self; 1898 int phy, reg, val; 1899 { 1900 struct gem_softc *sc = (void *)self; 1901 bus_space_tag_t t = sc->sc_bustag; 1902 bus_space_handle_t mif = sc->sc_h; 1903 int n; 1904 u_int32_t v; 1905 1906 #ifdef GEM_DEBUG1 1907 if (sc->sc_debug) 1908 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1909 phy, reg, val); 1910 #endif 1911 1912 #if 0 1913 /* Select the desired PHY in the MIF configuration register */ 1914 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1915 /* Clear PHY select bit */ 1916 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1917 if (phy == GEM_PHYAD_EXTERNAL) 1918 /* Set PHY select bit to get at external device */ 1919 v |= GEM_MIF_CONFIG_PHY_SEL; 1920 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1921 #endif 1922 /* Construct the frame command */ 1923 v = GEM_MIF_FRAME_WRITE | 1924 (phy << GEM_MIF_PHY_SHIFT) | 1925 (reg << GEM_MIF_REG_SHIFT) | 1926 (val & GEM_MIF_FRAME_DATA); 1927 1928 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1929 for (n = 0; n < 100; n++) { 1930 DELAY(1); 1931 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1932 if (v & GEM_MIF_FRAME_TA0) 1933 return; 1934 } 1935 1936 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1937 } 1938 1939 static void 1940 gem_mii_statchg(dev) 1941 struct device *dev; 1942 { 1943 struct gem_softc *sc = (void *)dev; 1944 #ifdef GEM_DEBUG 1945 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1946 #endif 1947 bus_space_tag_t t = sc->sc_bustag; 1948 bus_space_handle_t mac = sc->sc_h; 1949 u_int32_t v; 1950 1951 #ifdef GEM_DEBUG 1952 if (sc->sc_debug) 1953 printf("gem_mii_statchg: status change: phy = %d\n", 1954 sc->sc_phys[instance]); 1955 #endif 1956 1957 1958 /* Set tx full duplex options */ 1959 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1960 delay(10000); /* reg must be cleared and delay before changing. */ 1961 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1962 GEM_MAC_TX_ENABLE; 1963 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1964 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1965 } 1966 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1967 1968 /* XIF Configuration */ 1969 /* We should really calculate all this rather than rely on defaults */ 1970 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1971 v = GEM_MAC_XIF_LINK_LED; 1972 v |= GEM_MAC_XIF_TX_MII_ENA; 1973 1974 /* If an external transceiver is connected, enable its MII drivers */ 1975 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1976 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1977 /* External MII needs echo disable if half duplex. */ 1978 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1979 /* turn on full duplex LED */ 1980 v |= GEM_MAC_XIF_FDPLX_LED; 1981 else 1982 /* half duplex -- disable echo */ 1983 v |= GEM_MAC_XIF_ECHO_DISABL; 1984 1985 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 1986 v |= GEM_MAC_XIF_GMII_MODE; 1987 else 1988 v &= ~GEM_MAC_XIF_GMII_MODE; 1989 } else 1990 /* Internal MII needs buf enable */ 1991 v |= GEM_MAC_XIF_MII_BUF_ENA; 1992 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1993 } 1994 1995 int 1996 gem_mediachange(ifp) 1997 struct ifnet *ifp; 1998 { 1999 struct gem_softc *sc = ifp->if_softc; 2000 2001 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 2002 return (EINVAL); 2003 2004 return (mii_mediachg(&sc->sc_mii)); 2005 } 2006 2007 void 2008 gem_mediastatus(ifp, ifmr) 2009 struct ifnet *ifp; 2010 struct ifmediareq *ifmr; 2011 { 2012 struct gem_softc *sc = ifp->if_softc; 2013 2014 if ((ifp->if_flags & IFF_UP) == 0) 2015 return; 2016 2017 mii_pollstat(&sc->sc_mii); 2018 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2019 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2020 } 2021 2022 /* 2023 * Process an ioctl request. 2024 */ 2025 int 2026 gem_ioctl(ifp, cmd, data) 2027 struct ifnet *ifp; 2028 u_long cmd; 2029 caddr_t data; 2030 { 2031 struct gem_softc *sc = ifp->if_softc; 2032 struct ifreq *ifr = (struct ifreq *)data; 2033 int s, error = 0; 2034 2035 s = splnet(); 2036 2037 switch (cmd) { 2038 case SIOCGIFMEDIA: 2039 case SIOCSIFMEDIA: 2040 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 2041 break; 2042 case SIOCSIFFLAGS: 2043 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 2044 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 2045 == (IFF_UP|IFF_RUNNING)) 2046 && ((ifp->if_flags & (~RESETIGN)) 2047 == (sc->sc_if_flags & (~RESETIGN)))) { 2048 gem_setladrf(sc); 2049 break; 2050 } 2051 #undef RESETIGN 2052 /*FALLTHROUGH*/ 2053 default: 2054 error = ether_ioctl(ifp, cmd, data); 2055 if (error == ENETRESET) { 2056 /* 2057 * Multicast list has changed; set the hardware filter 2058 * accordingly. 2059 */ 2060 if (ifp->if_flags & IFF_RUNNING) 2061 gem_setladrf(sc); 2062 error = 0; 2063 } 2064 break; 2065 } 2066 2067 /* Try to get things going again */ 2068 if (ifp->if_flags & IFF_UP) 2069 gem_start(ifp); 2070 splx(s); 2071 return (error); 2072 } 2073 2074 2075 void 2076 gem_shutdown(arg) 2077 void *arg; 2078 { 2079 struct gem_softc *sc = (struct gem_softc *)arg; 2080 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2081 2082 gem_stop(ifp, 1); 2083 } 2084 2085 /* 2086 * Set up the logical address filter. 2087 */ 2088 void 2089 gem_setladrf(sc) 2090 struct gem_softc *sc; 2091 { 2092 struct ethercom *ec = &sc->sc_ethercom; 2093 struct ifnet *ifp = &ec->ec_if; 2094 struct ether_multi *enm; 2095 struct ether_multistep step; 2096 bus_space_tag_t t = sc->sc_bustag; 2097 bus_space_handle_t h = sc->sc_h; 2098 u_int32_t crc; 2099 u_int32_t hash[16]; 2100 u_int32_t v; 2101 int i; 2102 2103 /* Get current RX configuration */ 2104 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2105 2106 /* 2107 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2108 * and hash filter. Depending on the case, the right bit will be 2109 * enabled. 2110 */ 2111 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2112 GEM_MAC_RX_PROMISC_GRP); 2113 2114 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2115 /* Turn on promiscuous mode */ 2116 v |= GEM_MAC_RX_PROMISCUOUS; 2117 ifp->if_flags |= IFF_ALLMULTI; 2118 goto chipit; 2119 } 2120 2121 /* 2122 * Set up multicast address filter by passing all multicast addresses 2123 * through a crc generator, and then using the high order 8 bits as an 2124 * index into the 256 bit logical address filter. The high order 4 2125 * bits selects the word, while the other 4 bits select the bit within 2126 * the word (where bit 0 is the MSB). 2127 */ 2128 2129 /* Clear hash table */ 2130 memset(hash, 0, sizeof(hash)); 2131 2132 ETHER_FIRST_MULTI(step, ec, enm); 2133 while (enm != NULL) { 2134 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2135 /* 2136 * We must listen to a range of multicast addresses. 2137 * For now, just accept all multicasts, rather than 2138 * trying to set only those filter bits needed to match 2139 * the range. (At this time, the only use of address 2140 * ranges is for IP multicast routing, for which the 2141 * range is big enough to require all bits set.) 2142 * XXX use the addr filter for this 2143 */ 2144 ifp->if_flags |= IFF_ALLMULTI; 2145 v |= GEM_MAC_RX_PROMISC_GRP; 2146 goto chipit; 2147 } 2148 2149 /* Get the LE CRC32 of the address */ 2150 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2151 2152 /* Just want the 8 most significant bits. */ 2153 crc >>= 24; 2154 2155 /* Set the corresponding bit in the filter. */ 2156 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2157 2158 ETHER_NEXT_MULTI(step, enm); 2159 } 2160 2161 v |= GEM_MAC_RX_HASH_FILTER; 2162 ifp->if_flags &= ~IFF_ALLMULTI; 2163 2164 /* Now load the hash table into the chip (if we are using it) */ 2165 for (i = 0; i < 16; i++) { 2166 bus_space_write_4(t, h, 2167 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2168 hash[i]); 2169 } 2170 2171 chipit: 2172 sc->sc_if_flags = ifp->if_flags; 2173 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2174 } 2175 2176 #if notyet 2177 2178 /* 2179 * gem_power: 2180 * 2181 * Power management (suspend/resume) hook. 2182 */ 2183 void 2184 gem_power(why, arg) 2185 int why; 2186 void *arg; 2187 { 2188 struct gem_softc *sc = arg; 2189 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2190 int s; 2191 2192 s = splnet(); 2193 switch (why) { 2194 case PWR_SUSPEND: 2195 case PWR_STANDBY: 2196 gem_stop(ifp, 1); 2197 if (sc->sc_power != NULL) 2198 (*sc->sc_power)(sc, why); 2199 break; 2200 case PWR_RESUME: 2201 if (ifp->if_flags & IFF_UP) { 2202 if (sc->sc_power != NULL) 2203 (*sc->sc_power)(sc, why); 2204 gem_init(ifp); 2205 } 2206 break; 2207 case PWR_SOFTSUSPEND: 2208 case PWR_SOFTSTANDBY: 2209 case PWR_SOFTRESUME: 2210 break; 2211 } 2212 splx(s); 2213 } 2214 #endif 2215