1 /* $NetBSD: gem.c,v 1.98 2012/02/02 19:43:03 tls Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.98 2012/02/02 19:43:03 tls Exp $"); 41 42 #include "opt_inet.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/callout.h> 47 #include <sys/mbuf.h> 48 #include <sys/syslog.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/device.h> 55 56 #include <machine/endian.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #include <net/bpf.h> 73 74 #include <sys/bus.h> 75 #include <sys/intr.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/ic/gemreg.h> 82 #include <dev/ic/gemvar.h> 83 84 #define TRIES 10000 85 86 static void gem_inten(struct gem_softc *); 87 static void gem_start(struct ifnet *); 88 static void gem_stop(struct ifnet *, int); 89 int gem_ioctl(struct ifnet *, u_long, void *); 90 void gem_tick(void *); 91 void gem_watchdog(struct ifnet *); 92 void gem_pcs_start(struct gem_softc *sc); 93 void gem_pcs_stop(struct gem_softc *sc, int); 94 int gem_init(struct ifnet *); 95 void gem_init_regs(struct gem_softc *sc); 96 static int gem_ringsize(int sz); 97 static int gem_meminit(struct gem_softc *); 98 void gem_mifinit(struct gem_softc *); 99 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 100 u_int32_t, u_int32_t); 101 void gem_reset(struct gem_softc *); 102 int gem_reset_rx(struct gem_softc *sc); 103 static void gem_reset_rxdma(struct gem_softc *sc); 104 static void gem_rx_common(struct gem_softc *sc); 105 int gem_reset_tx(struct gem_softc *sc); 106 int gem_disable_rx(struct gem_softc *sc); 107 int gem_disable_tx(struct gem_softc *sc); 108 static void gem_rxdrain(struct gem_softc *sc); 109 int gem_add_rxbuf(struct gem_softc *sc, int idx); 110 void gem_setladrf(struct gem_softc *); 111 112 /* MII methods & callbacks */ 113 static int gem_mii_readreg(device_t, int, int); 114 static void gem_mii_writereg(device_t, int, int, int); 115 static void gem_mii_statchg(device_t); 116 117 static int gem_ifflags_cb(struct ethercom *); 118 119 void gem_statuschange(struct gem_softc *); 120 121 int gem_ser_mediachange(struct ifnet *); 122 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 123 124 static void gem_partial_detach(struct gem_softc *, enum gem_attach_stage); 125 126 struct mbuf *gem_get(struct gem_softc *, int, int); 127 int gem_put(struct gem_softc *, int, struct mbuf *); 128 void gem_read(struct gem_softc *, int, int); 129 int gem_pint(struct gem_softc *); 130 int gem_eint(struct gem_softc *, u_int); 131 int gem_rint(struct gem_softc *); 132 int gem_tint(struct gem_softc *); 133 void gem_power(int, void *); 134 135 #ifdef GEM_DEBUG 136 static void gem_txsoft_print(const struct gem_softc *, int, int); 137 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 138 printf x 139 #else 140 #define DPRINTF(sc, x) /* nothing */ 141 #endif 142 143 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 144 145 int 146 gem_detach(struct gem_softc *sc, int flags) 147 { 148 int i; 149 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 150 bus_space_tag_t t = sc->sc_bustag; 151 bus_space_handle_t h = sc->sc_h1; 152 153 /* 154 * Free any resources we've allocated during the attach. 155 * Do this in reverse order and fall through. 156 */ 157 switch (sc->sc_att_stage) { 158 case GEM_ATT_BACKEND_2: 159 case GEM_ATT_BACKEND_1: 160 case GEM_ATT_FINISHED: 161 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 162 gem_stop(&sc->sc_ethercom.ec_if, 1); 163 164 #ifdef GEM_COUNTERS 165 for (i = __arraycount(sc->sc_ev_rxhist); --i >= 0; ) 166 evcnt_detach(&sc->sc_ev_rxhist[i]); 167 evcnt_detach(&sc->sc_ev_rxnobuf); 168 evcnt_detach(&sc->sc_ev_rxfull); 169 evcnt_detach(&sc->sc_ev_rxint); 170 evcnt_detach(&sc->sc_ev_txint); 171 #endif 172 evcnt_detach(&sc->sc_ev_intr); 173 174 rnd_detach_source(&sc->rnd_source); 175 ether_ifdetach(ifp); 176 if_detach(ifp); 177 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 178 179 callout_destroy(&sc->sc_tick_ch); 180 181 /*FALLTHROUGH*/ 182 case GEM_ATT_MII: 183 sc->sc_att_stage = GEM_ATT_MII; 184 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 185 /*FALLTHROUGH*/ 186 case GEM_ATT_7: 187 for (i = 0; i < GEM_NRXDESC; i++) { 188 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 189 bus_dmamap_destroy(sc->sc_dmatag, 190 sc->sc_rxsoft[i].rxs_dmamap); 191 } 192 /*FALLTHROUGH*/ 193 case GEM_ATT_6: 194 for (i = 0; i < GEM_TXQUEUELEN; i++) { 195 if (sc->sc_txsoft[i].txs_dmamap != NULL) 196 bus_dmamap_destroy(sc->sc_dmatag, 197 sc->sc_txsoft[i].txs_dmamap); 198 } 199 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 200 /*FALLTHROUGH*/ 201 case GEM_ATT_5: 202 bus_dmamap_unload(sc->sc_dmatag, sc->sc_nulldmamap); 203 /*FALLTHROUGH*/ 204 case GEM_ATT_4: 205 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 206 /*FALLTHROUGH*/ 207 case GEM_ATT_3: 208 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 209 /*FALLTHROUGH*/ 210 case GEM_ATT_2: 211 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 212 sizeof(struct gem_control_data)); 213 /*FALLTHROUGH*/ 214 case GEM_ATT_1: 215 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 216 /*FALLTHROUGH*/ 217 case GEM_ATT_0: 218 sc->sc_att_stage = GEM_ATT_0; 219 /*FALLTHROUGH*/ 220 case GEM_ATT_BACKEND_0: 221 break; 222 } 223 return 0; 224 } 225 226 static void 227 gem_partial_detach(struct gem_softc *sc, enum gem_attach_stage stage) 228 { 229 cfattach_t ca = device_cfattach(sc->sc_dev); 230 231 sc->sc_att_stage = stage; 232 (*ca->ca_detach)(sc->sc_dev, 0); 233 } 234 235 /* 236 * gem_attach: 237 * 238 * Attach a Gem interface to the system. 239 */ 240 void 241 gem_attach(struct gem_softc *sc, const uint8_t *enaddr) 242 { 243 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 244 struct mii_data *mii = &sc->sc_mii; 245 bus_space_tag_t t = sc->sc_bustag; 246 bus_space_handle_t h = sc->sc_h1; 247 struct ifmedia_entry *ifm; 248 int i, error, phyaddr; 249 u_int32_t v; 250 char *nullbuf; 251 252 /* Make sure the chip is stopped. */ 253 ifp->if_softc = sc; 254 gem_reset(sc); 255 256 /* 257 * Allocate the control data structures, and create and load the 258 * DMA map for it. gem_control_data is 9216 bytes, we have space for 259 * the padding buffer in the bus_dmamem_alloc()'d memory. 260 */ 261 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 262 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 263 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 264 aprint_error_dev(sc->sc_dev, 265 "unable to allocate control data, error = %d\n", 266 error); 267 gem_partial_detach(sc, GEM_ATT_0); 268 return; 269 } 270 271 /* XXX should map this in with correct endianness */ 272 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 273 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 274 BUS_DMA_COHERENT)) != 0) { 275 aprint_error_dev(sc->sc_dev, 276 "unable to map control data, error = %d\n", error); 277 gem_partial_detach(sc, GEM_ATT_1); 278 return; 279 } 280 281 nullbuf = 282 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 283 284 if ((error = bus_dmamap_create(sc->sc_dmatag, 285 sizeof(struct gem_control_data), 1, 286 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 287 aprint_error_dev(sc->sc_dev, 288 "unable to create control data DMA map, error = %d\n", 289 error); 290 gem_partial_detach(sc, GEM_ATT_2); 291 return; 292 } 293 294 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 295 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 296 0)) != 0) { 297 aprint_error_dev(sc->sc_dev, 298 "unable to load control data DMA map, error = %d\n", 299 error); 300 gem_partial_detach(sc, GEM_ATT_3); 301 return; 302 } 303 304 memset(nullbuf, 0, ETHER_MIN_TX); 305 if ((error = bus_dmamap_create(sc->sc_dmatag, 306 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 307 aprint_error_dev(sc->sc_dev, 308 "unable to create padding DMA map, error = %d\n", error); 309 gem_partial_detach(sc, GEM_ATT_4); 310 return; 311 } 312 313 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 314 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 315 aprint_error_dev(sc->sc_dev, 316 "unable to load padding DMA map, error = %d\n", error); 317 gem_partial_detach(sc, GEM_ATT_5); 318 return; 319 } 320 321 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 322 BUS_DMASYNC_PREWRITE); 323 324 /* 325 * Initialize the transmit job descriptors. 326 */ 327 SIMPLEQ_INIT(&sc->sc_txfreeq); 328 SIMPLEQ_INIT(&sc->sc_txdirtyq); 329 330 /* 331 * Create the transmit buffer DMA maps. 332 */ 333 for (i = 0; i < GEM_TXQUEUELEN; i++) { 334 struct gem_txsoft *txs; 335 336 txs = &sc->sc_txsoft[i]; 337 txs->txs_mbuf = NULL; 338 if ((error = bus_dmamap_create(sc->sc_dmatag, 339 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 340 ETHER_MAX_LEN_JUMBO, 0, 0, 341 &txs->txs_dmamap)) != 0) { 342 aprint_error_dev(sc->sc_dev, 343 "unable to create tx DMA map %d, error = %d\n", 344 i, error); 345 gem_partial_detach(sc, GEM_ATT_6); 346 return; 347 } 348 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 349 } 350 351 /* 352 * Create the receive buffer DMA maps. 353 */ 354 for (i = 0; i < GEM_NRXDESC; i++) { 355 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 356 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 357 aprint_error_dev(sc->sc_dev, 358 "unable to create rx DMA map %d, error = %d\n", 359 i, error); 360 gem_partial_detach(sc, GEM_ATT_7); 361 return; 362 } 363 sc->sc_rxsoft[i].rxs_mbuf = NULL; 364 } 365 366 /* Initialize ifmedia structures and MII info */ 367 mii->mii_ifp = ifp; 368 mii->mii_readreg = gem_mii_readreg; 369 mii->mii_writereg = gem_mii_writereg; 370 mii->mii_statchg = gem_mii_statchg; 371 372 sc->sc_ethercom.ec_mii = mii; 373 374 /* 375 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 376 * Section 3.2.1 `Initialization Sequence'. 377 * However, we can't assume SERDES or Serialink if neither 378 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 379 * being set, as both are set on Sun X1141A (with SERDES). So, 380 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 381 * Also, for variants that report 2 PHY's, we prefer the external 382 * PHY over the internal PHY, so we look for that first. 383 */ 384 gem_mifinit(sc); 385 386 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 387 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 388 ether_mediastatus); 389 /* Look for external PHY */ 390 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 391 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 392 bus_space_write_4(t, h, GEM_MIF_CONFIG, 393 sc->sc_mif_config); 394 switch (sc->sc_variant) { 395 case GEM_SUN_ERI: 396 phyaddr = GEM_PHYAD_EXTERNAL; 397 break; 398 default: 399 phyaddr = MII_PHY_ANY; 400 break; 401 } 402 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 403 MII_OFFSET_ANY, MIIF_FORCEANEG); 404 } 405 #ifdef GEM_DEBUG 406 else 407 aprint_debug_dev(sc->sc_dev, "using external PHY\n"); 408 #endif 409 /* Look for internal PHY if no external PHY was found */ 410 if (LIST_EMPTY(&mii->mii_phys) && 411 sc->sc_mif_config & GEM_MIF_CONFIG_MDI0) { 412 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 413 bus_space_write_4(t, h, GEM_MIF_CONFIG, 414 sc->sc_mif_config); 415 switch (sc->sc_variant) { 416 case GEM_SUN_ERI: 417 case GEM_APPLE_K2_GMAC: 418 phyaddr = GEM_PHYAD_INTERNAL; 419 break; 420 case GEM_APPLE_GMAC: 421 phyaddr = GEM_PHYAD_EXTERNAL; 422 break; 423 default: 424 phyaddr = MII_PHY_ANY; 425 break; 426 } 427 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 428 MII_OFFSET_ANY, MIIF_FORCEANEG); 429 #ifdef GEM_DEBUG 430 if (!LIST_EMPTY(&mii->mii_phys)) 431 aprint_debug_dev(sc->sc_dev, 432 "using internal PHY\n"); 433 #endif 434 } 435 if (LIST_EMPTY(&mii->mii_phys)) { 436 /* No PHY attached */ 437 aprint_error_dev(sc->sc_dev, 438 "PHY probe failed\n"); 439 gem_partial_detach(sc, GEM_ATT_MII); 440 return; 441 } else { 442 struct mii_softc *child; 443 444 /* 445 * Walk along the list of attached MII devices and 446 * establish an `MII instance' to `PHY number' 447 * mapping. 448 */ 449 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 450 /* 451 * Note: we support just one PHY: the internal 452 * or external MII is already selected for us 453 * by the GEM_MIF_CONFIG register. 454 */ 455 if (child->mii_phy > 1 || child->mii_inst > 0) { 456 aprint_error_dev(sc->sc_dev, 457 "cannot accommodate MII device" 458 " %s at PHY %d, instance %d\n", 459 device_xname(child->mii_dev), 460 child->mii_phy, child->mii_inst); 461 continue; 462 } 463 sc->sc_phys[child->mii_inst] = child->mii_phy; 464 } 465 466 if (sc->sc_variant != GEM_SUN_ERI) 467 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 468 GEM_MII_DATAPATH_MII); 469 470 /* 471 * XXX - we can really do the following ONLY if the 472 * PHY indeed has the auto negotiation capability!! 473 */ 474 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 475 } 476 } else { 477 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 478 gem_ser_mediastatus); 479 /* SERDES or Serialink */ 480 if (sc->sc_flags & GEM_SERDES) { 481 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 482 GEM_MII_DATAPATH_SERDES); 483 } else { 484 sc->sc_flags |= GEM_SERIAL; 485 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 486 GEM_MII_DATAPATH_SERIAL); 487 } 488 489 aprint_normal_dev(sc->sc_dev, "using external PCS %s: ", 490 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 491 492 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL); 493 /* Check for FDX and HDX capabilities */ 494 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 495 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 496 ifmedia_add(&sc->sc_mii.mii_media, 497 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL); 498 aprint_normal("1000baseSX-FDX, "); 499 } 500 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 501 ifmedia_add(&sc->sc_mii.mii_media, 502 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL); 503 aprint_normal("1000baseSX-HDX, "); 504 } 505 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 506 sc->sc_mii_media = IFM_AUTO; 507 aprint_normal("auto\n"); 508 509 gem_pcs_stop(sc, 1); 510 } 511 512 /* 513 * From this point forward, the attachment cannot fail. A failure 514 * before this point releases all resources that may have been 515 * allocated. 516 */ 517 518 /* Announce ourselves. */ 519 aprint_normal_dev(sc->sc_dev, "Ethernet address %s", 520 ether_sprintf(enaddr)); 521 522 /* Get RX FIFO size */ 523 sc->sc_rxfifosize = 64 * 524 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 525 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 526 527 /* Get TX FIFO size */ 528 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 529 aprint_normal(", %uKB TX fifo\n", v / 16); 530 531 /* Initialize ifnet structure. */ 532 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 533 ifp->if_softc = sc; 534 ifp->if_flags = 535 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 536 sc->sc_if_flags = ifp->if_flags; 537 #if 0 538 /* 539 * The GEM hardware supports basic TCP checksum offloading only. 540 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 541 * have bugs in the receive checksum, so don't enable it for now. 542 */ 543 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 544 (GEM_IS_APPLE(sc) && 545 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 546 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 547 #endif 548 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 549 ifp->if_start = gem_start; 550 ifp->if_ioctl = gem_ioctl; 551 ifp->if_watchdog = gem_watchdog; 552 ifp->if_stop = gem_stop; 553 ifp->if_init = gem_init; 554 IFQ_SET_READY(&ifp->if_snd); 555 556 /* 557 * If we support GigE media, we support jumbo frames too. 558 * Unless we are Apple. 559 */ 560 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 561 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 562 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 563 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 564 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 565 if (!GEM_IS_APPLE(sc)) 566 sc->sc_ethercom.ec_capabilities 567 |= ETHERCAP_JUMBO_MTU; 568 sc->sc_flags |= GEM_GIGABIT; 569 break; 570 } 571 } 572 573 /* claim 802.1q capability */ 574 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 575 576 /* Attach the interface. */ 577 if_attach(ifp); 578 ether_ifattach(ifp, enaddr); 579 ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb); 580 581 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 582 RND_TYPE_NET, 0); 583 584 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 585 NULL, device_xname(sc->sc_dev), "interrupts"); 586 #ifdef GEM_COUNTERS 587 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 588 &sc->sc_ev_intr, device_xname(sc->sc_dev), "tx interrupts"); 589 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 590 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rx interrupts"); 591 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 592 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx ring full"); 593 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 594 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx malloc failure"); 595 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 596 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 0desc"); 597 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 598 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 1desc"); 599 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 600 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 2desc"); 601 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 602 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 3desc"); 603 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 604 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >3desc"); 605 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 606 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >7desc"); 607 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 608 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >15desc"); 609 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 610 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >31desc"); 611 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 612 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >63desc"); 613 #endif 614 615 callout_init(&sc->sc_tick_ch, 0); 616 617 sc->sc_att_stage = GEM_ATT_FINISHED; 618 619 return; 620 } 621 622 void 623 gem_tick(void *arg) 624 { 625 struct gem_softc *sc = arg; 626 int s; 627 628 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 629 /* 630 * We have to reset everything if we failed to get a 631 * PCS interrupt. Restarting the callout is handled 632 * in gem_pcs_start(). 633 */ 634 gem_init(&sc->sc_ethercom.ec_if); 635 } else { 636 s = splnet(); 637 mii_tick(&sc->sc_mii); 638 splx(s); 639 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 640 } 641 } 642 643 static int 644 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, u_int32_t clr, u_int32_t set) 645 { 646 int i; 647 u_int32_t reg; 648 649 for (i = TRIES; i--; DELAY(100)) { 650 reg = bus_space_read_4(sc->sc_bustag, h, r); 651 if ((reg & clr) == 0 && (reg & set) == set) 652 return (1); 653 } 654 return (0); 655 } 656 657 void 658 gem_reset(struct gem_softc *sc) 659 { 660 bus_space_tag_t t = sc->sc_bustag; 661 bus_space_handle_t h = sc->sc_h2; 662 int s; 663 664 s = splnet(); 665 DPRINTF(sc, ("%s: gem_reset\n", device_xname(sc->sc_dev))); 666 gem_reset_rx(sc); 667 gem_reset_tx(sc); 668 669 /* Do a full reset */ 670 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 671 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 672 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 673 splx(s); 674 } 675 676 677 /* 678 * gem_rxdrain: 679 * 680 * Drain the receive queue. 681 */ 682 static void 683 gem_rxdrain(struct gem_softc *sc) 684 { 685 struct gem_rxsoft *rxs; 686 int i; 687 688 for (i = 0; i < GEM_NRXDESC; i++) { 689 rxs = &sc->sc_rxsoft[i]; 690 if (rxs->rxs_mbuf != NULL) { 691 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 692 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 693 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 694 m_freem(rxs->rxs_mbuf); 695 rxs->rxs_mbuf = NULL; 696 } 697 } 698 } 699 700 /* 701 * Reset the whole thing. 702 */ 703 static void 704 gem_stop(struct ifnet *ifp, int disable) 705 { 706 struct gem_softc *sc = ifp->if_softc; 707 struct gem_txsoft *txs; 708 709 DPRINTF(sc, ("%s: gem_stop\n", device_xname(sc->sc_dev))); 710 711 callout_halt(&sc->sc_tick_ch, NULL); 712 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 713 gem_pcs_stop(sc, disable); 714 else 715 mii_down(&sc->sc_mii); 716 717 /* XXX - Should we reset these instead? */ 718 gem_disable_tx(sc); 719 gem_disable_rx(sc); 720 721 /* 722 * Release any queued transmit buffers. 723 */ 724 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 725 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 726 if (txs->txs_mbuf != NULL) { 727 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 728 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 729 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 730 m_freem(txs->txs_mbuf); 731 txs->txs_mbuf = NULL; 732 } 733 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 734 } 735 736 /* 737 * Mark the interface down and cancel the watchdog timer. 738 */ 739 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 740 sc->sc_if_flags = ifp->if_flags; 741 ifp->if_timer = 0; 742 743 if (disable) 744 gem_rxdrain(sc); 745 } 746 747 748 /* 749 * Reset the receiver 750 */ 751 int 752 gem_reset_rx(struct gem_softc *sc) 753 { 754 bus_space_tag_t t = sc->sc_bustag; 755 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 756 757 /* 758 * Resetting while DMA is in progress can cause a bus hang, so we 759 * disable DMA first. 760 */ 761 gem_disable_rx(sc); 762 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 763 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 764 /* Wait till it finishes */ 765 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 766 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 767 768 /* Finally, reset the ERX */ 769 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 770 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 771 /* Wait till it finishes */ 772 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 773 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 774 return (1); 775 } 776 return (0); 777 } 778 779 780 /* 781 * Reset the receiver DMA engine. 782 * 783 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 784 * etc in order to reset the receiver DMA engine only and not do a full 785 * reset which amongst others also downs the link and clears the FIFOs. 786 */ 787 static void 788 gem_reset_rxdma(struct gem_softc *sc) 789 { 790 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 791 bus_space_tag_t t = sc->sc_bustag; 792 bus_space_handle_t h = sc->sc_h1; 793 int i; 794 795 if (gem_reset_rx(sc) != 0) { 796 gem_init(ifp); 797 return; 798 } 799 for (i = 0; i < GEM_NRXDESC; i++) 800 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 801 GEM_UPDATE_RXDESC(sc, i); 802 sc->sc_rxptr = 0; 803 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 804 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 805 806 /* Reprogram Descriptor Ring Base Addresses */ 807 /* NOTE: we use only 32-bit DMA addresses here. */ 808 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 809 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 810 811 /* Redo ERX Configuration */ 812 gem_rx_common(sc); 813 814 /* Give the reciever a swift kick */ 815 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 816 } 817 818 /* 819 * Common RX configuration for gem_init() and gem_reset_rxdma(). 820 */ 821 static void 822 gem_rx_common(struct gem_softc *sc) 823 { 824 bus_space_tag_t t = sc->sc_bustag; 825 bus_space_handle_t h = sc->sc_h1; 826 u_int32_t v; 827 828 /* Encode Receive Descriptor ring size: four possible values */ 829 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 830 831 /* Set receive h/w checksum offset */ 832 #ifdef INET 833 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 834 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 835 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 836 #endif 837 838 /* Enable RX DMA */ 839 bus_space_write_4(t, h, GEM_RX_CONFIG, 840 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 841 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 842 843 /* 844 * The following value is for an OFF Threshold of about 3/4 full 845 * and an ON Threshold of 1/4 full. 846 */ 847 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 848 (3 * sc->sc_rxfifosize / 256) | 849 ((sc->sc_rxfifosize / 256) << 12)); 850 bus_space_write_4(t, h, GEM_RX_BLANKING, 851 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6); 852 } 853 854 /* 855 * Reset the transmitter 856 */ 857 int 858 gem_reset_tx(struct gem_softc *sc) 859 { 860 bus_space_tag_t t = sc->sc_bustag; 861 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 862 863 /* 864 * Resetting while DMA is in progress can cause a bus hang, so we 865 * disable DMA first. 866 */ 867 gem_disable_tx(sc); 868 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 869 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 870 /* Wait till it finishes */ 871 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 872 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 873 /* Wait 5ms extra. */ 874 delay(5000); 875 876 /* Finally, reset the ETX */ 877 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 878 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 879 /* Wait till it finishes */ 880 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 881 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 882 return (1); 883 } 884 return (0); 885 } 886 887 /* 888 * disable receiver. 889 */ 890 int 891 gem_disable_rx(struct gem_softc *sc) 892 { 893 bus_space_tag_t t = sc->sc_bustag; 894 bus_space_handle_t h = sc->sc_h1; 895 u_int32_t cfg; 896 897 /* Flip the enable bit */ 898 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 899 cfg &= ~GEM_MAC_RX_ENABLE; 900 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 901 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 902 /* Wait for it to finish */ 903 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 904 } 905 906 /* 907 * disable transmitter. 908 */ 909 int 910 gem_disable_tx(struct gem_softc *sc) 911 { 912 bus_space_tag_t t = sc->sc_bustag; 913 bus_space_handle_t h = sc->sc_h1; 914 u_int32_t cfg; 915 916 /* Flip the enable bit */ 917 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 918 cfg &= ~GEM_MAC_TX_ENABLE; 919 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 920 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 921 /* Wait for it to finish */ 922 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 923 } 924 925 /* 926 * Initialize interface. 927 */ 928 int 929 gem_meminit(struct gem_softc *sc) 930 { 931 struct gem_rxsoft *rxs; 932 int i, error; 933 934 /* 935 * Initialize the transmit descriptor ring. 936 */ 937 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 938 for (i = 0; i < GEM_NTXDESC; i++) { 939 sc->sc_txdescs[i].gd_flags = 0; 940 sc->sc_txdescs[i].gd_addr = 0; 941 } 942 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 943 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 944 sc->sc_txfree = GEM_NTXDESC-1; 945 sc->sc_txnext = 0; 946 sc->sc_txwin = 0; 947 948 /* 949 * Initialize the receive descriptor and receive job 950 * descriptor rings. 951 */ 952 for (i = 0; i < GEM_NRXDESC; i++) { 953 rxs = &sc->sc_rxsoft[i]; 954 if (rxs->rxs_mbuf == NULL) { 955 if ((error = gem_add_rxbuf(sc, i)) != 0) { 956 aprint_error_dev(sc->sc_dev, 957 "unable to allocate or map rx " 958 "buffer %d, error = %d\n", 959 i, error); 960 /* 961 * XXX Should attempt to run with fewer receive 962 * XXX buffers instead of just failing. 963 */ 964 gem_rxdrain(sc); 965 return (1); 966 } 967 } else 968 GEM_INIT_RXDESC(sc, i); 969 } 970 sc->sc_rxptr = 0; 971 sc->sc_meminited = 1; 972 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 973 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 974 975 return (0); 976 } 977 978 static int 979 gem_ringsize(int sz) 980 { 981 switch (sz) { 982 case 32: 983 return GEM_RING_SZ_32; 984 case 64: 985 return GEM_RING_SZ_64; 986 case 128: 987 return GEM_RING_SZ_128; 988 case 256: 989 return GEM_RING_SZ_256; 990 case 512: 991 return GEM_RING_SZ_512; 992 case 1024: 993 return GEM_RING_SZ_1024; 994 case 2048: 995 return GEM_RING_SZ_2048; 996 case 4096: 997 return GEM_RING_SZ_4096; 998 case 8192: 999 return GEM_RING_SZ_8192; 1000 default: 1001 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 1002 return GEM_RING_SZ_32; 1003 } 1004 } 1005 1006 1007 /* 1008 * Start PCS 1009 */ 1010 void 1011 gem_pcs_start(struct gem_softc *sc) 1012 { 1013 bus_space_tag_t t = sc->sc_bustag; 1014 bus_space_handle_t h = sc->sc_h1; 1015 uint32_t v; 1016 1017 #ifdef GEM_DEBUG 1018 aprint_debug_dev(sc->sc_dev, "gem_pcs_start()\n"); 1019 #endif 1020 1021 /* 1022 * Set up. We must disable the MII before modifying the 1023 * GEM_MII_ANAR register 1024 */ 1025 if (sc->sc_flags & GEM_SERDES) { 1026 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1027 GEM_MII_DATAPATH_SERDES); 1028 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1029 GEM_MII_SLINK_LOOPBACK); 1030 } else { 1031 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1032 GEM_MII_DATAPATH_SERIAL); 1033 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 1034 } 1035 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1036 v = bus_space_read_4(t, h, GEM_MII_ANAR); 1037 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 1038 if (sc->sc_mii_media == IFM_AUTO) 1039 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 1040 else if (sc->sc_mii_media == IFM_FDX) { 1041 v |= GEM_MII_ANEG_FUL_DUPLX; 1042 v &= ~GEM_MII_ANEG_HLF_DUPLX; 1043 } else if (sc->sc_mii_media == IFM_HDX) { 1044 v &= ~GEM_MII_ANEG_FUL_DUPLX; 1045 v |= GEM_MII_ANEG_HLF_DUPLX; 1046 } 1047 1048 /* Configure link. */ 1049 bus_space_write_4(t, h, GEM_MII_ANAR, v); 1050 bus_space_write_4(t, h, GEM_MII_CONTROL, 1051 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1052 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 1053 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 1054 1055 /* Start the 10 second timer */ 1056 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 1057 } 1058 1059 /* 1060 * Stop PCS 1061 */ 1062 void 1063 gem_pcs_stop(struct gem_softc *sc, int disable) 1064 { 1065 bus_space_tag_t t = sc->sc_bustag; 1066 bus_space_handle_t h = sc->sc_h1; 1067 1068 #ifdef GEM_DEBUG 1069 aprint_debug_dev(sc->sc_dev, "gem_pcs_stop()\n"); 1070 #endif 1071 1072 /* Tell link partner that we're going away */ 1073 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1074 1075 /* 1076 * Disable PCS MII. The documentation suggests that setting 1077 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1078 * negotiation will shut down the link. However, it appears 1079 * that we also need to unset the datapath mode. 1080 */ 1081 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1082 bus_space_write_4(t, h, GEM_MII_CONTROL, 1083 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1084 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1085 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1086 1087 if (disable) { 1088 if (sc->sc_flags & GEM_SERDES) 1089 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1090 GEM_MII_SLINK_POWER_OFF); 1091 else 1092 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1093 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1094 } 1095 1096 sc->sc_flags &= ~GEM_LINK; 1097 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1098 sc->sc_mii.mii_media_status = IFM_AVALID; 1099 } 1100 1101 1102 /* 1103 * Initialization of interface; set up initialization block 1104 * and transmit/receive descriptor rings. 1105 */ 1106 int 1107 gem_init(struct ifnet *ifp) 1108 { 1109 struct gem_softc *sc = ifp->if_softc; 1110 bus_space_tag_t t = sc->sc_bustag; 1111 bus_space_handle_t h = sc->sc_h1; 1112 int rc = 0, s; 1113 u_int max_frame_size; 1114 u_int32_t v; 1115 1116 s = splnet(); 1117 1118 DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(sc->sc_dev))); 1119 /* 1120 * Initialization sequence. The numbered steps below correspond 1121 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1122 * Channel Engine manual (part of the PCIO manual). 1123 * See also the STP2002-STQ document from Sun Microsystems. 1124 */ 1125 1126 /* step 1 & 2. Reset the Ethernet Channel */ 1127 gem_stop(ifp, 0); 1128 gem_reset(sc); 1129 DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(sc->sc_dev))); 1130 1131 /* Re-initialize the MIF */ 1132 gem_mifinit(sc); 1133 1134 /* Set up correct datapath for non-SERDES/Serialink */ 1135 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1136 sc->sc_variant != GEM_SUN_ERI) 1137 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1138 GEM_MII_DATAPATH_MII); 1139 1140 /* Call MI reset function if any */ 1141 if (sc->sc_hwreset) 1142 (*sc->sc_hwreset)(sc); 1143 1144 /* step 3. Setup data structures in host memory */ 1145 if (gem_meminit(sc) != 0) 1146 return 1; 1147 1148 /* step 4. TX MAC registers & counters */ 1149 gem_init_regs(sc); 1150 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1151 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1152 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1153 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1154 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1155 max_frame_size|/* burst size */(0x2000<<16)); 1156 1157 /* step 5. RX MAC registers & counters */ 1158 gem_setladrf(sc); 1159 1160 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1161 /* NOTE: we use only 32-bit DMA addresses here. */ 1162 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 1163 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1164 1165 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 1166 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1167 1168 /* step 8. Global Configuration & Interrupt Mask */ 1169 gem_inten(sc); 1170 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1171 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1172 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1173 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1174 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1175 1176 /* step 9. ETX Configuration: use mostly default values */ 1177 1178 /* Enable TX DMA */ 1179 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1180 bus_space_write_4(t, h, GEM_TX_CONFIG, 1181 v | GEM_TX_CONFIG_TXDMA_EN | 1182 (((sc->sc_flags & GEM_GIGABIT ? 0x4FF : 0x100) << 10) & 1183 GEM_TX_CONFIG_TXFIFO_TH)); 1184 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1185 1186 /* step 10. ERX Configuration */ 1187 gem_rx_common(sc); 1188 1189 /* step 11. Configure Media */ 1190 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1191 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1192 goto out; 1193 1194 /* step 12. RX_MAC Configuration Register */ 1195 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1196 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1197 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1198 1199 /* step 14. Issue Transmit Pending command */ 1200 1201 /* Call MI initialization function if any */ 1202 if (sc->sc_hwinit) 1203 (*sc->sc_hwinit)(sc); 1204 1205 1206 /* step 15. Give the reciever a swift kick */ 1207 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1208 1209 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1210 /* Configure PCS */ 1211 gem_pcs_start(sc); 1212 else 1213 /* Start the one second timer. */ 1214 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1215 1216 sc->sc_flags &= ~GEM_LINK; 1217 ifp->if_flags |= IFF_RUNNING; 1218 ifp->if_flags &= ~IFF_OACTIVE; 1219 ifp->if_timer = 0; 1220 sc->sc_if_flags = ifp->if_flags; 1221 out: 1222 splx(s); 1223 1224 return (0); 1225 } 1226 1227 void 1228 gem_init_regs(struct gem_softc *sc) 1229 { 1230 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1231 bus_space_tag_t t = sc->sc_bustag; 1232 bus_space_handle_t h = sc->sc_h1; 1233 const u_char *laddr = CLLADDR(ifp->if_sadl); 1234 u_int32_t v; 1235 1236 /* These regs are not cleared on reset */ 1237 if (!sc->sc_inited) { 1238 1239 /* Load recommended values */ 1240 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1241 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1242 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1243 1244 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1245 /* Max frame and max burst size */ 1246 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1247 ETHER_MAX_LEN | (0x2000<<16)); 1248 1249 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1250 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1251 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1252 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1253 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1254 ((laddr[5]<<8)|laddr[4])&0x3ff); 1255 1256 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1257 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1258 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1259 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1260 1261 /* MAC control addr set to 01:80:c2:00:00:01 */ 1262 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1263 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1264 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1265 1266 /* MAC filter addr set to 0:0:0:0:0:0 */ 1267 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1268 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1269 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1270 1271 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1272 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1273 1274 sc->sc_inited = 1; 1275 } 1276 1277 /* Counters need to be zeroed */ 1278 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1279 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1280 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1281 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1282 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1283 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1284 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1285 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1286 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1287 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1288 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1289 1290 /* Set XOFF PAUSE time. */ 1291 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1292 1293 /* 1294 * Set the internal arbitration to "infinite" bursts of the 1295 * maximum length of 31 * 64 bytes so DMA transfers aren't 1296 * split up in cache line size chunks. This greatly improves 1297 * especially RX performance. 1298 * Enable silicon bug workarounds for the Apple variants. 1299 */ 1300 bus_space_write_4(t, h, GEM_CONFIG, 1301 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1302 ((sc->sc_flags & GEM_PCI) ? 1303 GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1304 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1305 1306 /* 1307 * Set the station address. 1308 */ 1309 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1310 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1311 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1312 1313 /* 1314 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1315 */ 1316 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1317 v = GEM_MAC_XIF_TX_MII_ENA; 1318 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1319 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1320 v |= GEM_MAC_XIF_FDPLX_LED; 1321 if (sc->sc_flags & GEM_GIGABIT) 1322 v |= GEM_MAC_XIF_GMII_MODE; 1323 } 1324 } else { 1325 v |= GEM_MAC_XIF_GMII_MODE; 1326 } 1327 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1328 } 1329 1330 #ifdef GEM_DEBUG 1331 static void 1332 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1333 { 1334 int i; 1335 1336 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1337 printf("descriptor %d:\t", i); 1338 printf("gd_flags: 0x%016" PRIx64 "\t", 1339 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1340 printf("gd_addr: 0x%016" PRIx64 "\n", 1341 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1342 if (i == lastdesc) 1343 break; 1344 } 1345 } 1346 #endif 1347 1348 static void 1349 gem_start(struct ifnet *ifp) 1350 { 1351 struct gem_softc *sc = ifp->if_softc; 1352 struct mbuf *m0, *m; 1353 struct gem_txsoft *txs; 1354 bus_dmamap_t dmamap; 1355 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1356 uint64_t flags = 0; 1357 1358 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1359 return; 1360 1361 /* 1362 * Remember the previous number of free descriptors and 1363 * the first descriptor we'll use. 1364 */ 1365 ofree = sc->sc_txfree; 1366 firsttx = sc->sc_txnext; 1367 1368 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1369 device_xname(sc->sc_dev), ofree, firsttx)); 1370 1371 /* 1372 * Loop through the send queue, setting up transmit descriptors 1373 * until we drain the queue, or use up all available transmit 1374 * descriptors. 1375 */ 1376 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1377 sc->sc_txfree != 0) { 1378 /* 1379 * Grab a packet off the queue. 1380 */ 1381 IFQ_POLL(&ifp->if_snd, m0); 1382 if (m0 == NULL) 1383 break; 1384 m = NULL; 1385 1386 dmamap = txs->txs_dmamap; 1387 1388 /* 1389 * Load the DMA map. If this fails, the packet either 1390 * didn't fit in the alloted number of segments, or we were 1391 * short on resources. In this case, we'll copy and try 1392 * again. 1393 */ 1394 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1395 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1396 (m0->m_pkthdr.len < ETHER_MIN_TX && 1397 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1398 if (m0->m_pkthdr.len > MCLBYTES) { 1399 aprint_error_dev(sc->sc_dev, 1400 "unable to allocate jumbo Tx cluster\n"); 1401 IFQ_DEQUEUE(&ifp->if_snd, m0); 1402 m_freem(m0); 1403 continue; 1404 } 1405 MGETHDR(m, M_DONTWAIT, MT_DATA); 1406 if (m == NULL) { 1407 aprint_error_dev(sc->sc_dev, 1408 "unable to allocate Tx mbuf\n"); 1409 break; 1410 } 1411 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1412 if (m0->m_pkthdr.len > MHLEN) { 1413 MCLGET(m, M_DONTWAIT); 1414 if ((m->m_flags & M_EXT) == 0) { 1415 aprint_error_dev(sc->sc_dev, 1416 "unable to allocate Tx cluster\n"); 1417 m_freem(m); 1418 break; 1419 } 1420 } 1421 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1422 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1423 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1424 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1425 if (error) { 1426 aprint_error_dev(sc->sc_dev, 1427 "unable to load Tx buffer, error = %d\n", 1428 error); 1429 break; 1430 } 1431 } 1432 1433 /* 1434 * Ensure we have enough descriptors free to describe 1435 * the packet. 1436 */ 1437 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1438 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1439 /* 1440 * Not enough free descriptors to transmit this 1441 * packet. We haven't committed to anything yet, 1442 * so just unload the DMA map, put the packet 1443 * back on the queue, and punt. Notify the upper 1444 * layer that there are no more slots left. 1445 * 1446 * XXX We could allocate an mbuf and copy, but 1447 * XXX it is worth it? 1448 */ 1449 ifp->if_flags |= IFF_OACTIVE; 1450 sc->sc_if_flags = ifp->if_flags; 1451 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1452 if (m != NULL) 1453 m_freem(m); 1454 break; 1455 } 1456 1457 IFQ_DEQUEUE(&ifp->if_snd, m0); 1458 if (m != NULL) { 1459 m_freem(m0); 1460 m0 = m; 1461 } 1462 1463 /* 1464 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1465 */ 1466 1467 /* Sync the DMA map. */ 1468 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1469 BUS_DMASYNC_PREWRITE); 1470 1471 /* 1472 * Initialize the transmit descriptors. 1473 */ 1474 for (nexttx = sc->sc_txnext, seg = 0; 1475 seg < dmamap->dm_nsegs; 1476 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1477 1478 /* 1479 * If this is the first descriptor we're 1480 * enqueueing, set the start of packet flag, 1481 * and the checksum stuff if we want the hardware 1482 * to do it. 1483 */ 1484 sc->sc_txdescs[nexttx].gd_addr = 1485 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1486 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1487 if (nexttx == firsttx) { 1488 flags |= GEM_TD_START_OF_PACKET; 1489 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1490 sc->sc_txwin = 0; 1491 flags |= GEM_TD_INTERRUPT_ME; 1492 } 1493 1494 #ifdef INET 1495 /* h/w checksum */ 1496 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1497 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1498 struct ether_header *eh; 1499 uint16_t offset, start; 1500 1501 eh = mtod(m0, struct ether_header *); 1502 switch (ntohs(eh->ether_type)) { 1503 case ETHERTYPE_IP: 1504 start = ETHER_HDR_LEN; 1505 break; 1506 case ETHERTYPE_VLAN: 1507 start = ETHER_HDR_LEN + 1508 ETHER_VLAN_ENCAP_LEN; 1509 break; 1510 default: 1511 /* unsupported, drop it */ 1512 m_free(m0); 1513 continue; 1514 } 1515 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1516 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1517 flags |= (start << 1518 GEM_TD_CXSUM_STARTSHFT) | 1519 (offset << 1520 GEM_TD_CXSUM_STUFFSHFT) | 1521 GEM_TD_CXSUM_ENABLE; 1522 } 1523 #endif 1524 } 1525 if (seg == dmamap->dm_nsegs - 1) { 1526 flags |= GEM_TD_END_OF_PACKET; 1527 } else { 1528 /* last flag set outside of loop */ 1529 sc->sc_txdescs[nexttx].gd_flags = 1530 GEM_DMA_WRITE(sc, flags); 1531 } 1532 lasttx = nexttx; 1533 } 1534 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1535 /* add padding buffer at end of chain */ 1536 flags &= ~GEM_TD_END_OF_PACKET; 1537 sc->sc_txdescs[lasttx].gd_flags = 1538 GEM_DMA_WRITE(sc, flags); 1539 1540 sc->sc_txdescs[nexttx].gd_addr = 1541 GEM_DMA_WRITE(sc, 1542 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1543 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1544 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1545 lasttx = nexttx; 1546 nexttx = GEM_NEXTTX(nexttx); 1547 seg++; 1548 } 1549 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1550 1551 KASSERT(lasttx != -1); 1552 1553 /* 1554 * Store a pointer to the packet so we can free it later, 1555 * and remember what txdirty will be once the packet is 1556 * done. 1557 */ 1558 txs->txs_mbuf = m0; 1559 txs->txs_firstdesc = sc->sc_txnext; 1560 txs->txs_lastdesc = lasttx; 1561 txs->txs_ndescs = seg; 1562 1563 #ifdef GEM_DEBUG 1564 if (ifp->if_flags & IFF_DEBUG) { 1565 printf(" gem_start %p transmit chain:\n", txs); 1566 gem_txsoft_print(sc, txs->txs_firstdesc, 1567 txs->txs_lastdesc); 1568 } 1569 #endif 1570 1571 /* Sync the descriptors we're using. */ 1572 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1573 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1574 1575 /* Advance the tx pointer. */ 1576 sc->sc_txfree -= txs->txs_ndescs; 1577 sc->sc_txnext = nexttx; 1578 1579 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1580 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1581 1582 /* 1583 * Pass the packet to any BPF listeners. 1584 */ 1585 bpf_mtap(ifp, m0); 1586 } 1587 1588 if (txs == NULL || sc->sc_txfree == 0) { 1589 /* No more slots left; notify upper layer. */ 1590 ifp->if_flags |= IFF_OACTIVE; 1591 sc->sc_if_flags = ifp->if_flags; 1592 } 1593 1594 if (sc->sc_txfree != ofree) { 1595 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1596 device_xname(sc->sc_dev), lasttx, firsttx)); 1597 /* 1598 * The entire packet chain is set up. 1599 * Kick the transmitter. 1600 */ 1601 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1602 device_xname(sc->sc_dev), nexttx)); 1603 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1604 sc->sc_txnext); 1605 1606 /* Set a watchdog timer in case the chip flakes out. */ 1607 ifp->if_timer = 5; 1608 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1609 device_xname(sc->sc_dev), ifp->if_timer)); 1610 } 1611 } 1612 1613 /* 1614 * Transmit interrupt. 1615 */ 1616 int 1617 gem_tint(struct gem_softc *sc) 1618 { 1619 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1620 bus_space_tag_t t = sc->sc_bustag; 1621 bus_space_handle_t mac = sc->sc_h1; 1622 struct gem_txsoft *txs; 1623 int txlast; 1624 int progress = 0; 1625 u_int32_t v; 1626 1627 DPRINTF(sc, ("%s: gem_tint\n", device_xname(sc->sc_dev))); 1628 1629 /* Unload collision counters ... */ 1630 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1631 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1632 ifp->if_collisions += v + 1633 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1634 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT); 1635 ifp->if_oerrors += v; 1636 1637 /* ... then clear the hardware counters. */ 1638 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1639 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1640 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1641 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1642 1643 /* 1644 * Go through our Tx list and free mbufs for those 1645 * frames that have been transmitted. 1646 */ 1647 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1648 /* 1649 * In theory, we could harvest some descriptors before 1650 * the ring is empty, but that's a bit complicated. 1651 * 1652 * GEM_TX_COMPLETION points to the last descriptor 1653 * processed +1. 1654 * 1655 * Let's assume that the NIC writes back to the Tx 1656 * descriptors before it updates the completion 1657 * register. If the NIC has posted writes to the 1658 * Tx descriptors, PCI ordering requires that the 1659 * posted writes flush to RAM before the register-read 1660 * finishes. So let's read the completion register, 1661 * before syncing the descriptors, so that we 1662 * examine Tx descriptors that are at least as 1663 * current as the completion register. 1664 */ 1665 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1666 DPRINTF(sc, 1667 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1668 txs->txs_lastdesc, txlast)); 1669 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1670 if (txlast >= txs->txs_firstdesc && 1671 txlast <= txs->txs_lastdesc) 1672 break; 1673 } else if (txlast >= txs->txs_firstdesc || 1674 txlast <= txs->txs_lastdesc) 1675 break; 1676 1677 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1678 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1679 1680 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1681 if (ifp->if_flags & IFF_DEBUG) { 1682 printf(" txsoft %p transmit chain:\n", txs); 1683 gem_txsoft_print(sc, txs->txs_firstdesc, 1684 txs->txs_lastdesc); 1685 } 1686 #endif 1687 1688 1689 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1690 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1691 1692 sc->sc_txfree += txs->txs_ndescs; 1693 1694 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1695 0, txs->txs_dmamap->dm_mapsize, 1696 BUS_DMASYNC_POSTWRITE); 1697 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1698 if (txs->txs_mbuf != NULL) { 1699 m_freem(txs->txs_mbuf); 1700 txs->txs_mbuf = NULL; 1701 } 1702 1703 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1704 1705 ifp->if_opackets++; 1706 progress = 1; 1707 } 1708 1709 #if 0 1710 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1711 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1712 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1713 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1714 GEM_TX_DATA_PTR_HI) << 32) | 1715 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1716 GEM_TX_DATA_PTR_LO), 1717 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1718 #endif 1719 1720 if (progress) { 1721 if (sc->sc_txfree == GEM_NTXDESC - 1) 1722 sc->sc_txwin = 0; 1723 1724 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1725 ifp->if_flags &= ~IFF_OACTIVE; 1726 sc->sc_if_flags = ifp->if_flags; 1727 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1728 gem_start(ifp); 1729 } 1730 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1731 device_xname(sc->sc_dev), ifp->if_timer)); 1732 1733 return (1); 1734 } 1735 1736 /* 1737 * Receive interrupt. 1738 */ 1739 int 1740 gem_rint(struct gem_softc *sc) 1741 { 1742 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1743 bus_space_tag_t t = sc->sc_bustag; 1744 bus_space_handle_t h = sc->sc_h1; 1745 struct gem_rxsoft *rxs; 1746 struct mbuf *m; 1747 u_int64_t rxstat; 1748 u_int32_t rxcomp; 1749 int i, len, progress = 0; 1750 1751 DPRINTF(sc, ("%s: gem_rint\n", device_xname(sc->sc_dev))); 1752 1753 /* 1754 * Ignore spurious interrupt that sometimes occurs before 1755 * we are set up when we network boot. 1756 */ 1757 if (!sc->sc_meminited) 1758 return 1; 1759 1760 /* 1761 * Read the completion register once. This limits 1762 * how long the following loop can execute. 1763 */ 1764 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1765 1766 /* 1767 * XXX Read the lastrx only once at the top for speed. 1768 */ 1769 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1770 sc->sc_rxptr, rxcomp)); 1771 1772 /* 1773 * Go into the loop at least once. 1774 */ 1775 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1776 i = GEM_NEXTRX(i)) { 1777 rxs = &sc->sc_rxsoft[i]; 1778 1779 GEM_CDRXSYNC(sc, i, 1780 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1781 1782 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1783 1784 if (rxstat & GEM_RD_OWN) { 1785 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1786 /* 1787 * We have processed all of the receive buffers. 1788 */ 1789 break; 1790 } 1791 1792 progress++; 1793 ifp->if_ipackets++; 1794 1795 if (rxstat & GEM_RD_BAD_CRC) { 1796 ifp->if_ierrors++; 1797 aprint_error_dev(sc->sc_dev, 1798 "receive error: CRC error\n"); 1799 GEM_INIT_RXDESC(sc, i); 1800 continue; 1801 } 1802 1803 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1804 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1805 #ifdef GEM_DEBUG 1806 if (ifp->if_flags & IFF_DEBUG) { 1807 printf(" rxsoft %p descriptor %d: ", rxs, i); 1808 printf("gd_flags: 0x%016llx\t", (long long) 1809 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1810 printf("gd_addr: 0x%016llx\n", (long long) 1811 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1812 } 1813 #endif 1814 1815 /* No errors; receive the packet. */ 1816 len = GEM_RD_BUFLEN(rxstat); 1817 1818 /* 1819 * Allocate a new mbuf cluster. If that fails, we are 1820 * out of memory, and must drop the packet and recycle 1821 * the buffer that's already attached to this descriptor. 1822 */ 1823 m = rxs->rxs_mbuf; 1824 if (gem_add_rxbuf(sc, i) != 0) { 1825 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1826 ifp->if_ierrors++; 1827 GEM_INIT_RXDESC(sc, i); 1828 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1829 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1830 continue; 1831 } 1832 m->m_data += 2; /* We're already off by two */ 1833 1834 m->m_pkthdr.rcvif = ifp; 1835 m->m_pkthdr.len = m->m_len = len; 1836 1837 /* 1838 * Pass this up to any BPF listeners, but only 1839 * pass it up the stack if it's for us. 1840 */ 1841 bpf_mtap(ifp, m); 1842 1843 #ifdef INET 1844 /* hardware checksum */ 1845 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1846 struct ether_header *eh; 1847 struct ip *ip; 1848 int32_t hlen, pktlen; 1849 1850 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1851 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1852 ETHER_VLAN_ENCAP_LEN; 1853 eh = (struct ether_header *) (mtod(m, char *) + 1854 ETHER_VLAN_ENCAP_LEN); 1855 } else { 1856 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1857 eh = mtod(m, struct ether_header *); 1858 } 1859 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1860 goto swcsum; 1861 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1862 1863 /* IPv4 only */ 1864 if (ip->ip_v != IPVERSION) 1865 goto swcsum; 1866 1867 hlen = ip->ip_hl << 2; 1868 if (hlen < sizeof(struct ip)) 1869 goto swcsum; 1870 1871 /* 1872 * bail if too short, has random trailing garbage, 1873 * truncated, fragment, or has ethernet pad. 1874 */ 1875 if ((ntohs(ip->ip_len) < hlen) || 1876 (ntohs(ip->ip_len) != pktlen) || 1877 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1878 goto swcsum; 1879 1880 switch (ip->ip_p) { 1881 case IPPROTO_TCP: 1882 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1883 goto swcsum; 1884 if (pktlen < (hlen + sizeof(struct tcphdr))) 1885 goto swcsum; 1886 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1887 break; 1888 case IPPROTO_UDP: 1889 /* FALLTHROUGH */ 1890 default: 1891 goto swcsum; 1892 } 1893 1894 /* the uncomplemented sum is expected */ 1895 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1896 1897 /* if the pkt had ip options, we have to deduct them */ 1898 if (hlen > sizeof(struct ip)) { 1899 uint16_t *opts; 1900 uint32_t optsum, temp; 1901 1902 optsum = 0; 1903 temp = hlen - sizeof(struct ip); 1904 opts = (uint16_t *) ((char *) ip + 1905 sizeof(struct ip)); 1906 1907 while (temp > 1) { 1908 optsum += ntohs(*opts++); 1909 temp -= 2; 1910 } 1911 while (optsum >> 16) 1912 optsum = (optsum >> 16) + 1913 (optsum & 0xffff); 1914 1915 /* Deduct ip opts sum from hwsum. */ 1916 m->m_pkthdr.csum_data += (uint16_t)~optsum; 1917 1918 while (m->m_pkthdr.csum_data >> 16) 1919 m->m_pkthdr.csum_data = 1920 (m->m_pkthdr.csum_data >> 16) + 1921 (m->m_pkthdr.csum_data & 1922 0xffff); 1923 } 1924 1925 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1926 M_CSUM_NO_PSEUDOHDR; 1927 } else 1928 swcsum: 1929 m->m_pkthdr.csum_flags = 0; 1930 #endif 1931 /* Pass it on. */ 1932 (*ifp->if_input)(ifp, m); 1933 } 1934 1935 if (progress) { 1936 /* Update the receive pointer. */ 1937 if (i == sc->sc_rxptr) { 1938 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1939 #ifdef GEM_DEBUG 1940 if (ifp->if_flags & IFF_DEBUG) 1941 printf("%s: rint: ring wrap\n", 1942 device_xname(sc->sc_dev)); 1943 #endif 1944 } 1945 sc->sc_rxptr = i; 1946 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1947 } 1948 #ifdef GEM_COUNTERS 1949 if (progress <= 4) { 1950 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1951 } else if (progress < 32) { 1952 if (progress < 16) 1953 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1954 else 1955 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1956 1957 } else { 1958 if (progress < 64) 1959 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1960 else 1961 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1962 } 1963 #endif 1964 1965 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1966 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1967 1968 /* Read error counters ... */ 1969 ifp->if_ierrors += 1970 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1971 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1972 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1973 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL); 1974 1975 /* ... then clear the hardware counters. */ 1976 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1977 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1978 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1979 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1980 1981 return (1); 1982 } 1983 1984 1985 /* 1986 * gem_add_rxbuf: 1987 * 1988 * Add a receive buffer to the indicated descriptor. 1989 */ 1990 int 1991 gem_add_rxbuf(struct gem_softc *sc, int idx) 1992 { 1993 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1994 struct mbuf *m; 1995 int error; 1996 1997 MGETHDR(m, M_DONTWAIT, MT_DATA); 1998 if (m == NULL) 1999 return (ENOBUFS); 2000 2001 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2002 MCLGET(m, M_DONTWAIT); 2003 if ((m->m_flags & M_EXT) == 0) { 2004 m_freem(m); 2005 return (ENOBUFS); 2006 } 2007 2008 #ifdef GEM_DEBUG 2009 /* bzero the packet to check DMA */ 2010 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 2011 #endif 2012 2013 if (rxs->rxs_mbuf != NULL) 2014 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 2015 2016 rxs->rxs_mbuf = m; 2017 2018 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 2019 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2020 BUS_DMA_READ|BUS_DMA_NOWAIT); 2021 if (error) { 2022 aprint_error_dev(sc->sc_dev, 2023 "can't load rx DMA map %d, error = %d\n", idx, error); 2024 panic("gem_add_rxbuf"); /* XXX */ 2025 } 2026 2027 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 2028 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2029 2030 GEM_INIT_RXDESC(sc, idx); 2031 2032 return (0); 2033 } 2034 2035 2036 int 2037 gem_eint(struct gem_softc *sc, u_int status) 2038 { 2039 char bits[128]; 2040 u_int32_t r, v; 2041 2042 if ((status & GEM_INTR_MIF) != 0) { 2043 printf("%s: XXXlink status changed\n", device_xname(sc->sc_dev)); 2044 return (1); 2045 } 2046 2047 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 2048 gem_reset_rxdma(sc); 2049 return (1); 2050 } 2051 2052 if (status & GEM_INTR_BERR) { 2053 if (sc->sc_flags & GEM_PCI) 2054 r = GEM_ERROR_STATUS; 2055 else 2056 r = GEM_SBUS_ERROR_STATUS; 2057 bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2058 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2059 aprint_error_dev(sc->sc_dev, "bus error interrupt: 0x%02x\n", 2060 v); 2061 return (1); 2062 } 2063 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2064 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 2065 2066 return (1); 2067 } 2068 2069 2070 /* 2071 * PCS interrupts. 2072 * We should receive these when the link status changes, but sometimes 2073 * we don't receive them for link up. We compensate for this in the 2074 * gem_tick() callout. 2075 */ 2076 int 2077 gem_pint(struct gem_softc *sc) 2078 { 2079 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2080 bus_space_tag_t t = sc->sc_bustag; 2081 bus_space_handle_t h = sc->sc_h1; 2082 u_int32_t v, v2; 2083 2084 /* 2085 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2086 * latched, so we have to read it twice. There is only one bit in 2087 * use, so the value is meaningless. 2088 */ 2089 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2090 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2091 2092 if ((ifp->if_flags & IFF_UP) == 0) 2093 return 1; 2094 2095 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2096 return 1; 2097 2098 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2099 /* If we see remote fault, our link partner is probably going away */ 2100 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2101 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2102 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2103 /* Otherwise, we may need to wait after auto-negotiation completes */ 2104 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2105 GEM_MII_STATUS_ANEG_CPT) { 2106 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2107 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2108 } 2109 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2110 if (sc->sc_flags & GEM_LINK) { 2111 return 1; 2112 } 2113 callout_stop(&sc->sc_tick_ch); 2114 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2115 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2116 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2117 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2118 v &= v2; 2119 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2120 sc->sc_mii.mii_media_active |= IFM_FDX; 2121 #ifdef GEM_DEBUG 2122 aprint_debug_dev(sc->sc_dev, "link up: full duplex\n"); 2123 #endif 2124 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2125 sc->sc_mii.mii_media_active |= IFM_HDX; 2126 #ifdef GEM_DEBUG 2127 aprint_debug_dev(sc->sc_dev, "link up: half duplex\n"); 2128 #endif 2129 } else { 2130 #ifdef GEM_DEBUG 2131 aprint_debug_dev(sc->sc_dev, "duplex mismatch\n"); 2132 #endif 2133 } 2134 gem_statuschange(sc); 2135 } else { 2136 if ((sc->sc_flags & GEM_LINK) == 0) { 2137 return 1; 2138 } 2139 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2140 sc->sc_mii.mii_media_status = IFM_AVALID; 2141 #ifdef GEM_DEBUG 2142 aprint_debug_dev(sc->sc_dev, "link down\n"); 2143 #endif 2144 gem_statuschange(sc); 2145 2146 /* Start the 10 second timer */ 2147 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 2148 } 2149 return 1; 2150 } 2151 2152 2153 2154 int 2155 gem_intr(void *v) 2156 { 2157 struct gem_softc *sc = v; 2158 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2159 bus_space_tag_t t = sc->sc_bustag; 2160 bus_space_handle_t h = sc->sc_h1; 2161 u_int32_t status; 2162 int r = 0; 2163 #ifdef GEM_DEBUG 2164 char bits[128]; 2165 #endif 2166 2167 /* XXX We should probably mask out interrupts until we're done */ 2168 2169 sc->sc_ev_intr.ev_count++; 2170 2171 status = bus_space_read_4(t, h, GEM_STATUS); 2172 #ifdef GEM_DEBUG 2173 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2174 #endif 2175 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2176 device_xname(sc->sc_dev), (status >> 19), bits)); 2177 2178 2179 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2180 r |= gem_eint(sc, status); 2181 2182 /* We don't bother with GEM_INTR_TX_DONE */ 2183 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2184 GEM_COUNTER_INCR(sc, sc_ev_txint); 2185 r |= gem_tint(sc); 2186 } 2187 2188 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2189 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2190 r |= gem_rint(sc); 2191 } 2192 2193 /* We should eventually do more than just print out error stats. */ 2194 if (status & GEM_INTR_TX_MAC) { 2195 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2196 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2197 printf("%s: MAC tx fault, status %x\n", 2198 device_xname(sc->sc_dev), txstat); 2199 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2200 gem_init(ifp); 2201 } 2202 if (status & GEM_INTR_RX_MAC) { 2203 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2204 /* 2205 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2206 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2207 * silicon bug so handle them silently. Moreover, it's 2208 * likely that the receiver has hung so we reset it. 2209 */ 2210 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2211 ifp->if_ierrors++; 2212 gem_reset_rxdma(sc); 2213 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2214 printf("%s: MAC rx fault, status 0x%02x\n", 2215 device_xname(sc->sc_dev), rxstat); 2216 } 2217 if (status & GEM_INTR_PCS) { 2218 r |= gem_pint(sc); 2219 } 2220 2221 /* Do we need to do anything with these? 2222 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2223 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2224 if ((status2 & GEM_MAC_PAUSED) != 0) 2225 aprintf_debug_dev(sc->sc_dev, "PAUSE received (%d slots)\n", 2226 GEM_MAC_PAUSE_TIME(status2)); 2227 if ((status2 & GEM_MAC_PAUSE) != 0) 2228 aprintf_debug_dev(sc->sc_dev, "transited to PAUSE state\n"); 2229 if ((status2 & GEM_MAC_RESUME) != 0) 2230 aprintf_debug_dev(sc->sc_dev, "transited to non-PAUSE state\n"); 2231 } 2232 if ((status & GEM_INTR_MIF) != 0) 2233 aprintf_debug_dev(sc->sc_dev, "MIF interrupt\n"); 2234 */ 2235 rnd_add_uint32(&sc->rnd_source, status); 2236 return (r); 2237 } 2238 2239 2240 void 2241 gem_watchdog(struct ifnet *ifp) 2242 { 2243 struct gem_softc *sc = ifp->if_softc; 2244 2245 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2246 "GEM_MAC_RX_CONFIG %x\n", 2247 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2248 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2249 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2250 2251 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 2252 ++ifp->if_oerrors; 2253 2254 /* Try to get more packets going. */ 2255 gem_start(ifp); 2256 } 2257 2258 /* 2259 * Initialize the MII Management Interface 2260 */ 2261 void 2262 gem_mifinit(struct gem_softc *sc) 2263 { 2264 bus_space_tag_t t = sc->sc_bustag; 2265 bus_space_handle_t mif = sc->sc_h1; 2266 2267 /* Configure the MIF in frame mode */ 2268 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2269 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2270 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2271 } 2272 2273 /* 2274 * MII interface 2275 * 2276 * The GEM MII interface supports at least three different operating modes: 2277 * 2278 * Bitbang mode is implemented using data, clock and output enable registers. 2279 * 2280 * Frame mode is implemented by loading a complete frame into the frame 2281 * register and polling the valid bit for completion. 2282 * 2283 * Polling mode uses the frame register but completion is indicated by 2284 * an interrupt. 2285 * 2286 */ 2287 static int 2288 gem_mii_readreg(device_t self, int phy, int reg) 2289 { 2290 struct gem_softc *sc = device_private(self); 2291 bus_space_tag_t t = sc->sc_bustag; 2292 bus_space_handle_t mif = sc->sc_h1; 2293 int n; 2294 u_int32_t v; 2295 2296 #ifdef GEM_DEBUG1 2297 if (sc->sc_debug) 2298 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2299 #endif 2300 2301 /* Construct the frame command */ 2302 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2303 GEM_MIF_FRAME_READ; 2304 2305 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2306 for (n = 0; n < 100; n++) { 2307 DELAY(1); 2308 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2309 if (v & GEM_MIF_FRAME_TA0) 2310 return (v & GEM_MIF_FRAME_DATA); 2311 } 2312 2313 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 2314 return (0); 2315 } 2316 2317 static void 2318 gem_mii_writereg(device_t self, int phy, int reg, int val) 2319 { 2320 struct gem_softc *sc = device_private(self); 2321 bus_space_tag_t t = sc->sc_bustag; 2322 bus_space_handle_t mif = sc->sc_h1; 2323 int n; 2324 u_int32_t v; 2325 2326 #ifdef GEM_DEBUG1 2327 if (sc->sc_debug) 2328 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2329 phy, reg, val); 2330 #endif 2331 2332 /* Construct the frame command */ 2333 v = GEM_MIF_FRAME_WRITE | 2334 (phy << GEM_MIF_PHY_SHIFT) | 2335 (reg << GEM_MIF_REG_SHIFT) | 2336 (val & GEM_MIF_FRAME_DATA); 2337 2338 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2339 for (n = 0; n < 100; n++) { 2340 DELAY(1); 2341 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2342 if (v & GEM_MIF_FRAME_TA0) 2343 return; 2344 } 2345 2346 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 2347 } 2348 2349 static void 2350 gem_mii_statchg(device_t self) 2351 { 2352 struct gem_softc *sc = device_private(self); 2353 #ifdef GEM_DEBUG 2354 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2355 #endif 2356 2357 #ifdef GEM_DEBUG 2358 if (sc->sc_debug) 2359 printf("gem_mii_statchg: status change: phy = %d\n", 2360 sc->sc_phys[instance]); 2361 #endif 2362 gem_statuschange(sc); 2363 } 2364 2365 /* 2366 * Common status change for gem_mii_statchg() and gem_pint() 2367 */ 2368 void 2369 gem_statuschange(struct gem_softc* sc) 2370 { 2371 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2372 bus_space_tag_t t = sc->sc_bustag; 2373 bus_space_handle_t mac = sc->sc_h1; 2374 int gigabit; 2375 u_int32_t rxcfg, txcfg, v; 2376 2377 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2378 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2379 sc->sc_flags |= GEM_LINK; 2380 else 2381 sc->sc_flags &= ~GEM_LINK; 2382 2383 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2384 gigabit = 1; 2385 else 2386 gigabit = 0; 2387 2388 /* 2389 * The configuration done here corresponds to the steps F) and 2390 * G) and as far as enabling of RX and TX MAC goes also step H) 2391 * of the initialization sequence outlined in section 3.2.1 of 2392 * the GEM Gigabit Ethernet ASIC Specification. 2393 */ 2394 2395 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2396 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2397 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2398 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2399 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2400 else if (gigabit) { 2401 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2402 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2403 } 2404 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2405 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2406 BUS_SPACE_BARRIER_WRITE); 2407 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2408 aprint_normal_dev(sc->sc_dev, "cannot disable TX MAC\n"); 2409 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2410 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2411 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2412 BUS_SPACE_BARRIER_WRITE); 2413 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2414 aprint_normal_dev(sc->sc_dev, "cannot disable RX MAC\n"); 2415 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2416 2417 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2418 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2419 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2420 2421 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2422 gigabit != 0) 2423 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2424 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2425 else 2426 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2427 GEM_MAC_SLOT_TIME_NORMAL); 2428 2429 /* XIF Configuration */ 2430 if (sc->sc_flags & GEM_LINK) 2431 v = GEM_MAC_XIF_LINK_LED; 2432 else 2433 v = 0; 2434 v |= GEM_MAC_XIF_TX_MII_ENA; 2435 2436 /* If an external transceiver is connected, enable its MII drivers */ 2437 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2438 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2439 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2440 if (gigabit) 2441 v |= GEM_MAC_XIF_GMII_MODE; 2442 else 2443 v &= ~GEM_MAC_XIF_GMII_MODE; 2444 } else 2445 /* Internal MII needs buf enable */ 2446 v |= GEM_MAC_XIF_MII_BUF_ENA; 2447 /* MII needs echo disable if half duplex. */ 2448 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2449 /* turn on full duplex LED */ 2450 v |= GEM_MAC_XIF_FDPLX_LED; 2451 else 2452 /* half duplex -- disable echo */ 2453 v |= GEM_MAC_XIF_ECHO_DISABL; 2454 } else { 2455 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2456 v |= GEM_MAC_XIF_FDPLX_LED; 2457 v |= GEM_MAC_XIF_GMII_MODE; 2458 } 2459 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2460 2461 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2462 (sc->sc_flags & GEM_LINK) != 0) { 2463 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2464 txcfg | GEM_MAC_TX_ENABLE); 2465 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2466 rxcfg | GEM_MAC_RX_ENABLE); 2467 } 2468 } 2469 2470 int 2471 gem_ser_mediachange(struct ifnet *ifp) 2472 { 2473 struct gem_softc *sc = ifp->if_softc; 2474 u_int s, t; 2475 2476 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2477 return EINVAL; 2478 2479 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2480 if (s == IFM_AUTO) { 2481 if (sc->sc_mii_media != s) { 2482 #ifdef GEM_DEBUG 2483 aprint_debug_dev(sc->sc_dev, "setting media to auto\n"); 2484 #endif 2485 sc->sc_mii_media = s; 2486 if (ifp->if_flags & IFF_UP) { 2487 gem_pcs_stop(sc, 0); 2488 gem_pcs_start(sc); 2489 } 2490 } 2491 return 0; 2492 } 2493 if (s == IFM_1000_SX) { 2494 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media); 2495 if (t == IFM_FDX || t == IFM_HDX) { 2496 if (sc->sc_mii_media != t) { 2497 sc->sc_mii_media = t; 2498 #ifdef GEM_DEBUG 2499 aprint_debug_dev(sc->sc_dev, 2500 "setting media to 1000baseSX-%s\n", 2501 t == IFM_FDX ? "FDX" : "HDX"); 2502 #endif 2503 if (ifp->if_flags & IFF_UP) { 2504 gem_pcs_stop(sc, 0); 2505 gem_pcs_start(sc); 2506 } 2507 } 2508 return 0; 2509 } 2510 } 2511 return EINVAL; 2512 } 2513 2514 void 2515 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2516 { 2517 struct gem_softc *sc = ifp->if_softc; 2518 2519 if ((ifp->if_flags & IFF_UP) == 0) 2520 return; 2521 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2522 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2523 } 2524 2525 static int 2526 gem_ifflags_cb(struct ethercom *ec) 2527 { 2528 struct ifnet *ifp = &ec->ec_if; 2529 struct gem_softc *sc = ifp->if_softc; 2530 int change = ifp->if_flags ^ sc->sc_if_flags; 2531 2532 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 2533 return ENETRESET; 2534 else if ((change & IFF_PROMISC) != 0) 2535 gem_setladrf(sc); 2536 return 0; 2537 } 2538 2539 /* 2540 * Process an ioctl request. 2541 */ 2542 int 2543 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 2544 { 2545 struct gem_softc *sc = ifp->if_softc; 2546 int s, error = 0; 2547 2548 s = splnet(); 2549 2550 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2551 error = 0; 2552 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2553 ; 2554 else if (ifp->if_flags & IFF_RUNNING) { 2555 /* 2556 * Multicast list has changed; set the hardware filter 2557 * accordingly. 2558 */ 2559 gem_setladrf(sc); 2560 } 2561 } 2562 2563 /* Try to get things going again */ 2564 if (ifp->if_flags & IFF_UP) 2565 gem_start(ifp); 2566 splx(s); 2567 return (error); 2568 } 2569 2570 static void 2571 gem_inten(struct gem_softc *sc) 2572 { 2573 bus_space_tag_t t = sc->sc_bustag; 2574 bus_space_handle_t h = sc->sc_h1; 2575 uint32_t v; 2576 2577 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 2578 v = GEM_INTR_PCS; 2579 else 2580 v = GEM_INTR_MIF; 2581 bus_space_write_4(t, h, GEM_INTMASK, 2582 ~(GEM_INTR_TX_INTME | 2583 GEM_INTR_TX_EMPTY | 2584 GEM_INTR_TX_MAC | 2585 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF| 2586 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL| 2587 GEM_INTR_BERR | v)); 2588 } 2589 2590 bool 2591 gem_resume(device_t self, const pmf_qual_t *qual) 2592 { 2593 struct gem_softc *sc = device_private(self); 2594 2595 gem_inten(sc); 2596 2597 return true; 2598 } 2599 2600 bool 2601 gem_suspend(device_t self, const pmf_qual_t *qual) 2602 { 2603 struct gem_softc *sc = device_private(self); 2604 bus_space_tag_t t = sc->sc_bustag; 2605 bus_space_handle_t h = sc->sc_h1; 2606 2607 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 2608 2609 return true; 2610 } 2611 2612 bool 2613 gem_shutdown(device_t self, int howto) 2614 { 2615 struct gem_softc *sc = device_private(self); 2616 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2617 2618 gem_stop(ifp, 1); 2619 2620 return true; 2621 } 2622 2623 /* 2624 * Set up the logical address filter. 2625 */ 2626 void 2627 gem_setladrf(struct gem_softc *sc) 2628 { 2629 struct ethercom *ec = &sc->sc_ethercom; 2630 struct ifnet *ifp = &ec->ec_if; 2631 struct ether_multi *enm; 2632 struct ether_multistep step; 2633 bus_space_tag_t t = sc->sc_bustag; 2634 bus_space_handle_t h = sc->sc_h1; 2635 u_int32_t crc; 2636 u_int32_t hash[16]; 2637 u_int32_t v; 2638 int i; 2639 2640 /* Get current RX configuration */ 2641 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2642 2643 /* 2644 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2645 * and hash filter. Depending on the case, the right bit will be 2646 * enabled. 2647 */ 2648 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2649 GEM_MAC_RX_PROMISC_GRP); 2650 2651 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2652 /* Turn on promiscuous mode */ 2653 v |= GEM_MAC_RX_PROMISCUOUS; 2654 ifp->if_flags |= IFF_ALLMULTI; 2655 goto chipit; 2656 } 2657 2658 /* 2659 * Set up multicast address filter by passing all multicast addresses 2660 * through a crc generator, and then using the high order 8 bits as an 2661 * index into the 256 bit logical address filter. The high order 4 2662 * bits selects the word, while the other 4 bits select the bit within 2663 * the word (where bit 0 is the MSB). 2664 */ 2665 2666 /* Clear hash table */ 2667 memset(hash, 0, sizeof(hash)); 2668 2669 ETHER_FIRST_MULTI(step, ec, enm); 2670 while (enm != NULL) { 2671 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2672 /* 2673 * We must listen to a range of multicast addresses. 2674 * For now, just accept all multicasts, rather than 2675 * trying to set only those filter bits needed to match 2676 * the range. (At this time, the only use of address 2677 * ranges is for IP multicast routing, for which the 2678 * range is big enough to require all bits set.) 2679 * XXX should use the address filters for this 2680 */ 2681 ifp->if_flags |= IFF_ALLMULTI; 2682 v |= GEM_MAC_RX_PROMISC_GRP; 2683 goto chipit; 2684 } 2685 2686 /* Get the LE CRC32 of the address */ 2687 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2688 2689 /* Just want the 8 most significant bits. */ 2690 crc >>= 24; 2691 2692 /* Set the corresponding bit in the filter. */ 2693 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2694 2695 ETHER_NEXT_MULTI(step, enm); 2696 } 2697 2698 v |= GEM_MAC_RX_HASH_FILTER; 2699 ifp->if_flags &= ~IFF_ALLMULTI; 2700 2701 /* Now load the hash table into the chip (if we are using it) */ 2702 for (i = 0; i < 16; i++) { 2703 bus_space_write_4(t, h, 2704 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2705 hash[i]); 2706 } 2707 2708 chipit: 2709 sc->sc_if_flags = ifp->if_flags; 2710 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2711 } 2712