1 /* $NetBSD: gem.c,v 1.37 2005/02/27 00:27:01 perry Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.37 2005/02/27 00:27:01 perry Exp $"); 38 39 #include "opt_inet.h" 40 #include "bpfilter.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/syslog.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 54 #include <machine/endian.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #endif 75 76 #include <machine/bus.h> 77 #include <machine/intr.h> 78 79 #include <dev/mii/mii.h> 80 #include <dev/mii/miivar.h> 81 #include <dev/mii/mii_bitbang.h> 82 83 #include <dev/ic/gemreg.h> 84 #include <dev/ic/gemvar.h> 85 86 #define TRIES 10000 87 88 void gem_start(struct ifnet *); 89 void gem_stop(struct ifnet *, int); 90 int gem_ioctl(struct ifnet *, u_long, caddr_t); 91 void gem_tick(void *); 92 void gem_watchdog(struct ifnet *); 93 void gem_shutdown(void *); 94 int gem_init(struct ifnet *); 95 void gem_init_regs(struct gem_softc *sc); 96 static int gem_ringsize(int sz); 97 int gem_meminit(struct gem_softc *); 98 void gem_mifinit(struct gem_softc *); 99 void gem_reset(struct gem_softc *); 100 int gem_reset_rx(struct gem_softc *sc); 101 int gem_reset_tx(struct gem_softc *sc); 102 int gem_disable_rx(struct gem_softc *sc); 103 int gem_disable_tx(struct gem_softc *sc); 104 void gem_rxdrain(struct gem_softc *sc); 105 int gem_add_rxbuf(struct gem_softc *sc, int idx); 106 void gem_setladrf(struct gem_softc *); 107 108 /* MII methods & callbacks */ 109 static int gem_mii_readreg(struct device *, int, int); 110 static void gem_mii_writereg(struct device *, int, int, int); 111 static void gem_mii_statchg(struct device *); 112 113 int gem_mediachange(struct ifnet *); 114 void gem_mediastatus(struct ifnet *, struct ifmediareq *); 115 116 struct mbuf *gem_get(struct gem_softc *, int, int); 117 int gem_put(struct gem_softc *, int, struct mbuf *); 118 void gem_read(struct gem_softc *, int, int); 119 int gem_eint(struct gem_softc *, u_int); 120 int gem_rint(struct gem_softc *); 121 int gem_tint(struct gem_softc *); 122 void gem_power(int, void *); 123 124 #ifdef GEM_DEBUG 125 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 126 printf x 127 #else 128 #define DPRINTF(sc, x) /* nothing */ 129 #endif 130 131 132 /* 133 * gem_attach: 134 * 135 * Attach a Gem interface to the system. 136 */ 137 void 138 gem_attach(sc, enaddr) 139 struct gem_softc *sc; 140 const uint8_t *enaddr; 141 { 142 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 143 struct mii_data *mii = &sc->sc_mii; 144 struct mii_softc *child; 145 struct ifmedia_entry *ifm; 146 int i, error; 147 u_int32_t v; 148 149 /* Make sure the chip is stopped. */ 150 ifp->if_softc = sc; 151 gem_reset(sc); 152 153 /* 154 * Allocate the control data structures, and create and load the 155 * DMA map for it. 156 */ 157 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 158 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 159 1, &sc->sc_cdnseg, 0)) != 0) { 160 aprint_error( 161 "%s: unable to allocate control data, error = %d\n", 162 sc->sc_dev.dv_xname, error); 163 goto fail_0; 164 } 165 166 /* XXX should map this in with correct endianness */ 167 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 168 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 169 BUS_DMA_COHERENT)) != 0) { 170 aprint_error("%s: unable to map control data, error = %d\n", 171 sc->sc_dev.dv_xname, error); 172 goto fail_1; 173 } 174 175 if ((error = bus_dmamap_create(sc->sc_dmatag, 176 sizeof(struct gem_control_data), 1, 177 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 178 aprint_error("%s: unable to create control data DMA map, " 179 "error = %d\n", sc->sc_dev.dv_xname, error); 180 goto fail_2; 181 } 182 183 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 184 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 185 0)) != 0) { 186 aprint_error( 187 "%s: unable to load control data DMA map, error = %d\n", 188 sc->sc_dev.dv_xname, error); 189 goto fail_3; 190 } 191 192 /* 193 * Initialize the transmit job descriptors. 194 */ 195 SIMPLEQ_INIT(&sc->sc_txfreeq); 196 SIMPLEQ_INIT(&sc->sc_txdirtyq); 197 198 /* 199 * Create the transmit buffer DMA maps. 200 */ 201 for (i = 0; i < GEM_TXQUEUELEN; i++) { 202 struct gem_txsoft *txs; 203 204 txs = &sc->sc_txsoft[i]; 205 txs->txs_mbuf = NULL; 206 if ((error = bus_dmamap_create(sc->sc_dmatag, 207 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 208 ETHER_MAX_LEN_JUMBO, 0, 0, 209 &txs->txs_dmamap)) != 0) { 210 aprint_error("%s: unable to create tx DMA map %d, " 211 "error = %d\n", sc->sc_dev.dv_xname, i, error); 212 goto fail_4; 213 } 214 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 215 } 216 217 /* 218 * Create the receive buffer DMA maps. 219 */ 220 for (i = 0; i < GEM_NRXDESC; i++) { 221 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 222 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 223 aprint_error("%s: unable to create rx DMA map %d, " 224 "error = %d\n", sc->sc_dev.dv_xname, i, error); 225 goto fail_5; 226 } 227 sc->sc_rxsoft[i].rxs_mbuf = NULL; 228 } 229 230 /* 231 * From this point forward, the attachment cannot fail. A failure 232 * before this point releases all resources that may have been 233 * allocated. 234 */ 235 236 /* Announce ourselves. */ 237 aprint_normal("%s: Ethernet address %s", sc->sc_dev.dv_xname, 238 ether_sprintf(enaddr)); 239 240 /* Get RX FIFO size */ 241 sc->sc_rxfifosize = 64 * 242 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 243 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 244 245 /* Get TX FIFO size */ 246 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 247 aprint_normal(", %uKB TX fifo\n", v / 16); 248 249 /* Initialize ifnet structure. */ 250 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 251 ifp->if_softc = sc; 252 ifp->if_flags = 253 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 254 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx 255 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 256 ifp->if_start = gem_start; 257 ifp->if_ioctl = gem_ioctl; 258 ifp->if_watchdog = gem_watchdog; 259 ifp->if_stop = gem_stop; 260 ifp->if_init = gem_init; 261 IFQ_SET_READY(&ifp->if_snd); 262 263 /* Initialize ifmedia structures and MII info */ 264 mii->mii_ifp = ifp; 265 mii->mii_readreg = gem_mii_readreg; 266 mii->mii_writereg = gem_mii_writereg; 267 mii->mii_statchg = gem_mii_statchg; 268 269 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_mediachange, gem_mediastatus); 270 271 gem_mifinit(sc); 272 273 mii_attach(&sc->sc_dev, mii, 0xffffffff, 274 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 275 276 child = LIST_FIRST(&mii->mii_phys); 277 if (child == NULL) { 278 /* No PHY attached */ 279 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 280 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 281 } else { 282 /* 283 * Walk along the list of attached MII devices and 284 * establish an `MII instance' to `phy number' 285 * mapping. We'll use this mapping in media change 286 * requests to determine which phy to use to program 287 * the MIF configuration register. 288 */ 289 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 290 /* 291 * Note: we support just two PHYs: the built-in 292 * internal device and an external on the MII 293 * connector. 294 */ 295 if (child->mii_phy > 1 || child->mii_inst > 1) { 296 aprint_error( 297 "%s: cannot accomodate MII device %s" 298 " at phy %d, instance %d\n", 299 sc->sc_dev.dv_xname, 300 child->mii_dev.dv_xname, 301 child->mii_phy, child->mii_inst); 302 continue; 303 } 304 305 sc->sc_phys[child->mii_inst] = child->mii_phy; 306 } 307 308 /* 309 * Now select and activate the PHY we will use. 310 * 311 * The order of preference is External (MDI1), 312 * Internal (MDI0), Serial Link (no MII). 313 */ 314 if (sc->sc_phys[1]) { 315 #ifdef DEBUG 316 aprint_debug("using external phy\n"); 317 #endif 318 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 319 } else { 320 #ifdef DEBUG 321 aprint_debug("using internal phy\n"); 322 #endif 323 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 324 } 325 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 326 sc->sc_mif_config); 327 328 /* 329 * XXX - we can really do the following ONLY if the 330 * phy indeed has the auto negotiation capability!! 331 */ 332 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 333 } 334 335 /* 336 * If we support GigE media, we support jumbo frames too. 337 * Unless we are Apple. 338 */ 339 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 340 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 341 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 342 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 343 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 344 if (sc->sc_variant != GEM_APPLE_GMAC) 345 sc->sc_ethercom.ec_capabilities 346 |= ETHERCAP_JUMBO_MTU; 347 348 sc->sc_flags |= GEM_GIGABIT; 349 break; 350 } 351 } 352 353 /* claim 802.1q capability */ 354 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 355 356 /* Attach the interface. */ 357 if_attach(ifp); 358 ether_ifattach(ifp, enaddr); 359 360 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 361 if (sc->sc_sh == NULL) 362 panic("gem_config: can't establish shutdownhook"); 363 364 #if NRND > 0 365 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 366 RND_TYPE_NET, 0); 367 #endif 368 369 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 370 NULL, sc->sc_dev.dv_xname, "interrupts"); 371 #ifdef GEM_COUNTERS 372 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 373 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "tx interrupts"); 374 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 375 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "rx interrupts"); 376 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 377 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx ring full"); 378 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 379 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx malloc failure"); 380 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 381 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 0desc"); 382 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 383 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 1desc"); 384 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 385 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 2desc"); 386 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 387 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 3desc"); 388 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 389 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >3desc"); 390 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 391 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >7desc"); 392 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 393 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >15desc"); 394 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 395 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >31desc"); 396 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 397 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >63desc"); 398 #endif 399 400 #if notyet 401 /* 402 * Add a suspend hook to make sure we come back up after a 403 * resume. 404 */ 405 sc->sc_powerhook = powerhook_establish(gem_power, sc); 406 if (sc->sc_powerhook == NULL) 407 aprint_error("%s: WARNING: unable to establish power hook\n", 408 sc->sc_dev.dv_xname); 409 #endif 410 411 callout_init(&sc->sc_tick_ch); 412 return; 413 414 /* 415 * Free any resources we've allocated during the failed attach 416 * attempt. Do this in reverse order and fall through. 417 */ 418 fail_5: 419 for (i = 0; i < GEM_NRXDESC; i++) { 420 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 421 bus_dmamap_destroy(sc->sc_dmatag, 422 sc->sc_rxsoft[i].rxs_dmamap); 423 } 424 fail_4: 425 for (i = 0; i < GEM_TXQUEUELEN; i++) { 426 if (sc->sc_txsoft[i].txs_dmamap != NULL) 427 bus_dmamap_destroy(sc->sc_dmatag, 428 sc->sc_txsoft[i].txs_dmamap); 429 } 430 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 431 fail_3: 432 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 433 fail_2: 434 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 435 sizeof(struct gem_control_data)); 436 fail_1: 437 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 438 fail_0: 439 return; 440 } 441 442 443 void 444 gem_tick(arg) 445 void *arg; 446 { 447 struct gem_softc *sc = arg; 448 int s; 449 450 s = splnet(); 451 mii_tick(&sc->sc_mii); 452 splx(s); 453 454 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 455 456 } 457 458 void 459 gem_reset(sc) 460 struct gem_softc *sc; 461 { 462 bus_space_tag_t t = sc->sc_bustag; 463 bus_space_handle_t h = sc->sc_h; 464 int i; 465 int s; 466 467 s = splnet(); 468 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 469 gem_reset_rx(sc); 470 gem_reset_tx(sc); 471 472 /* Do a full reset */ 473 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 474 for (i=TRIES; i--; delay(100)) 475 if ((bus_space_read_4(t, h, GEM_RESET) & 476 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 477 break; 478 if ((bus_space_read_4(t, h, GEM_RESET) & 479 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 480 printf("%s: cannot reset device\n", 481 sc->sc_dev.dv_xname); 482 } 483 splx(s); 484 } 485 486 487 /* 488 * gem_rxdrain: 489 * 490 * Drain the receive queue. 491 */ 492 void 493 gem_rxdrain(struct gem_softc *sc) 494 { 495 struct gem_rxsoft *rxs; 496 int i; 497 498 for (i = 0; i < GEM_NRXDESC; i++) { 499 rxs = &sc->sc_rxsoft[i]; 500 if (rxs->rxs_mbuf != NULL) { 501 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 502 m_freem(rxs->rxs_mbuf); 503 rxs->rxs_mbuf = NULL; 504 } 505 } 506 } 507 508 /* 509 * Reset the whole thing. 510 */ 511 void 512 gem_stop(struct ifnet *ifp, int disable) 513 { 514 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 515 struct gem_txsoft *txs; 516 517 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 518 519 callout_stop(&sc->sc_tick_ch); 520 mii_down(&sc->sc_mii); 521 522 /* XXX - Should we reset these instead? */ 523 gem_disable_rx(sc); 524 gem_disable_tx(sc); 525 526 /* 527 * Release any queued transmit buffers. 528 */ 529 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 530 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 531 if (txs->txs_mbuf != NULL) { 532 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 533 m_freem(txs->txs_mbuf); 534 txs->txs_mbuf = NULL; 535 } 536 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 537 } 538 539 if (disable) { 540 gem_rxdrain(sc); 541 } 542 543 /* 544 * Mark the interface down and cancel the watchdog timer. 545 */ 546 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 547 ifp->if_timer = 0; 548 } 549 550 551 /* 552 * Reset the receiver 553 */ 554 int 555 gem_reset_rx(struct gem_softc *sc) 556 { 557 bus_space_tag_t t = sc->sc_bustag; 558 bus_space_handle_t h = sc->sc_h; 559 int i; 560 561 562 /* 563 * Resetting while DMA is in progress can cause a bus hang, so we 564 * disable DMA first. 565 */ 566 gem_disable_rx(sc); 567 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 568 /* Wait till it finishes */ 569 for (i=TRIES; i--; delay(100)) 570 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 571 break; 572 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 573 printf("%s: cannot disable read DMA\n", 574 sc->sc_dev.dv_xname); 575 576 /* Wait 5ms extra. */ 577 delay(5000); 578 579 /* Finally, reset the ERX */ 580 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 581 /* Wait till it finishes */ 582 for (i=TRIES; i--; delay(100)) 583 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 584 break; 585 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 586 printf("%s: cannot reset receiver\n", 587 sc->sc_dev.dv_xname); 588 return (1); 589 } 590 return (0); 591 } 592 593 594 /* 595 * Reset the transmitter 596 */ 597 int 598 gem_reset_tx(struct gem_softc *sc) 599 { 600 bus_space_tag_t t = sc->sc_bustag; 601 bus_space_handle_t h = sc->sc_h; 602 int i; 603 604 /* 605 * Resetting while DMA is in progress can cause a bus hang, so we 606 * disable DMA first. 607 */ 608 gem_disable_tx(sc); 609 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 610 /* Wait till it finishes */ 611 for (i=TRIES; i--; delay(100)) 612 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 613 break; 614 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 615 printf("%s: cannot disable read DMA\n", 616 sc->sc_dev.dv_xname); 617 618 /* Wait 5ms extra. */ 619 delay(5000); 620 621 /* Finally, reset the ETX */ 622 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 623 /* Wait till it finishes */ 624 for (i=TRIES; i--; delay(100)) 625 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 626 break; 627 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 628 printf("%s: cannot reset receiver\n", 629 sc->sc_dev.dv_xname); 630 return (1); 631 } 632 return (0); 633 } 634 635 /* 636 * disable receiver. 637 */ 638 int 639 gem_disable_rx(struct gem_softc *sc) 640 { 641 bus_space_tag_t t = sc->sc_bustag; 642 bus_space_handle_t h = sc->sc_h; 643 int i; 644 u_int32_t cfg; 645 646 /* Flip the enable bit */ 647 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 648 cfg &= ~GEM_MAC_RX_ENABLE; 649 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 650 651 /* Wait for it to finish */ 652 for (i=TRIES; i--; delay(100)) 653 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 654 GEM_MAC_RX_ENABLE) == 0) 655 return (0); 656 return (1); 657 } 658 659 /* 660 * disable transmitter. 661 */ 662 int 663 gem_disable_tx(struct gem_softc *sc) 664 { 665 bus_space_tag_t t = sc->sc_bustag; 666 bus_space_handle_t h = sc->sc_h; 667 int i; 668 u_int32_t cfg; 669 670 /* Flip the enable bit */ 671 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 672 cfg &= ~GEM_MAC_TX_ENABLE; 673 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 674 675 /* Wait for it to finish */ 676 for (i=TRIES; i--; delay(100)) 677 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 678 GEM_MAC_TX_ENABLE) == 0) 679 return (0); 680 return (1); 681 } 682 683 /* 684 * Initialize interface. 685 */ 686 int 687 gem_meminit(struct gem_softc *sc) 688 { 689 struct gem_rxsoft *rxs; 690 int i, error; 691 692 /* 693 * Initialize the transmit descriptor ring. 694 */ 695 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 696 for (i = 0; i < GEM_NTXDESC; i++) { 697 sc->sc_txdescs[i].gd_flags = 0; 698 sc->sc_txdescs[i].gd_addr = 0; 699 } 700 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 701 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 702 sc->sc_txfree = GEM_NTXDESC-1; 703 sc->sc_txnext = 0; 704 sc->sc_txwin = 0; 705 706 /* 707 * Initialize the receive descriptor and receive job 708 * descriptor rings. 709 */ 710 for (i = 0; i < GEM_NRXDESC; i++) { 711 rxs = &sc->sc_rxsoft[i]; 712 if (rxs->rxs_mbuf == NULL) { 713 if ((error = gem_add_rxbuf(sc, i)) != 0) { 714 printf("%s: unable to allocate or map rx " 715 "buffer %d, error = %d\n", 716 sc->sc_dev.dv_xname, i, error); 717 /* 718 * XXX Should attempt to run with fewer receive 719 * XXX buffers instead of just failing. 720 */ 721 gem_rxdrain(sc); 722 return (1); 723 } 724 } else 725 GEM_INIT_RXDESC(sc, i); 726 } 727 sc->sc_rxptr = 0; 728 729 return (0); 730 } 731 732 static int 733 gem_ringsize(int sz) 734 { 735 switch (sz) { 736 case 32: 737 return GEM_RING_SZ_32; 738 case 64: 739 return GEM_RING_SZ_64; 740 case 128: 741 return GEM_RING_SZ_128; 742 case 256: 743 return GEM_RING_SZ_256; 744 case 512: 745 return GEM_RING_SZ_512; 746 case 1024: 747 return GEM_RING_SZ_1024; 748 case 2048: 749 return GEM_RING_SZ_2048; 750 case 4096: 751 return GEM_RING_SZ_4096; 752 case 8192: 753 return GEM_RING_SZ_8192; 754 default: 755 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 756 return GEM_RING_SZ_32; 757 } 758 } 759 760 /* 761 * Initialization of interface; set up initialization block 762 * and transmit/receive descriptor rings. 763 */ 764 int 765 gem_init(struct ifnet *ifp) 766 { 767 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 768 bus_space_tag_t t = sc->sc_bustag; 769 bus_space_handle_t h = sc->sc_h; 770 int s; 771 u_int max_frame_size; 772 u_int32_t v; 773 774 s = splnet(); 775 776 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 777 /* 778 * Initialization sequence. The numbered steps below correspond 779 * to the sequence outlined in section 6.3.5.1 in the Ethernet 780 * Channel Engine manual (part of the PCIO manual). 781 * See also the STP2002-STQ document from Sun Microsystems. 782 */ 783 784 /* step 1 & 2. Reset the Ethernet Channel */ 785 gem_stop(ifp, 0); 786 gem_reset(sc); 787 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 788 789 /* Re-initialize the MIF */ 790 gem_mifinit(sc); 791 792 /* Call MI reset function if any */ 793 if (sc->sc_hwreset) 794 (*sc->sc_hwreset)(sc); 795 796 /* step 3. Setup data structures in host memory */ 797 gem_meminit(sc); 798 799 /* step 4. TX MAC registers & counters */ 800 gem_init_regs(sc); 801 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 802 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 803 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 804 max_frame_size += ETHER_VLAN_ENCAP_LEN; 805 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 806 max_frame_size|/* burst size */(0x2000<<16)); 807 808 /* step 5. RX MAC registers & counters */ 809 gem_setladrf(sc); 810 811 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 812 /* NOTE: we use only 32-bit DMA addresses here. */ 813 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 814 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 815 816 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 817 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 818 819 /* step 8. Global Configuration & Interrupt Mask */ 820 bus_space_write_4(t, h, GEM_INTMASK, 821 ~(GEM_INTR_TX_INTME| 822 GEM_INTR_TX_EMPTY| 823 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 824 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 825 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 826 GEM_INTR_BERR)); 827 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 828 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 829 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 830 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 831 832 /* step 9. ETX Configuration: use mostly default values */ 833 834 /* Enable DMA */ 835 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 836 bus_space_write_4(t, h, GEM_TX_CONFIG, 837 v|GEM_TX_CONFIG_TXDMA_EN| 838 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 839 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 840 841 /* step 10. ERX Configuration */ 842 843 /* Encode Receive Descriptor ring size: four possible values */ 844 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 845 846 /* Set receive h/w checksum offset */ 847 #ifdef INET 848 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 849 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 850 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 851 #endif 852 853 /* Enable DMA */ 854 bus_space_write_4(t, h, GEM_RX_CONFIG, 855 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 856 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN); 857 858 /* 859 * The following value is for an OFF Threshold of about 3/4 full 860 * and an ON Threshold of 1/4 full. 861 */ 862 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 863 (3 * sc->sc_rxfifosize / 256) | 864 ( (sc->sc_rxfifosize / 256) << 12)); 865 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 866 867 /* step 11. Configure Media */ 868 mii_mediachg(&sc->sc_mii); 869 870 /* XXXX Serial link needs a whole different setup. */ 871 872 873 /* step 12. RX_MAC Configuration Register */ 874 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 875 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 876 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 877 878 /* step 14. Issue Transmit Pending command */ 879 880 /* Call MI initialization function if any */ 881 if (sc->sc_hwinit) 882 (*sc->sc_hwinit)(sc); 883 884 885 /* step 15. Give the reciever a swift kick */ 886 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 887 888 /* Start the one second timer. */ 889 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 890 891 ifp->if_flags |= IFF_RUNNING; 892 ifp->if_flags &= ~IFF_OACTIVE; 893 ifp->if_timer = 0; 894 splx(s); 895 896 return (0); 897 } 898 899 void 900 gem_init_regs(struct gem_softc *sc) 901 { 902 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 903 bus_space_tag_t t = sc->sc_bustag; 904 bus_space_handle_t h = sc->sc_h; 905 const u_char *laddr = LLADDR(ifp->if_sadl); 906 u_int32_t v; 907 908 /* These regs are not cleared on reset */ 909 if (!sc->sc_inited) { 910 911 /* Wooo. Magic values. */ 912 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 913 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 914 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 915 916 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 917 /* Max frame and max burst size */ 918 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 919 ETHER_MAX_LEN | (0x2000<<16)); 920 921 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 922 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 923 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 924 /* Dunno.... */ 925 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 926 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 927 ((laddr[5]<<8)|laddr[4])&0x3ff); 928 929 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 930 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 931 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 932 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 933 934 /* MAC control addr set to 01:80:c2:00:00:01 */ 935 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 936 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 937 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 938 939 /* MAC filter addr set to 0:0:0:0:0:0 */ 940 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 941 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 942 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 943 944 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 945 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 946 947 sc->sc_inited = 1; 948 } 949 950 /* Counters need to be zeroed */ 951 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 952 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 953 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 954 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 955 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 956 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 957 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 958 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 959 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 960 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 961 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 962 963 /* Un-pause stuff */ 964 #if 0 965 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 966 #else 967 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 968 #endif 969 970 /* 971 * Set the station address. 972 */ 973 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 974 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 975 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 976 977 #if 0 978 if (sc->sc_variant != APPLE_GMAC) 979 return; 980 #endif 981 982 /* 983 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 984 */ 985 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 986 v = GEM_MAC_XIF_TX_MII_ENA; 987 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 988 v |= GEM_MAC_XIF_FDPLX_LED; 989 if (sc->sc_flags & GEM_GIGABIT) 990 v |= GEM_MAC_XIF_GMII_MODE; 991 } 992 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 993 } 994 995 void 996 gem_start(ifp) 997 struct ifnet *ifp; 998 { 999 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1000 struct mbuf *m0, *m; 1001 struct gem_txsoft *txs, *last_txs; 1002 bus_dmamap_t dmamap; 1003 int error, firsttx, nexttx, lasttx = -1, ofree, seg; 1004 1005 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1006 return; 1007 1008 /* 1009 * Remember the previous number of free descriptors and 1010 * the first descriptor we'll use. 1011 */ 1012 ofree = sc->sc_txfree; 1013 firsttx = sc->sc_txnext; 1014 1015 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1016 sc->sc_dev.dv_xname, ofree, firsttx)); 1017 1018 /* 1019 * Loop through the send queue, setting up transmit descriptors 1020 * until we drain the queue, or use up all available transmit 1021 * descriptors. 1022 */ 1023 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1024 sc->sc_txfree != 0) { 1025 /* 1026 * Grab a packet off the queue. 1027 */ 1028 IFQ_POLL(&ifp->if_snd, m0); 1029 if (m0 == NULL) 1030 break; 1031 m = NULL; 1032 1033 dmamap = txs->txs_dmamap; 1034 1035 /* 1036 * Load the DMA map. If this fails, the packet either 1037 * didn't fit in the alloted number of segments, or we were 1038 * short on resources. In this case, we'll copy and try 1039 * again. 1040 */ 1041 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1042 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1043 if (m0->m_pkthdr.len > MCLBYTES) { 1044 printf("%s: unable to allocate jumbo Tx " 1045 "cluster\n", sc->sc_dev.dv_xname); 1046 IFQ_DEQUEUE(&ifp->if_snd, m0); 1047 m_freem(m0); 1048 continue; 1049 } 1050 MGETHDR(m, M_DONTWAIT, MT_DATA); 1051 if (m == NULL) { 1052 printf("%s: unable to allocate Tx mbuf\n", 1053 sc->sc_dev.dv_xname); 1054 break; 1055 } 1056 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1057 if (m0->m_pkthdr.len > MHLEN) { 1058 MCLGET(m, M_DONTWAIT); 1059 if ((m->m_flags & M_EXT) == 0) { 1060 printf("%s: unable to allocate Tx " 1061 "cluster\n", sc->sc_dev.dv_xname); 1062 m_freem(m); 1063 break; 1064 } 1065 } 1066 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1067 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1068 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1069 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1070 if (error) { 1071 printf("%s: unable to load Tx buffer, " 1072 "error = %d\n", sc->sc_dev.dv_xname, error); 1073 break; 1074 } 1075 } 1076 1077 /* 1078 * Ensure we have enough descriptors free to describe 1079 * the packet. 1080 */ 1081 if (dmamap->dm_nsegs > sc->sc_txfree) { 1082 /* 1083 * Not enough free descriptors to transmit this 1084 * packet. We haven't committed to anything yet, 1085 * so just unload the DMA map, put the packet 1086 * back on the queue, and punt. Notify the upper 1087 * layer that there are no more slots left. 1088 * 1089 * XXX We could allocate an mbuf and copy, but 1090 * XXX it is worth it? 1091 */ 1092 ifp->if_flags |= IFF_OACTIVE; 1093 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1094 if (m != NULL) 1095 m_freem(m); 1096 break; 1097 } 1098 1099 IFQ_DEQUEUE(&ifp->if_snd, m0); 1100 if (m != NULL) { 1101 m_freem(m0); 1102 m0 = m; 1103 } 1104 1105 /* 1106 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1107 */ 1108 1109 /* Sync the DMA map. */ 1110 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1111 BUS_DMASYNC_PREWRITE); 1112 1113 /* 1114 * Initialize the transmit descriptors. 1115 */ 1116 for (nexttx = sc->sc_txnext, seg = 0; 1117 seg < dmamap->dm_nsegs; 1118 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1119 uint64_t flags; 1120 1121 /* 1122 * If this is the first descriptor we're 1123 * enqueueing, set the start of packet flag, 1124 * and the checksum stuff if we want the hardware 1125 * to do it. 1126 */ 1127 sc->sc_txdescs[nexttx].gd_addr = 1128 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1129 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1130 if (nexttx == firsttx) { 1131 flags |= GEM_TD_START_OF_PACKET; 1132 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1133 sc->sc_txwin = 0; 1134 flags |= GEM_TD_INTERRUPT_ME; 1135 } 1136 1137 #ifdef INET 1138 /* h/w checksum */ 1139 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | 1140 M_CSUM_UDPv4) && m0->m_pkthdr.csum_flags & 1141 (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1142 struct ether_header *eh; 1143 uint16_t offset, start; 1144 1145 eh = mtod(m0, struct ether_header *); 1146 switch (ntohs(eh->ether_type)) { 1147 case ETHERTYPE_IP: 1148 start = ETHER_HDR_LEN; 1149 break; 1150 case ETHERTYPE_VLAN: 1151 start = ETHER_HDR_LEN + 1152 ETHER_VLAN_ENCAP_LEN; 1153 break; 1154 default: 1155 /* unsupported, drop it */ 1156 m_free(m0); 1157 continue; 1158 } 1159 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1160 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1161 flags |= (start << 1162 GEM_TD_CXSUM_STARTSHFT) | 1163 (offset << 1164 GEM_TD_CXSUM_STUFFSHFT) | 1165 GEM_TD_CXSUM_ENABLE; 1166 } 1167 #endif 1168 } 1169 if (seg == dmamap->dm_nsegs - 1) { 1170 flags |= GEM_TD_END_OF_PACKET; 1171 } 1172 sc->sc_txdescs[nexttx].gd_flags = 1173 GEM_DMA_WRITE(sc, flags); 1174 lasttx = nexttx; 1175 } 1176 1177 KASSERT(lasttx != -1); 1178 1179 #ifdef GEM_DEBUG 1180 if (ifp->if_flags & IFF_DEBUG) { 1181 printf(" gem_start %p transmit chain:\n", txs); 1182 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1183 printf("descriptor %d:\t", seg); 1184 printf("gd_flags: 0x%016llx\t", (long long) 1185 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1186 printf("gd_addr: 0x%016llx\n", (long long) 1187 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1188 if (seg == lasttx) 1189 break; 1190 } 1191 } 1192 #endif 1193 1194 /* Sync the descriptors we're using. */ 1195 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1196 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1197 1198 /* 1199 * Store a pointer to the packet so we can free it later, 1200 * and remember what txdirty will be once the packet is 1201 * done. 1202 */ 1203 txs->txs_mbuf = m0; 1204 txs->txs_firstdesc = sc->sc_txnext; 1205 txs->txs_lastdesc = lasttx; 1206 txs->txs_ndescs = dmamap->dm_nsegs; 1207 1208 /* Advance the tx pointer. */ 1209 sc->sc_txfree -= dmamap->dm_nsegs; 1210 sc->sc_txnext = nexttx; 1211 1212 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1213 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1214 1215 last_txs = txs; 1216 1217 #if NBPFILTER > 0 1218 /* 1219 * Pass the packet to any BPF listeners. 1220 */ 1221 if (ifp->if_bpf) 1222 bpf_mtap(ifp->if_bpf, m0); 1223 #endif /* NBPFILTER > 0 */ 1224 } 1225 1226 if (txs == NULL || sc->sc_txfree == 0) { 1227 /* No more slots left; notify upper layer. */ 1228 ifp->if_flags |= IFF_OACTIVE; 1229 } 1230 1231 if (sc->sc_txfree != ofree) { 1232 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1233 sc->sc_dev.dv_xname, lasttx, firsttx)); 1234 /* 1235 * The entire packet chain is set up. 1236 * Kick the transmitter. 1237 */ 1238 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1239 sc->sc_dev.dv_xname, nexttx)); 1240 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1241 sc->sc_txnext); 1242 1243 /* Set a watchdog timer in case the chip flakes out. */ 1244 ifp->if_timer = 5; 1245 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1246 sc->sc_dev.dv_xname, ifp->if_timer)); 1247 } 1248 } 1249 1250 /* 1251 * Transmit interrupt. 1252 */ 1253 int 1254 gem_tint(sc) 1255 struct gem_softc *sc; 1256 { 1257 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1258 bus_space_tag_t t = sc->sc_bustag; 1259 bus_space_handle_t mac = sc->sc_h; 1260 struct gem_txsoft *txs; 1261 int txlast; 1262 int progress = 0; 1263 1264 1265 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1266 1267 /* 1268 * Unload collision counters 1269 */ 1270 ifp->if_collisions += 1271 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1272 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1273 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1274 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1275 1276 /* 1277 * then clear the hardware counters. 1278 */ 1279 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1280 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1281 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1282 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1283 1284 /* 1285 * Go through our Tx list and free mbufs for those 1286 * frames that have been transmitted. 1287 */ 1288 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1289 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1290 txs->txs_ndescs, 1291 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1292 1293 #ifdef GEM_DEBUG 1294 if (ifp->if_flags & IFF_DEBUG) { 1295 int i; 1296 printf(" txsoft %p transmit chain:\n", txs); 1297 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1298 printf("descriptor %d: ", i); 1299 printf("gd_flags: 0x%016llx\t", (long long) 1300 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1301 printf("gd_addr: 0x%016llx\n", (long long) 1302 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1303 if (i == txs->txs_lastdesc) 1304 break; 1305 } 1306 } 1307 #endif 1308 1309 /* 1310 * In theory, we could harveast some descriptors before 1311 * the ring is empty, but that's a bit complicated. 1312 * 1313 * GEM_TX_COMPLETION points to the last descriptor 1314 * processed +1. 1315 */ 1316 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1317 DPRINTF(sc, 1318 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1319 txs->txs_lastdesc, txlast)); 1320 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1321 if ((txlast >= txs->txs_firstdesc) && 1322 (txlast <= txs->txs_lastdesc)) 1323 break; 1324 } else { 1325 /* Ick -- this command wraps */ 1326 if ((txlast >= txs->txs_firstdesc) || 1327 (txlast <= txs->txs_lastdesc)) 1328 break; 1329 } 1330 1331 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1332 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1333 1334 sc->sc_txfree += txs->txs_ndescs; 1335 1336 if (txs->txs_mbuf == NULL) { 1337 #ifdef DIAGNOSTIC 1338 panic("gem_txintr: null mbuf"); 1339 #endif 1340 } 1341 1342 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1343 0, txs->txs_dmamap->dm_mapsize, 1344 BUS_DMASYNC_POSTWRITE); 1345 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1346 m_freem(txs->txs_mbuf); 1347 txs->txs_mbuf = NULL; 1348 1349 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1350 1351 ifp->if_opackets++; 1352 progress = 1; 1353 } 1354 1355 #if 0 1356 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1357 "GEM_TX_DATA_PTR %llx " 1358 "GEM_TX_COMPLETION %x\n", 1359 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1360 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1361 GEM_TX_DATA_PTR_HI) << 32) | 1362 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1363 GEM_TX_DATA_PTR_LO), 1364 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1365 #endif 1366 1367 if (progress) { 1368 if (sc->sc_txfree == GEM_NTXDESC - 1) 1369 sc->sc_txwin = 0; 1370 1371 ifp->if_flags &= ~IFF_OACTIVE; 1372 gem_start(ifp); 1373 1374 if (SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) 1375 ifp->if_timer = 0; 1376 } 1377 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1378 sc->sc_dev.dv_xname, ifp->if_timer)); 1379 1380 return (1); 1381 } 1382 1383 /* 1384 * Receive interrupt. 1385 */ 1386 int 1387 gem_rint(sc) 1388 struct gem_softc *sc; 1389 { 1390 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1391 bus_space_tag_t t = sc->sc_bustag; 1392 bus_space_handle_t h = sc->sc_h; 1393 struct gem_rxsoft *rxs; 1394 struct mbuf *m; 1395 u_int64_t rxstat; 1396 u_int32_t rxcomp; 1397 int i, len, progress = 0; 1398 1399 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1400 1401 /* 1402 * Read the completion register once. This limits 1403 * how long the following loop can execute. 1404 */ 1405 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1406 1407 /* 1408 * XXXX Read the lastrx only once at the top for speed. 1409 */ 1410 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1411 sc->sc_rxptr, rxcomp)); 1412 1413 /* 1414 * Go into the loop at least once. 1415 */ 1416 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1417 i = GEM_NEXTRX(i)) { 1418 rxs = &sc->sc_rxsoft[i]; 1419 1420 GEM_CDRXSYNC(sc, i, 1421 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1422 1423 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1424 1425 if (rxstat & GEM_RD_OWN) { 1426 /* 1427 * We have processed all of the receive buffers. 1428 */ 1429 break; 1430 } 1431 1432 progress++; 1433 ifp->if_ipackets++; 1434 1435 if (rxstat & GEM_RD_BAD_CRC) { 1436 ifp->if_ierrors++; 1437 printf("%s: receive error: CRC error\n", 1438 sc->sc_dev.dv_xname); 1439 GEM_INIT_RXDESC(sc, i); 1440 continue; 1441 } 1442 1443 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1444 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1445 #ifdef GEM_DEBUG 1446 if (ifp->if_flags & IFF_DEBUG) { 1447 printf(" rxsoft %p descriptor %d: ", rxs, i); 1448 printf("gd_flags: 0x%016llx\t", (long long) 1449 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1450 printf("gd_addr: 0x%016llx\n", (long long) 1451 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1452 } 1453 #endif 1454 1455 /* No errors; receive the packet. */ 1456 len = GEM_RD_BUFLEN(rxstat); 1457 1458 /* 1459 * Allocate a new mbuf cluster. If that fails, we are 1460 * out of memory, and must drop the packet and recycle 1461 * the buffer that's already attached to this descriptor. 1462 */ 1463 m = rxs->rxs_mbuf; 1464 if (gem_add_rxbuf(sc, i) != 0) { 1465 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1466 ifp->if_ierrors++; 1467 GEM_INIT_RXDESC(sc, i); 1468 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1469 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1470 continue; 1471 } 1472 m->m_data += 2; /* We're already off by two */ 1473 1474 m->m_pkthdr.rcvif = ifp; 1475 m->m_pkthdr.len = m->m_len = len; 1476 1477 #if NBPFILTER > 0 1478 /* 1479 * Pass this up to any BPF listeners, but only 1480 * pass it up the stack if its for us. 1481 */ 1482 if (ifp->if_bpf) 1483 bpf_mtap(ifp->if_bpf, m); 1484 #endif /* NPBFILTER > 0 */ 1485 1486 #ifdef INET 1487 /* hardware checksum */ 1488 if (ifp->if_csum_flags_rx & (M_CSUM_UDPv4 | M_CSUM_TCPv4)) { 1489 struct ether_header *eh; 1490 struct ip *ip; 1491 struct udphdr *uh; 1492 int32_t hlen, pktlen; 1493 1494 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1495 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1496 ETHER_VLAN_ENCAP_LEN; 1497 eh = (struct ether_header *) mtod(m, caddr_t) + 1498 ETHER_VLAN_ENCAP_LEN; 1499 } else { 1500 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1501 eh = mtod(m, struct ether_header *); 1502 } 1503 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1504 goto swcsum; 1505 ip = (struct ip *) ((caddr_t)eh + ETHER_HDR_LEN); 1506 1507 /* IPv4 only */ 1508 if (ip->ip_v != IPVERSION) 1509 goto swcsum; 1510 1511 hlen = ip->ip_hl << 2; 1512 if (hlen < sizeof(struct ip)) 1513 goto swcsum; 1514 1515 /* too short, truncated, fragment */ 1516 if ((ntohs(ip->ip_len) < hlen) || 1517 (ntohs(ip->ip_len) > pktlen) || 1518 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1519 goto swcsum; 1520 1521 switch (ip->ip_p) { 1522 case IPPROTO_TCP: 1523 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1524 goto swcsum; 1525 if (pktlen < (hlen + sizeof(struct tcphdr))) 1526 goto swcsum; 1527 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1528 break; 1529 case IPPROTO_UDP: 1530 if (! (ifp->if_csum_flags_rx & M_CSUM_UDPv4)) 1531 goto swcsum; 1532 if (pktlen < (hlen + sizeof(struct udphdr))) 1533 goto swcsum; 1534 uh = (struct udphdr *)((caddr_t)ip + hlen); 1535 /* no checksum */ 1536 if (uh->uh_sum == 0) 1537 goto swcsum; 1538 m->m_pkthdr.csum_flags = M_CSUM_UDPv4; 1539 break; 1540 default: 1541 goto swcsum; 1542 } 1543 1544 /* the uncomplemented sum is expected */ 1545 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1546 1547 /* if the pkt had ip options, we have to deduct them */ 1548 if (hlen > sizeof(struct ip)) { 1549 uint16_t *opts; 1550 uint32_t optsum, temp; 1551 1552 optsum = 0; 1553 temp = hlen - sizeof(struct ip); 1554 opts = (uint16_t *) ((caddr_t) ip + 1555 sizeof(struct ip)); 1556 1557 while (temp > 1) { 1558 optsum += ntohs(*opts++); 1559 temp -= 2; 1560 } 1561 while (optsum >> 16) 1562 optsum = (optsum >> 16) + 1563 (optsum & 0xffff); 1564 1565 /* Deduct ip opts sum from hwsum (rfc 1624). */ 1566 m->m_pkthdr.csum_data = 1567 ~((~m->m_pkthdr.csum_data) - ~optsum); 1568 1569 while (m->m_pkthdr.csum_data >> 16) 1570 m->m_pkthdr.csum_data = 1571 (m->m_pkthdr.csum_data >> 16) + 1572 (m->m_pkthdr.csum_data & 1573 0xffff); 1574 } 1575 1576 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1577 M_CSUM_NO_PSEUDOHDR; 1578 } else 1579 swcsum: 1580 m->m_pkthdr.csum_flags = 0; 1581 #endif 1582 /* Pass it on. */ 1583 (*ifp->if_input)(ifp, m); 1584 } 1585 1586 if (progress) { 1587 /* Update the receive pointer. */ 1588 if (i == sc->sc_rxptr) { 1589 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1590 #ifdef GEM_DEBUG 1591 if (ifp->if_flags & IFF_DEBUG) 1592 printf("%s: rint: ring wrap\n", 1593 sc->sc_dev.dv_xname); 1594 #endif 1595 } 1596 sc->sc_rxptr = i; 1597 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1598 } 1599 #ifdef GEM_COUNTERS 1600 if (progress <= 4) { 1601 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1602 } else if (progress < 32) { 1603 if (progress < 16) 1604 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1605 else 1606 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1607 1608 } else { 1609 if (progress < 64) 1610 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1611 else 1612 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1613 } 1614 #endif 1615 1616 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1617 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1618 1619 return (1); 1620 } 1621 1622 1623 /* 1624 * gem_add_rxbuf: 1625 * 1626 * Add a receive buffer to the indicated descriptor. 1627 */ 1628 int 1629 gem_add_rxbuf(struct gem_softc *sc, int idx) 1630 { 1631 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1632 struct mbuf *m; 1633 int error; 1634 1635 MGETHDR(m, M_DONTWAIT, MT_DATA); 1636 if (m == NULL) 1637 return (ENOBUFS); 1638 1639 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1640 MCLGET(m, M_DONTWAIT); 1641 if ((m->m_flags & M_EXT) == 0) { 1642 m_freem(m); 1643 return (ENOBUFS); 1644 } 1645 1646 #ifdef GEM_DEBUG 1647 /* bzero the packet to check DMA */ 1648 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1649 #endif 1650 1651 if (rxs->rxs_mbuf != NULL) 1652 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1653 1654 rxs->rxs_mbuf = m; 1655 1656 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1657 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1658 BUS_DMA_READ|BUS_DMA_NOWAIT); 1659 if (error) { 1660 printf("%s: can't load rx DMA map %d, error = %d\n", 1661 sc->sc_dev.dv_xname, idx, error); 1662 panic("gem_add_rxbuf"); /* XXX */ 1663 } 1664 1665 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1666 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1667 1668 GEM_INIT_RXDESC(sc, idx); 1669 1670 return (0); 1671 } 1672 1673 1674 int 1675 gem_eint(sc, status) 1676 struct gem_softc *sc; 1677 u_int status; 1678 { 1679 char bits[128]; 1680 1681 if ((status & GEM_INTR_MIF) != 0) { 1682 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1683 return (1); 1684 } 1685 1686 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1687 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1688 return (1); 1689 } 1690 1691 1692 int 1693 gem_intr(v) 1694 void *v; 1695 { 1696 struct gem_softc *sc = (struct gem_softc *)v; 1697 bus_space_tag_t t = sc->sc_bustag; 1698 bus_space_handle_t seb = sc->sc_h; 1699 u_int32_t status; 1700 int r = 0; 1701 #ifdef GEM_DEBUG 1702 char bits[128]; 1703 #endif 1704 1705 sc->sc_ev_intr.ev_count++; 1706 1707 status = bus_space_read_4(t, seb, GEM_STATUS); 1708 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 1709 sc->sc_dev.dv_xname, (status >> 19), 1710 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1711 1712 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1713 r |= gem_eint(sc, status); 1714 1715 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 1716 GEM_COUNTER_INCR(sc, sc_ev_txint); 1717 r |= gem_tint(sc); 1718 } 1719 1720 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 1721 GEM_COUNTER_INCR(sc, sc_ev_rxint); 1722 r |= gem_rint(sc); 1723 } 1724 1725 /* We should eventually do more than just print out error stats. */ 1726 if (status & GEM_INTR_TX_MAC) { 1727 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1728 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1729 printf("%s: MAC tx fault, status %x\n", 1730 sc->sc_dev.dv_xname, txstat); 1731 } 1732 if (status & GEM_INTR_RX_MAC) { 1733 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1734 if (rxstat & ~GEM_MAC_RX_DONE) 1735 printf("%s: MAC rx fault, status %x\n", 1736 sc->sc_dev.dv_xname, rxstat); 1737 } 1738 return (r); 1739 } 1740 1741 1742 void 1743 gem_watchdog(ifp) 1744 struct ifnet *ifp; 1745 { 1746 struct gem_softc *sc = ifp->if_softc; 1747 1748 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1749 "GEM_MAC_RX_CONFIG %x\n", 1750 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1751 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1752 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1753 1754 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1755 ++ifp->if_oerrors; 1756 1757 /* Try to get more packets going. */ 1758 gem_start(ifp); 1759 } 1760 1761 /* 1762 * Initialize the MII Management Interface 1763 */ 1764 void 1765 gem_mifinit(sc) 1766 struct gem_softc *sc; 1767 { 1768 bus_space_tag_t t = sc->sc_bustag; 1769 bus_space_handle_t mif = sc->sc_h; 1770 1771 /* Configure the MIF in frame mode */ 1772 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1773 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1774 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1775 } 1776 1777 /* 1778 * MII interface 1779 * 1780 * The GEM MII interface supports at least three different operating modes: 1781 * 1782 * Bitbang mode is implemented using data, clock and output enable registers. 1783 * 1784 * Frame mode is implemented by loading a complete frame into the frame 1785 * register and polling the valid bit for completion. 1786 * 1787 * Polling mode uses the frame register but completion is indicated by 1788 * an interrupt. 1789 * 1790 */ 1791 static int 1792 gem_mii_readreg(self, phy, reg) 1793 struct device *self; 1794 int phy, reg; 1795 { 1796 struct gem_softc *sc = (void *)self; 1797 bus_space_tag_t t = sc->sc_bustag; 1798 bus_space_handle_t mif = sc->sc_h; 1799 int n; 1800 u_int32_t v; 1801 1802 #ifdef GEM_DEBUG1 1803 if (sc->sc_debug) 1804 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1805 #endif 1806 1807 #if 0 1808 /* Select the desired PHY in the MIF configuration register */ 1809 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1810 /* Clear PHY select bit */ 1811 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1812 if (phy == GEM_PHYAD_EXTERNAL) 1813 /* Set PHY select bit to get at external device */ 1814 v |= GEM_MIF_CONFIG_PHY_SEL; 1815 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1816 #endif 1817 1818 /* Construct the frame command */ 1819 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1820 GEM_MIF_FRAME_READ; 1821 1822 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1823 for (n = 0; n < 100; n++) { 1824 DELAY(1); 1825 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1826 if (v & GEM_MIF_FRAME_TA0) 1827 return (v & GEM_MIF_FRAME_DATA); 1828 } 1829 1830 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1831 return (0); 1832 } 1833 1834 static void 1835 gem_mii_writereg(self, phy, reg, val) 1836 struct device *self; 1837 int phy, reg, val; 1838 { 1839 struct gem_softc *sc = (void *)self; 1840 bus_space_tag_t t = sc->sc_bustag; 1841 bus_space_handle_t mif = sc->sc_h; 1842 int n; 1843 u_int32_t v; 1844 1845 #ifdef GEM_DEBUG1 1846 if (sc->sc_debug) 1847 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1848 phy, reg, val); 1849 #endif 1850 1851 #if 0 1852 /* Select the desired PHY in the MIF configuration register */ 1853 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1854 /* Clear PHY select bit */ 1855 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1856 if (phy == GEM_PHYAD_EXTERNAL) 1857 /* Set PHY select bit to get at external device */ 1858 v |= GEM_MIF_CONFIG_PHY_SEL; 1859 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1860 #endif 1861 /* Construct the frame command */ 1862 v = GEM_MIF_FRAME_WRITE | 1863 (phy << GEM_MIF_PHY_SHIFT) | 1864 (reg << GEM_MIF_REG_SHIFT) | 1865 (val & GEM_MIF_FRAME_DATA); 1866 1867 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1868 for (n = 0; n < 100; n++) { 1869 DELAY(1); 1870 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1871 if (v & GEM_MIF_FRAME_TA0) 1872 return; 1873 } 1874 1875 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1876 } 1877 1878 static void 1879 gem_mii_statchg(dev) 1880 struct device *dev; 1881 { 1882 struct gem_softc *sc = (void *)dev; 1883 #ifdef GEM_DEBUG 1884 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1885 #endif 1886 bus_space_tag_t t = sc->sc_bustag; 1887 bus_space_handle_t mac = sc->sc_h; 1888 u_int32_t v; 1889 1890 #ifdef GEM_DEBUG 1891 if (sc->sc_debug) 1892 printf("gem_mii_statchg: status change: phy = %d\n", 1893 sc->sc_phys[instance]); 1894 #endif 1895 1896 1897 /* Set tx full duplex options */ 1898 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1899 delay(10000); /* reg must be cleared and delay before changing. */ 1900 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1901 GEM_MAC_TX_ENABLE; 1902 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1903 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1904 } 1905 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1906 1907 /* XIF Configuration */ 1908 /* We should really calculate all this rather than rely on defaults */ 1909 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1910 v = GEM_MAC_XIF_LINK_LED; 1911 v |= GEM_MAC_XIF_TX_MII_ENA; 1912 1913 /* If an external transceiver is connected, enable its MII drivers */ 1914 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1915 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1916 /* External MII needs echo disable if half duplex. */ 1917 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1918 /* turn on full duplex LED */ 1919 v |= GEM_MAC_XIF_FDPLX_LED; 1920 else 1921 /* half duplex -- disable echo */ 1922 v |= GEM_MAC_XIF_ECHO_DISABL; 1923 1924 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 1925 v |= GEM_MAC_XIF_GMII_MODE; 1926 else 1927 v &= ~GEM_MAC_XIF_GMII_MODE; 1928 } else 1929 /* Internal MII needs buf enable */ 1930 v |= GEM_MAC_XIF_MII_BUF_ENA; 1931 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1932 } 1933 1934 int 1935 gem_mediachange(ifp) 1936 struct ifnet *ifp; 1937 { 1938 struct gem_softc *sc = ifp->if_softc; 1939 1940 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1941 return (EINVAL); 1942 1943 return (mii_mediachg(&sc->sc_mii)); 1944 } 1945 1946 void 1947 gem_mediastatus(ifp, ifmr) 1948 struct ifnet *ifp; 1949 struct ifmediareq *ifmr; 1950 { 1951 struct gem_softc *sc = ifp->if_softc; 1952 1953 if ((ifp->if_flags & IFF_UP) == 0) 1954 return; 1955 1956 mii_pollstat(&sc->sc_mii); 1957 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1958 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1959 } 1960 1961 int gem_ioctldebug = 0; 1962 /* 1963 * Process an ioctl request. 1964 */ 1965 int 1966 gem_ioctl(ifp, cmd, data) 1967 struct ifnet *ifp; 1968 u_long cmd; 1969 caddr_t data; 1970 { 1971 struct gem_softc *sc = ifp->if_softc; 1972 struct ifreq *ifr = (struct ifreq *)data; 1973 int s, error = 0; 1974 1975 s = splnet(); 1976 1977 switch (cmd) { 1978 case SIOCGIFMEDIA: 1979 case SIOCSIFMEDIA: 1980 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1981 break; 1982 1983 default: 1984 error = ether_ioctl(ifp, cmd, data); 1985 if (error == ENETRESET) { 1986 /* 1987 * Multicast list has changed; set the hardware filter 1988 * accordingly. 1989 */ 1990 if (ifp->if_flags & IFF_RUNNING) { 1991 if (gem_ioctldebug) printf("reset1\n"); 1992 gem_init(ifp); 1993 delay(50000); 1994 } 1995 error = 0; 1996 } 1997 break; 1998 } 1999 2000 /* Try to get things going again */ 2001 if (ifp->if_flags & IFF_UP) { 2002 if (gem_ioctldebug) printf("start\n"); 2003 gem_start(ifp); 2004 } 2005 splx(s); 2006 return (error); 2007 } 2008 2009 2010 void 2011 gem_shutdown(arg) 2012 void *arg; 2013 { 2014 struct gem_softc *sc = (struct gem_softc *)arg; 2015 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2016 2017 gem_stop(ifp, 1); 2018 } 2019 2020 /* 2021 * Set up the logical address filter. 2022 */ 2023 void 2024 gem_setladrf(sc) 2025 struct gem_softc *sc; 2026 { 2027 struct ethercom *ec = &sc->sc_ethercom; 2028 struct ifnet *ifp = &ec->ec_if; 2029 struct ether_multi *enm; 2030 struct ether_multistep step; 2031 bus_space_tag_t t = sc->sc_bustag; 2032 bus_space_handle_t h = sc->sc_h; 2033 u_int32_t crc; 2034 u_int32_t hash[16]; 2035 u_int32_t v; 2036 int i; 2037 2038 /* Get current RX configuration */ 2039 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2040 2041 /* 2042 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2043 * and hash filter. Depending on the case, the right bit will be 2044 * enabled. 2045 */ 2046 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2047 GEM_MAC_RX_PROMISC_GRP); 2048 2049 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2050 /* Turn on promiscuous mode */ 2051 v |= GEM_MAC_RX_PROMISCUOUS; 2052 ifp->if_flags |= IFF_ALLMULTI; 2053 goto chipit; 2054 } 2055 2056 /* 2057 * Set up multicast address filter by passing all multicast addresses 2058 * through a crc generator, and then using the high order 8 bits as an 2059 * index into the 256 bit logical address filter. The high order 4 2060 * bits select the word, while the other 4 bits select the bit within 2061 * the word (where bit 0 is the MSB). 2062 */ 2063 2064 /* Clear hash table */ 2065 memset(hash, 0, sizeof(hash)); 2066 2067 ETHER_FIRST_MULTI(step, ec, enm); 2068 while (enm != NULL) { 2069 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2070 /* 2071 * We must listen to a range of multicast addresses. 2072 * For now, just accept all multicasts, rather than 2073 * trying to set only those filter bits needed to match 2074 * the range. (At this time, the only use of address 2075 * ranges is for IP multicast routing, for which the 2076 * range is big enough to require all bits set.) 2077 * XXX use the addr filter for this 2078 */ 2079 ifp->if_flags |= IFF_ALLMULTI; 2080 v |= GEM_MAC_RX_PROMISC_GRP; 2081 goto chipit; 2082 } 2083 2084 /* Get the LE CRC32 of the address */ 2085 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2086 2087 /* Just want the 8 most significant bits. */ 2088 crc >>= 24; 2089 2090 /* Set the corresponding bit in the filter. */ 2091 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2092 2093 ETHER_NEXT_MULTI(step, enm); 2094 } 2095 2096 v |= GEM_MAC_RX_HASH_FILTER; 2097 ifp->if_flags &= ~IFF_ALLMULTI; 2098 2099 /* Now load the hash table into the chip (if we are using it) */ 2100 for (i = 0; i < 16; i++) { 2101 bus_space_write_4(t, h, 2102 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2103 hash[i]); 2104 } 2105 2106 chipit: 2107 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2108 } 2109 2110 #if notyet 2111 2112 /* 2113 * gem_power: 2114 * 2115 * Power management (suspend/resume) hook. 2116 */ 2117 void 2118 gem_power(why, arg) 2119 int why; 2120 void *arg; 2121 { 2122 struct gem_softc *sc = arg; 2123 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2124 int s; 2125 2126 s = splnet(); 2127 switch (why) { 2128 case PWR_SUSPEND: 2129 case PWR_STANDBY: 2130 gem_stop(ifp, 1); 2131 if (sc->sc_power != NULL) 2132 (*sc->sc_power)(sc, why); 2133 break; 2134 case PWR_RESUME: 2135 if (ifp->if_flags & IFF_UP) { 2136 if (sc->sc_power != NULL) 2137 (*sc->sc_power)(sc, why); 2138 gem_init(ifp); 2139 } 2140 break; 2141 case PWR_SOFTSUSPEND: 2142 case PWR_SOFTSTANDBY: 2143 case PWR_SOFTRESUME: 2144 break; 2145 } 2146 splx(s); 2147 } 2148 #endif 2149