1 /* $NetBSD: gem.c,v 1.60 2007/10/19 11:59:51 ad Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.60 2007/10/19 11:59:51 ad Exp $"); 38 39 #include "opt_inet.h" 40 #include "bpfilter.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/syslog.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 54 #include <machine/endian.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #endif 75 76 #include <sys/bus.h> 77 #include <sys/intr.h> 78 79 #include <dev/mii/mii.h> 80 #include <dev/mii/miivar.h> 81 #include <dev/mii/mii_bitbang.h> 82 83 #include <dev/ic/gemreg.h> 84 #include <dev/ic/gemvar.h> 85 86 #define TRIES 10000 87 88 static void gem_start(struct ifnet *); 89 static void gem_stop(struct ifnet *, int); 90 int gem_ioctl(struct ifnet *, u_long, void *); 91 void gem_tick(void *); 92 void gem_watchdog(struct ifnet *); 93 void gem_shutdown(void *); 94 int gem_init(struct ifnet *); 95 void gem_init_regs(struct gem_softc *sc); 96 static int gem_ringsize(int sz); 97 static int gem_meminit(struct gem_softc *); 98 void gem_mifinit(struct gem_softc *); 99 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 100 u_int32_t, u_int32_t); 101 void gem_reset(struct gem_softc *); 102 int gem_reset_rx(struct gem_softc *sc); 103 int gem_reset_tx(struct gem_softc *sc); 104 int gem_disable_rx(struct gem_softc *sc); 105 int gem_disable_tx(struct gem_softc *sc); 106 static void gem_rxdrain(struct gem_softc *sc); 107 int gem_add_rxbuf(struct gem_softc *sc, int idx); 108 void gem_setladrf(struct gem_softc *); 109 110 /* MII methods & callbacks */ 111 static int gem_mii_readreg(struct device *, int, int); 112 static void gem_mii_writereg(struct device *, int, int, int); 113 static void gem_mii_statchg(struct device *); 114 115 int gem_mediachange(struct ifnet *); 116 void gem_mediastatus(struct ifnet *, struct ifmediareq *); 117 118 struct mbuf *gem_get(struct gem_softc *, int, int); 119 int gem_put(struct gem_softc *, int, struct mbuf *); 120 void gem_read(struct gem_softc *, int, int); 121 int gem_eint(struct gem_softc *, u_int); 122 int gem_rint(struct gem_softc *); 123 int gem_tint(struct gem_softc *); 124 void gem_power(int, void *); 125 126 #ifdef GEM_DEBUG 127 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 128 printf x 129 #else 130 #define DPRINTF(sc, x) /* nothing */ 131 #endif 132 133 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 134 135 136 /* 137 * gem_attach: 138 * 139 * Attach a Gem interface to the system. 140 */ 141 void 142 gem_attach(sc, enaddr) 143 struct gem_softc *sc; 144 const uint8_t *enaddr; 145 { 146 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 147 struct mii_data *mii = &sc->sc_mii; 148 struct mii_softc *child; 149 struct ifmedia_entry *ifm; 150 int i, error; 151 u_int32_t v; 152 char *nullbuf; 153 154 /* Make sure the chip is stopped. */ 155 ifp->if_softc = sc; 156 gem_reset(sc); 157 158 /* 159 * Allocate the control data structures, and create and load the 160 * DMA map for it. gem_control_data is 9216 bytes, we have space for 161 * the padding buffer in the bus_dmamem_alloc()'d memory. 162 */ 163 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 164 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 165 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 166 aprint_error( 167 "%s: unable to allocate control data, error = %d\n", 168 sc->sc_dev.dv_xname, error); 169 goto fail_0; 170 } 171 172 /* XXX should map this in with correct endianness */ 173 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 174 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 175 BUS_DMA_COHERENT)) != 0) { 176 aprint_error("%s: unable to map control data, error = %d\n", 177 sc->sc_dev.dv_xname, error); 178 goto fail_1; 179 } 180 181 nullbuf = 182 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 183 184 if ((error = bus_dmamap_create(sc->sc_dmatag, 185 sizeof(struct gem_control_data), 1, 186 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 187 aprint_error("%s: unable to create control data DMA map, " 188 "error = %d\n", sc->sc_dev.dv_xname, error); 189 goto fail_2; 190 } 191 192 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 193 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 194 0)) != 0) { 195 aprint_error( 196 "%s: unable to load control data DMA map, error = %d\n", 197 sc->sc_dev.dv_xname, error); 198 goto fail_3; 199 } 200 201 memset(nullbuf, 0, ETHER_MIN_TX); 202 if ((error = bus_dmamap_create(sc->sc_dmatag, 203 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 204 aprint_error("%s: unable to create padding DMA map, " 205 "error = %d\n", sc->sc_dev.dv_xname, error); 206 goto fail_4; 207 } 208 209 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 210 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 211 aprint_error( 212 "%s: unable to load padding DMA map, error = %d\n", 213 sc->sc_dev.dv_xname, error); 214 goto fail_5; 215 } 216 217 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 218 BUS_DMASYNC_PREWRITE); 219 220 /* 221 * Initialize the transmit job descriptors. 222 */ 223 SIMPLEQ_INIT(&sc->sc_txfreeq); 224 SIMPLEQ_INIT(&sc->sc_txdirtyq); 225 226 /* 227 * Create the transmit buffer DMA maps. 228 */ 229 for (i = 0; i < GEM_TXQUEUELEN; i++) { 230 struct gem_txsoft *txs; 231 232 txs = &sc->sc_txsoft[i]; 233 txs->txs_mbuf = NULL; 234 if ((error = bus_dmamap_create(sc->sc_dmatag, 235 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 236 ETHER_MAX_LEN_JUMBO, 0, 0, 237 &txs->txs_dmamap)) != 0) { 238 aprint_error("%s: unable to create tx DMA map %d, " 239 "error = %d\n", sc->sc_dev.dv_xname, i, error); 240 goto fail_6; 241 } 242 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 243 } 244 245 /* 246 * Create the receive buffer DMA maps. 247 */ 248 for (i = 0; i < GEM_NRXDESC; i++) { 249 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 250 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 251 aprint_error("%s: unable to create rx DMA map %d, " 252 "error = %d\n", sc->sc_dev.dv_xname, i, error); 253 goto fail_7; 254 } 255 sc->sc_rxsoft[i].rxs_mbuf = NULL; 256 } 257 258 /* 259 * From this point forward, the attachment cannot fail. A failure 260 * before this point releases all resources that may have been 261 * allocated. 262 */ 263 264 /* Announce ourselves. */ 265 aprint_normal("%s: Ethernet address %s", sc->sc_dev.dv_xname, 266 ether_sprintf(enaddr)); 267 268 /* Get RX FIFO size */ 269 sc->sc_rxfifosize = 64 * 270 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_FIFO_SIZE); 271 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 272 273 /* Get TX FIFO size */ 274 v = bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_FIFO_SIZE); 275 aprint_normal(", %uKB TX fifo\n", v / 16); 276 277 /* Initialize ifnet structure. */ 278 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 279 ifp->if_softc = sc; 280 ifp->if_flags = 281 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 282 sc->sc_if_flags = ifp->if_flags; 283 ifp->if_capabilities |= 284 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 285 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 286 ifp->if_start = gem_start; 287 ifp->if_ioctl = gem_ioctl; 288 ifp->if_watchdog = gem_watchdog; 289 ifp->if_stop = gem_stop; 290 ifp->if_init = gem_init; 291 IFQ_SET_READY(&ifp->if_snd); 292 293 /* Initialize ifmedia structures and MII info */ 294 mii->mii_ifp = ifp; 295 mii->mii_readreg = gem_mii_readreg; 296 mii->mii_writereg = gem_mii_writereg; 297 mii->mii_statchg = gem_mii_statchg; 298 299 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_mediachange, gem_mediastatus); 300 301 gem_mifinit(sc); 302 303 #if defined (PMAC_G5) 304 mii_attach(&sc->sc_dev, mii, 0xffffffff, 305 1, MII_OFFSET_ANY, MIIF_FORCEANEG); 306 #else 307 mii_attach(&sc->sc_dev, mii, 0xffffffff, 308 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 309 #endif 310 311 child = LIST_FIRST(&mii->mii_phys); 312 if (child == NULL) { 313 /* No PHY attached */ 314 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 315 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 316 } else { 317 /* 318 * Walk along the list of attached MII devices and 319 * establish an `MII instance' to `phy number' 320 * mapping. We'll use this mapping in media change 321 * requests to determine which phy to use to program 322 * the MIF configuration register. 323 */ 324 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 325 /* 326 * Note: we support just two PHYs: the built-in 327 * internal device and an external on the MII 328 * connector. 329 */ 330 if (child->mii_phy > 1 || child->mii_inst > 1) { 331 aprint_error( 332 "%s: cannot accommodate MII device %s" 333 " at phy %d, instance %d\n", 334 sc->sc_dev.dv_xname, 335 child->mii_dev.dv_xname, 336 child->mii_phy, child->mii_inst); 337 continue; 338 } 339 340 sc->sc_phys[child->mii_inst] = child->mii_phy; 341 } 342 343 /* 344 * Now select and activate the PHY we will use. 345 * 346 * The order of preference is External (MDI1), 347 * Internal (MDI0), Serial Link (no MII). 348 */ 349 if (sc->sc_phys[1]) { 350 #ifdef GEM_DEBUG 351 aprint_debug("using external phy\n"); 352 #endif 353 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 354 } else { 355 #ifdef GEM_DEBUG 356 aprint_debug("using internal phy\n"); 357 #endif 358 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 359 } 360 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_MIF_CONFIG, 361 sc->sc_mif_config); 362 363 /* 364 * XXX - we can really do the following ONLY if the 365 * phy indeed has the auto negotiation capability!! 366 */ 367 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 368 } 369 370 /* 371 * If we support GigE media, we support jumbo frames too. 372 * Unless we are Apple. 373 */ 374 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 375 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 376 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 377 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 378 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 379 if (sc->sc_variant != GEM_APPLE_GMAC) 380 sc->sc_ethercom.ec_capabilities 381 |= ETHERCAP_JUMBO_MTU; 382 383 sc->sc_flags |= GEM_GIGABIT; 384 break; 385 } 386 } 387 388 /* claim 802.1q capability */ 389 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 390 391 /* Attach the interface. */ 392 if_attach(ifp); 393 ether_ifattach(ifp, enaddr); 394 395 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 396 if (sc->sc_sh == NULL) 397 panic("gem_config: can't establish shutdownhook"); 398 399 #if NRND > 0 400 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 401 RND_TYPE_NET, 0); 402 #endif 403 404 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 405 NULL, sc->sc_dev.dv_xname, "interrupts"); 406 #ifdef GEM_COUNTERS 407 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 408 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "tx interrupts"); 409 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 410 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "rx interrupts"); 411 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 412 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx ring full"); 413 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 414 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx malloc failure"); 415 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 416 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 0desc"); 417 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 418 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 1desc"); 419 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 420 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 2desc"); 421 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 422 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 3desc"); 423 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 424 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >3desc"); 425 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 426 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >7desc"); 427 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 428 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >15desc"); 429 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 430 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >31desc"); 431 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 432 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >63desc"); 433 #endif 434 435 #if notyet 436 /* 437 * Add a suspend hook to make sure we come back up after a 438 * resume. 439 */ 440 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 441 gem_power, sc); 442 if (sc->sc_powerhook == NULL) 443 aprint_error("%s: WARNING: unable to establish power hook\n", 444 sc->sc_dev.dv_xname); 445 #endif 446 447 callout_init(&sc->sc_tick_ch, 0); 448 return; 449 450 /* 451 * Free any resources we've allocated during the failed attach 452 * attempt. Do this in reverse order and fall through. 453 */ 454 fail_7: 455 for (i = 0; i < GEM_NRXDESC; i++) { 456 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 457 bus_dmamap_destroy(sc->sc_dmatag, 458 sc->sc_rxsoft[i].rxs_dmamap); 459 } 460 fail_6: 461 for (i = 0; i < GEM_TXQUEUELEN; i++) { 462 if (sc->sc_txsoft[i].txs_dmamap != NULL) 463 bus_dmamap_destroy(sc->sc_dmatag, 464 sc->sc_txsoft[i].txs_dmamap); 465 } 466 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 467 fail_5: 468 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 469 fail_4: 470 bus_dmamem_unmap(sc->sc_dmatag, (void *)nullbuf, ETHER_MIN_TX); 471 fail_3: 472 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 473 fail_2: 474 bus_dmamem_unmap(sc->sc_dmatag, (void *)sc->sc_control_data, 475 sizeof(struct gem_control_data)); 476 fail_1: 477 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 478 fail_0: 479 return; 480 } 481 482 483 void 484 gem_tick(arg) 485 void *arg; 486 { 487 struct gem_softc *sc = arg; 488 int s; 489 490 s = splnet(); 491 mii_tick(&sc->sc_mii); 492 splx(s); 493 494 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 495 496 } 497 498 static int 499 gem_bitwait(sc, h, r, clr, set) 500 struct gem_softc *sc; 501 bus_space_handle_t h; 502 int r; 503 u_int32_t clr; 504 u_int32_t set; 505 { 506 int i; 507 u_int32_t reg; 508 509 for (i = TRIES; i--; DELAY(100)) { 510 reg = bus_space_read_4(sc->sc_bustag, h, r); 511 if ((reg & clr) == 0 && (reg & set) == set) 512 return (1); 513 } 514 return (0); 515 } 516 517 void 518 gem_reset(sc) 519 struct gem_softc *sc; 520 { 521 bus_space_tag_t t = sc->sc_bustag; 522 bus_space_handle_t h = sc->sc_h2; 523 int s; 524 525 s = splnet(); 526 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 527 gem_reset_rx(sc); 528 gem_reset_tx(sc); 529 530 /* Do a full reset */ 531 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 532 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 533 printf("%s: cannot reset device\n", sc->sc_dev.dv_xname); 534 splx(s); 535 } 536 537 538 /* 539 * gem_rxdrain: 540 * 541 * Drain the receive queue. 542 */ 543 static void 544 gem_rxdrain(struct gem_softc *sc) 545 { 546 struct gem_rxsoft *rxs; 547 int i; 548 549 for (i = 0; i < GEM_NRXDESC; i++) { 550 rxs = &sc->sc_rxsoft[i]; 551 if (rxs->rxs_mbuf != NULL) { 552 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 553 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 554 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 555 m_freem(rxs->rxs_mbuf); 556 rxs->rxs_mbuf = NULL; 557 } 558 } 559 } 560 561 /* 562 * Reset the whole thing. 563 */ 564 static void 565 gem_stop(struct ifnet *ifp, int disable) 566 { 567 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 568 struct gem_txsoft *txs; 569 570 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 571 572 callout_stop(&sc->sc_tick_ch); 573 mii_down(&sc->sc_mii); 574 575 /* XXX - Should we reset these instead? */ 576 gem_disable_rx(sc); 577 gem_disable_tx(sc); 578 579 /* 580 * Release any queued transmit buffers. 581 */ 582 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 583 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 584 if (txs->txs_mbuf != NULL) { 585 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 586 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 587 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 588 m_freem(txs->txs_mbuf); 589 txs->txs_mbuf = NULL; 590 } 591 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 592 } 593 594 if (disable) { 595 gem_rxdrain(sc); 596 } 597 598 /* 599 * Mark the interface down and cancel the watchdog timer. 600 */ 601 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 602 sc->sc_if_flags = ifp->if_flags; 603 ifp->if_timer = 0; 604 } 605 606 607 /* 608 * Reset the receiver 609 */ 610 int 611 gem_reset_rx(struct gem_softc *sc) 612 { 613 bus_space_tag_t t = sc->sc_bustag; 614 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 615 616 /* 617 * Resetting while DMA is in progress can cause a bus hang, so we 618 * disable DMA first. 619 */ 620 gem_disable_rx(sc); 621 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 622 /* Wait till it finishes */ 623 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 624 printf("%s: cannot disable read dma\n", sc->sc_dev.dv_xname); 625 /* Wait 5ms extra. */ 626 delay(5000); 627 628 /* Finally, reset the ERX */ 629 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 630 /* Wait till it finishes */ 631 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 632 printf("%s: cannot reset receiver\n", sc->sc_dev.dv_xname); 633 return (1); 634 } 635 return (0); 636 } 637 638 639 /* 640 * Reset the transmitter 641 */ 642 int 643 gem_reset_tx(struct gem_softc *sc) 644 { 645 bus_space_tag_t t = sc->sc_bustag; 646 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 647 648 /* 649 * Resetting while DMA is in progress can cause a bus hang, so we 650 * disable DMA first. 651 */ 652 gem_disable_tx(sc); 653 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 654 /* Wait till it finishes */ 655 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 656 printf("%s: cannot disable read dma\n", sc->sc_dev.dv_xname); 657 /* Wait 5ms extra. */ 658 delay(5000); 659 660 /* Finally, reset the ETX */ 661 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 662 /* Wait till it finishes */ 663 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 664 printf("%s: cannot reset receiver\n", 665 sc->sc_dev.dv_xname); 666 return (1); 667 } 668 return (0); 669 } 670 671 /* 672 * disable receiver. 673 */ 674 int 675 gem_disable_rx(struct gem_softc *sc) 676 { 677 bus_space_tag_t t = sc->sc_bustag; 678 bus_space_handle_t h = sc->sc_h1; 679 u_int32_t cfg; 680 681 /* Flip the enable bit */ 682 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 683 cfg &= ~GEM_MAC_RX_ENABLE; 684 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 685 686 /* Wait for it to finish */ 687 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 688 } 689 690 /* 691 * disable transmitter. 692 */ 693 int 694 gem_disable_tx(struct gem_softc *sc) 695 { 696 bus_space_tag_t t = sc->sc_bustag; 697 bus_space_handle_t h = sc->sc_h1; 698 u_int32_t cfg; 699 700 /* Flip the enable bit */ 701 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 702 cfg &= ~GEM_MAC_TX_ENABLE; 703 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 704 705 /* Wait for it to finish */ 706 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 707 } 708 709 /* 710 * Initialize interface. 711 */ 712 int 713 gem_meminit(struct gem_softc *sc) 714 { 715 struct gem_rxsoft *rxs; 716 int i, error; 717 718 /* 719 * Initialize the transmit descriptor ring. 720 */ 721 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 722 for (i = 0; i < GEM_NTXDESC; i++) { 723 sc->sc_txdescs[i].gd_flags = 0; 724 sc->sc_txdescs[i].gd_addr = 0; 725 } 726 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 727 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 728 sc->sc_txfree = GEM_NTXDESC-1; 729 sc->sc_txnext = 0; 730 sc->sc_txwin = 0; 731 732 /* 733 * Initialize the receive descriptor and receive job 734 * descriptor rings. 735 */ 736 for (i = 0; i < GEM_NRXDESC; i++) { 737 rxs = &sc->sc_rxsoft[i]; 738 if (rxs->rxs_mbuf == NULL) { 739 if ((error = gem_add_rxbuf(sc, i)) != 0) { 740 printf("%s: unable to allocate or map rx " 741 "buffer %d, error = %d\n", 742 sc->sc_dev.dv_xname, i, error); 743 /* 744 * XXX Should attempt to run with fewer receive 745 * XXX buffers instead of just failing. 746 */ 747 gem_rxdrain(sc); 748 return (1); 749 } 750 } else 751 GEM_INIT_RXDESC(sc, i); 752 } 753 sc->sc_rxptr = 0; 754 755 return (0); 756 } 757 758 static int 759 gem_ringsize(int sz) 760 { 761 switch (sz) { 762 case 32: 763 return GEM_RING_SZ_32; 764 case 64: 765 return GEM_RING_SZ_64; 766 case 128: 767 return GEM_RING_SZ_128; 768 case 256: 769 return GEM_RING_SZ_256; 770 case 512: 771 return GEM_RING_SZ_512; 772 case 1024: 773 return GEM_RING_SZ_1024; 774 case 2048: 775 return GEM_RING_SZ_2048; 776 case 4096: 777 return GEM_RING_SZ_4096; 778 case 8192: 779 return GEM_RING_SZ_8192; 780 default: 781 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 782 return GEM_RING_SZ_32; 783 } 784 } 785 786 /* 787 * Initialization of interface; set up initialization block 788 * and transmit/receive descriptor rings. 789 */ 790 int 791 gem_init(struct ifnet *ifp) 792 { 793 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 794 bus_space_tag_t t = sc->sc_bustag; 795 bus_space_handle_t h = sc->sc_h1; 796 int s; 797 u_int max_frame_size; 798 u_int32_t v; 799 800 s = splnet(); 801 802 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 803 /* 804 * Initialization sequence. The numbered steps below correspond 805 * to the sequence outlined in section 6.3.5.1 in the Ethernet 806 * Channel Engine manual (part of the PCIO manual). 807 * See also the STP2002-STQ document from Sun Microsystems. 808 */ 809 810 /* step 1 & 2. Reset the Ethernet Channel */ 811 gem_stop(ifp, 0); 812 gem_reset(sc); 813 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 814 815 /* Re-initialize the MIF */ 816 gem_mifinit(sc); 817 818 /* Call MI reset function if any */ 819 if (sc->sc_hwreset) 820 (*sc->sc_hwreset)(sc); 821 822 /* step 3. Setup data structures in host memory */ 823 gem_meminit(sc); 824 825 /* step 4. TX MAC registers & counters */ 826 gem_init_regs(sc); 827 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 828 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 829 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 830 max_frame_size += ETHER_VLAN_ENCAP_LEN; 831 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 832 max_frame_size|/* burst size */(0x2000<<16)); 833 834 /* step 5. RX MAC registers & counters */ 835 gem_setladrf(sc); 836 837 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 838 /* NOTE: we use only 32-bit DMA addresses here. */ 839 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 840 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 841 842 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 843 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 844 845 /* step 8. Global Configuration & Interrupt Mask */ 846 bus_space_write_4(t, h, GEM_INTMASK, 847 ~(GEM_INTR_TX_INTME| 848 GEM_INTR_TX_EMPTY| 849 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 850 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 851 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 852 GEM_INTR_BERR)); 853 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 854 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 855 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 856 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 857 858 /* step 9. ETX Configuration: use mostly default values */ 859 860 /* Enable DMA */ 861 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 862 bus_space_write_4(t, h, GEM_TX_CONFIG, 863 v|GEM_TX_CONFIG_TXDMA_EN| 864 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 865 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 866 867 /* step 10. ERX Configuration */ 868 869 /* Encode Receive Descriptor ring size: four possible values */ 870 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 871 872 /* Set receive h/w checksum offset */ 873 #ifdef INET 874 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 875 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 876 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 877 #endif 878 879 /* Enable DMA */ 880 bus_space_write_4(t, h, GEM_RX_CONFIG, 881 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 882 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN); 883 884 /* 885 * The following value is for an OFF Threshold of about 3/4 full 886 * and an ON Threshold of 1/4 full. 887 */ 888 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 889 (3 * sc->sc_rxfifosize / 256) | 890 ( (sc->sc_rxfifosize / 256) << 12)); 891 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 892 893 /* step 11. Configure Media */ 894 mii_mediachg(&sc->sc_mii); 895 896 /* XXXX Serial link needs a whole different setup. */ 897 898 899 /* step 12. RX_MAC Configuration Register */ 900 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 901 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 902 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 903 904 /* step 14. Issue Transmit Pending command */ 905 906 /* Call MI initialization function if any */ 907 if (sc->sc_hwinit) 908 (*sc->sc_hwinit)(sc); 909 910 911 /* step 15. Give the reciever a swift kick */ 912 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 913 914 /* Start the one second timer. */ 915 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 916 917 ifp->if_flags |= IFF_RUNNING; 918 ifp->if_flags &= ~IFF_OACTIVE; 919 ifp->if_timer = 0; 920 sc->sc_if_flags = ifp->if_flags; 921 splx(s); 922 923 return (0); 924 } 925 926 void 927 gem_init_regs(struct gem_softc *sc) 928 { 929 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 930 bus_space_tag_t t = sc->sc_bustag; 931 bus_space_handle_t h = sc->sc_h1; 932 const u_char *laddr = CLLADDR(ifp->if_sadl); 933 u_int32_t v; 934 935 /* These regs are not cleared on reset */ 936 if (!sc->sc_inited) { 937 938 /* Wooo. Magic values. */ 939 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 940 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 941 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 942 943 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 944 /* Max frame and max burst size */ 945 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 946 ETHER_MAX_LEN | (0x2000<<16)); 947 948 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 949 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 950 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 951 /* Dunno.... */ 952 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 953 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 954 ((laddr[5]<<8)|laddr[4])&0x3ff); 955 956 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 957 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 958 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 959 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 960 961 /* MAC control addr set to 01:80:c2:00:00:01 */ 962 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 963 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 964 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 965 966 /* MAC filter addr set to 0:0:0:0:0:0 */ 967 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 968 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 969 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 970 971 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 972 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 973 974 sc->sc_inited = 1; 975 } 976 977 /* Counters need to be zeroed */ 978 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 979 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 980 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 981 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 982 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 983 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 984 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 985 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 986 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 987 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 988 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 989 990 /* Un-pause stuff */ 991 #if 0 992 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 993 #else 994 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 995 #endif 996 997 /* 998 * Set the station address. 999 */ 1000 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1001 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1002 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1003 1004 #if 0 1005 if (sc->sc_variant != APPLE_GMAC) 1006 return; 1007 #endif 1008 1009 /* 1010 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1011 */ 1012 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1013 v = GEM_MAC_XIF_TX_MII_ENA; 1014 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1015 v |= GEM_MAC_XIF_FDPLX_LED; 1016 if (sc->sc_flags & GEM_GIGABIT) 1017 v |= GEM_MAC_XIF_GMII_MODE; 1018 } 1019 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1020 } 1021 1022 static void 1023 gem_start(ifp) 1024 struct ifnet *ifp; 1025 { 1026 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1027 struct mbuf *m0, *m; 1028 struct gem_txsoft *txs, *last_txs; 1029 bus_dmamap_t dmamap; 1030 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1031 uint64_t flags = 0; 1032 1033 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1034 return; 1035 1036 /* 1037 * Remember the previous number of free descriptors and 1038 * the first descriptor we'll use. 1039 */ 1040 ofree = sc->sc_txfree; 1041 firsttx = sc->sc_txnext; 1042 1043 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1044 sc->sc_dev.dv_xname, ofree, firsttx)); 1045 1046 /* 1047 * Loop through the send queue, setting up transmit descriptors 1048 * until we drain the queue, or use up all available transmit 1049 * descriptors. 1050 */ 1051 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1052 sc->sc_txfree != 0) { 1053 /* 1054 * Grab a packet off the queue. 1055 */ 1056 IFQ_POLL(&ifp->if_snd, m0); 1057 if (m0 == NULL) 1058 break; 1059 m = NULL; 1060 1061 dmamap = txs->txs_dmamap; 1062 1063 /* 1064 * Load the DMA map. If this fails, the packet either 1065 * didn't fit in the alloted number of segments, or we were 1066 * short on resources. In this case, we'll copy and try 1067 * again. 1068 */ 1069 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1070 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1071 (m0->m_pkthdr.len < ETHER_MIN_TX && 1072 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1073 if (m0->m_pkthdr.len > MCLBYTES) { 1074 printf("%s: unable to allocate jumbo Tx " 1075 "cluster\n", sc->sc_dev.dv_xname); 1076 IFQ_DEQUEUE(&ifp->if_snd, m0); 1077 m_freem(m0); 1078 continue; 1079 } 1080 MGETHDR(m, M_DONTWAIT, MT_DATA); 1081 if (m == NULL) { 1082 printf("%s: unable to allocate Tx mbuf\n", 1083 sc->sc_dev.dv_xname); 1084 break; 1085 } 1086 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1087 if (m0->m_pkthdr.len > MHLEN) { 1088 MCLGET(m, M_DONTWAIT); 1089 if ((m->m_flags & M_EXT) == 0) { 1090 printf("%s: unable to allocate Tx " 1091 "cluster\n", sc->sc_dev.dv_xname); 1092 m_freem(m); 1093 break; 1094 } 1095 } 1096 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1097 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1098 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1099 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1100 if (error) { 1101 printf("%s: unable to load Tx buffer, " 1102 "error = %d\n", sc->sc_dev.dv_xname, error); 1103 break; 1104 } 1105 } 1106 1107 /* 1108 * Ensure we have enough descriptors free to describe 1109 * the packet. 1110 */ 1111 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1112 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1113 /* 1114 * Not enough free descriptors to transmit this 1115 * packet. We haven't committed to anything yet, 1116 * so just unload the DMA map, put the packet 1117 * back on the queue, and punt. Notify the upper 1118 * layer that there are no more slots left. 1119 * 1120 * XXX We could allocate an mbuf and copy, but 1121 * XXX it is worth it? 1122 */ 1123 ifp->if_flags |= IFF_OACTIVE; 1124 sc->sc_if_flags = ifp->if_flags; 1125 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1126 if (m != NULL) 1127 m_freem(m); 1128 break; 1129 } 1130 1131 IFQ_DEQUEUE(&ifp->if_snd, m0); 1132 if (m != NULL) { 1133 m_freem(m0); 1134 m0 = m; 1135 } 1136 1137 /* 1138 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1139 */ 1140 1141 /* Sync the DMA map. */ 1142 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1143 BUS_DMASYNC_PREWRITE); 1144 1145 /* 1146 * Initialize the transmit descriptors. 1147 */ 1148 for (nexttx = sc->sc_txnext, seg = 0; 1149 seg < dmamap->dm_nsegs; 1150 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1151 1152 /* 1153 * If this is the first descriptor we're 1154 * enqueueing, set the start of packet flag, 1155 * and the checksum stuff if we want the hardware 1156 * to do it. 1157 */ 1158 sc->sc_txdescs[nexttx].gd_addr = 1159 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1160 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1161 if (nexttx == firsttx) { 1162 flags |= GEM_TD_START_OF_PACKET; 1163 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1164 sc->sc_txwin = 0; 1165 flags |= GEM_TD_INTERRUPT_ME; 1166 } 1167 1168 #ifdef INET 1169 /* h/w checksum */ 1170 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | 1171 M_CSUM_UDPv4) && m0->m_pkthdr.csum_flags & 1172 (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1173 struct ether_header *eh; 1174 uint16_t offset, start; 1175 1176 eh = mtod(m0, struct ether_header *); 1177 switch (ntohs(eh->ether_type)) { 1178 case ETHERTYPE_IP: 1179 start = ETHER_HDR_LEN; 1180 break; 1181 case ETHERTYPE_VLAN: 1182 start = ETHER_HDR_LEN + 1183 ETHER_VLAN_ENCAP_LEN; 1184 break; 1185 default: 1186 /* unsupported, drop it */ 1187 m_free(m0); 1188 continue; 1189 } 1190 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1191 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1192 flags |= (start << 1193 GEM_TD_CXSUM_STARTSHFT) | 1194 (offset << 1195 GEM_TD_CXSUM_STUFFSHFT) | 1196 GEM_TD_CXSUM_ENABLE; 1197 } 1198 #endif 1199 } 1200 if (seg == dmamap->dm_nsegs - 1) { 1201 flags |= GEM_TD_END_OF_PACKET; 1202 } else { 1203 /* last flag set outside of loop */ 1204 sc->sc_txdescs[nexttx].gd_flags = 1205 GEM_DMA_WRITE(sc, flags); 1206 } 1207 lasttx = nexttx; 1208 } 1209 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1210 /* add padding buffer at end of chain */ 1211 flags &= ~GEM_TD_END_OF_PACKET; 1212 sc->sc_txdescs[lasttx].gd_flags = 1213 GEM_DMA_WRITE(sc, flags); 1214 1215 sc->sc_txdescs[nexttx].gd_addr = 1216 GEM_DMA_WRITE(sc, 1217 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1218 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1219 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1220 lasttx = nexttx; 1221 nexttx = GEM_NEXTTX(nexttx); 1222 seg++; 1223 } 1224 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1225 1226 KASSERT(lasttx != -1); 1227 1228 /* 1229 * Store a pointer to the packet so we can free it later, 1230 * and remember what txdirty will be once the packet is 1231 * done. 1232 */ 1233 txs->txs_mbuf = m0; 1234 txs->txs_firstdesc = sc->sc_txnext; 1235 txs->txs_lastdesc = lasttx; 1236 txs->txs_ndescs = seg; 1237 1238 #ifdef GEM_DEBUG 1239 if (ifp->if_flags & IFF_DEBUG) { 1240 printf(" gem_start %p transmit chain:\n", txs); 1241 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1242 printf("descriptor %d:\t", seg); 1243 printf("gd_flags: 0x%016llx\t", (long long) 1244 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1245 printf("gd_addr: 0x%016llx\n", (long long) 1246 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1247 if (seg == lasttx) 1248 break; 1249 } 1250 } 1251 #endif 1252 1253 /* Sync the descriptors we're using. */ 1254 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1255 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1256 1257 /* Advance the tx pointer. */ 1258 sc->sc_txfree -= txs->txs_ndescs; 1259 sc->sc_txnext = nexttx; 1260 1261 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1262 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1263 1264 last_txs = txs; 1265 1266 #if NBPFILTER > 0 1267 /* 1268 * Pass the packet to any BPF listeners. 1269 */ 1270 if (ifp->if_bpf) 1271 bpf_mtap(ifp->if_bpf, m0); 1272 #endif /* NBPFILTER > 0 */ 1273 } 1274 1275 if (txs == NULL || sc->sc_txfree == 0) { 1276 /* No more slots left; notify upper layer. */ 1277 ifp->if_flags |= IFF_OACTIVE; 1278 sc->sc_if_flags = ifp->if_flags; 1279 } 1280 1281 if (sc->sc_txfree != ofree) { 1282 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1283 sc->sc_dev.dv_xname, lasttx, firsttx)); 1284 /* 1285 * The entire packet chain is set up. 1286 * Kick the transmitter. 1287 */ 1288 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1289 sc->sc_dev.dv_xname, nexttx)); 1290 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1291 sc->sc_txnext); 1292 1293 /* Set a watchdog timer in case the chip flakes out. */ 1294 ifp->if_timer = 5; 1295 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1296 sc->sc_dev.dv_xname, ifp->if_timer)); 1297 } 1298 } 1299 1300 /* 1301 * Transmit interrupt. 1302 */ 1303 int 1304 gem_tint(sc) 1305 struct gem_softc *sc; 1306 { 1307 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1308 bus_space_tag_t t = sc->sc_bustag; 1309 bus_space_handle_t mac = sc->sc_h1; 1310 struct gem_txsoft *txs; 1311 int txlast; 1312 int progress = 0; 1313 1314 1315 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1316 1317 /* 1318 * Unload collision counters 1319 */ 1320 ifp->if_collisions += 1321 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1322 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1323 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1324 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1325 1326 /* 1327 * then clear the hardware counters. 1328 */ 1329 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1330 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1331 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1332 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1333 1334 /* 1335 * Go through our Tx list and free mbufs for those 1336 * frames that have been transmitted. 1337 */ 1338 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1339 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1340 txs->txs_ndescs, 1341 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1342 1343 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1344 if (ifp->if_flags & IFF_DEBUG) { 1345 int i; 1346 printf(" txsoft %p transmit chain:\n", txs); 1347 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1348 printf("descriptor %d: ", i); 1349 printf("gd_flags: 0x%016" PRIx64 "\t", 1350 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1351 printf("gd_addr: 0x%016" PRIx64 "\n", 1352 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1353 if (i == txs->txs_lastdesc) 1354 break; 1355 } 1356 } 1357 #endif 1358 1359 /* 1360 * In theory, we could harveast some descriptors before 1361 * the ring is empty, but that's a bit complicated. 1362 * 1363 * GEM_TX_COMPLETION points to the last descriptor 1364 * processed +1. 1365 */ 1366 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1367 DPRINTF(sc, 1368 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1369 txs->txs_lastdesc, txlast)); 1370 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1371 if ((txlast >= txs->txs_firstdesc) && 1372 (txlast <= txs->txs_lastdesc)) 1373 break; 1374 } else { 1375 /* Ick -- this command wraps */ 1376 if ((txlast >= txs->txs_firstdesc) || 1377 (txlast <= txs->txs_lastdesc)) 1378 break; 1379 } 1380 1381 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1382 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1383 1384 sc->sc_txfree += txs->txs_ndescs; 1385 1386 if (txs->txs_mbuf == NULL) { 1387 #ifdef DIAGNOSTIC 1388 panic("gem_txintr: null mbuf"); 1389 #endif 1390 } 1391 1392 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1393 0, txs->txs_dmamap->dm_mapsize, 1394 BUS_DMASYNC_POSTWRITE); 1395 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1396 m_freem(txs->txs_mbuf); 1397 txs->txs_mbuf = NULL; 1398 1399 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1400 1401 ifp->if_opackets++; 1402 progress = 1; 1403 } 1404 1405 #if 0 1406 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1407 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1408 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1409 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1410 GEM_TX_DATA_PTR_HI) << 32) | 1411 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1412 GEM_TX_DATA_PTR_LO), 1413 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1414 #endif 1415 1416 if (progress) { 1417 if (sc->sc_txfree == GEM_NTXDESC - 1) 1418 sc->sc_txwin = 0; 1419 1420 ifp->if_flags &= ~IFF_OACTIVE; 1421 sc->sc_if_flags = ifp->if_flags; 1422 gem_start(ifp); 1423 1424 if (SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) 1425 ifp->if_timer = 0; 1426 } 1427 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1428 sc->sc_dev.dv_xname, ifp->if_timer)); 1429 1430 return (1); 1431 } 1432 1433 /* 1434 * Receive interrupt. 1435 */ 1436 int 1437 gem_rint(sc) 1438 struct gem_softc *sc; 1439 { 1440 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1441 bus_space_tag_t t = sc->sc_bustag; 1442 bus_space_handle_t h = sc->sc_h1; 1443 struct gem_rxsoft *rxs; 1444 struct mbuf *m; 1445 u_int64_t rxstat; 1446 u_int32_t rxcomp; 1447 int i, len, progress = 0; 1448 1449 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1450 1451 /* 1452 * Read the completion register once. This limits 1453 * how long the following loop can execute. 1454 */ 1455 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1456 1457 /* 1458 * XXXX Read the lastrx only once at the top for speed. 1459 */ 1460 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1461 sc->sc_rxptr, rxcomp)); 1462 1463 /* 1464 * Go into the loop at least once. 1465 */ 1466 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1467 i = GEM_NEXTRX(i)) { 1468 rxs = &sc->sc_rxsoft[i]; 1469 1470 GEM_CDRXSYNC(sc, i, 1471 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1472 1473 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1474 1475 if (rxstat & GEM_RD_OWN) { 1476 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1477 /* 1478 * We have processed all of the receive buffers. 1479 */ 1480 break; 1481 } 1482 1483 progress++; 1484 ifp->if_ipackets++; 1485 1486 if (rxstat & GEM_RD_BAD_CRC) { 1487 ifp->if_ierrors++; 1488 printf("%s: receive error: CRC error\n", 1489 sc->sc_dev.dv_xname); 1490 GEM_INIT_RXDESC(sc, i); 1491 continue; 1492 } 1493 1494 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1495 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1496 #ifdef GEM_DEBUG 1497 if (ifp->if_flags & IFF_DEBUG) { 1498 printf(" rxsoft %p descriptor %d: ", rxs, i); 1499 printf("gd_flags: 0x%016llx\t", (long long) 1500 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1501 printf("gd_addr: 0x%016llx\n", (long long) 1502 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1503 } 1504 #endif 1505 1506 /* No errors; receive the packet. */ 1507 len = GEM_RD_BUFLEN(rxstat); 1508 1509 /* 1510 * Allocate a new mbuf cluster. If that fails, we are 1511 * out of memory, and must drop the packet and recycle 1512 * the buffer that's already attached to this descriptor. 1513 */ 1514 m = rxs->rxs_mbuf; 1515 if (gem_add_rxbuf(sc, i) != 0) { 1516 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1517 ifp->if_ierrors++; 1518 GEM_INIT_RXDESC(sc, i); 1519 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1520 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1521 continue; 1522 } 1523 m->m_data += 2; /* We're already off by two */ 1524 1525 m->m_pkthdr.rcvif = ifp; 1526 m->m_pkthdr.len = m->m_len = len; 1527 1528 #if NBPFILTER > 0 1529 /* 1530 * Pass this up to any BPF listeners, but only 1531 * pass it up the stack if its for us. 1532 */ 1533 if (ifp->if_bpf) 1534 bpf_mtap(ifp->if_bpf, m); 1535 #endif /* NBPFILTER > 0 */ 1536 1537 #ifdef INET 1538 /* hardware checksum */ 1539 if (ifp->if_csum_flags_rx & (M_CSUM_UDPv4 | M_CSUM_TCPv4)) { 1540 struct ether_header *eh; 1541 struct ip *ip; 1542 struct udphdr *uh; 1543 int32_t hlen, pktlen; 1544 1545 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1546 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1547 ETHER_VLAN_ENCAP_LEN; 1548 eh = (struct ether_header *) mtod(m, void *) + 1549 ETHER_VLAN_ENCAP_LEN; 1550 } else { 1551 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1552 eh = mtod(m, struct ether_header *); 1553 } 1554 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1555 goto swcsum; 1556 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1557 1558 /* IPv4 only */ 1559 if (ip->ip_v != IPVERSION) 1560 goto swcsum; 1561 1562 hlen = ip->ip_hl << 2; 1563 if (hlen < sizeof(struct ip)) 1564 goto swcsum; 1565 1566 /* 1567 * bail if too short, has random trailing garbage, 1568 * truncated, fragment, or has ethernet pad. 1569 */ 1570 if ((ntohs(ip->ip_len) < hlen) || 1571 (ntohs(ip->ip_len) != pktlen) || 1572 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1573 goto swcsum; 1574 1575 switch (ip->ip_p) { 1576 case IPPROTO_TCP: 1577 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1578 goto swcsum; 1579 if (pktlen < (hlen + sizeof(struct tcphdr))) 1580 goto swcsum; 1581 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1582 break; 1583 case IPPROTO_UDP: 1584 if (! (ifp->if_csum_flags_rx & M_CSUM_UDPv4)) 1585 goto swcsum; 1586 if (pktlen < (hlen + sizeof(struct udphdr))) 1587 goto swcsum; 1588 uh = (struct udphdr *)((char *)ip + hlen); 1589 /* no checksum */ 1590 if (uh->uh_sum == 0) 1591 goto swcsum; 1592 m->m_pkthdr.csum_flags = M_CSUM_UDPv4; 1593 break; 1594 default: 1595 goto swcsum; 1596 } 1597 1598 /* the uncomplemented sum is expected */ 1599 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1600 1601 /* if the pkt had ip options, we have to deduct them */ 1602 if (hlen > sizeof(struct ip)) { 1603 uint16_t *opts; 1604 uint32_t optsum, temp; 1605 1606 optsum = 0; 1607 temp = hlen - sizeof(struct ip); 1608 opts = (uint16_t *) ((char *) ip + 1609 sizeof(struct ip)); 1610 1611 while (temp > 1) { 1612 optsum += ntohs(*opts++); 1613 temp -= 2; 1614 } 1615 while (optsum >> 16) 1616 optsum = (optsum >> 16) + 1617 (optsum & 0xffff); 1618 1619 /* Deduct ip opts sum from hwsum (rfc 1624). */ 1620 m->m_pkthdr.csum_data = 1621 ~((~m->m_pkthdr.csum_data) - ~optsum); 1622 1623 while (m->m_pkthdr.csum_data >> 16) 1624 m->m_pkthdr.csum_data = 1625 (m->m_pkthdr.csum_data >> 16) + 1626 (m->m_pkthdr.csum_data & 1627 0xffff); 1628 } 1629 1630 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1631 M_CSUM_NO_PSEUDOHDR; 1632 } else 1633 swcsum: 1634 m->m_pkthdr.csum_flags = 0; 1635 #endif 1636 /* Pass it on. */ 1637 (*ifp->if_input)(ifp, m); 1638 } 1639 1640 if (progress) { 1641 /* Update the receive pointer. */ 1642 if (i == sc->sc_rxptr) { 1643 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1644 #ifdef GEM_DEBUG 1645 if (ifp->if_flags & IFF_DEBUG) 1646 printf("%s: rint: ring wrap\n", 1647 sc->sc_dev.dv_xname); 1648 #endif 1649 } 1650 sc->sc_rxptr = i; 1651 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1652 } 1653 #ifdef GEM_COUNTERS 1654 if (progress <= 4) { 1655 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1656 } else if (progress < 32) { 1657 if (progress < 16) 1658 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1659 else 1660 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1661 1662 } else { 1663 if (progress < 64) 1664 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1665 else 1666 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1667 } 1668 #endif 1669 1670 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1671 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1672 1673 return (1); 1674 } 1675 1676 1677 /* 1678 * gem_add_rxbuf: 1679 * 1680 * Add a receive buffer to the indicated descriptor. 1681 */ 1682 int 1683 gem_add_rxbuf(struct gem_softc *sc, int idx) 1684 { 1685 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1686 struct mbuf *m; 1687 int error; 1688 1689 MGETHDR(m, M_DONTWAIT, MT_DATA); 1690 if (m == NULL) 1691 return (ENOBUFS); 1692 1693 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1694 MCLGET(m, M_DONTWAIT); 1695 if ((m->m_flags & M_EXT) == 0) { 1696 m_freem(m); 1697 return (ENOBUFS); 1698 } 1699 1700 #ifdef GEM_DEBUG 1701 /* bzero the packet to check DMA */ 1702 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1703 #endif 1704 1705 if (rxs->rxs_mbuf != NULL) 1706 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1707 1708 rxs->rxs_mbuf = m; 1709 1710 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1711 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1712 BUS_DMA_READ|BUS_DMA_NOWAIT); 1713 if (error) { 1714 printf("%s: can't load rx DMA map %d, error = %d\n", 1715 sc->sc_dev.dv_xname, idx, error); 1716 panic("gem_add_rxbuf"); /* XXX */ 1717 } 1718 1719 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1720 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1721 1722 GEM_INIT_RXDESC(sc, idx); 1723 1724 return (0); 1725 } 1726 1727 1728 int 1729 gem_eint(sc, status) 1730 struct gem_softc *sc; 1731 u_int status; 1732 { 1733 char bits[128]; 1734 1735 if ((status & GEM_INTR_MIF) != 0) { 1736 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1737 return (1); 1738 } 1739 1740 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1741 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1742 return (1); 1743 } 1744 1745 1746 int 1747 gem_intr(v) 1748 void *v; 1749 { 1750 struct gem_softc *sc = (struct gem_softc *)v; 1751 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1752 bus_space_tag_t t = sc->sc_bustag; 1753 bus_space_handle_t seb = sc->sc_h1; 1754 u_int32_t status; 1755 int r = 0; 1756 #ifdef GEM_DEBUG 1757 char bits[128]; 1758 #endif 1759 1760 sc->sc_ev_intr.ev_count++; 1761 1762 status = bus_space_read_4(t, seb, GEM_STATUS); 1763 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 1764 sc->sc_dev.dv_xname, (status >> 19), 1765 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1766 1767 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1768 r |= gem_eint(sc, status); 1769 1770 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 1771 GEM_COUNTER_INCR(sc, sc_ev_txint); 1772 r |= gem_tint(sc); 1773 } 1774 1775 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 1776 GEM_COUNTER_INCR(sc, sc_ev_rxint); 1777 r |= gem_rint(sc); 1778 } 1779 1780 /* We should eventually do more than just print out error stats. */ 1781 if (status & GEM_INTR_TX_MAC) { 1782 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1783 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1784 printf("%s: MAC tx fault, status %x\n", 1785 sc->sc_dev.dv_xname, txstat); 1786 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 1787 gem_init(ifp); 1788 } 1789 if (status & GEM_INTR_RX_MAC) { 1790 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1791 if (rxstat & ~GEM_MAC_RX_DONE) 1792 printf("%s: MAC rx fault, status %x\n", 1793 sc->sc_dev.dv_xname, rxstat); 1794 /* 1795 * On some chip revisions GEM_MAC_RX_OVERFLOW happen often 1796 * due to a silicon bug so handle them silently. 1797 */ 1798 if (rxstat & GEM_MAC_RX_OVERFLOW) 1799 gem_init(ifp); 1800 else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 1801 printf("%s: MAC rx fault, status %x\n", 1802 sc->sc_dev.dv_xname, rxstat); 1803 } 1804 #if NRND > 0 1805 rnd_add_uint32(&sc->rnd_source, status); 1806 #endif 1807 return (r); 1808 } 1809 1810 1811 void 1812 gem_watchdog(ifp) 1813 struct ifnet *ifp; 1814 { 1815 struct gem_softc *sc = ifp->if_softc; 1816 1817 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1818 "GEM_MAC_RX_CONFIG %x\n", 1819 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 1820 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 1821 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 1822 1823 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1824 ++ifp->if_oerrors; 1825 1826 /* Try to get more packets going. */ 1827 gem_start(ifp); 1828 } 1829 1830 /* 1831 * Initialize the MII Management Interface 1832 */ 1833 void 1834 gem_mifinit(sc) 1835 struct gem_softc *sc; 1836 { 1837 bus_space_tag_t t = sc->sc_bustag; 1838 bus_space_handle_t mif = sc->sc_h1; 1839 1840 /* Configure the MIF in frame mode */ 1841 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1842 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1843 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1844 } 1845 1846 /* 1847 * MII interface 1848 * 1849 * The GEM MII interface supports at least three different operating modes: 1850 * 1851 * Bitbang mode is implemented using data, clock and output enable registers. 1852 * 1853 * Frame mode is implemented by loading a complete frame into the frame 1854 * register and polling the valid bit for completion. 1855 * 1856 * Polling mode uses the frame register but completion is indicated by 1857 * an interrupt. 1858 * 1859 */ 1860 static int 1861 gem_mii_readreg(self, phy, reg) 1862 struct device *self; 1863 int phy, reg; 1864 { 1865 struct gem_softc *sc = (void *)self; 1866 bus_space_tag_t t = sc->sc_bustag; 1867 bus_space_handle_t mif = sc->sc_h1; 1868 int n; 1869 u_int32_t v; 1870 1871 #ifdef GEM_DEBUG1 1872 if (sc->sc_debug) 1873 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1874 #endif 1875 1876 #if 0 1877 /* Select the desired PHY in the MIF configuration register */ 1878 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1879 /* Clear PHY select bit */ 1880 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1881 if (phy == GEM_PHYAD_EXTERNAL) 1882 /* Set PHY select bit to get at external device */ 1883 v |= GEM_MIF_CONFIG_PHY_SEL; 1884 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1885 #endif 1886 1887 /* Construct the frame command */ 1888 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1889 GEM_MIF_FRAME_READ; 1890 1891 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1892 for (n = 0; n < 100; n++) { 1893 DELAY(1); 1894 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1895 if (v & GEM_MIF_FRAME_TA0) 1896 return (v & GEM_MIF_FRAME_DATA); 1897 } 1898 1899 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1900 return (0); 1901 } 1902 1903 static void 1904 gem_mii_writereg(self, phy, reg, val) 1905 struct device *self; 1906 int phy, reg, val; 1907 { 1908 struct gem_softc *sc = (void *)self; 1909 bus_space_tag_t t = sc->sc_bustag; 1910 bus_space_handle_t mif = sc->sc_h1; 1911 int n; 1912 u_int32_t v; 1913 1914 #ifdef GEM_DEBUG1 1915 if (sc->sc_debug) 1916 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1917 phy, reg, val); 1918 #endif 1919 1920 #if 0 1921 /* Select the desired PHY in the MIF configuration register */ 1922 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1923 /* Clear PHY select bit */ 1924 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1925 if (phy == GEM_PHYAD_EXTERNAL) 1926 /* Set PHY select bit to get at external device */ 1927 v |= GEM_MIF_CONFIG_PHY_SEL; 1928 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1929 #endif 1930 /* Construct the frame command */ 1931 v = GEM_MIF_FRAME_WRITE | 1932 (phy << GEM_MIF_PHY_SHIFT) | 1933 (reg << GEM_MIF_REG_SHIFT) | 1934 (val & GEM_MIF_FRAME_DATA); 1935 1936 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1937 for (n = 0; n < 100; n++) { 1938 DELAY(1); 1939 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1940 if (v & GEM_MIF_FRAME_TA0) 1941 return; 1942 } 1943 1944 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1945 } 1946 1947 static void 1948 gem_mii_statchg(dev) 1949 struct device *dev; 1950 { 1951 struct gem_softc *sc = (void *)dev; 1952 #ifdef GEM_DEBUG 1953 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1954 #endif 1955 bus_space_tag_t t = sc->sc_bustag; 1956 bus_space_handle_t mac = sc->sc_h1; 1957 u_int32_t v; 1958 1959 #ifdef GEM_DEBUG 1960 if (sc->sc_debug) 1961 printf("gem_mii_statchg: status change: phy = %d\n", 1962 sc->sc_phys[instance]); 1963 #endif 1964 1965 1966 /* Set tx full duplex options */ 1967 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1968 delay(10000); /* reg must be cleared and delay before changing. */ 1969 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1970 GEM_MAC_TX_ENABLE; 1971 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1972 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1973 } 1974 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1975 1976 /* XIF Configuration */ 1977 /* We should really calculate all this rather than rely on defaults */ 1978 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1979 v = GEM_MAC_XIF_LINK_LED; 1980 v |= GEM_MAC_XIF_TX_MII_ENA; 1981 1982 /* If an external transceiver is connected, enable its MII drivers */ 1983 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1984 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1985 /* External MII needs echo disable if half duplex. */ 1986 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1987 /* turn on full duplex LED */ 1988 v |= GEM_MAC_XIF_FDPLX_LED; 1989 else 1990 /* half duplex -- disable echo */ 1991 v |= GEM_MAC_XIF_ECHO_DISABL; 1992 1993 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 1994 v |= GEM_MAC_XIF_GMII_MODE; 1995 else 1996 v &= ~GEM_MAC_XIF_GMII_MODE; 1997 } else 1998 /* Internal MII needs buf enable */ 1999 v |= GEM_MAC_XIF_MII_BUF_ENA; 2000 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2001 } 2002 2003 int 2004 gem_mediachange(ifp) 2005 struct ifnet *ifp; 2006 { 2007 struct gem_softc *sc = ifp->if_softc; 2008 2009 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 2010 return (EINVAL); 2011 2012 return (mii_mediachg(&sc->sc_mii)); 2013 } 2014 2015 void 2016 gem_mediastatus(ifp, ifmr) 2017 struct ifnet *ifp; 2018 struct ifmediareq *ifmr; 2019 { 2020 struct gem_softc *sc = ifp->if_softc; 2021 2022 if ((ifp->if_flags & IFF_UP) == 0) 2023 return; 2024 2025 mii_pollstat(&sc->sc_mii); 2026 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2027 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2028 } 2029 2030 /* 2031 * Process an ioctl request. 2032 */ 2033 int 2034 gem_ioctl(ifp, cmd, data) 2035 struct ifnet *ifp; 2036 u_long cmd; 2037 void *data; 2038 { 2039 struct gem_softc *sc = ifp->if_softc; 2040 struct ifreq *ifr = (struct ifreq *)data; 2041 int s, error = 0; 2042 2043 s = splnet(); 2044 2045 switch (cmd) { 2046 case SIOCGIFMEDIA: 2047 case SIOCSIFMEDIA: 2048 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 2049 break; 2050 case SIOCSIFFLAGS: 2051 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 2052 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 2053 == (IFF_UP|IFF_RUNNING)) 2054 && ((ifp->if_flags & (~RESETIGN)) 2055 == (sc->sc_if_flags & (~RESETIGN)))) { 2056 gem_setladrf(sc); 2057 break; 2058 } 2059 #undef RESETIGN 2060 /*FALLTHROUGH*/ 2061 default: 2062 error = ether_ioctl(ifp, cmd, data); 2063 if (error == ENETRESET) { 2064 /* 2065 * Multicast list has changed; set the hardware filter 2066 * accordingly. 2067 */ 2068 if (ifp->if_flags & IFF_RUNNING) 2069 gem_setladrf(sc); 2070 error = 0; 2071 } 2072 break; 2073 } 2074 2075 /* Try to get things going again */ 2076 if (ifp->if_flags & IFF_UP) 2077 gem_start(ifp); 2078 splx(s); 2079 return (error); 2080 } 2081 2082 2083 void 2084 gem_shutdown(arg) 2085 void *arg; 2086 { 2087 struct gem_softc *sc = (struct gem_softc *)arg; 2088 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2089 2090 gem_stop(ifp, 1); 2091 } 2092 2093 /* 2094 * Set up the logical address filter. 2095 */ 2096 void 2097 gem_setladrf(sc) 2098 struct gem_softc *sc; 2099 { 2100 struct ethercom *ec = &sc->sc_ethercom; 2101 struct ifnet *ifp = &ec->ec_if; 2102 struct ether_multi *enm; 2103 struct ether_multistep step; 2104 bus_space_tag_t t = sc->sc_bustag; 2105 bus_space_handle_t h = sc->sc_h1; 2106 u_int32_t crc; 2107 u_int32_t hash[16]; 2108 u_int32_t v; 2109 int i; 2110 2111 /* Get current RX configuration */ 2112 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2113 2114 /* 2115 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2116 * and hash filter. Depending on the case, the right bit will be 2117 * enabled. 2118 */ 2119 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2120 GEM_MAC_RX_PROMISC_GRP); 2121 2122 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2123 /* Turn on promiscuous mode */ 2124 v |= GEM_MAC_RX_PROMISCUOUS; 2125 ifp->if_flags |= IFF_ALLMULTI; 2126 goto chipit; 2127 } 2128 2129 /* 2130 * Set up multicast address filter by passing all multicast addresses 2131 * through a crc generator, and then using the high order 8 bits as an 2132 * index into the 256 bit logical address filter. The high order 4 2133 * bits selects the word, while the other 4 bits select the bit within 2134 * the word (where bit 0 is the MSB). 2135 */ 2136 2137 /* Clear hash table */ 2138 memset(hash, 0, sizeof(hash)); 2139 2140 ETHER_FIRST_MULTI(step, ec, enm); 2141 while (enm != NULL) { 2142 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2143 /* 2144 * We must listen to a range of multicast addresses. 2145 * For now, just accept all multicasts, rather than 2146 * trying to set only those filter bits needed to match 2147 * the range. (At this time, the only use of address 2148 * ranges is for IP multicast routing, for which the 2149 * range is big enough to require all bits set.) 2150 * XXX use the addr filter for this 2151 */ 2152 ifp->if_flags |= IFF_ALLMULTI; 2153 v |= GEM_MAC_RX_PROMISC_GRP; 2154 goto chipit; 2155 } 2156 2157 /* Get the LE CRC32 of the address */ 2158 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2159 2160 /* Just want the 8 most significant bits. */ 2161 crc >>= 24; 2162 2163 /* Set the corresponding bit in the filter. */ 2164 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2165 2166 ETHER_NEXT_MULTI(step, enm); 2167 } 2168 2169 v |= GEM_MAC_RX_HASH_FILTER; 2170 ifp->if_flags &= ~IFF_ALLMULTI; 2171 2172 /* Now load the hash table into the chip (if we are using it) */ 2173 for (i = 0; i < 16; i++) { 2174 bus_space_write_4(t, h, 2175 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2176 hash[i]); 2177 } 2178 2179 chipit: 2180 sc->sc_if_flags = ifp->if_flags; 2181 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2182 } 2183 2184 #if notyet 2185 2186 /* 2187 * gem_power: 2188 * 2189 * Power management (suspend/resume) hook. 2190 */ 2191 void 2192 gem_power(why, arg) 2193 int why; 2194 void *arg; 2195 { 2196 struct gem_softc *sc = arg; 2197 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2198 int s; 2199 2200 s = splnet(); 2201 switch (why) { 2202 case PWR_SUSPEND: 2203 case PWR_STANDBY: 2204 gem_stop(ifp, 1); 2205 if (sc->sc_power != NULL) 2206 (*sc->sc_power)(sc, why); 2207 break; 2208 case PWR_RESUME: 2209 if (ifp->if_flags & IFF_UP) { 2210 if (sc->sc_power != NULL) 2211 (*sc->sc_power)(sc, why); 2212 gem_init(ifp); 2213 } 2214 break; 2215 case PWR_SOFTSUSPEND: 2216 case PWR_SOFTSTANDBY: 2217 case PWR_SOFTRESUME: 2218 break; 2219 } 2220 splx(s); 2221 } 2222 #endif 2223