1 /* $NetBSD: gem.c,v 1.3 2001/10/01 23:55:00 eeh Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include "bpfilter.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/callout.h> 41 #include <sys/mbuf.h> 42 #include <sys/syslog.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/ioctl.h> 47 #include <sys/errno.h> 48 #include <sys/device.h> 49 50 #include <machine/endian.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_ether.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 #include <dev/mii/mii_bitbang.h> 69 70 #include <dev/ic/gemreg.h> 71 #include <dev/ic/gemvar.h> 72 73 #define TRIES 10000 74 75 void gem_start __P((struct ifnet *)); 76 void gem_stop __P((struct ifnet *, int)); 77 int gem_ioctl __P((struct ifnet *, u_long, caddr_t)); 78 void gem_tick __P((void *)); 79 void gem_watchdog __P((struct ifnet *)); 80 void gem_shutdown __P((void *)); 81 int gem_init __P((struct ifnet *)); 82 void gem_init_regs(struct gem_softc *sc); 83 static int gem_ringsize(int sz); 84 int gem_meminit __P((struct gem_softc *)); 85 void gem_mifinit __P((struct gem_softc *)); 86 void gem_reset __P((struct gem_softc *)); 87 int gem_reset_rx(struct gem_softc *sc); 88 int gem_reset_tx(struct gem_softc *sc); 89 int gem_disable_rx(struct gem_softc *sc); 90 int gem_disable_tx(struct gem_softc *sc); 91 void gem_rxdrain(struct gem_softc *sc); 92 int gem_add_rxbuf(struct gem_softc *sc, int idx); 93 void gem_setladrf __P((struct gem_softc *)); 94 95 /* MII methods & callbacks */ 96 static int gem_mii_readreg __P((struct device *, int, int)); 97 static void gem_mii_writereg __P((struct device *, int, int, int)); 98 static void gem_mii_statchg __P((struct device *)); 99 100 int gem_mediachange __P((struct ifnet *)); 101 void gem_mediastatus __P((struct ifnet *, struct ifmediareq *)); 102 103 struct mbuf *gem_get __P((struct gem_softc *, int, int)); 104 int gem_put __P((struct gem_softc *, int, struct mbuf *)); 105 void gem_read __P((struct gem_softc *, int, int)); 106 int gem_eint __P((struct gem_softc *, u_int)); 107 int gem_rint __P((struct gem_softc *)); 108 int gem_tint __P((struct gem_softc *)); 109 void gem_power __P((int, void *)); 110 111 static int ether_cmp __P((u_char *, u_char *)); 112 113 /* Default buffer copy routines */ 114 void gem_copytobuf_contig __P((struct gem_softc *, void *, int, int)); 115 void gem_copyfrombuf_contig __P((struct gem_softc *, void *, int, int)); 116 void gem_zerobuf_contig __P((struct gem_softc *, int, int)); 117 118 119 #ifdef GEM_DEBUG 120 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 121 printf x 122 #else 123 #define DPRINTF(sc, x) /* nothing */ 124 #endif 125 126 127 /* 128 * gem_config: 129 * 130 * Attach a Gem interface to the system. 131 */ 132 void 133 gem_config(sc) 134 struct gem_softc *sc; 135 { 136 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 137 struct mii_data *mii = &sc->sc_mii; 138 struct mii_softc *child; 139 int i, error; 140 141 /* Make sure the chip is stopped. */ 142 ifp->if_softc = sc; 143 gem_reset(sc); 144 145 /* 146 * Allocate the control data structures, and create and load the 147 * DMA map for it. 148 */ 149 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 150 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 151 1, &sc->sc_cdnseg, 0)) != 0) { 152 printf("%s: unable to allocate control data, error = %d\n", 153 sc->sc_dev.dv_xname, error); 154 goto fail_0; 155 } 156 157 /* XXX should map this in with correct endianness */ 158 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 159 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 160 BUS_DMA_COHERENT)) != 0) { 161 printf("%s: unable to map control data, error = %d\n", 162 sc->sc_dev.dv_xname, error); 163 goto fail_1; 164 } 165 166 if ((error = bus_dmamap_create(sc->sc_dmatag, 167 sizeof(struct gem_control_data), 1, 168 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 169 printf("%s: unable to create control data DMA map, " 170 "error = %d\n", sc->sc_dev.dv_xname, error); 171 goto fail_2; 172 } 173 174 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 175 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 176 0)) != 0) { 177 printf("%s: unable to load control data DMA map, error = %d\n", 178 sc->sc_dev.dv_xname, error); 179 goto fail_3; 180 } 181 182 /* 183 * Initialize the transmit job descriptors. 184 */ 185 SIMPLEQ_INIT(&sc->sc_txfreeq); 186 SIMPLEQ_INIT(&sc->sc_txdirtyq); 187 188 /* 189 * Create the transmit buffer DMA maps. 190 */ 191 for (i = 0; i < GEM_TXQUEUELEN; i++) { 192 struct gem_txsoft *txs; 193 194 txs = &sc->sc_txsoft[i]; 195 txs->txs_mbuf = NULL; 196 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 197 GEM_NTXSEGS, MCLBYTES, 0, 0, 198 &txs->txs_dmamap)) != 0) { 199 printf("%s: unable to create tx DMA map %d, " 200 "error = %d\n", sc->sc_dev.dv_xname, i, error); 201 goto fail_4; 202 } 203 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 204 } 205 206 /* 207 * Create the receive buffer DMA maps. 208 */ 209 for (i = 0; i < GEM_NRXDESC; i++) { 210 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 211 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 212 printf("%s: unable to create rx DMA map %d, " 213 "error = %d\n", sc->sc_dev.dv_xname, i, error); 214 goto fail_5; 215 } 216 sc->sc_rxsoft[i].rxs_mbuf = NULL; 217 } 218 219 /* 220 * From this point forward, the attachment cannot fail. A failure 221 * before this point releases all resources that may have been 222 * allocated. 223 */ 224 225 /* Announce ourselves. */ 226 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 227 ether_sprintf(sc->sc_enaddr)); 228 229 /* Initialize ifnet structure. */ 230 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 231 ifp->if_softc = sc; 232 ifp->if_flags = 233 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 234 ifp->if_start = gem_start; 235 ifp->if_ioctl = gem_ioctl; 236 ifp->if_watchdog = gem_watchdog; 237 ifp->if_stop = gem_stop; 238 ifp->if_init = gem_init; 239 IFQ_SET_READY(&ifp->if_snd); 240 241 /* Initialize ifmedia structures and MII info */ 242 mii->mii_ifp = ifp; 243 mii->mii_readreg = gem_mii_readreg; 244 mii->mii_writereg = gem_mii_writereg; 245 mii->mii_statchg = gem_mii_statchg; 246 247 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus); 248 249 gem_mifinit(sc); 250 251 mii_attach(&sc->sc_dev, mii, 0xffffffff, 252 MII_PHY_ANY, MII_OFFSET_ANY, 0); 253 254 child = LIST_FIRST(&mii->mii_phys); 255 if (child == NULL) { 256 /* No PHY attached */ 257 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 258 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 259 } else { 260 /* 261 * Walk along the list of attached MII devices and 262 * establish an `MII instance' to `phy number' 263 * mapping. We'll use this mapping in media change 264 * requests to determine which phy to use to program 265 * the MIF configuration register. 266 */ 267 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 268 /* 269 * Note: we support just two PHYs: the built-in 270 * internal device and an external on the MII 271 * connector. 272 */ 273 if (child->mii_phy > 1 || child->mii_inst > 1) { 274 printf("%s: cannot accomodate MII device %s" 275 " at phy %d, instance %d\n", 276 sc->sc_dev.dv_xname, 277 child->mii_dev.dv_xname, 278 child->mii_phy, child->mii_inst); 279 continue; 280 } 281 282 sc->sc_phys[child->mii_inst] = child->mii_phy; 283 } 284 285 /* 286 * Now select and activate the PHY we will use. 287 * 288 * The order of preference is External (MDI1), 289 * Internal (MDI0), Serial Link (no MII). 290 */ 291 if (sc->sc_phys[1]) { 292 #ifdef DEBUG 293 printf("using external phy\n"); 294 #endif 295 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 296 } else { 297 #ifdef DEBUG 298 printf("using internal phy\n"); 299 #endif 300 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 301 } 302 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 303 sc->sc_mif_config); 304 305 /* 306 * XXX - we can really do the following ONLY if the 307 * phy indeed has the auto negotiation capability!! 308 */ 309 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 310 } 311 312 /* claim 802.1q capability */ 313 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 314 315 /* Attach the interface. */ 316 if_attach(ifp); 317 ether_ifattach(ifp, sc->sc_enaddr); 318 319 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 320 if (sc->sc_sh == NULL) 321 panic("gem_config: can't establish shutdownhook"); 322 323 #if NRND > 0 324 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 325 RND_TYPE_NET, 0); 326 #endif 327 328 329 #if notyet 330 /* 331 * Add a suspend hook to make sure we come back up after a 332 * resume. 333 */ 334 sc->sc_powerhook = powerhook_establish(gem_power, sc); 335 if (sc->sc_powerhook == NULL) 336 printf("%s: WARNING: unable to establish power hook\n", 337 sc->sc_dev.dv_xname); 338 #endif 339 340 callout_init(&sc->sc_tick_ch); 341 return; 342 343 /* 344 * Free any resources we've allocated during the failed attach 345 * attempt. Do this in reverse order and fall through. 346 */ 347 fail_5: 348 for (i = 0; i < GEM_NRXDESC; i++) { 349 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 350 bus_dmamap_destroy(sc->sc_dmatag, 351 sc->sc_rxsoft[i].rxs_dmamap); 352 } 353 fail_4: 354 for (i = 0; i < GEM_TXQUEUELEN; i++) { 355 if (sc->sc_txsoft[i].txs_dmamap != NULL) 356 bus_dmamap_destroy(sc->sc_dmatag, 357 sc->sc_txsoft[i].txs_dmamap); 358 } 359 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 360 fail_3: 361 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 362 fail_2: 363 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 364 sizeof(struct gem_control_data)); 365 fail_1: 366 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 367 fail_0: 368 return; 369 } 370 371 372 void 373 gem_tick(arg) 374 void *arg; 375 { 376 struct gem_softc *sc = arg; 377 int s; 378 379 s = splnet(); 380 mii_tick(&sc->sc_mii); 381 splx(s); 382 383 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 384 385 } 386 387 void 388 gem_reset(sc) 389 struct gem_softc *sc; 390 { 391 bus_space_tag_t t = sc->sc_bustag; 392 bus_space_handle_t h = sc->sc_h; 393 int i; 394 int s; 395 396 s = splnet(); 397 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 398 gem_reset_rx(sc); 399 gem_reset_tx(sc); 400 401 /* Do a full reset */ 402 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 403 for (i=TRIES; i--; delay(100)) 404 if ((bus_space_read_4(t, h, GEM_RESET) & 405 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 406 break; 407 if ((bus_space_read_4(t, h, GEM_RESET) & 408 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 409 printf("%s: cannot reset device\n", 410 sc->sc_dev.dv_xname); 411 } 412 splx(s); 413 } 414 415 416 /* 417 * gem_rxdrain: 418 * 419 * Drain the receive queue. 420 */ 421 void 422 gem_rxdrain(struct gem_softc *sc) 423 { 424 struct gem_rxsoft *rxs; 425 int i; 426 427 for (i = 0; i < GEM_NRXDESC; i++) { 428 rxs = &sc->sc_rxsoft[i]; 429 if (rxs->rxs_mbuf != NULL) { 430 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 431 m_freem(rxs->rxs_mbuf); 432 rxs->rxs_mbuf = NULL; 433 } 434 } 435 } 436 437 /* 438 * Reset the whole thing. 439 */ 440 void 441 gem_stop(struct ifnet *ifp, int disable) 442 { 443 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 444 struct gem_txsoft *txs; 445 446 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 447 448 callout_stop(&sc->sc_tick_ch); 449 mii_down(&sc->sc_mii); 450 451 /* XXX - Should we reset these instead? */ 452 gem_disable_rx(sc); 453 gem_disable_rx(sc); 454 455 /* 456 * Release any queued transmit buffers. 457 */ 458 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 459 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 460 if (txs->txs_mbuf != NULL) { 461 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 462 m_freem(txs->txs_mbuf); 463 txs->txs_mbuf = NULL; 464 } 465 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 466 } 467 468 if (disable) { 469 gem_rxdrain(sc); 470 } 471 472 /* 473 * Mark the interface down and cancel the watchdog timer. 474 */ 475 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 476 ifp->if_timer = 0; 477 } 478 479 480 /* 481 * Reset the receiver 482 */ 483 int 484 gem_reset_rx(struct gem_softc *sc) 485 { 486 bus_space_tag_t t = sc->sc_bustag; 487 bus_space_handle_t h = sc->sc_h; 488 int i; 489 490 491 /* 492 * Resetting while DMA is in progress can cause a bus hang, so we 493 * disable DMA first. 494 */ 495 gem_disable_rx(sc); 496 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 497 /* Wait till it finishes */ 498 for (i=TRIES; i--; delay(100)) 499 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 500 break; 501 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 502 printf("%s: cannot disable read dma\n", 503 sc->sc_dev.dv_xname); 504 505 /* Wait 5ms extra. */ 506 delay(5000); 507 508 /* Finally, reset the ERX */ 509 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 510 /* Wait till it finishes */ 511 for (i=TRIES; i--; delay(100)) 512 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 513 break; 514 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 515 printf("%s: cannot reset receiver\n", 516 sc->sc_dev.dv_xname); 517 return (1); 518 } 519 return (0); 520 } 521 522 523 /* 524 * Reset the transmitter 525 */ 526 int 527 gem_reset_tx(struct gem_softc *sc) 528 { 529 bus_space_tag_t t = sc->sc_bustag; 530 bus_space_handle_t h = sc->sc_h; 531 int i; 532 533 /* 534 * Resetting while DMA is in progress can cause a bus hang, so we 535 * disable DMA first. 536 */ 537 gem_disable_tx(sc); 538 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 539 /* Wait till it finishes */ 540 for (i=TRIES; i--; delay(100)) 541 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 542 break; 543 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 544 printf("%s: cannot disable read dma\n", 545 sc->sc_dev.dv_xname); 546 547 /* Wait 5ms extra. */ 548 delay(5000); 549 550 /* Finally, reset the ETX */ 551 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 552 /* Wait till it finishes */ 553 for (i=TRIES; i--; delay(100)) 554 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 555 break; 556 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 557 printf("%s: cannot reset receiver\n", 558 sc->sc_dev.dv_xname); 559 return (1); 560 } 561 return (0); 562 } 563 564 /* 565 * disable receiver. 566 */ 567 int 568 gem_disable_rx(struct gem_softc *sc) 569 { 570 bus_space_tag_t t = sc->sc_bustag; 571 bus_space_handle_t h = sc->sc_h; 572 int i; 573 u_int32_t cfg; 574 575 /* Flip the enable bit */ 576 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 577 cfg &= ~GEM_MAC_RX_ENABLE; 578 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 579 580 /* Wait for it to finish */ 581 for (i=TRIES; i--; delay(100)) 582 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 583 GEM_MAC_RX_ENABLE) == 0) 584 return (0); 585 return (1); 586 } 587 588 /* 589 * disable transmitter. 590 */ 591 int 592 gem_disable_tx(struct gem_softc *sc) 593 { 594 bus_space_tag_t t = sc->sc_bustag; 595 bus_space_handle_t h = sc->sc_h; 596 int i; 597 u_int32_t cfg; 598 599 /* Flip the enable bit */ 600 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 601 cfg &= ~GEM_MAC_TX_ENABLE; 602 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 603 604 /* Wait for it to finish */ 605 for (i=TRIES; i--; delay(100)) 606 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 607 GEM_MAC_TX_ENABLE) == 0) 608 return (0); 609 return (1); 610 } 611 612 /* 613 * Initialize interface. 614 */ 615 int 616 gem_meminit(struct gem_softc *sc) 617 { 618 struct gem_rxsoft *rxs; 619 int i, error; 620 621 /* 622 * Initialize the transmit descriptor ring. 623 */ 624 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 625 for (i = 0; i < GEM_NTXDESC; i++) { 626 sc->sc_txdescs[i].gd_flags = 0; 627 sc->sc_txdescs[i].gd_addr = 0; 628 } 629 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 630 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 631 sc->sc_txfree = GEM_NTXDESC; 632 sc->sc_txnext = 0; 633 634 /* 635 * Initialize the receive descriptor and receive job 636 * descriptor rings. 637 */ 638 for (i = 0; i < GEM_NRXDESC; i++) { 639 rxs = &sc->sc_rxsoft[i]; 640 if (rxs->rxs_mbuf == NULL) { 641 if ((error = gem_add_rxbuf(sc, i)) != 0) { 642 printf("%s: unable to allocate or map rx " 643 "buffer %d, error = %d\n", 644 sc->sc_dev.dv_xname, i, error); 645 /* 646 * XXX Should attempt to run with fewer receive 647 * XXX buffers instead of just failing. 648 */ 649 gem_rxdrain(sc); 650 return (1); 651 } 652 } else 653 GEM_INIT_RXDESC(sc, i); 654 } 655 sc->sc_rxptr = 0; 656 657 return (0); 658 } 659 660 static int 661 gem_ringsize(int sz) 662 { 663 int v; 664 665 switch (sz) { 666 case 32: 667 v = GEM_RING_SZ_32; 668 break; 669 case 64: 670 v = GEM_RING_SZ_64; 671 break; 672 case 128: 673 v = GEM_RING_SZ_128; 674 break; 675 case 256: 676 v = GEM_RING_SZ_256; 677 break; 678 case 512: 679 v = GEM_RING_SZ_512; 680 break; 681 case 1024: 682 v = GEM_RING_SZ_1024; 683 break; 684 case 2048: 685 v = GEM_RING_SZ_2048; 686 break; 687 case 4096: 688 v = GEM_RING_SZ_4096; 689 break; 690 case 8192: 691 v = GEM_RING_SZ_8192; 692 break; 693 default: 694 printf("gem: invalid Receive Descriptor ring size\n"); 695 break; 696 } 697 return (v); 698 } 699 700 /* 701 * Initialization of interface; set up initialization block 702 * and transmit/receive descriptor rings. 703 */ 704 int 705 gem_init(struct ifnet *ifp) 706 { 707 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 708 bus_space_tag_t t = sc->sc_bustag; 709 bus_space_handle_t h = sc->sc_h; 710 int s; 711 u_int32_t v; 712 713 s = splnet(); 714 715 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 716 /* 717 * Initialization sequence. The numbered steps below correspond 718 * to the sequence outlined in section 6.3.5.1 in the Ethernet 719 * Channel Engine manual (part of the PCIO manual). 720 * See also the STP2002-STQ document from Sun Microsystems. 721 */ 722 723 /* step 1 & 2. Reset the Ethernet Channel */ 724 gem_stop(ifp, 0); 725 gem_reset(sc); 726 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 727 728 /* Re-initialize the MIF */ 729 gem_mifinit(sc); 730 731 /* Call MI reset function if any */ 732 if (sc->sc_hwreset) 733 (*sc->sc_hwreset)(sc); 734 735 /* step 3. Setup data structures in host memory */ 736 gem_meminit(sc); 737 738 /* step 4. TX MAC registers & counters */ 739 gem_init_regs(sc); 740 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 741 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 742 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN + sizeof(struct ether_header): 743 ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16)); 744 745 /* step 5. RX MAC registers & counters */ 746 gem_setladrf(sc); 747 748 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 749 bus_space_write_8(t, h, GEM_TX_RING_PTR, 750 GEM_CDTXADDR(sc, 0)); 751 /* Yeeech. The following has endianness issues. */ 752 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 753 (((uint64_t)GEM_CDRXADDR(sc, 0))>>32)); 754 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, 755 GEM_CDRXADDR(sc, 0)); 756 757 /* step 8. Global Configuration & Interrupt Mask */ 758 bus_space_write_4(t, h, GEM_INTMASK, 759 ~(GEM_INTR_TX_INTME| 760 GEM_INTR_TX_EMPTY| 761 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 762 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 763 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 764 GEM_INTR_BERR)); 765 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 0); /* XXXX */ 766 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 767 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 768 #if 0 769 if (!sc->sc_pci) { 770 /* Config SBus */ 771 switch (sc->sc_burst) { 772 default: 773 v = 0; 774 break; 775 case 16: 776 v = GEM_SEB_CFG_BURST16; 777 break; 778 case 32: 779 v = GEM_SEB_CFG_BURST32; 780 break; 781 case 64: 782 v = GEM_SEB_CFG_BURST64; 783 break; 784 } 785 bus_space_write_4(t, seb, GEM_SEBI_CFG, 786 v|GE_SIOCFG_PARITY|GE_SIOCFG_BMODE64); 787 } 788 #endif 789 /* step 9. ETX Configuration: use mostly default values */ 790 791 /* Enable DMA */ 792 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 793 bus_space_write_4(t, h, GEM_TX_CONFIG, 794 v|GEM_TX_CONFIG_TXDMA_EN| 795 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 796 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 797 798 /* step 10. ERX Configuration */ 799 800 /* Encode Receive Descriptor ring size: four possible values */ 801 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 802 803 /* Enable DMA */ 804 bus_space_write_4(t, h, GEM_RX_CONFIG, 805 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 806 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 807 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 808 /* 809 * The following value is for an OFF Threshold of about 15.5 Kbytes 810 * and an ON Threshold of 4K bytes. 811 */ 812 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 0xf8 | (0x40 << 12)); 813 bus_space_write_4(t, h, GEM_RX_BLANKING, (2<<12)|6); 814 815 /* step 11. Configure Media */ 816 gem_mii_statchg(&sc->sc_dev); 817 818 /* XXXX Serial link needs a whole different setup. */ 819 820 821 /* step 12. RX_MAC Configuration Register */ 822 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 823 v |= GEM_MAC_RX_ENABLE; 824 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 825 826 /* step 14. Issue Transmit Pending command */ 827 828 /* Call MI initialization function if any */ 829 if (sc->sc_hwinit) 830 (*sc->sc_hwinit)(sc); 831 832 833 /* step 15. Give the reciever a swift kick */ 834 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 835 836 /* Start the one second timer. */ 837 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 838 839 ifp->if_flags |= IFF_RUNNING; 840 ifp->if_flags &= ~IFF_OACTIVE; 841 ifp->if_timer = 0; 842 splx(s); 843 844 return (0); 845 } 846 847 /* 848 * Compare two Ether/802 addresses for equality, inlined and unrolled for 849 * speed. 850 */ 851 static __inline__ int 852 ether_cmp(a, b) 853 u_char *a, *b; 854 { 855 856 if (a[5] != b[5] || a[4] != b[4] || a[3] != b[3] || 857 a[2] != b[2] || a[1] != b[1] || a[0] != b[0]) 858 return (0); 859 return (1); 860 } 861 862 863 void 864 gem_init_regs(struct gem_softc *sc) 865 { 866 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 867 bus_space_tag_t t = sc->sc_bustag; 868 bus_space_handle_t h = sc->sc_h; 869 870 /* These regs are not cleared on reset */ 871 sc->sc_inited = 0; 872 if (!sc->sc_inited) { 873 874 /* Wooo. Magic values. */ 875 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 876 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 877 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 878 879 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 880 /* Max frame and max burst size */ 881 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 882 (ifp->if_mtu+18) | (0x2000<<16)/* Burst size */); 883 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 884 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 885 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 886 /* Dunno.... */ 887 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 888 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 889 ((sc->sc_enaddr[5]<<8)|sc->sc_enaddr[4])&0x3ff); 890 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 891 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 892 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 893 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 894 /* MAC control addr set to 0:1:c2:0:1:80 */ 895 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 896 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 897 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 898 899 /* MAC filter addr set to 0:0:0:0:0:0 */ 900 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 901 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 902 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 903 904 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 905 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 906 907 sc->sc_inited = 1; 908 } 909 910 /* Counters need to be zeroed */ 911 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 912 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 913 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 914 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 915 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 916 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 917 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 918 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 919 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 920 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 921 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 922 923 /* Un-pause stuff */ 924 #if 0 925 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 926 #else 927 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 928 #endif 929 930 /* 931 * Set the station address. 932 */ 933 bus_space_write_4(t, h, GEM_MAC_ADDR0, 934 (sc->sc_enaddr[4]<<8) | sc->sc_enaddr[5]); 935 bus_space_write_4(t, h, GEM_MAC_ADDR1, 936 (sc->sc_enaddr[2]<<8) | sc->sc_enaddr[3]); 937 bus_space_write_4(t, h, GEM_MAC_ADDR2, 938 (sc->sc_enaddr[0]<<8) | sc->sc_enaddr[1]); 939 940 } 941 942 943 944 void 945 gem_start(ifp) 946 struct ifnet *ifp; 947 { 948 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 949 struct mbuf *m0, *m; 950 struct gem_txsoft *txs, *last_txs; 951 bus_dmamap_t dmamap; 952 int error, firsttx, nexttx, lasttx, ofree, seg; 953 954 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 955 return; 956 957 /* 958 * Remember the previous number of free descriptors and 959 * the first descriptor we'll use. 960 */ 961 ofree = sc->sc_txfree; 962 firsttx = sc->sc_txnext; 963 964 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 965 sc->sc_dev.dv_xname, ofree, firsttx)); 966 967 /* 968 * Loop through the send queue, setting up transmit descriptors 969 * until we drain the queue, or use up all available transmit 970 * descriptors. 971 */ 972 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 973 sc->sc_txfree != 0) { 974 /* 975 * Grab a packet off the queue. 976 */ 977 IFQ_POLL(&ifp->if_snd, m0); 978 if (m0 == NULL) 979 break; 980 m = NULL; 981 982 dmamap = txs->txs_dmamap; 983 984 /* 985 * Load the DMA map. If this fails, the packet either 986 * didn't fit in the alloted number of segments, or we were 987 * short on resources. In this case, we'll copy and try 988 * again. 989 */ 990 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 991 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 992 MGETHDR(m, M_DONTWAIT, MT_DATA); 993 if (m == NULL) { 994 printf("%s: unable to allocate Tx mbuf\n", 995 sc->sc_dev.dv_xname); 996 break; 997 } 998 if (m0->m_pkthdr.len > MHLEN) { 999 MCLGET(m, M_DONTWAIT); 1000 if ((m->m_flags & M_EXT) == 0) { 1001 printf("%s: unable to allocate Tx " 1002 "cluster\n", sc->sc_dev.dv_xname); 1003 m_freem(m); 1004 break; 1005 } 1006 } 1007 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1008 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1009 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1010 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1011 if (error) { 1012 printf("%s: unable to load Tx buffer, " 1013 "error = %d\n", sc->sc_dev.dv_xname, error); 1014 break; 1015 } 1016 } 1017 1018 /* 1019 * Ensure we have enough descriptors free to describe 1020 * the packet. 1021 */ 1022 if (dmamap->dm_nsegs > sc->sc_txfree) { 1023 /* 1024 * Not enough free descriptors to transmit this 1025 * packet. We haven't committed to anything yet, 1026 * so just unload the DMA map, put the packet 1027 * back on the queue, and punt. Notify the upper 1028 * layer that there are no more slots left. 1029 * 1030 * XXX We could allocate an mbuf and copy, but 1031 * XXX it is worth it? 1032 */ 1033 ifp->if_flags |= IFF_OACTIVE; 1034 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1035 if (m != NULL) 1036 m_freem(m); 1037 break; 1038 } 1039 1040 IFQ_DEQUEUE(&ifp->if_snd, m0); 1041 if (m != NULL) { 1042 m_freem(m0); 1043 m0 = m; 1044 } 1045 1046 /* 1047 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1048 */ 1049 1050 /* Sync the DMA map. */ 1051 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1052 BUS_DMASYNC_PREWRITE); 1053 1054 /* 1055 * Initialize the transmit descriptors. 1056 */ 1057 for (nexttx = sc->sc_txnext, seg = 0; 1058 seg < dmamap->dm_nsegs; 1059 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1060 uint64_t flags; 1061 1062 /* 1063 * If this is the first descriptor we're 1064 * enqueueing, set the start of packet flag, 1065 * and the checksum stuff if we want the hardware 1066 * to do it. 1067 */ 1068 sc->sc_txdescs[nexttx].gd_addr = 1069 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1070 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1071 if (nexttx == firsttx) { 1072 flags |= GEM_TD_START_OF_PACKET; 1073 } 1074 if (seg == dmamap->dm_nsegs - 1) { 1075 flags |= GEM_TD_END_OF_PACKET; 1076 } 1077 sc->sc_txdescs[nexttx].gd_flags = 1078 GEM_DMA_WRITE(sc, flags); 1079 lasttx = nexttx; 1080 } 1081 1082 #ifdef GEM_DEBUG 1083 if (ifp->if_flags & IFF_DEBUG) { 1084 printf(" gem_start %p transmit chain:\n", txs); 1085 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1086 printf("descriptor %d:\t", seg); 1087 printf("gd_flags: 0x%016llx\t", (long long) 1088 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1089 printf("gd_addr: 0x%016llx\n", (long long) 1090 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1091 if (seg == lasttx) 1092 break; 1093 } 1094 } 1095 #endif 1096 1097 /* Sync the descriptors we're using. */ 1098 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1099 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1100 1101 /* 1102 * Store a pointer to the packet so we can free it later, 1103 * and remember what txdirty will be once the packet is 1104 * done. 1105 */ 1106 txs->txs_mbuf = m0; 1107 txs->txs_firstdesc = sc->sc_txnext; 1108 txs->txs_lastdesc = lasttx; 1109 txs->txs_ndescs = dmamap->dm_nsegs; 1110 1111 /* Advance the tx pointer. */ 1112 sc->sc_txfree -= dmamap->dm_nsegs; 1113 sc->sc_txnext = nexttx; 1114 1115 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1116 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1117 1118 last_txs = txs; 1119 1120 #if NBPFILTER > 0 1121 /* 1122 * Pass the packet to any BPF listeners. 1123 */ 1124 if (ifp->if_bpf) 1125 bpf_mtap(ifp->if_bpf, m0); 1126 #endif /* NBPFILTER > 0 */ 1127 } 1128 1129 if (txs == NULL || sc->sc_txfree == 0) { 1130 /* No more slots left; notify upper layer. */ 1131 ifp->if_flags |= IFF_OACTIVE; 1132 } 1133 1134 if (sc->sc_txfree != ofree) { 1135 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1136 sc->sc_dev.dv_xname, lasttx, firsttx)); 1137 /* 1138 * The entire packet chain is set up. 1139 * Kick the transmitter. 1140 */ 1141 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1142 sc->sc_dev.dv_xname, nexttx)); 1143 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1144 sc->sc_txnext); 1145 1146 /* Set a watchdog timer in case the chip flakes out. */ 1147 ifp->if_timer = 5; 1148 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1149 sc->sc_dev.dv_xname, ifp->if_timer)); 1150 } 1151 } 1152 1153 /* 1154 * Transmit interrupt. 1155 */ 1156 int 1157 gem_tint(sc) 1158 struct gem_softc *sc; 1159 { 1160 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1161 bus_space_tag_t t = sc->sc_bustag; 1162 bus_space_handle_t mac = sc->sc_h; 1163 struct gem_txsoft *txs; 1164 int txlast; 1165 1166 1167 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1168 1169 /* 1170 * Unload collision counters 1171 */ 1172 ifp->if_collisions += 1173 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1174 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1175 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1176 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1177 1178 /* 1179 * then clear the hardware counters. 1180 */ 1181 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1182 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1183 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1184 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1185 1186 /* 1187 * Go through our Tx list and free mbufs for those 1188 * frames that have been transmitted. 1189 */ 1190 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1191 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1192 txs->txs_ndescs, 1193 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1194 1195 #ifdef GEM_DEBUG 1196 if (ifp->if_flags & IFF_DEBUG) { 1197 int i; 1198 printf(" txsoft %p transmit chain:\n", txs); 1199 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1200 printf("descriptor %d: ", i); 1201 printf("gd_flags: 0x%016llx\t", (long long) 1202 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1203 printf("gd_addr: 0x%016llx\n", (long long) 1204 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1205 if (i == txs->txs_lastdesc) 1206 break; 1207 } 1208 } 1209 #endif 1210 1211 /* 1212 * In theory, we could harveast some descriptors before 1213 * the ring is empty, but that's a bit complicated. 1214 * 1215 * GEM_TX_COMPLETION points to the last descriptor 1216 * processed +1. 1217 */ 1218 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1219 DPRINTF(sc, 1220 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1221 txs->txs_lastdesc, txlast)); 1222 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1223 if ((txlast >= txs->txs_firstdesc) && 1224 (txlast <= txs->txs_lastdesc)) 1225 break; 1226 } else { 1227 /* Ick -- this command wraps */ 1228 if ((txlast >= txs->txs_firstdesc) || 1229 (txlast <= txs->txs_lastdesc)) 1230 break; 1231 } 1232 1233 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1234 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1235 1236 sc->sc_txfree += txs->txs_ndescs; 1237 1238 if (txs->txs_mbuf == NULL) { 1239 #ifdef DIAGNOSTIC 1240 panic("gem_txintr: null mbuf"); 1241 #endif 1242 } 1243 1244 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1245 0, txs->txs_dmamap->dm_mapsize, 1246 BUS_DMASYNC_POSTWRITE); 1247 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1248 m_freem(txs->txs_mbuf); 1249 txs->txs_mbuf = NULL; 1250 1251 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1252 1253 ifp->if_opackets++; 1254 } 1255 1256 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1257 "GEM_TX_DATA_PTR %llx " 1258 "GEM_TX_COMPLETION %x\n", 1259 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1260 (long long)bus_space_read_8(sc->sc_bustag, sc->sc_h, 1261 GEM_TX_DATA_PTR), 1262 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1263 1264 gem_start(ifp); 1265 1266 if (SIMPLEQ_FIRST(&sc->sc_txdirtyq) == NULL) 1267 ifp->if_timer = 0; 1268 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1269 sc->sc_dev.dv_xname, ifp->if_timer)); 1270 1271 return (1); 1272 } 1273 1274 /* 1275 * Receive interrupt. 1276 */ 1277 int 1278 gem_rint(sc) 1279 struct gem_softc *sc; 1280 { 1281 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1282 bus_space_tag_t t = sc->sc_bustag; 1283 bus_space_handle_t h = sc->sc_h; 1284 struct ether_header *eh; 1285 struct gem_rxsoft *rxs; 1286 struct mbuf *m; 1287 u_int64_t rxstat; 1288 int i, len; 1289 1290 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1291 /* 1292 * XXXX Read the lastrx only once at the top for speed. 1293 */ 1294 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1295 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1296 for (i = sc->sc_rxptr; i != bus_space_read_4(t, h, GEM_RX_COMPLETION); 1297 i = GEM_NEXTRX(i)) { 1298 rxs = &sc->sc_rxsoft[i]; 1299 1300 GEM_CDRXSYNC(sc, i, 1301 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1302 1303 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1304 1305 if (rxstat & GEM_RD_OWN) { 1306 printf("gem_rint: completed descriptor " 1307 "still owned %d\n", i); 1308 /* 1309 * We have processed all of the receive buffers. 1310 */ 1311 break; 1312 } 1313 1314 if (rxstat & GEM_RD_BAD_CRC) { 1315 printf("%s: receive error: CRC error\n", 1316 sc->sc_dev.dv_xname); 1317 GEM_INIT_RXDESC(sc, i); 1318 continue; 1319 } 1320 1321 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1322 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1323 #ifdef GEM_DEBUG 1324 if (ifp->if_flags & IFF_DEBUG) { 1325 printf(" rxsoft %p descriptor %d: ", rxs, i); 1326 printf("gd_flags: 0x%016llx\t", (long long) 1327 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1328 printf("gd_addr: 0x%016llx\n", (long long) 1329 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1330 } 1331 #endif 1332 1333 /* 1334 * No errors; receive the packet. Note the Gem 1335 * includes the CRC with every packet. 1336 */ 1337 len = GEM_RD_BUFLEN(rxstat); 1338 1339 /* 1340 * Allocate a new mbuf cluster. If that fails, we are 1341 * out of memory, and must drop the packet and recycle 1342 * the buffer that's already attached to this descriptor. 1343 */ 1344 m = rxs->rxs_mbuf; 1345 if (gem_add_rxbuf(sc, i) != 0) { 1346 ifp->if_ierrors++; 1347 GEM_INIT_RXDESC(sc, i); 1348 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1349 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1350 continue; 1351 } 1352 m->m_data += 2; /* We're already off by two */ 1353 1354 ifp->if_ipackets++; 1355 eh = mtod(m, struct ether_header *); 1356 m->m_flags |= M_HASFCS; 1357 m->m_pkthdr.rcvif = ifp; 1358 m->m_pkthdr.len = m->m_len = len; 1359 1360 #if NBPFILTER > 0 1361 /* 1362 * Pass this up to any BPF listeners, but only 1363 * pass it up the stack if its for us. 1364 */ 1365 if (ifp->if_bpf) 1366 bpf_mtap(ifp->if_bpf, m); 1367 #endif /* NPBFILTER > 0 */ 1368 1369 #if 0 1370 /* 1371 * We sometimes have to run the 21140 in Hash-Only 1372 * mode. If we're in that mode, and not in promiscuous 1373 * mode, and we have a unicast packet that isn't for 1374 * us, then drop it. 1375 */ 1376 if (sc->sc_filtmode == TDCTL_Tx_FT_HASHONLY && 1377 (ifp->if_flags & IFF_PROMISC) == 0 && 1378 ETHER_IS_MULTICAST(eh->ether_dhost) == 0 && 1379 memcmp(LLADDR(ifp->if_sadl), eh->ether_dhost, 1380 ETHER_ADDR_LEN) != 0) { 1381 m_freem(m); 1382 continue; 1383 } 1384 #endif 1385 1386 /* Pass it on. */ 1387 (*ifp->if_input)(ifp, m); 1388 } 1389 1390 /* Update the receive pointer. */ 1391 sc->sc_rxptr = i; 1392 bus_space_write_4(t, h, GEM_RX_KICK, i); 1393 1394 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1395 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1396 1397 return (1); 1398 } 1399 1400 1401 /* 1402 * gem_add_rxbuf: 1403 * 1404 * Add a receive buffer to the indicated descriptor. 1405 */ 1406 int 1407 gem_add_rxbuf(struct gem_softc *sc, int idx) 1408 { 1409 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1410 struct mbuf *m; 1411 int error; 1412 1413 MGETHDR(m, M_DONTWAIT, MT_DATA); 1414 if (m == NULL) 1415 return (ENOBUFS); 1416 1417 MCLGET(m, M_DONTWAIT); 1418 if ((m->m_flags & M_EXT) == 0) { 1419 m_freem(m); 1420 return (ENOBUFS); 1421 } 1422 1423 #ifdef GEM_DEBUG 1424 /* bzero the packet to check dma */ 1425 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1426 #endif 1427 1428 if (rxs->rxs_mbuf != NULL) 1429 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1430 1431 rxs->rxs_mbuf = m; 1432 1433 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1434 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1435 BUS_DMA_READ|BUS_DMA_NOWAIT); 1436 if (error) { 1437 printf("%s: can't load rx DMA map %d, error = %d\n", 1438 sc->sc_dev.dv_xname, idx, error); 1439 panic("gem_add_rxbuf"); /* XXX */ 1440 } 1441 1442 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1443 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1444 1445 GEM_INIT_RXDESC(sc, idx); 1446 1447 return (0); 1448 } 1449 1450 1451 int 1452 gem_eint(sc, status) 1453 struct gem_softc *sc; 1454 u_int status; 1455 { 1456 char bits[128]; 1457 1458 if ((status & GEM_INTR_MIF) != 0) { 1459 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1460 return (1); 1461 } 1462 1463 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1464 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1465 return (1); 1466 } 1467 1468 1469 int 1470 gem_intr(v) 1471 void *v; 1472 { 1473 struct gem_softc *sc = (struct gem_softc *)v; 1474 bus_space_tag_t t = sc->sc_bustag; 1475 bus_space_handle_t seb = sc->sc_h; 1476 u_int32_t status; 1477 int r = 0; 1478 #ifdef GEM_DEBUG 1479 char bits[128]; 1480 #endif 1481 1482 status = bus_space_read_4(t, seb, GEM_STATUS); 1483 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %s\n", 1484 sc->sc_dev.dv_xname, (status>>19), 1485 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1486 1487 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1488 r |= gem_eint(sc, status); 1489 1490 if ((status & 1491 (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) 1492 != 0) 1493 r |= gem_tint(sc); 1494 1495 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1496 r |= gem_rint(sc); 1497 1498 /* We should eventually do more than just print out error stats. */ 1499 if (status & GEM_INTR_TX_MAC) { 1500 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1501 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1502 printf("MAC tx fault, status %x\n", txstat); 1503 } 1504 if (status & GEM_INTR_RX_MAC) { 1505 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1506 if (rxstat & ~GEM_MAC_RX_DONE) 1507 printf("MAC rx fault, status %x\n", rxstat); 1508 } 1509 return (r); 1510 } 1511 1512 1513 void 1514 gem_watchdog(ifp) 1515 struct ifnet *ifp; 1516 { 1517 struct gem_softc *sc = ifp->if_softc; 1518 1519 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1520 "GEM_MAC_RX_CONFIG %x\n", 1521 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1522 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1523 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1524 1525 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1526 ++ifp->if_oerrors; 1527 1528 /* Try to get more packets going. */ 1529 gem_start(ifp); 1530 } 1531 1532 /* 1533 * Initialize the MII Management Interface 1534 */ 1535 void 1536 gem_mifinit(sc) 1537 struct gem_softc *sc; 1538 { 1539 bus_space_tag_t t = sc->sc_bustag; 1540 bus_space_handle_t mif = sc->sc_h; 1541 1542 /* Configure the MIF in frame mode */ 1543 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1544 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1545 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1546 } 1547 1548 /* 1549 * MII interface 1550 * 1551 * The GEM MII interface supports at least three different operating modes: 1552 * 1553 * Bitbang mode is implemented using data, clock and output enable registers. 1554 * 1555 * Frame mode is implemented by loading a complete frame into the frame 1556 * register and polling the valid bit for completion. 1557 * 1558 * Polling mode uses the frame register but completion is indicated by 1559 * an interrupt. 1560 * 1561 */ 1562 static int 1563 gem_mii_readreg(self, phy, reg) 1564 struct device *self; 1565 int phy, reg; 1566 { 1567 struct gem_softc *sc = (void *)self; 1568 bus_space_tag_t t = sc->sc_bustag; 1569 bus_space_handle_t mif = sc->sc_h; 1570 int n; 1571 u_int32_t v; 1572 1573 #ifdef GEM_DEBUG1 1574 if (sc->sc_debug) 1575 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1576 #endif 1577 1578 #if 0 1579 /* Select the desired PHY in the MIF configuration register */ 1580 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1581 /* Clear PHY select bit */ 1582 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1583 if (phy == GEM_PHYAD_EXTERNAL) 1584 /* Set PHY select bit to get at external device */ 1585 v |= GEM_MIF_CONFIG_PHY_SEL; 1586 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1587 #endif 1588 1589 /* Construct the frame command */ 1590 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1591 GEM_MIF_FRAME_READ; 1592 1593 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1594 for (n = 0; n < 100; n++) { 1595 DELAY(1); 1596 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1597 if (v & GEM_MIF_FRAME_TA0) 1598 return (v & GEM_MIF_FRAME_DATA); 1599 } 1600 1601 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1602 return (0); 1603 } 1604 1605 static void 1606 gem_mii_writereg(self, phy, reg, val) 1607 struct device *self; 1608 int phy, reg, val; 1609 { 1610 struct gem_softc *sc = (void *)self; 1611 bus_space_tag_t t = sc->sc_bustag; 1612 bus_space_handle_t mif = sc->sc_h; 1613 int n; 1614 u_int32_t v; 1615 1616 #ifdef GEM_DEBUG1 1617 if (sc->sc_debug) 1618 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1619 phy, reg, val); 1620 #endif 1621 1622 #if 0 1623 /* Select the desired PHY in the MIF configuration register */ 1624 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1625 /* Clear PHY select bit */ 1626 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1627 if (phy == GEM_PHYAD_EXTERNAL) 1628 /* Set PHY select bit to get at external device */ 1629 v |= GEM_MIF_CONFIG_PHY_SEL; 1630 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1631 #endif 1632 /* Construct the frame command */ 1633 v = GEM_MIF_FRAME_WRITE | 1634 (phy << GEM_MIF_PHY_SHIFT) | 1635 (reg << GEM_MIF_REG_SHIFT) | 1636 (val & GEM_MIF_FRAME_DATA); 1637 1638 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1639 for (n = 0; n < 100; n++) { 1640 DELAY(1); 1641 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1642 if (v & GEM_MIF_FRAME_TA0) 1643 return; 1644 } 1645 1646 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1647 } 1648 1649 static void 1650 gem_mii_statchg(dev) 1651 struct device *dev; 1652 { 1653 struct gem_softc *sc = (void *)dev; 1654 #ifdef GEM_DEBUG 1655 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1656 #endif 1657 bus_space_tag_t t = sc->sc_bustag; 1658 bus_space_handle_t mac = sc->sc_h; 1659 u_int32_t v; 1660 1661 #ifdef GEM_DEBUG 1662 if (sc->sc_debug) 1663 printf("gem_mii_statchg: status change: phy = %d\n", 1664 sc->sc_phys[instance];); 1665 #endif 1666 1667 1668 /* Set tx full duplex options */ 1669 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1670 delay(10000); /* reg must be cleared and delay before changing. */ 1671 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1672 GEM_MAC_TX_ENABLE; 1673 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1674 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1675 } 1676 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1677 1678 /* XIF Configuration */ 1679 /* We should really calculate all this rather than rely on defaults */ 1680 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1681 v = GEM_MAC_XIF_LINK_LED; 1682 v |= GEM_MAC_XIF_TX_MII_ENA; 1683 /* If an external transceiver is connected, enable its MII drivers */ 1684 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1685 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1686 /* External MII needs echo disable if half duplex. */ 1687 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1688 /* turn on full duplex LED */ 1689 v |= GEM_MAC_XIF_FDPLX_LED; 1690 else 1691 /* half duplex -- disable echo */ 1692 v |= GEM_MAC_XIF_ECHO_DISABL; 1693 } else 1694 /* Internal MII needs buf enable */ 1695 v |= GEM_MAC_XIF_MII_BUF_ENA; 1696 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1697 } 1698 1699 int 1700 gem_mediachange(ifp) 1701 struct ifnet *ifp; 1702 { 1703 struct gem_softc *sc = ifp->if_softc; 1704 1705 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1706 return (EINVAL); 1707 1708 return (mii_mediachg(&sc->sc_mii)); 1709 } 1710 1711 void 1712 gem_mediastatus(ifp, ifmr) 1713 struct ifnet *ifp; 1714 struct ifmediareq *ifmr; 1715 { 1716 struct gem_softc *sc = ifp->if_softc; 1717 1718 if ((ifp->if_flags & IFF_UP) == 0) 1719 return; 1720 1721 mii_pollstat(&sc->sc_mii); 1722 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1723 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1724 } 1725 1726 int gem_ioctldebug = 0; 1727 /* 1728 * Process an ioctl request. 1729 */ 1730 int 1731 gem_ioctl(ifp, cmd, data) 1732 struct ifnet *ifp; 1733 u_long cmd; 1734 caddr_t data; 1735 { 1736 struct gem_softc *sc = ifp->if_softc; 1737 struct ifreq *ifr = (struct ifreq *)data; 1738 int s, error = 0; 1739 1740 1741 switch (cmd) { 1742 case SIOCGIFMEDIA: 1743 case SIOCSIFMEDIA: 1744 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1745 break; 1746 1747 default: 1748 error = ether_ioctl(ifp, cmd, data); 1749 if (error == ENETRESET) { 1750 /* 1751 * Multicast list has changed; set the hardware filter 1752 * accordingly. 1753 */ 1754 if (gem_ioctldebug) printf("reset1\n"); 1755 gem_init(ifp); 1756 delay(50000); 1757 error = 0; 1758 } 1759 break; 1760 } 1761 1762 /* Try to get things going again */ 1763 if (ifp->if_flags & IFF_UP) { 1764 if (gem_ioctldebug) printf("start\n"); 1765 gem_start(ifp); 1766 } 1767 splx(s); 1768 return (error); 1769 } 1770 1771 1772 void 1773 gem_shutdown(arg) 1774 void *arg; 1775 { 1776 struct gem_softc *sc = (struct gem_softc *)arg; 1777 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1778 1779 gem_stop(ifp, 1); 1780 } 1781 1782 /* 1783 * Set up the logical address filter. 1784 */ 1785 void 1786 gem_setladrf(sc) 1787 struct gem_softc *sc; 1788 { 1789 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1790 struct ether_multi *enm; 1791 struct ether_multistep step; 1792 struct ethercom *ec = &sc->sc_ethercom; 1793 bus_space_tag_t t = sc->sc_bustag; 1794 bus_space_handle_t h = sc->sc_h; 1795 u_char *cp; 1796 u_int32_t crc; 1797 u_int32_t hash[16]; 1798 u_int32_t v; 1799 int len; 1800 1801 /* Clear hash table */ 1802 memset(hash, 0, sizeof(hash)); 1803 1804 /* Get current RX configuration */ 1805 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1806 1807 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1808 /* Turn on promiscuous mode; turn off the hash filter */ 1809 v |= GEM_MAC_RX_PROMISCUOUS; 1810 v &= ~GEM_MAC_RX_HASH_FILTER; 1811 ifp->if_flags |= IFF_ALLMULTI; 1812 goto chipit; 1813 } 1814 1815 /* Turn off promiscuous mode; turn on the hash filter */ 1816 v &= ~GEM_MAC_RX_PROMISCUOUS; 1817 v |= GEM_MAC_RX_HASH_FILTER; 1818 1819 /* 1820 * Set up multicast address filter by passing all multicast addresses 1821 * through a crc generator, and then using the high order 6 bits as an 1822 * index into the 256 bit logical address filter. The high order bit 1823 * selects the word, while the rest of the bits select the bit within 1824 * the word. 1825 */ 1826 1827 ETHER_FIRST_MULTI(step, ec, enm); 1828 while (enm != NULL) { 1829 if (ether_cmp(enm->enm_addrlo, enm->enm_addrhi)) { 1830 /* 1831 * We must listen to a range of multicast addresses. 1832 * For now, just accept all multicasts, rather than 1833 * trying to set only those filter bits needed to match 1834 * the range. (At this time, the only use of address 1835 * ranges is for IP multicast routing, for which the 1836 * range is big enough to require all bits set.) 1837 */ 1838 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1839 ifp->if_flags |= IFF_ALLMULTI; 1840 goto chipit; 1841 } 1842 1843 cp = enm->enm_addrlo; 1844 crc = 0xffffffff; 1845 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1846 int octet = *cp++; 1847 int i; 1848 1849 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1850 for (i = 0; i < 8; i++) { 1851 if ((crc & 1) ^ (octet & 1)) { 1852 crc >>= 1; 1853 crc ^= MC_POLY_LE; 1854 } else { 1855 crc >>= 1; 1856 } 1857 octet >>= 1; 1858 } 1859 } 1860 /* Just want the 8 most significant bits. */ 1861 crc >>= 24; 1862 1863 /* Set the corresponding bit in the filter. */ 1864 hash[crc >> 4] |= 1 << (crc & 0xf); 1865 1866 ETHER_NEXT_MULTI(step, enm); 1867 } 1868 1869 ifp->if_flags &= ~IFF_ALLMULTI; 1870 1871 chipit: 1872 /* Now load the hash table into the chip */ 1873 bus_space_write_4(t, h, GEM_MAC_HASH0, hash[0]); 1874 bus_space_write_4(t, h, GEM_MAC_HASH1, hash[1]); 1875 bus_space_write_4(t, h, GEM_MAC_HASH2, hash[2]); 1876 bus_space_write_4(t, h, GEM_MAC_HASH3, hash[3]); 1877 bus_space_write_4(t, h, GEM_MAC_HASH4, hash[4]); 1878 bus_space_write_4(t, h, GEM_MAC_HASH5, hash[5]); 1879 bus_space_write_4(t, h, GEM_MAC_HASH6, hash[6]); 1880 bus_space_write_4(t, h, GEM_MAC_HASH7, hash[7]); 1881 bus_space_write_4(t, h, GEM_MAC_HASH8, hash[8]); 1882 bus_space_write_4(t, h, GEM_MAC_HASH9, hash[9]); 1883 bus_space_write_4(t, h, GEM_MAC_HASH10, hash[10]); 1884 bus_space_write_4(t, h, GEM_MAC_HASH11, hash[11]); 1885 bus_space_write_4(t, h, GEM_MAC_HASH12, hash[12]); 1886 bus_space_write_4(t, h, GEM_MAC_HASH13, hash[13]); 1887 bus_space_write_4(t, h, GEM_MAC_HASH14, hash[14]); 1888 bus_space_write_4(t, h, GEM_MAC_HASH15, hash[15]); 1889 1890 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1891 } 1892 1893 #if notyet 1894 1895 /* 1896 * gem_power: 1897 * 1898 * Power management (suspend/resume) hook. 1899 */ 1900 void 1901 gem_power(why, arg) 1902 int why; 1903 void *arg; 1904 { 1905 struct gem_softc *sc = arg; 1906 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1907 int s; 1908 1909 s = splnet(); 1910 switch (why) { 1911 case PWR_SUSPEND: 1912 case PWR_STANDBY: 1913 gem_stop(ifp, 1); 1914 if (sc->sc_power != NULL) 1915 (*sc->sc_power)(sc, why); 1916 break; 1917 case PWR_RESUME: 1918 if (ifp->if_flags & IFF_UP) { 1919 if (sc->sc_power != NULL) 1920 (*sc->sc_power)(sc, why); 1921 gem_init(ifp); 1922 } 1923 break; 1924 case PWR_SOFTSUSPEND: 1925 case PWR_SOFTSTANDBY: 1926 case PWR_SOFTRESUME: 1927 break; 1928 } 1929 splx(s); 1930 } 1931 #endif 1932