1 /* $NetBSD: gem.c,v 1.108 2017/02/20 07:43:29 ozaki-r Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.108 2017/02/20 07:43:29 ozaki-r Exp $"); 41 42 #include "opt_inet.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/callout.h> 47 #include <sys/mbuf.h> 48 #include <sys/syslog.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/device.h> 55 56 #include <machine/endian.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #include <net/bpf.h> 73 74 #include <sys/bus.h> 75 #include <sys/intr.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/ic/gemreg.h> 82 #include <dev/ic/gemvar.h> 83 84 #define TRIES 10000 85 86 static void gem_inten(struct gem_softc *); 87 static void gem_start(struct ifnet *); 88 static void gem_stop(struct ifnet *, int); 89 int gem_ioctl(struct ifnet *, u_long, void *); 90 void gem_tick(void *); 91 void gem_watchdog(struct ifnet *); 92 void gem_rx_watchdog(void *); 93 void gem_pcs_start(struct gem_softc *sc); 94 void gem_pcs_stop(struct gem_softc *sc, int); 95 int gem_init(struct ifnet *); 96 void gem_init_regs(struct gem_softc *sc); 97 static int gem_ringsize(int sz); 98 static int gem_meminit(struct gem_softc *); 99 void gem_mifinit(struct gem_softc *); 100 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 101 u_int32_t, u_int32_t); 102 void gem_reset(struct gem_softc *); 103 int gem_reset_rx(struct gem_softc *sc); 104 static void gem_reset_rxdma(struct gem_softc *sc); 105 static void gem_rx_common(struct gem_softc *sc); 106 int gem_reset_tx(struct gem_softc *sc); 107 int gem_disable_rx(struct gem_softc *sc); 108 int gem_disable_tx(struct gem_softc *sc); 109 static void gem_rxdrain(struct gem_softc *sc); 110 int gem_add_rxbuf(struct gem_softc *sc, int idx); 111 void gem_setladrf(struct gem_softc *); 112 113 /* MII methods & callbacks */ 114 static int gem_mii_readreg(device_t, int, int); 115 static void gem_mii_writereg(device_t, int, int, int); 116 static void gem_mii_statchg(struct ifnet *); 117 118 static int gem_ifflags_cb(struct ethercom *); 119 120 void gem_statuschange(struct gem_softc *); 121 122 int gem_ser_mediachange(struct ifnet *); 123 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 124 125 static void gem_partial_detach(struct gem_softc *, enum gem_attach_stage); 126 127 struct mbuf *gem_get(struct gem_softc *, int, int); 128 int gem_put(struct gem_softc *, int, struct mbuf *); 129 void gem_read(struct gem_softc *, int, int); 130 int gem_pint(struct gem_softc *); 131 int gem_eint(struct gem_softc *, u_int); 132 int gem_rint(struct gem_softc *); 133 int gem_tint(struct gem_softc *); 134 void gem_power(int, void *); 135 136 #ifdef GEM_DEBUG 137 static void gem_txsoft_print(const struct gem_softc *, int, int); 138 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 139 printf x 140 #else 141 #define DPRINTF(sc, x) /* nothing */ 142 #endif 143 144 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 145 146 int 147 gem_detach(struct gem_softc *sc, int flags) 148 { 149 int i; 150 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 151 bus_space_tag_t t = sc->sc_bustag; 152 bus_space_handle_t h = sc->sc_h1; 153 154 /* 155 * Free any resources we've allocated during the attach. 156 * Do this in reverse order and fall through. 157 */ 158 switch (sc->sc_att_stage) { 159 case GEM_ATT_BACKEND_2: 160 case GEM_ATT_BACKEND_1: 161 case GEM_ATT_FINISHED: 162 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 163 gem_stop(&sc->sc_ethercom.ec_if, 1); 164 165 #ifdef GEM_COUNTERS 166 for (i = __arraycount(sc->sc_ev_rxhist); --i >= 0; ) 167 evcnt_detach(&sc->sc_ev_rxhist[i]); 168 evcnt_detach(&sc->sc_ev_rxnobuf); 169 evcnt_detach(&sc->sc_ev_rxfull); 170 evcnt_detach(&sc->sc_ev_rxint); 171 evcnt_detach(&sc->sc_ev_txint); 172 #endif 173 evcnt_detach(&sc->sc_ev_intr); 174 175 rnd_detach_source(&sc->rnd_source); 176 ether_ifdetach(ifp); 177 if_detach(ifp); 178 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 179 180 callout_destroy(&sc->sc_tick_ch); 181 callout_destroy(&sc->sc_rx_watchdog); 182 183 /*FALLTHROUGH*/ 184 case GEM_ATT_MII: 185 sc->sc_att_stage = GEM_ATT_MII; 186 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 187 /*FALLTHROUGH*/ 188 case GEM_ATT_7: 189 for (i = 0; i < GEM_NRXDESC; i++) { 190 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 191 bus_dmamap_destroy(sc->sc_dmatag, 192 sc->sc_rxsoft[i].rxs_dmamap); 193 } 194 /*FALLTHROUGH*/ 195 case GEM_ATT_6: 196 for (i = 0; i < GEM_TXQUEUELEN; i++) { 197 if (sc->sc_txsoft[i].txs_dmamap != NULL) 198 bus_dmamap_destroy(sc->sc_dmatag, 199 sc->sc_txsoft[i].txs_dmamap); 200 } 201 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 202 /*FALLTHROUGH*/ 203 case GEM_ATT_5: 204 bus_dmamap_unload(sc->sc_dmatag, sc->sc_nulldmamap); 205 /*FALLTHROUGH*/ 206 case GEM_ATT_4: 207 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 208 /*FALLTHROUGH*/ 209 case GEM_ATT_3: 210 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 211 /*FALLTHROUGH*/ 212 case GEM_ATT_2: 213 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 214 sizeof(struct gem_control_data)); 215 /*FALLTHROUGH*/ 216 case GEM_ATT_1: 217 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 218 /*FALLTHROUGH*/ 219 case GEM_ATT_0: 220 sc->sc_att_stage = GEM_ATT_0; 221 /*FALLTHROUGH*/ 222 case GEM_ATT_BACKEND_0: 223 break; 224 } 225 return 0; 226 } 227 228 static void 229 gem_partial_detach(struct gem_softc *sc, enum gem_attach_stage stage) 230 { 231 cfattach_t ca = device_cfattach(sc->sc_dev); 232 233 sc->sc_att_stage = stage; 234 (*ca->ca_detach)(sc->sc_dev, 0); 235 } 236 237 /* 238 * gem_attach: 239 * 240 * Attach a Gem interface to the system. 241 */ 242 void 243 gem_attach(struct gem_softc *sc, const uint8_t *enaddr) 244 { 245 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 246 struct mii_data *mii = &sc->sc_mii; 247 bus_space_tag_t t = sc->sc_bustag; 248 bus_space_handle_t h = sc->sc_h1; 249 struct ifmedia_entry *ifm; 250 int i, error, phyaddr; 251 u_int32_t v; 252 char *nullbuf; 253 254 /* Make sure the chip is stopped. */ 255 ifp->if_softc = sc; 256 gem_reset(sc); 257 258 /* 259 * Allocate the control data structures, and create and load the 260 * DMA map for it. gem_control_data is 9216 bytes, we have space for 261 * the padding buffer in the bus_dmamem_alloc()'d memory. 262 */ 263 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 264 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 265 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 266 aprint_error_dev(sc->sc_dev, 267 "unable to allocate control data, error = %d\n", 268 error); 269 gem_partial_detach(sc, GEM_ATT_0); 270 return; 271 } 272 273 /* XXX should map this in with correct endianness */ 274 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 275 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 276 BUS_DMA_COHERENT)) != 0) { 277 aprint_error_dev(sc->sc_dev, 278 "unable to map control data, error = %d\n", error); 279 gem_partial_detach(sc, GEM_ATT_1); 280 return; 281 } 282 283 nullbuf = 284 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 285 286 if ((error = bus_dmamap_create(sc->sc_dmatag, 287 sizeof(struct gem_control_data), 1, 288 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 289 aprint_error_dev(sc->sc_dev, 290 "unable to create control data DMA map, error = %d\n", 291 error); 292 gem_partial_detach(sc, GEM_ATT_2); 293 return; 294 } 295 296 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 297 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 298 0)) != 0) { 299 aprint_error_dev(sc->sc_dev, 300 "unable to load control data DMA map, error = %d\n", 301 error); 302 gem_partial_detach(sc, GEM_ATT_3); 303 return; 304 } 305 306 memset(nullbuf, 0, ETHER_MIN_TX); 307 if ((error = bus_dmamap_create(sc->sc_dmatag, 308 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 309 aprint_error_dev(sc->sc_dev, 310 "unable to create padding DMA map, error = %d\n", error); 311 gem_partial_detach(sc, GEM_ATT_4); 312 return; 313 } 314 315 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 316 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 317 aprint_error_dev(sc->sc_dev, 318 "unable to load padding DMA map, error = %d\n", error); 319 gem_partial_detach(sc, GEM_ATT_5); 320 return; 321 } 322 323 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 324 BUS_DMASYNC_PREWRITE); 325 326 /* 327 * Initialize the transmit job descriptors. 328 */ 329 SIMPLEQ_INIT(&sc->sc_txfreeq); 330 SIMPLEQ_INIT(&sc->sc_txdirtyq); 331 332 /* 333 * Create the transmit buffer DMA maps. 334 */ 335 for (i = 0; i < GEM_TXQUEUELEN; i++) { 336 struct gem_txsoft *txs; 337 338 txs = &sc->sc_txsoft[i]; 339 txs->txs_mbuf = NULL; 340 if ((error = bus_dmamap_create(sc->sc_dmatag, 341 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 342 ETHER_MAX_LEN_JUMBO, 0, 0, 343 &txs->txs_dmamap)) != 0) { 344 aprint_error_dev(sc->sc_dev, 345 "unable to create tx DMA map %d, error = %d\n", 346 i, error); 347 gem_partial_detach(sc, GEM_ATT_6); 348 return; 349 } 350 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 351 } 352 353 /* 354 * Create the receive buffer DMA maps. 355 */ 356 for (i = 0; i < GEM_NRXDESC; i++) { 357 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 358 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 359 aprint_error_dev(sc->sc_dev, 360 "unable to create rx DMA map %d, error = %d\n", 361 i, error); 362 gem_partial_detach(sc, GEM_ATT_7); 363 return; 364 } 365 sc->sc_rxsoft[i].rxs_mbuf = NULL; 366 } 367 368 /* Initialize ifmedia structures and MII info */ 369 mii->mii_ifp = ifp; 370 mii->mii_readreg = gem_mii_readreg; 371 mii->mii_writereg = gem_mii_writereg; 372 mii->mii_statchg = gem_mii_statchg; 373 374 sc->sc_ethercom.ec_mii = mii; 375 376 /* 377 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 378 * Section 3.2.1 `Initialization Sequence'. 379 * However, we can't assume SERDES or Serialink if neither 380 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 381 * being set, as both are set on Sun X1141A (with SERDES). So, 382 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 383 * Also, for variants that report 2 PHY's, we prefer the external 384 * PHY over the internal PHY, so we look for that first. 385 */ 386 gem_mifinit(sc); 387 388 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 389 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 390 ether_mediastatus); 391 /* Look for external PHY */ 392 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 393 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 394 bus_space_write_4(t, h, GEM_MIF_CONFIG, 395 sc->sc_mif_config); 396 switch (sc->sc_variant) { 397 case GEM_SUN_ERI: 398 phyaddr = GEM_PHYAD_EXTERNAL; 399 break; 400 default: 401 phyaddr = MII_PHY_ANY; 402 break; 403 } 404 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 405 MII_OFFSET_ANY, MIIF_FORCEANEG); 406 } 407 #ifdef GEM_DEBUG 408 else 409 aprint_debug_dev(sc->sc_dev, "using external PHY\n"); 410 #endif 411 /* Look for internal PHY if no external PHY was found */ 412 if (LIST_EMPTY(&mii->mii_phys) && 413 sc->sc_mif_config & GEM_MIF_CONFIG_MDI0) { 414 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 415 bus_space_write_4(t, h, GEM_MIF_CONFIG, 416 sc->sc_mif_config); 417 switch (sc->sc_variant) { 418 case GEM_SUN_ERI: 419 case GEM_APPLE_K2_GMAC: 420 phyaddr = GEM_PHYAD_INTERNAL; 421 break; 422 case GEM_APPLE_GMAC: 423 phyaddr = GEM_PHYAD_EXTERNAL; 424 break; 425 default: 426 phyaddr = MII_PHY_ANY; 427 break; 428 } 429 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 430 MII_OFFSET_ANY, MIIF_FORCEANEG); 431 #ifdef GEM_DEBUG 432 if (!LIST_EMPTY(&mii->mii_phys)) 433 aprint_debug_dev(sc->sc_dev, 434 "using internal PHY\n"); 435 #endif 436 } 437 if (LIST_EMPTY(&mii->mii_phys)) { 438 /* No PHY attached */ 439 aprint_error_dev(sc->sc_dev, 440 "PHY probe failed\n"); 441 gem_partial_detach(sc, GEM_ATT_MII); 442 return; 443 } else { 444 struct mii_softc *child; 445 446 /* 447 * Walk along the list of attached MII devices and 448 * establish an `MII instance' to `PHY number' 449 * mapping. 450 */ 451 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 452 /* 453 * Note: we support just one PHY: the internal 454 * or external MII is already selected for us 455 * by the GEM_MIF_CONFIG register. 456 */ 457 if (child->mii_phy > 1 || child->mii_inst > 0) { 458 aprint_error_dev(sc->sc_dev, 459 "cannot accommodate MII device" 460 " %s at PHY %d, instance %d\n", 461 device_xname(child->mii_dev), 462 child->mii_phy, child->mii_inst); 463 continue; 464 } 465 sc->sc_phys[child->mii_inst] = child->mii_phy; 466 } 467 468 if (sc->sc_variant != GEM_SUN_ERI) 469 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 470 GEM_MII_DATAPATH_MII); 471 472 /* 473 * XXX - we can really do the following ONLY if the 474 * PHY indeed has the auto negotiation capability!! 475 */ 476 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 477 } 478 } else { 479 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 480 gem_ser_mediastatus); 481 /* SERDES or Serialink */ 482 if (sc->sc_flags & GEM_SERDES) { 483 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 484 GEM_MII_DATAPATH_SERDES); 485 } else { 486 sc->sc_flags |= GEM_SERIAL; 487 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 488 GEM_MII_DATAPATH_SERIAL); 489 } 490 491 aprint_normal_dev(sc->sc_dev, "using external PCS %s: ", 492 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 493 494 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL); 495 /* Check for FDX and HDX capabilities */ 496 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 497 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 498 ifmedia_add(&sc->sc_mii.mii_media, 499 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL); 500 aprint_normal("1000baseSX-FDX, "); 501 } 502 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 503 ifmedia_add(&sc->sc_mii.mii_media, 504 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL); 505 aprint_normal("1000baseSX-HDX, "); 506 } 507 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 508 sc->sc_mii_media = IFM_AUTO; 509 aprint_normal("auto\n"); 510 511 gem_pcs_stop(sc, 1); 512 } 513 514 /* 515 * From this point forward, the attachment cannot fail. A failure 516 * before this point releases all resources that may have been 517 * allocated. 518 */ 519 520 /* Announce ourselves. */ 521 aprint_normal_dev(sc->sc_dev, "Ethernet address %s", 522 ether_sprintf(enaddr)); 523 524 /* Get RX FIFO size */ 525 sc->sc_rxfifosize = 64 * 526 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 527 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 528 529 /* Get TX FIFO size */ 530 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 531 aprint_normal(", %uKB TX fifo\n", v / 16); 532 533 /* Initialize ifnet structure. */ 534 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 535 ifp->if_softc = sc; 536 ifp->if_flags = 537 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 538 sc->sc_if_flags = ifp->if_flags; 539 #if 0 540 /* 541 * The GEM hardware supports basic TCP checksum offloading only. 542 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 543 * have bugs in the receive checksum, so don't enable it for now. 544 */ 545 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 546 (GEM_IS_APPLE(sc) && 547 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 548 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 549 #endif 550 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 551 ifp->if_start = gem_start; 552 ifp->if_ioctl = gem_ioctl; 553 ifp->if_watchdog = gem_watchdog; 554 ifp->if_stop = gem_stop; 555 ifp->if_init = gem_init; 556 IFQ_SET_READY(&ifp->if_snd); 557 558 /* 559 * If we support GigE media, we support jumbo frames too. 560 * Unless we are Apple. 561 */ 562 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 563 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 564 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 565 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 566 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 567 if (!GEM_IS_APPLE(sc)) 568 sc->sc_ethercom.ec_capabilities 569 |= ETHERCAP_JUMBO_MTU; 570 sc->sc_flags |= GEM_GIGABIT; 571 break; 572 } 573 } 574 575 /* claim 802.1q capability */ 576 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 577 578 /* Attach the interface. */ 579 if_attach(ifp); 580 if_deferred_start_init(ifp, NULL); 581 ether_ifattach(ifp, enaddr); 582 ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb); 583 584 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 585 RND_TYPE_NET, RND_FLAG_DEFAULT); 586 587 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 588 NULL, device_xname(sc->sc_dev), "interrupts"); 589 #ifdef GEM_COUNTERS 590 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 591 &sc->sc_ev_intr, device_xname(sc->sc_dev), "tx interrupts"); 592 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 593 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rx interrupts"); 594 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 595 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx ring full"); 596 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 597 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx malloc failure"); 598 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 599 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 0desc"); 600 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 601 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 1desc"); 602 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 603 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 2desc"); 604 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 605 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 3desc"); 606 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 607 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >3desc"); 608 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 609 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >7desc"); 610 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 611 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >15desc"); 612 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 613 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >31desc"); 614 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 615 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >63desc"); 616 #endif 617 618 callout_init(&sc->sc_tick_ch, 0); 619 callout_init(&sc->sc_rx_watchdog, 0); 620 callout_setfunc(&sc->sc_rx_watchdog, gem_rx_watchdog, sc); 621 622 sc->sc_att_stage = GEM_ATT_FINISHED; 623 624 return; 625 } 626 627 void 628 gem_tick(void *arg) 629 { 630 struct gem_softc *sc = arg; 631 int s; 632 633 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 634 /* 635 * We have to reset everything if we failed to get a 636 * PCS interrupt. Restarting the callout is handled 637 * in gem_pcs_start(). 638 */ 639 gem_init(&sc->sc_ethercom.ec_if); 640 } else { 641 s = splnet(); 642 mii_tick(&sc->sc_mii); 643 splx(s); 644 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 645 } 646 } 647 648 static int 649 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, u_int32_t clr, u_int32_t set) 650 { 651 int i; 652 u_int32_t reg; 653 654 for (i = TRIES; i--; DELAY(100)) { 655 reg = bus_space_read_4(sc->sc_bustag, h, r); 656 if ((reg & clr) == 0 && (reg & set) == set) 657 return (1); 658 } 659 return (0); 660 } 661 662 void 663 gem_reset(struct gem_softc *sc) 664 { 665 bus_space_tag_t t = sc->sc_bustag; 666 bus_space_handle_t h = sc->sc_h2; 667 int s; 668 669 s = splnet(); 670 DPRINTF(sc, ("%s: gem_reset\n", device_xname(sc->sc_dev))); 671 gem_reset_rx(sc); 672 gem_reset_tx(sc); 673 674 /* Do a full reset */ 675 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 676 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 677 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 678 splx(s); 679 } 680 681 682 /* 683 * gem_rxdrain: 684 * 685 * Drain the receive queue. 686 */ 687 static void 688 gem_rxdrain(struct gem_softc *sc) 689 { 690 struct gem_rxsoft *rxs; 691 int i; 692 693 for (i = 0; i < GEM_NRXDESC; i++) { 694 rxs = &sc->sc_rxsoft[i]; 695 if (rxs->rxs_mbuf != NULL) { 696 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 697 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 698 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 699 m_freem(rxs->rxs_mbuf); 700 rxs->rxs_mbuf = NULL; 701 } 702 } 703 } 704 705 /* 706 * Reset the whole thing. 707 */ 708 static void 709 gem_stop(struct ifnet *ifp, int disable) 710 { 711 struct gem_softc *sc = ifp->if_softc; 712 struct gem_txsoft *txs; 713 714 DPRINTF(sc, ("%s: gem_stop\n", device_xname(sc->sc_dev))); 715 716 callout_halt(&sc->sc_tick_ch, NULL); 717 callout_halt(&sc->sc_rx_watchdog, NULL); 718 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 719 gem_pcs_stop(sc, disable); 720 else 721 mii_down(&sc->sc_mii); 722 723 /* XXX - Should we reset these instead? */ 724 gem_disable_tx(sc); 725 gem_disable_rx(sc); 726 727 /* 728 * Release any queued transmit buffers. 729 */ 730 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 731 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 732 if (txs->txs_mbuf != NULL) { 733 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 734 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 735 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 736 m_freem(txs->txs_mbuf); 737 txs->txs_mbuf = NULL; 738 } 739 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 740 } 741 742 /* 743 * Mark the interface down and cancel the watchdog timer. 744 */ 745 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 746 sc->sc_if_flags = ifp->if_flags; 747 ifp->if_timer = 0; 748 749 if (disable) 750 gem_rxdrain(sc); 751 } 752 753 754 /* 755 * Reset the receiver 756 */ 757 int 758 gem_reset_rx(struct gem_softc *sc) 759 { 760 bus_space_tag_t t = sc->sc_bustag; 761 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 762 763 /* 764 * Resetting while DMA is in progress can cause a bus hang, so we 765 * disable DMA first. 766 */ 767 gem_disable_rx(sc); 768 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 769 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 770 /* Wait till it finishes */ 771 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 772 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 773 /* Wait 5ms extra. */ 774 delay(5000); 775 776 /* Finally, reset the ERX */ 777 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 778 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 779 /* Wait till it finishes */ 780 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 781 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 782 return (1); 783 } 784 return (0); 785 } 786 787 788 /* 789 * Reset the receiver DMA engine. 790 * 791 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 792 * etc in order to reset the receiver DMA engine only and not do a full 793 * reset which amongst others also downs the link and clears the FIFOs. 794 */ 795 static void 796 gem_reset_rxdma(struct gem_softc *sc) 797 { 798 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 799 bus_space_tag_t t = sc->sc_bustag; 800 bus_space_handle_t h = sc->sc_h1; 801 int i; 802 803 if (gem_reset_rx(sc) != 0) { 804 gem_init(ifp); 805 return; 806 } 807 for (i = 0; i < GEM_NRXDESC; i++) 808 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 809 GEM_UPDATE_RXDESC(sc, i); 810 sc->sc_rxptr = 0; 811 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 812 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 813 814 /* Reprogram Descriptor Ring Base Addresses */ 815 /* NOTE: we use only 32-bit DMA addresses here. */ 816 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 817 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 818 819 /* Redo ERX Configuration */ 820 gem_rx_common(sc); 821 822 /* Give the reciever a swift kick */ 823 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 824 } 825 826 /* 827 * Common RX configuration for gem_init() and gem_reset_rxdma(). 828 */ 829 static void 830 gem_rx_common(struct gem_softc *sc) 831 { 832 bus_space_tag_t t = sc->sc_bustag; 833 bus_space_handle_t h = sc->sc_h1; 834 u_int32_t v; 835 836 /* Encode Receive Descriptor ring size: four possible values */ 837 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 838 839 /* Set receive h/w checksum offset */ 840 #ifdef INET 841 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 842 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 843 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 844 #endif 845 846 /* Enable RX DMA */ 847 bus_space_write_4(t, h, GEM_RX_CONFIG, 848 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 849 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 850 851 /* 852 * The following value is for an OFF Threshold of about 3/4 full 853 * and an ON Threshold of 1/4 full. 854 */ 855 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 856 (3 * sc->sc_rxfifosize / 256) | 857 ((sc->sc_rxfifosize / 256) << 12)); 858 bus_space_write_4(t, h, GEM_RX_BLANKING, 859 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 8); 860 } 861 862 /* 863 * Reset the transmitter 864 */ 865 int 866 gem_reset_tx(struct gem_softc *sc) 867 { 868 bus_space_tag_t t = sc->sc_bustag; 869 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 870 871 /* 872 * Resetting while DMA is in progress can cause a bus hang, so we 873 * disable DMA first. 874 */ 875 gem_disable_tx(sc); 876 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 877 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 878 /* Wait till it finishes */ 879 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 880 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 881 /* Wait 5ms extra. */ 882 delay(5000); 883 884 /* Finally, reset the ETX */ 885 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 886 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 887 /* Wait till it finishes */ 888 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 889 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 890 return (1); 891 } 892 return (0); 893 } 894 895 /* 896 * disable receiver. 897 */ 898 int 899 gem_disable_rx(struct gem_softc *sc) 900 { 901 bus_space_tag_t t = sc->sc_bustag; 902 bus_space_handle_t h = sc->sc_h1; 903 u_int32_t cfg; 904 905 /* Flip the enable bit */ 906 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 907 cfg &= ~GEM_MAC_RX_ENABLE; 908 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 909 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 910 /* Wait for it to finish */ 911 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 912 } 913 914 /* 915 * disable transmitter. 916 */ 917 int 918 gem_disable_tx(struct gem_softc *sc) 919 { 920 bus_space_tag_t t = sc->sc_bustag; 921 bus_space_handle_t h = sc->sc_h1; 922 u_int32_t cfg; 923 924 /* Flip the enable bit */ 925 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 926 cfg &= ~GEM_MAC_TX_ENABLE; 927 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 928 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 929 /* Wait for it to finish */ 930 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 931 } 932 933 /* 934 * Initialize interface. 935 */ 936 int 937 gem_meminit(struct gem_softc *sc) 938 { 939 struct gem_rxsoft *rxs; 940 int i, error; 941 942 /* 943 * Initialize the transmit descriptor ring. 944 */ 945 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 946 for (i = 0; i < GEM_NTXDESC; i++) { 947 sc->sc_txdescs[i].gd_flags = 0; 948 sc->sc_txdescs[i].gd_addr = 0; 949 } 950 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 951 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 952 sc->sc_txfree = GEM_NTXDESC-1; 953 sc->sc_txnext = 0; 954 sc->sc_txwin = 0; 955 956 /* 957 * Initialize the receive descriptor and receive job 958 * descriptor rings. 959 */ 960 for (i = 0; i < GEM_NRXDESC; i++) { 961 rxs = &sc->sc_rxsoft[i]; 962 if (rxs->rxs_mbuf == NULL) { 963 if ((error = gem_add_rxbuf(sc, i)) != 0) { 964 aprint_error_dev(sc->sc_dev, 965 "unable to allocate or map rx " 966 "buffer %d, error = %d\n", 967 i, error); 968 /* 969 * XXX Should attempt to run with fewer receive 970 * XXX buffers instead of just failing. 971 */ 972 gem_rxdrain(sc); 973 return (1); 974 } 975 } else 976 GEM_INIT_RXDESC(sc, i); 977 } 978 sc->sc_rxptr = 0; 979 sc->sc_meminited = 1; 980 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 981 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 982 983 return (0); 984 } 985 986 static int 987 gem_ringsize(int sz) 988 { 989 switch (sz) { 990 case 32: 991 return GEM_RING_SZ_32; 992 case 64: 993 return GEM_RING_SZ_64; 994 case 128: 995 return GEM_RING_SZ_128; 996 case 256: 997 return GEM_RING_SZ_256; 998 case 512: 999 return GEM_RING_SZ_512; 1000 case 1024: 1001 return GEM_RING_SZ_1024; 1002 case 2048: 1003 return GEM_RING_SZ_2048; 1004 case 4096: 1005 return GEM_RING_SZ_4096; 1006 case 8192: 1007 return GEM_RING_SZ_8192; 1008 default: 1009 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 1010 return GEM_RING_SZ_32; 1011 } 1012 } 1013 1014 1015 /* 1016 * Start PCS 1017 */ 1018 void 1019 gem_pcs_start(struct gem_softc *sc) 1020 { 1021 bus_space_tag_t t = sc->sc_bustag; 1022 bus_space_handle_t h = sc->sc_h1; 1023 uint32_t v; 1024 1025 #ifdef GEM_DEBUG 1026 aprint_debug_dev(sc->sc_dev, "gem_pcs_start()\n"); 1027 #endif 1028 1029 /* 1030 * Set up. We must disable the MII before modifying the 1031 * GEM_MII_ANAR register 1032 */ 1033 if (sc->sc_flags & GEM_SERDES) { 1034 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1035 GEM_MII_DATAPATH_SERDES); 1036 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1037 GEM_MII_SLINK_LOOPBACK); 1038 } else { 1039 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1040 GEM_MII_DATAPATH_SERIAL); 1041 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 1042 } 1043 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1044 v = bus_space_read_4(t, h, GEM_MII_ANAR); 1045 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 1046 if (sc->sc_mii_media == IFM_AUTO) 1047 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 1048 else if (sc->sc_mii_media == IFM_FDX) { 1049 v |= GEM_MII_ANEG_FUL_DUPLX; 1050 v &= ~GEM_MII_ANEG_HLF_DUPLX; 1051 } else if (sc->sc_mii_media == IFM_HDX) { 1052 v &= ~GEM_MII_ANEG_FUL_DUPLX; 1053 v |= GEM_MII_ANEG_HLF_DUPLX; 1054 } 1055 1056 /* Configure link. */ 1057 bus_space_write_4(t, h, GEM_MII_ANAR, v); 1058 bus_space_write_4(t, h, GEM_MII_CONTROL, 1059 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1060 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 1061 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 1062 1063 /* Start the 10 second timer */ 1064 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 1065 } 1066 1067 /* 1068 * Stop PCS 1069 */ 1070 void 1071 gem_pcs_stop(struct gem_softc *sc, int disable) 1072 { 1073 bus_space_tag_t t = sc->sc_bustag; 1074 bus_space_handle_t h = sc->sc_h1; 1075 1076 #ifdef GEM_DEBUG 1077 aprint_debug_dev(sc->sc_dev, "gem_pcs_stop()\n"); 1078 #endif 1079 1080 /* Tell link partner that we're going away */ 1081 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1082 1083 /* 1084 * Disable PCS MII. The documentation suggests that setting 1085 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1086 * negotiation will shut down the link. However, it appears 1087 * that we also need to unset the datapath mode. 1088 */ 1089 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1090 bus_space_write_4(t, h, GEM_MII_CONTROL, 1091 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1092 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1093 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1094 1095 if (disable) { 1096 if (sc->sc_flags & GEM_SERDES) 1097 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1098 GEM_MII_SLINK_POWER_OFF); 1099 else 1100 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1101 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1102 } 1103 1104 sc->sc_flags &= ~GEM_LINK; 1105 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1106 sc->sc_mii.mii_media_status = IFM_AVALID; 1107 } 1108 1109 1110 /* 1111 * Initialization of interface; set up initialization block 1112 * and transmit/receive descriptor rings. 1113 */ 1114 int 1115 gem_init(struct ifnet *ifp) 1116 { 1117 struct gem_softc *sc = ifp->if_softc; 1118 bus_space_tag_t t = sc->sc_bustag; 1119 bus_space_handle_t h = sc->sc_h1; 1120 int rc = 0, s; 1121 u_int max_frame_size; 1122 u_int32_t v; 1123 1124 s = splnet(); 1125 1126 DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(sc->sc_dev))); 1127 /* 1128 * Initialization sequence. The numbered steps below correspond 1129 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1130 * Channel Engine manual (part of the PCIO manual). 1131 * See also the STP2002-STQ document from Sun Microsystems. 1132 */ 1133 1134 /* step 1 & 2. Reset the Ethernet Channel */ 1135 gem_stop(ifp, 0); 1136 gem_reset(sc); 1137 DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(sc->sc_dev))); 1138 1139 /* Re-initialize the MIF */ 1140 gem_mifinit(sc); 1141 1142 /* Set up correct datapath for non-SERDES/Serialink */ 1143 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1144 sc->sc_variant != GEM_SUN_ERI) 1145 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1146 GEM_MII_DATAPATH_MII); 1147 1148 /* Call MI reset function if any */ 1149 if (sc->sc_hwreset) 1150 (*sc->sc_hwreset)(sc); 1151 1152 /* step 3. Setup data structures in host memory */ 1153 if (gem_meminit(sc) != 0) { 1154 splx(s); 1155 return 1; 1156 } 1157 1158 /* step 4. TX MAC registers & counters */ 1159 gem_init_regs(sc); 1160 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1161 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1162 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1163 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1164 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1165 max_frame_size|/* burst size */(0x2000<<16)); 1166 1167 /* step 5. RX MAC registers & counters */ 1168 gem_setladrf(sc); 1169 1170 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1171 /* NOTE: we use only 32-bit DMA addresses here. */ 1172 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 1173 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1174 1175 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 1176 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1177 1178 /* step 8. Global Configuration & Interrupt Mask */ 1179 gem_inten(sc); 1180 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1181 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1182 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1183 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1184 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1185 1186 /* step 9. ETX Configuration: use mostly default values */ 1187 1188 /* Enable TX DMA */ 1189 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1190 bus_space_write_4(t, h, GEM_TX_CONFIG, 1191 v | GEM_TX_CONFIG_TXDMA_EN | 1192 (((sc->sc_flags & GEM_GIGABIT ? 0x4FF : 0x100) << 10) & 1193 GEM_TX_CONFIG_TXFIFO_TH)); 1194 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1195 1196 /* step 10. ERX Configuration */ 1197 gem_rx_common(sc); 1198 1199 /* step 11. Configure Media */ 1200 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1201 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1202 goto out; 1203 1204 /* step 12. RX_MAC Configuration Register */ 1205 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1206 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1207 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1208 1209 /* step 14. Issue Transmit Pending command */ 1210 1211 /* Call MI initialization function if any */ 1212 if (sc->sc_hwinit) 1213 (*sc->sc_hwinit)(sc); 1214 1215 1216 /* step 15. Give the reciever a swift kick */ 1217 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1218 1219 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1220 /* Configure PCS */ 1221 gem_pcs_start(sc); 1222 else 1223 /* Start the one second timer. */ 1224 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1225 1226 sc->sc_flags &= ~GEM_LINK; 1227 ifp->if_flags |= IFF_RUNNING; 1228 ifp->if_flags &= ~IFF_OACTIVE; 1229 ifp->if_timer = 0; 1230 sc->sc_if_flags = ifp->if_flags; 1231 out: 1232 splx(s); 1233 1234 return (0); 1235 } 1236 1237 void 1238 gem_init_regs(struct gem_softc *sc) 1239 { 1240 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1241 bus_space_tag_t t = sc->sc_bustag; 1242 bus_space_handle_t h = sc->sc_h1; 1243 const u_char *laddr = CLLADDR(ifp->if_sadl); 1244 u_int32_t v; 1245 1246 /* These regs are not cleared on reset */ 1247 if (!sc->sc_inited) { 1248 1249 /* Load recommended values */ 1250 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1251 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1252 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1253 1254 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1255 /* Max frame and max burst size */ 1256 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1257 ETHER_MAX_LEN | (0x2000<<16)); 1258 1259 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1260 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1261 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1262 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1263 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1264 ((laddr[5]<<8)|laddr[4])&0x3ff); 1265 1266 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1267 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1268 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1269 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1270 1271 /* MAC control addr set to 01:80:c2:00:00:01 */ 1272 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1273 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1274 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1275 1276 /* MAC filter addr set to 0:0:0:0:0:0 */ 1277 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1278 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1279 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1280 1281 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1282 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1283 1284 sc->sc_inited = 1; 1285 } 1286 1287 /* Counters need to be zeroed */ 1288 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1289 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1290 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1291 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1292 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1293 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1294 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1295 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1296 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1297 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1298 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1299 1300 /* Set XOFF PAUSE time. */ 1301 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1302 1303 /* 1304 * Set the internal arbitration to "infinite" bursts of the 1305 * maximum length of 31 * 64 bytes so DMA transfers aren't 1306 * split up in cache line size chunks. This greatly improves 1307 * especially RX performance. 1308 * Enable silicon bug workarounds for the Apple variants. 1309 */ 1310 bus_space_write_4(t, h, GEM_CONFIG, 1311 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1312 ((sc->sc_flags & GEM_PCI) ? 1313 GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1314 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1315 1316 /* 1317 * Set the station address. 1318 */ 1319 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1320 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1321 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1322 1323 /* 1324 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1325 */ 1326 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1327 v = GEM_MAC_XIF_TX_MII_ENA; 1328 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1329 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1330 v |= GEM_MAC_XIF_FDPLX_LED; 1331 if (sc->sc_flags & GEM_GIGABIT) 1332 v |= GEM_MAC_XIF_GMII_MODE; 1333 } 1334 } else { 1335 v |= GEM_MAC_XIF_GMII_MODE; 1336 } 1337 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1338 } 1339 1340 #ifdef GEM_DEBUG 1341 static void 1342 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1343 { 1344 int i; 1345 1346 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1347 printf("descriptor %d:\t", i); 1348 printf("gd_flags: 0x%016" PRIx64 "\t", 1349 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1350 printf("gd_addr: 0x%016" PRIx64 "\n", 1351 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1352 if (i == lastdesc) 1353 break; 1354 } 1355 } 1356 #endif 1357 1358 static void 1359 gem_start(struct ifnet *ifp) 1360 { 1361 struct gem_softc *sc = ifp->if_softc; 1362 struct mbuf *m0, *m; 1363 struct gem_txsoft *txs; 1364 bus_dmamap_t dmamap; 1365 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1366 #ifdef GEM_DEBUG 1367 int otxnext; 1368 #endif 1369 uint64_t flags = 0; 1370 1371 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1372 return; 1373 1374 /* 1375 * Remember the previous number of free descriptors and 1376 * the first descriptor we'll use. 1377 */ 1378 ofree = sc->sc_txfree; 1379 #ifdef GEM_DEBUG 1380 otxnext = sc->sc_txnext; 1381 #endif 1382 1383 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1384 device_xname(sc->sc_dev), ofree, otxnext)); 1385 1386 /* 1387 * Loop through the send queue, setting up transmit descriptors 1388 * until we drain the queue, or use up all available transmit 1389 * descriptors. 1390 */ 1391 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1392 sc->sc_txfree != 0) { 1393 /* 1394 * Grab a packet off the queue. 1395 */ 1396 IFQ_POLL(&ifp->if_snd, m0); 1397 if (m0 == NULL) 1398 break; 1399 m = NULL; 1400 1401 dmamap = txs->txs_dmamap; 1402 1403 /* 1404 * Load the DMA map. If this fails, the packet either 1405 * didn't fit in the alloted number of segments, or we were 1406 * short on resources. In this case, we'll copy and try 1407 * again. 1408 */ 1409 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1410 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1411 (m0->m_pkthdr.len < ETHER_MIN_TX && 1412 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1413 if (m0->m_pkthdr.len > MCLBYTES) { 1414 aprint_error_dev(sc->sc_dev, 1415 "unable to allocate jumbo Tx cluster\n"); 1416 IFQ_DEQUEUE(&ifp->if_snd, m0); 1417 m_freem(m0); 1418 continue; 1419 } 1420 MGETHDR(m, M_DONTWAIT, MT_DATA); 1421 if (m == NULL) { 1422 aprint_error_dev(sc->sc_dev, 1423 "unable to allocate Tx mbuf\n"); 1424 break; 1425 } 1426 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1427 if (m0->m_pkthdr.len > MHLEN) { 1428 MCLGET(m, M_DONTWAIT); 1429 if ((m->m_flags & M_EXT) == 0) { 1430 aprint_error_dev(sc->sc_dev, 1431 "unable to allocate Tx cluster\n"); 1432 m_freem(m); 1433 break; 1434 } 1435 } 1436 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1437 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1438 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1439 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1440 if (error) { 1441 aprint_error_dev(sc->sc_dev, 1442 "unable to load Tx buffer, error = %d\n", 1443 error); 1444 break; 1445 } 1446 } 1447 1448 /* 1449 * Ensure we have enough descriptors free to describe 1450 * the packet. 1451 */ 1452 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1453 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1454 /* 1455 * Not enough free descriptors to transmit this 1456 * packet. We haven't committed to anything yet, 1457 * so just unload the DMA map, put the packet 1458 * back on the queue, and punt. Notify the upper 1459 * layer that there are no more slots left. 1460 * 1461 * XXX We could allocate an mbuf and copy, but 1462 * XXX it is worth it? 1463 */ 1464 ifp->if_flags |= IFF_OACTIVE; 1465 sc->sc_if_flags = ifp->if_flags; 1466 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1467 if (m != NULL) 1468 m_freem(m); 1469 break; 1470 } 1471 1472 IFQ_DEQUEUE(&ifp->if_snd, m0); 1473 if (m != NULL) { 1474 m_freem(m0); 1475 m0 = m; 1476 } 1477 1478 /* 1479 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1480 */ 1481 1482 /* Sync the DMA map. */ 1483 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1484 BUS_DMASYNC_PREWRITE); 1485 1486 /* 1487 * Initialize the transmit descriptors. 1488 */ 1489 firsttx = sc->sc_txnext; 1490 for (nexttx = firsttx, seg = 0; 1491 seg < dmamap->dm_nsegs; 1492 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1493 1494 /* 1495 * If this is the first descriptor we're 1496 * enqueueing, set the start of packet flag, 1497 * and the checksum stuff if we want the hardware 1498 * to do it. 1499 */ 1500 sc->sc_txdescs[nexttx].gd_addr = 1501 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1502 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1503 if (nexttx == firsttx) { 1504 flags |= GEM_TD_START_OF_PACKET; 1505 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1506 sc->sc_txwin = 0; 1507 flags |= GEM_TD_INTERRUPT_ME; 1508 } 1509 1510 #ifdef INET 1511 /* h/w checksum */ 1512 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1513 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1514 struct ether_header *eh; 1515 uint16_t offset, start; 1516 1517 eh = mtod(m0, struct ether_header *); 1518 switch (ntohs(eh->ether_type)) { 1519 case ETHERTYPE_IP: 1520 start = ETHER_HDR_LEN; 1521 break; 1522 case ETHERTYPE_VLAN: 1523 start = ETHER_HDR_LEN + 1524 ETHER_VLAN_ENCAP_LEN; 1525 break; 1526 default: 1527 /* unsupported, drop it */ 1528 m_free(m0); 1529 continue; 1530 } 1531 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1532 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1533 flags |= (start << 1534 GEM_TD_CXSUM_STARTSHFT) | 1535 (offset << 1536 GEM_TD_CXSUM_STUFFSHFT) | 1537 GEM_TD_CXSUM_ENABLE; 1538 } 1539 #endif 1540 } 1541 if (seg == dmamap->dm_nsegs - 1) { 1542 flags |= GEM_TD_END_OF_PACKET; 1543 } else { 1544 /* last flag set outside of loop */ 1545 sc->sc_txdescs[nexttx].gd_flags = 1546 GEM_DMA_WRITE(sc, flags); 1547 } 1548 lasttx = nexttx; 1549 } 1550 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1551 /* add padding buffer at end of chain */ 1552 flags &= ~GEM_TD_END_OF_PACKET; 1553 sc->sc_txdescs[lasttx].gd_flags = 1554 GEM_DMA_WRITE(sc, flags); 1555 1556 sc->sc_txdescs[nexttx].gd_addr = 1557 GEM_DMA_WRITE(sc, 1558 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1559 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1560 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1561 lasttx = nexttx; 1562 nexttx = GEM_NEXTTX(nexttx); 1563 seg++; 1564 } 1565 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1566 1567 KASSERT(lasttx != -1); 1568 1569 /* 1570 * Store a pointer to the packet so we can free it later, 1571 * and remember what txdirty will be once the packet is 1572 * done. 1573 */ 1574 txs->txs_mbuf = m0; 1575 txs->txs_firstdesc = sc->sc_txnext; 1576 txs->txs_lastdesc = lasttx; 1577 txs->txs_ndescs = seg; 1578 1579 #ifdef GEM_DEBUG 1580 if (ifp->if_flags & IFF_DEBUG) { 1581 printf(" gem_start %p transmit chain:\n", txs); 1582 gem_txsoft_print(sc, txs->txs_firstdesc, 1583 txs->txs_lastdesc); 1584 } 1585 #endif 1586 1587 /* Sync the descriptors we're using. */ 1588 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1589 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1590 1591 /* Advance the tx pointer. */ 1592 sc->sc_txfree -= txs->txs_ndescs; 1593 sc->sc_txnext = nexttx; 1594 1595 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1596 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1597 1598 /* 1599 * Pass the packet to any BPF listeners. 1600 */ 1601 bpf_mtap(ifp, m0); 1602 } 1603 1604 if (txs == NULL || sc->sc_txfree == 0) { 1605 /* No more slots left; notify upper layer. */ 1606 ifp->if_flags |= IFF_OACTIVE; 1607 sc->sc_if_flags = ifp->if_flags; 1608 } 1609 1610 if (sc->sc_txfree != ofree) { 1611 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1612 device_xname(sc->sc_dev), lasttx, otxnext)); 1613 /* 1614 * The entire packet chain is set up. 1615 * Kick the transmitter. 1616 */ 1617 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1618 device_xname(sc->sc_dev), nexttx)); 1619 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1620 sc->sc_txnext); 1621 1622 /* Set a watchdog timer in case the chip flakes out. */ 1623 ifp->if_timer = 5; 1624 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1625 device_xname(sc->sc_dev), ifp->if_timer)); 1626 } 1627 } 1628 1629 /* 1630 * Transmit interrupt. 1631 */ 1632 int 1633 gem_tint(struct gem_softc *sc) 1634 { 1635 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1636 bus_space_tag_t t = sc->sc_bustag; 1637 bus_space_handle_t mac = sc->sc_h1; 1638 struct gem_txsoft *txs; 1639 int txlast; 1640 int progress = 0; 1641 u_int32_t v; 1642 1643 DPRINTF(sc, ("%s: gem_tint\n", device_xname(sc->sc_dev))); 1644 1645 /* Unload collision counters ... */ 1646 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1647 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1648 ifp->if_collisions += v + 1649 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1650 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT); 1651 ifp->if_oerrors += v; 1652 1653 /* ... then clear the hardware counters. */ 1654 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1655 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1656 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1657 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1658 1659 /* 1660 * Go through our Tx list and free mbufs for those 1661 * frames that have been transmitted. 1662 */ 1663 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1664 /* 1665 * In theory, we could harvest some descriptors before 1666 * the ring is empty, but that's a bit complicated. 1667 * 1668 * GEM_TX_COMPLETION points to the last descriptor 1669 * processed +1. 1670 * 1671 * Let's assume that the NIC writes back to the Tx 1672 * descriptors before it updates the completion 1673 * register. If the NIC has posted writes to the 1674 * Tx descriptors, PCI ordering requires that the 1675 * posted writes flush to RAM before the register-read 1676 * finishes. So let's read the completion register, 1677 * before syncing the descriptors, so that we 1678 * examine Tx descriptors that are at least as 1679 * current as the completion register. 1680 */ 1681 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1682 DPRINTF(sc, 1683 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1684 txs->txs_lastdesc, txlast)); 1685 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1686 if (txlast >= txs->txs_firstdesc && 1687 txlast <= txs->txs_lastdesc) 1688 break; 1689 } else if (txlast >= txs->txs_firstdesc || 1690 txlast <= txs->txs_lastdesc) 1691 break; 1692 1693 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1694 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1695 1696 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1697 if (ifp->if_flags & IFF_DEBUG) { 1698 printf(" txsoft %p transmit chain:\n", txs); 1699 gem_txsoft_print(sc, txs->txs_firstdesc, 1700 txs->txs_lastdesc); 1701 } 1702 #endif 1703 1704 1705 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1706 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1707 1708 sc->sc_txfree += txs->txs_ndescs; 1709 1710 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1711 0, txs->txs_dmamap->dm_mapsize, 1712 BUS_DMASYNC_POSTWRITE); 1713 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1714 if (txs->txs_mbuf != NULL) { 1715 m_freem(txs->txs_mbuf); 1716 txs->txs_mbuf = NULL; 1717 } 1718 1719 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1720 1721 ifp->if_opackets++; 1722 progress = 1; 1723 } 1724 1725 #if 0 1726 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1727 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1728 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1729 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1730 GEM_TX_DATA_PTR_HI) << 32) | 1731 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1732 GEM_TX_DATA_PTR_LO), 1733 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1734 #endif 1735 1736 if (progress) { 1737 if (sc->sc_txfree == GEM_NTXDESC - 1) 1738 sc->sc_txwin = 0; 1739 1740 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1741 ifp->if_flags &= ~IFF_OACTIVE; 1742 sc->sc_if_flags = ifp->if_flags; 1743 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1744 if_schedule_deferred_start(ifp); 1745 } 1746 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1747 device_xname(sc->sc_dev), ifp->if_timer)); 1748 1749 return (1); 1750 } 1751 1752 /* 1753 * Receive interrupt. 1754 */ 1755 int 1756 gem_rint(struct gem_softc *sc) 1757 { 1758 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1759 bus_space_tag_t t = sc->sc_bustag; 1760 bus_space_handle_t h = sc->sc_h1; 1761 struct gem_rxsoft *rxs; 1762 struct mbuf *m; 1763 u_int64_t rxstat; 1764 u_int32_t rxcomp; 1765 int i, len, progress = 0; 1766 1767 DPRINTF(sc, ("%s: gem_rint\n", device_xname(sc->sc_dev))); 1768 1769 /* 1770 * Ignore spurious interrupt that sometimes occurs before 1771 * we are set up when we network boot. 1772 */ 1773 if (!sc->sc_meminited) 1774 return 1; 1775 1776 /* 1777 * Read the completion register once. This limits 1778 * how long the following loop can execute. 1779 */ 1780 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1781 1782 /* 1783 * XXX Read the lastrx only once at the top for speed. 1784 */ 1785 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1786 sc->sc_rxptr, rxcomp)); 1787 1788 /* 1789 * Go into the loop at least once. 1790 */ 1791 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1792 i = GEM_NEXTRX(i)) { 1793 rxs = &sc->sc_rxsoft[i]; 1794 1795 GEM_CDRXSYNC(sc, i, 1796 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1797 1798 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1799 1800 if (rxstat & GEM_RD_OWN) { 1801 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1802 /* 1803 * We have processed all of the receive buffers. 1804 */ 1805 break; 1806 } 1807 1808 progress++; 1809 1810 if (rxstat & GEM_RD_BAD_CRC) { 1811 ifp->if_ierrors++; 1812 aprint_error_dev(sc->sc_dev, 1813 "receive error: CRC error\n"); 1814 GEM_INIT_RXDESC(sc, i); 1815 continue; 1816 } 1817 1818 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1819 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1820 #ifdef GEM_DEBUG 1821 if (ifp->if_flags & IFF_DEBUG) { 1822 printf(" rxsoft %p descriptor %d: ", rxs, i); 1823 printf("gd_flags: 0x%016llx\t", (long long) 1824 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1825 printf("gd_addr: 0x%016llx\n", (long long) 1826 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1827 } 1828 #endif 1829 1830 /* No errors; receive the packet. */ 1831 len = GEM_RD_BUFLEN(rxstat); 1832 1833 /* 1834 * Allocate a new mbuf cluster. If that fails, we are 1835 * out of memory, and must drop the packet and recycle 1836 * the buffer that's already attached to this descriptor. 1837 */ 1838 m = rxs->rxs_mbuf; 1839 if (gem_add_rxbuf(sc, i) != 0) { 1840 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1841 ifp->if_ierrors++; 1842 aprint_error_dev(sc->sc_dev, 1843 "receive error: RX no buffer space\n"); 1844 GEM_INIT_RXDESC(sc, i); 1845 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1846 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1847 continue; 1848 } 1849 m->m_data += 2; /* We're already off by two */ 1850 1851 m_set_rcvif(m, ifp); 1852 m->m_pkthdr.len = m->m_len = len; 1853 1854 #ifdef INET 1855 /* hardware checksum */ 1856 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1857 struct ether_header *eh; 1858 struct ip *ip; 1859 int32_t hlen, pktlen; 1860 1861 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1862 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1863 ETHER_VLAN_ENCAP_LEN; 1864 eh = (struct ether_header *) (mtod(m, char *) + 1865 ETHER_VLAN_ENCAP_LEN); 1866 } else { 1867 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1868 eh = mtod(m, struct ether_header *); 1869 } 1870 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1871 goto swcsum; 1872 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1873 1874 /* IPv4 only */ 1875 if (ip->ip_v != IPVERSION) 1876 goto swcsum; 1877 1878 hlen = ip->ip_hl << 2; 1879 if (hlen < sizeof(struct ip)) 1880 goto swcsum; 1881 1882 /* 1883 * bail if too short, has random trailing garbage, 1884 * truncated, fragment, or has ethernet pad. 1885 */ 1886 if ((ntohs(ip->ip_len) < hlen) || 1887 (ntohs(ip->ip_len) != pktlen) || 1888 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1889 goto swcsum; 1890 1891 switch (ip->ip_p) { 1892 case IPPROTO_TCP: 1893 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1894 goto swcsum; 1895 if (pktlen < (hlen + sizeof(struct tcphdr))) 1896 goto swcsum; 1897 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1898 break; 1899 case IPPROTO_UDP: 1900 /* FALLTHROUGH */ 1901 default: 1902 goto swcsum; 1903 } 1904 1905 /* the uncomplemented sum is expected */ 1906 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1907 1908 /* if the pkt had ip options, we have to deduct them */ 1909 if (hlen > sizeof(struct ip)) { 1910 uint16_t *opts; 1911 uint32_t optsum, temp; 1912 1913 optsum = 0; 1914 temp = hlen - sizeof(struct ip); 1915 opts = (uint16_t *) ((char *) ip + 1916 sizeof(struct ip)); 1917 1918 while (temp > 1) { 1919 optsum += ntohs(*opts++); 1920 temp -= 2; 1921 } 1922 while (optsum >> 16) 1923 optsum = (optsum >> 16) + 1924 (optsum & 0xffff); 1925 1926 /* Deduct ip opts sum from hwsum. */ 1927 m->m_pkthdr.csum_data += (uint16_t)~optsum; 1928 1929 while (m->m_pkthdr.csum_data >> 16) 1930 m->m_pkthdr.csum_data = 1931 (m->m_pkthdr.csum_data >> 16) + 1932 (m->m_pkthdr.csum_data & 1933 0xffff); 1934 } 1935 1936 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1937 M_CSUM_NO_PSEUDOHDR; 1938 } else 1939 swcsum: 1940 m->m_pkthdr.csum_flags = 0; 1941 #endif 1942 /* Pass it on. */ 1943 if_percpuq_enqueue(ifp->if_percpuq, m); 1944 } 1945 1946 if (progress) { 1947 /* Update the receive pointer. */ 1948 if (i == sc->sc_rxptr) { 1949 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1950 #ifdef GEM_DEBUG 1951 if (ifp->if_flags & IFF_DEBUG) 1952 printf("%s: rint: ring wrap\n", 1953 device_xname(sc->sc_dev)); 1954 #endif 1955 } 1956 sc->sc_rxptr = i; 1957 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1958 } 1959 #ifdef GEM_COUNTERS 1960 if (progress <= 4) { 1961 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1962 } else if (progress < 32) { 1963 if (progress < 16) 1964 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1965 else 1966 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1967 1968 } else { 1969 if (progress < 64) 1970 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1971 else 1972 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1973 } 1974 #endif 1975 1976 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1977 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1978 1979 /* Read error counters ... */ 1980 ifp->if_ierrors += 1981 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1982 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1983 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1984 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL); 1985 1986 /* ... then clear the hardware counters. */ 1987 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1988 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1989 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1990 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1991 1992 return (1); 1993 } 1994 1995 1996 /* 1997 * gem_add_rxbuf: 1998 * 1999 * Add a receive buffer to the indicated descriptor. 2000 */ 2001 int 2002 gem_add_rxbuf(struct gem_softc *sc, int idx) 2003 { 2004 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2005 struct mbuf *m; 2006 int error; 2007 2008 MGETHDR(m, M_DONTWAIT, MT_DATA); 2009 if (m == NULL) 2010 return (ENOBUFS); 2011 2012 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2013 MCLGET(m, M_DONTWAIT); 2014 if ((m->m_flags & M_EXT) == 0) { 2015 m_freem(m); 2016 return (ENOBUFS); 2017 } 2018 2019 #ifdef GEM_DEBUG 2020 /* bzero the packet to check DMA */ 2021 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 2022 #endif 2023 2024 if (rxs->rxs_mbuf != NULL) 2025 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 2026 2027 rxs->rxs_mbuf = m; 2028 2029 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 2030 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2031 BUS_DMA_READ|BUS_DMA_NOWAIT); 2032 if (error) { 2033 aprint_error_dev(sc->sc_dev, 2034 "can't load rx DMA map %d, error = %d\n", idx, error); 2035 panic("gem_add_rxbuf"); /* XXX */ 2036 } 2037 2038 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 2039 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2040 2041 GEM_INIT_RXDESC(sc, idx); 2042 2043 return (0); 2044 } 2045 2046 2047 int 2048 gem_eint(struct gem_softc *sc, u_int status) 2049 { 2050 char bits[128]; 2051 u_int32_t r, v; 2052 2053 if ((status & GEM_INTR_MIF) != 0) { 2054 printf("%s: XXXlink status changed\n", device_xname(sc->sc_dev)); 2055 return (1); 2056 } 2057 2058 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 2059 gem_reset_rxdma(sc); 2060 return (1); 2061 } 2062 2063 if (status & GEM_INTR_BERR) { 2064 if (sc->sc_flags & GEM_PCI) 2065 r = GEM_ERROR_STATUS; 2066 else 2067 r = GEM_SBUS_ERROR_STATUS; 2068 bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2069 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2070 aprint_error_dev(sc->sc_dev, "bus error interrupt: 0x%02x\n", 2071 v); 2072 return (1); 2073 } 2074 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2075 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 2076 2077 return (1); 2078 } 2079 2080 2081 /* 2082 * PCS interrupts. 2083 * We should receive these when the link status changes, but sometimes 2084 * we don't receive them for link up. We compensate for this in the 2085 * gem_tick() callout. 2086 */ 2087 int 2088 gem_pint(struct gem_softc *sc) 2089 { 2090 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2091 bus_space_tag_t t = sc->sc_bustag; 2092 bus_space_handle_t h = sc->sc_h1; 2093 u_int32_t v, v2; 2094 2095 /* 2096 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2097 * latched, so we have to read it twice. There is only one bit in 2098 * use, so the value is meaningless. 2099 */ 2100 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2101 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2102 2103 if ((ifp->if_flags & IFF_UP) == 0) 2104 return 1; 2105 2106 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2107 return 1; 2108 2109 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2110 /* If we see remote fault, our link partner is probably going away */ 2111 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2112 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2113 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2114 /* Otherwise, we may need to wait after auto-negotiation completes */ 2115 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2116 GEM_MII_STATUS_ANEG_CPT) { 2117 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2118 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2119 } 2120 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2121 if (sc->sc_flags & GEM_LINK) { 2122 return 1; 2123 } 2124 callout_stop(&sc->sc_tick_ch); 2125 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2126 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2127 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2128 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2129 v &= v2; 2130 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2131 sc->sc_mii.mii_media_active |= IFM_FDX; 2132 #ifdef GEM_DEBUG 2133 aprint_debug_dev(sc->sc_dev, "link up: full duplex\n"); 2134 #endif 2135 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2136 sc->sc_mii.mii_media_active |= IFM_HDX; 2137 #ifdef GEM_DEBUG 2138 aprint_debug_dev(sc->sc_dev, "link up: half duplex\n"); 2139 #endif 2140 } else { 2141 #ifdef GEM_DEBUG 2142 aprint_debug_dev(sc->sc_dev, "duplex mismatch\n"); 2143 #endif 2144 } 2145 gem_statuschange(sc); 2146 } else { 2147 if ((sc->sc_flags & GEM_LINK) == 0) { 2148 return 1; 2149 } 2150 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2151 sc->sc_mii.mii_media_status = IFM_AVALID; 2152 #ifdef GEM_DEBUG 2153 aprint_debug_dev(sc->sc_dev, "link down\n"); 2154 #endif 2155 gem_statuschange(sc); 2156 2157 /* Start the 10 second timer */ 2158 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 2159 } 2160 return 1; 2161 } 2162 2163 2164 2165 int 2166 gem_intr(void *v) 2167 { 2168 struct gem_softc *sc = v; 2169 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2170 bus_space_tag_t t = sc->sc_bustag; 2171 bus_space_handle_t h = sc->sc_h1; 2172 u_int32_t status; 2173 int r = 0; 2174 #ifdef GEM_DEBUG 2175 char bits[128]; 2176 #endif 2177 2178 /* XXX We should probably mask out interrupts until we're done */ 2179 2180 sc->sc_ev_intr.ev_count++; 2181 2182 status = bus_space_read_4(t, h, GEM_STATUS); 2183 #ifdef GEM_DEBUG 2184 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2185 #endif 2186 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2187 device_xname(sc->sc_dev), (status >> 19), bits)); 2188 2189 2190 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2191 r |= gem_eint(sc, status); 2192 2193 /* We don't bother with GEM_INTR_TX_DONE */ 2194 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2195 GEM_COUNTER_INCR(sc, sc_ev_txint); 2196 r |= gem_tint(sc); 2197 } 2198 2199 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2200 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2201 r |= gem_rint(sc); 2202 } 2203 2204 /* We should eventually do more than just print out error stats. */ 2205 if (status & GEM_INTR_TX_MAC) { 2206 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2207 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2208 printf("%s: MAC tx fault, status %x\n", 2209 device_xname(sc->sc_dev), txstat); 2210 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2211 gem_init(ifp); 2212 } 2213 if (status & GEM_INTR_RX_MAC) { 2214 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2215 /* 2216 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2217 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2218 * silicon bug so handle them silently. So if we detect 2219 * an RX FIFO overflow, we fire off a timer, and check 2220 * whether we're still making progress by looking at the 2221 * RX FIFO write and read pointers. 2222 */ 2223 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2224 ifp->if_ierrors++; 2225 aprint_error_dev(sc->sc_dev, 2226 "receive error: RX overflow sc->rxptr %d, complete %d\n", sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)); 2227 sc->sc_rx_fifo_wr_ptr = 2228 bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 2229 sc->sc_rx_fifo_rd_ptr = 2230 bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 2231 callout_schedule(&sc->sc_rx_watchdog, 400); 2232 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2233 printf("%s: MAC rx fault, status 0x%02x\n", 2234 device_xname(sc->sc_dev), rxstat); 2235 } 2236 if (status & GEM_INTR_PCS) { 2237 r |= gem_pint(sc); 2238 } 2239 2240 /* Do we need to do anything with these? 2241 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2242 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2243 if ((status2 & GEM_MAC_PAUSED) != 0) 2244 aprintf_debug_dev(sc->sc_dev, "PAUSE received (%d slots)\n", 2245 GEM_MAC_PAUSE_TIME(status2)); 2246 if ((status2 & GEM_MAC_PAUSE) != 0) 2247 aprintf_debug_dev(sc->sc_dev, "transited to PAUSE state\n"); 2248 if ((status2 & GEM_MAC_RESUME) != 0) 2249 aprintf_debug_dev(sc->sc_dev, "transited to non-PAUSE state\n"); 2250 } 2251 if ((status & GEM_INTR_MIF) != 0) 2252 aprintf_debug_dev(sc->sc_dev, "MIF interrupt\n"); 2253 */ 2254 rnd_add_uint32(&sc->rnd_source, status); 2255 return (r); 2256 } 2257 2258 void 2259 gem_rx_watchdog(void *arg) 2260 { 2261 struct gem_softc *sc = arg; 2262 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2263 bus_space_tag_t t = sc->sc_bustag; 2264 bus_space_handle_t h = sc->sc_h1; 2265 u_int32_t rx_fifo_wr_ptr; 2266 u_int32_t rx_fifo_rd_ptr; 2267 u_int32_t state; 2268 2269 if ((ifp->if_flags & IFF_RUNNING) == 0) { 2270 aprint_error_dev(sc->sc_dev, "receiver not running\n"); 2271 return; 2272 } 2273 2274 rx_fifo_wr_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 2275 rx_fifo_rd_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 2276 state = bus_space_read_4(t, h, GEM_MAC_MAC_STATE); 2277 if ((state & GEM_MAC_STATE_OVERFLOW) == GEM_MAC_STATE_OVERFLOW && 2278 ((rx_fifo_wr_ptr == rx_fifo_rd_ptr) || 2279 ((sc->sc_rx_fifo_wr_ptr == rx_fifo_wr_ptr) && 2280 (sc->sc_rx_fifo_rd_ptr == rx_fifo_rd_ptr)))) 2281 { 2282 /* 2283 * The RX state machine is still in overflow state and 2284 * the RX FIFO write and read pointers seem to be 2285 * stuck. Whack the chip over the head to get things 2286 * going again. 2287 */ 2288 aprint_error_dev(sc->sc_dev, 2289 "receiver stuck in overflow, resetting\n"); 2290 gem_init(ifp); 2291 } else { 2292 if ((state & GEM_MAC_STATE_OVERFLOW) != GEM_MAC_STATE_OVERFLOW) { 2293 aprint_error_dev(sc->sc_dev, 2294 "rx_watchdog: not in overflow state: 0x%x\n", 2295 state); 2296 } 2297 if (rx_fifo_wr_ptr != rx_fifo_rd_ptr) { 2298 aprint_error_dev(sc->sc_dev, 2299 "rx_watchdog: wr & rd ptr different\n"); 2300 } 2301 if (sc->sc_rx_fifo_wr_ptr != rx_fifo_wr_ptr) { 2302 aprint_error_dev(sc->sc_dev, 2303 "rx_watchdog: wr pointer != saved\n"); 2304 } 2305 if (sc->sc_rx_fifo_rd_ptr != rx_fifo_rd_ptr) { 2306 aprint_error_dev(sc->sc_dev, 2307 "rx_watchdog: rd pointer != saved\n"); 2308 } 2309 aprint_error_dev(sc->sc_dev, "resetting anyway\n"); 2310 gem_init(ifp); 2311 } 2312 } 2313 2314 void 2315 gem_watchdog(struct ifnet *ifp) 2316 { 2317 struct gem_softc *sc = ifp->if_softc; 2318 2319 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2320 "GEM_MAC_RX_CONFIG %x\n", 2321 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2322 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2323 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2324 2325 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 2326 ++ifp->if_oerrors; 2327 2328 /* Try to get more packets going. */ 2329 gem_init(ifp); 2330 gem_start(ifp); 2331 } 2332 2333 /* 2334 * Initialize the MII Management Interface 2335 */ 2336 void 2337 gem_mifinit(struct gem_softc *sc) 2338 { 2339 bus_space_tag_t t = sc->sc_bustag; 2340 bus_space_handle_t mif = sc->sc_h1; 2341 2342 /* Configure the MIF in frame mode */ 2343 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2344 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2345 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2346 } 2347 2348 /* 2349 * MII interface 2350 * 2351 * The GEM MII interface supports at least three different operating modes: 2352 * 2353 * Bitbang mode is implemented using data, clock and output enable registers. 2354 * 2355 * Frame mode is implemented by loading a complete frame into the frame 2356 * register and polling the valid bit for completion. 2357 * 2358 * Polling mode uses the frame register but completion is indicated by 2359 * an interrupt. 2360 * 2361 */ 2362 static int 2363 gem_mii_readreg(device_t self, int phy, int reg) 2364 { 2365 struct gem_softc *sc = device_private(self); 2366 bus_space_tag_t t = sc->sc_bustag; 2367 bus_space_handle_t mif = sc->sc_h1; 2368 int n; 2369 u_int32_t v; 2370 2371 #ifdef GEM_DEBUG1 2372 if (sc->sc_debug) 2373 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2374 #endif 2375 2376 /* Construct the frame command */ 2377 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2378 GEM_MIF_FRAME_READ; 2379 2380 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2381 for (n = 0; n < 100; n++) { 2382 DELAY(1); 2383 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2384 if (v & GEM_MIF_FRAME_TA0) 2385 return (v & GEM_MIF_FRAME_DATA); 2386 } 2387 2388 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 2389 return (0); 2390 } 2391 2392 static void 2393 gem_mii_writereg(device_t self, int phy, int reg, int val) 2394 { 2395 struct gem_softc *sc = device_private(self); 2396 bus_space_tag_t t = sc->sc_bustag; 2397 bus_space_handle_t mif = sc->sc_h1; 2398 int n; 2399 u_int32_t v; 2400 2401 #ifdef GEM_DEBUG1 2402 if (sc->sc_debug) 2403 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2404 phy, reg, val); 2405 #endif 2406 2407 /* Construct the frame command */ 2408 v = GEM_MIF_FRAME_WRITE | 2409 (phy << GEM_MIF_PHY_SHIFT) | 2410 (reg << GEM_MIF_REG_SHIFT) | 2411 (val & GEM_MIF_FRAME_DATA); 2412 2413 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2414 for (n = 0; n < 100; n++) { 2415 DELAY(1); 2416 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2417 if (v & GEM_MIF_FRAME_TA0) 2418 return; 2419 } 2420 2421 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 2422 } 2423 2424 static void 2425 gem_mii_statchg(struct ifnet *ifp) 2426 { 2427 struct gem_softc *sc = ifp->if_softc; 2428 #ifdef GEM_DEBUG 2429 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2430 #endif 2431 2432 #ifdef GEM_DEBUG 2433 if (sc->sc_debug) 2434 printf("gem_mii_statchg: status change: phy = %d\n", 2435 sc->sc_phys[instance]); 2436 #endif 2437 gem_statuschange(sc); 2438 } 2439 2440 /* 2441 * Common status change for gem_mii_statchg() and gem_pint() 2442 */ 2443 void 2444 gem_statuschange(struct gem_softc* sc) 2445 { 2446 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2447 bus_space_tag_t t = sc->sc_bustag; 2448 bus_space_handle_t mac = sc->sc_h1; 2449 int gigabit; 2450 u_int32_t rxcfg, txcfg, v; 2451 2452 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2453 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2454 sc->sc_flags |= GEM_LINK; 2455 else 2456 sc->sc_flags &= ~GEM_LINK; 2457 2458 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2459 gigabit = 1; 2460 else 2461 gigabit = 0; 2462 2463 /* 2464 * The configuration done here corresponds to the steps F) and 2465 * G) and as far as enabling of RX and TX MAC goes also step H) 2466 * of the initialization sequence outlined in section 3.2.1 of 2467 * the GEM Gigabit Ethernet ASIC Specification. 2468 */ 2469 2470 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2471 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2472 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2473 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2474 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2475 else if (gigabit) { 2476 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2477 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2478 } 2479 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2480 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2481 BUS_SPACE_BARRIER_WRITE); 2482 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2483 aprint_normal_dev(sc->sc_dev, "cannot disable TX MAC\n"); 2484 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2485 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2486 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2487 BUS_SPACE_BARRIER_WRITE); 2488 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2489 aprint_normal_dev(sc->sc_dev, "cannot disable RX MAC\n"); 2490 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2491 2492 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2493 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2494 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2495 2496 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2497 gigabit != 0) 2498 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2499 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2500 else 2501 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2502 GEM_MAC_SLOT_TIME_NORMAL); 2503 2504 /* XIF Configuration */ 2505 if (sc->sc_flags & GEM_LINK) 2506 v = GEM_MAC_XIF_LINK_LED; 2507 else 2508 v = 0; 2509 v |= GEM_MAC_XIF_TX_MII_ENA; 2510 2511 /* If an external transceiver is connected, enable its MII drivers */ 2512 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2513 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2514 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2515 if (gigabit) 2516 v |= GEM_MAC_XIF_GMII_MODE; 2517 else 2518 v &= ~GEM_MAC_XIF_GMII_MODE; 2519 } else 2520 /* Internal MII needs buf enable */ 2521 v |= GEM_MAC_XIF_MII_BUF_ENA; 2522 /* MII needs echo disable if half duplex. */ 2523 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2524 /* turn on full duplex LED */ 2525 v |= GEM_MAC_XIF_FDPLX_LED; 2526 else 2527 /* half duplex -- disable echo */ 2528 v |= GEM_MAC_XIF_ECHO_DISABL; 2529 } else { 2530 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2531 v |= GEM_MAC_XIF_FDPLX_LED; 2532 v |= GEM_MAC_XIF_GMII_MODE; 2533 } 2534 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2535 2536 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2537 (sc->sc_flags & GEM_LINK) != 0) { 2538 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2539 txcfg | GEM_MAC_TX_ENABLE); 2540 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2541 rxcfg | GEM_MAC_RX_ENABLE); 2542 } 2543 } 2544 2545 int 2546 gem_ser_mediachange(struct ifnet *ifp) 2547 { 2548 struct gem_softc *sc = ifp->if_softc; 2549 u_int s, t; 2550 2551 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2552 return EINVAL; 2553 2554 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2555 if (s == IFM_AUTO) { 2556 if (sc->sc_mii_media != s) { 2557 #ifdef GEM_DEBUG 2558 aprint_debug_dev(sc->sc_dev, "setting media to auto\n"); 2559 #endif 2560 sc->sc_mii_media = s; 2561 if (ifp->if_flags & IFF_UP) { 2562 gem_pcs_stop(sc, 0); 2563 gem_pcs_start(sc); 2564 } 2565 } 2566 return 0; 2567 } 2568 if (s == IFM_1000_SX) { 2569 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media); 2570 if (t == IFM_FDX || t == IFM_HDX) { 2571 if (sc->sc_mii_media != t) { 2572 sc->sc_mii_media = t; 2573 #ifdef GEM_DEBUG 2574 aprint_debug_dev(sc->sc_dev, 2575 "setting media to 1000baseSX-%s\n", 2576 t == IFM_FDX ? "FDX" : "HDX"); 2577 #endif 2578 if (ifp->if_flags & IFF_UP) { 2579 gem_pcs_stop(sc, 0); 2580 gem_pcs_start(sc); 2581 } 2582 } 2583 return 0; 2584 } 2585 } 2586 return EINVAL; 2587 } 2588 2589 void 2590 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2591 { 2592 struct gem_softc *sc = ifp->if_softc; 2593 2594 if ((ifp->if_flags & IFF_UP) == 0) 2595 return; 2596 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2597 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2598 } 2599 2600 static int 2601 gem_ifflags_cb(struct ethercom *ec) 2602 { 2603 struct ifnet *ifp = &ec->ec_if; 2604 struct gem_softc *sc = ifp->if_softc; 2605 int change = ifp->if_flags ^ sc->sc_if_flags; 2606 2607 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 2608 return ENETRESET; 2609 else if ((change & IFF_PROMISC) != 0) 2610 gem_setladrf(sc); 2611 return 0; 2612 } 2613 2614 /* 2615 * Process an ioctl request. 2616 */ 2617 int 2618 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 2619 { 2620 struct gem_softc *sc = ifp->if_softc; 2621 int s, error = 0; 2622 2623 s = splnet(); 2624 2625 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2626 error = 0; 2627 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2628 ; 2629 else if (ifp->if_flags & IFF_RUNNING) { 2630 /* 2631 * Multicast list has changed; set the hardware filter 2632 * accordingly. 2633 */ 2634 gem_setladrf(sc); 2635 } 2636 } 2637 2638 /* Try to get things going again */ 2639 if (ifp->if_flags & IFF_UP) 2640 gem_start(ifp); 2641 splx(s); 2642 return (error); 2643 } 2644 2645 static void 2646 gem_inten(struct gem_softc *sc) 2647 { 2648 bus_space_tag_t t = sc->sc_bustag; 2649 bus_space_handle_t h = sc->sc_h1; 2650 uint32_t v; 2651 2652 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 2653 v = GEM_INTR_PCS; 2654 else 2655 v = GEM_INTR_MIF; 2656 bus_space_write_4(t, h, GEM_INTMASK, 2657 ~(GEM_INTR_TX_INTME | 2658 GEM_INTR_TX_EMPTY | 2659 GEM_INTR_TX_MAC | 2660 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF| 2661 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL| 2662 GEM_INTR_BERR | v)); 2663 } 2664 2665 bool 2666 gem_resume(device_t self, const pmf_qual_t *qual) 2667 { 2668 struct gem_softc *sc = device_private(self); 2669 2670 gem_inten(sc); 2671 2672 return true; 2673 } 2674 2675 bool 2676 gem_suspend(device_t self, const pmf_qual_t *qual) 2677 { 2678 struct gem_softc *sc = device_private(self); 2679 bus_space_tag_t t = sc->sc_bustag; 2680 bus_space_handle_t h = sc->sc_h1; 2681 2682 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 2683 2684 return true; 2685 } 2686 2687 bool 2688 gem_shutdown(device_t self, int howto) 2689 { 2690 struct gem_softc *sc = device_private(self); 2691 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2692 2693 gem_stop(ifp, 1); 2694 2695 return true; 2696 } 2697 2698 /* 2699 * Set up the logical address filter. 2700 */ 2701 void 2702 gem_setladrf(struct gem_softc *sc) 2703 { 2704 struct ethercom *ec = &sc->sc_ethercom; 2705 struct ifnet *ifp = &ec->ec_if; 2706 struct ether_multi *enm; 2707 struct ether_multistep step; 2708 bus_space_tag_t t = sc->sc_bustag; 2709 bus_space_handle_t h = sc->sc_h1; 2710 u_int32_t crc; 2711 u_int32_t hash[16]; 2712 u_int32_t v; 2713 int i; 2714 2715 /* Get current RX configuration */ 2716 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2717 2718 /* 2719 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2720 * and hash filter. Depending on the case, the right bit will be 2721 * enabled. 2722 */ 2723 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2724 GEM_MAC_RX_PROMISC_GRP); 2725 2726 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2727 /* Turn on promiscuous mode */ 2728 v |= GEM_MAC_RX_PROMISCUOUS; 2729 ifp->if_flags |= IFF_ALLMULTI; 2730 goto chipit; 2731 } 2732 2733 /* 2734 * Set up multicast address filter by passing all multicast addresses 2735 * through a crc generator, and then using the high order 8 bits as an 2736 * index into the 256 bit logical address filter. The high order 4 2737 * bits selects the word, while the other 4 bits select the bit within 2738 * the word (where bit 0 is the MSB). 2739 */ 2740 2741 /* Clear hash table */ 2742 memset(hash, 0, sizeof(hash)); 2743 2744 ETHER_FIRST_MULTI(step, ec, enm); 2745 while (enm != NULL) { 2746 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2747 /* 2748 * We must listen to a range of multicast addresses. 2749 * For now, just accept all multicasts, rather than 2750 * trying to set only those filter bits needed to match 2751 * the range. (At this time, the only use of address 2752 * ranges is for IP multicast routing, for which the 2753 * range is big enough to require all bits set.) 2754 * XXX should use the address filters for this 2755 */ 2756 ifp->if_flags |= IFF_ALLMULTI; 2757 v |= GEM_MAC_RX_PROMISC_GRP; 2758 goto chipit; 2759 } 2760 2761 /* Get the LE CRC32 of the address */ 2762 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2763 2764 /* Just want the 8 most significant bits. */ 2765 crc >>= 24; 2766 2767 /* Set the corresponding bit in the filter. */ 2768 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2769 2770 ETHER_NEXT_MULTI(step, enm); 2771 } 2772 2773 v |= GEM_MAC_RX_HASH_FILTER; 2774 ifp->if_flags &= ~IFF_ALLMULTI; 2775 2776 /* Now load the hash table into the chip (if we are using it) */ 2777 for (i = 0; i < 16; i++) { 2778 bus_space_write_4(t, h, 2779 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2780 hash[i]); 2781 } 2782 2783 chipit: 2784 sc->sc_if_flags = ifp->if_flags; 2785 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2786 } 2787