1 /* $NetBSD: gem.c,v 1.129 2020/03/01 05:50:56 thorpej Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.129 2020/03/01 05:50:56 thorpej Exp $"); 41 42 #include "opt_inet.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/callout.h> 47 #include <sys/mbuf.h> 48 #include <sys/syslog.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/device.h> 55 56 #include <machine/endian.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #include <net/bpf.h> 73 74 #include <sys/bus.h> 75 #include <sys/intr.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/ic/gemreg.h> 82 #include <dev/ic/gemvar.h> 83 84 #define TRIES 10000 85 86 static void gem_inten(struct gem_softc *); 87 static void gem_start(struct ifnet *); 88 static void gem_stop(struct ifnet *, int); 89 int gem_ioctl(struct ifnet *, u_long, void *); 90 void gem_tick(void *); 91 void gem_watchdog(struct ifnet *); 92 void gem_rx_watchdog(void *); 93 void gem_pcs_start(struct gem_softc *sc); 94 void gem_pcs_stop(struct gem_softc *sc, int); 95 int gem_init(struct ifnet *); 96 void gem_init_regs(struct gem_softc *sc); 97 static int gem_ringsize(int sz); 98 static int gem_meminit(struct gem_softc *); 99 void gem_mifinit(struct gem_softc *); 100 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 101 uint32_t, uint32_t); 102 void gem_reset(struct gem_softc *); 103 int gem_reset_rx(struct gem_softc *sc); 104 static void gem_reset_rxdma(struct gem_softc *sc); 105 static void gem_rx_common(struct gem_softc *sc); 106 int gem_reset_tx(struct gem_softc *sc); 107 int gem_disable_rx(struct gem_softc *sc); 108 int gem_disable_tx(struct gem_softc *sc); 109 static void gem_rxdrain(struct gem_softc *sc); 110 int gem_add_rxbuf(struct gem_softc *sc, int idx); 111 void gem_setladrf(struct gem_softc *); 112 113 /* MII methods & callbacks */ 114 static int gem_mii_readreg(device_t, int, int, uint16_t *); 115 static int gem_mii_writereg(device_t, int, int, uint16_t); 116 static void gem_mii_statchg(struct ifnet *); 117 118 static int gem_ifflags_cb(struct ethercom *); 119 120 void gem_statuschange(struct gem_softc *); 121 122 int gem_ser_mediachange(struct ifnet *); 123 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 124 125 static void gem_partial_detach(struct gem_softc *, enum gem_attach_stage); 126 127 struct mbuf *gem_get(struct gem_softc *, int, int); 128 int gem_put(struct gem_softc *, int, struct mbuf *); 129 void gem_read(struct gem_softc *, int, int); 130 int gem_pint(struct gem_softc *); 131 int gem_eint(struct gem_softc *, u_int); 132 int gem_rint(struct gem_softc *); 133 int gem_tint(struct gem_softc *); 134 void gem_power(int, void *); 135 136 #ifdef GEM_DEBUG 137 static void gem_txsoft_print(const struct gem_softc *, int, int); 138 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 139 printf x 140 #else 141 #define DPRINTF(sc, x) /* nothing */ 142 #endif 143 144 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 145 146 int 147 gem_detach(struct gem_softc *sc, int flags) 148 { 149 int i; 150 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 151 bus_space_tag_t t = sc->sc_bustag; 152 bus_space_handle_t h = sc->sc_h1; 153 154 /* 155 * Free any resources we've allocated during the attach. 156 * Do this in reverse order and fall through. 157 */ 158 switch (sc->sc_att_stage) { 159 case GEM_ATT_BACKEND_2: 160 case GEM_ATT_BACKEND_1: 161 case GEM_ATT_FINISHED: 162 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 163 gem_stop(&sc->sc_ethercom.ec_if, 1); 164 165 #ifdef GEM_COUNTERS 166 for (i = __arraycount(sc->sc_ev_rxhist); --i >= 0; ) 167 evcnt_detach(&sc->sc_ev_rxhist[i]); 168 evcnt_detach(&sc->sc_ev_rxnobuf); 169 evcnt_detach(&sc->sc_ev_rxfull); 170 evcnt_detach(&sc->sc_ev_rxint); 171 evcnt_detach(&sc->sc_ev_txint); 172 #endif 173 evcnt_detach(&sc->sc_ev_intr); 174 175 rnd_detach_source(&sc->rnd_source); 176 ether_ifdetach(ifp); 177 if_detach(ifp); 178 ifmedia_fini(&sc->sc_mii.mii_media); 179 180 callout_destroy(&sc->sc_tick_ch); 181 callout_destroy(&sc->sc_rx_watchdog); 182 183 /*FALLTHROUGH*/ 184 case GEM_ATT_MII: 185 sc->sc_att_stage = GEM_ATT_MII; 186 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 187 /*FALLTHROUGH*/ 188 case GEM_ATT_7: 189 for (i = 0; i < GEM_NRXDESC; i++) { 190 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 191 bus_dmamap_destroy(sc->sc_dmatag, 192 sc->sc_rxsoft[i].rxs_dmamap); 193 } 194 /*FALLTHROUGH*/ 195 case GEM_ATT_6: 196 for (i = 0; i < GEM_TXQUEUELEN; i++) { 197 if (sc->sc_txsoft[i].txs_dmamap != NULL) 198 bus_dmamap_destroy(sc->sc_dmatag, 199 sc->sc_txsoft[i].txs_dmamap); 200 } 201 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 202 /*FALLTHROUGH*/ 203 case GEM_ATT_5: 204 bus_dmamap_unload(sc->sc_dmatag, sc->sc_nulldmamap); 205 /*FALLTHROUGH*/ 206 case GEM_ATT_4: 207 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 208 /*FALLTHROUGH*/ 209 case GEM_ATT_3: 210 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 211 /*FALLTHROUGH*/ 212 case GEM_ATT_2: 213 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 214 sizeof(struct gem_control_data)); 215 /*FALLTHROUGH*/ 216 case GEM_ATT_1: 217 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 218 /*FALLTHROUGH*/ 219 case GEM_ATT_0: 220 sc->sc_att_stage = GEM_ATT_0; 221 /*FALLTHROUGH*/ 222 case GEM_ATT_BACKEND_0: 223 break; 224 } 225 return 0; 226 } 227 228 static void 229 gem_partial_detach(struct gem_softc *sc, enum gem_attach_stage stage) 230 { 231 cfattach_t ca = device_cfattach(sc->sc_dev); 232 233 sc->sc_att_stage = stage; 234 (*ca->ca_detach)(sc->sc_dev, 0); 235 } 236 237 /* 238 * gem_attach: 239 * 240 * Attach a Gem interface to the system. 241 */ 242 void 243 gem_attach(struct gem_softc *sc, const uint8_t *enaddr) 244 { 245 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 246 struct mii_data *mii = &sc->sc_mii; 247 bus_space_tag_t t = sc->sc_bustag; 248 bus_space_handle_t h = sc->sc_h1; 249 struct ifmedia_entry *ife; 250 int i, error, phyaddr; 251 uint32_t v; 252 char *nullbuf; 253 254 /* Make sure the chip is stopped. */ 255 ifp->if_softc = sc; 256 gem_reset(sc); 257 258 /* 259 * Allocate the control data structures, and create and load the 260 * DMA map for it. gem_control_data is 9216 bytes, we have space for 261 * the padding buffer in the bus_dmamem_alloc()'d memory. 262 */ 263 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 264 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 265 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 266 aprint_error_dev(sc->sc_dev, 267 "unable to allocate control data, error = %d\n", 268 error); 269 gem_partial_detach(sc, GEM_ATT_0); 270 return; 271 } 272 273 /* XXX should map this in with correct endianness */ 274 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 275 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 276 BUS_DMA_COHERENT)) != 0) { 277 aprint_error_dev(sc->sc_dev, 278 "unable to map control data, error = %d\n", error); 279 gem_partial_detach(sc, GEM_ATT_1); 280 return; 281 } 282 283 nullbuf = 284 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 285 286 if ((error = bus_dmamap_create(sc->sc_dmatag, 287 sizeof(struct gem_control_data), 1, 288 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 289 aprint_error_dev(sc->sc_dev, 290 "unable to create control data DMA map, error = %d\n", 291 error); 292 gem_partial_detach(sc, GEM_ATT_2); 293 return; 294 } 295 296 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 297 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 298 0)) != 0) { 299 aprint_error_dev(sc->sc_dev, 300 "unable to load control data DMA map, error = %d\n", 301 error); 302 gem_partial_detach(sc, GEM_ATT_3); 303 return; 304 } 305 306 memset(nullbuf, 0, ETHER_MIN_TX); 307 if ((error = bus_dmamap_create(sc->sc_dmatag, 308 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 309 aprint_error_dev(sc->sc_dev, 310 "unable to create padding DMA map, error = %d\n", error); 311 gem_partial_detach(sc, GEM_ATT_4); 312 return; 313 } 314 315 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 316 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 317 aprint_error_dev(sc->sc_dev, 318 "unable to load padding DMA map, error = %d\n", error); 319 gem_partial_detach(sc, GEM_ATT_5); 320 return; 321 } 322 323 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 324 BUS_DMASYNC_PREWRITE); 325 326 /* 327 * Initialize the transmit job descriptors. 328 */ 329 SIMPLEQ_INIT(&sc->sc_txfreeq); 330 SIMPLEQ_INIT(&sc->sc_txdirtyq); 331 332 /* 333 * Create the transmit buffer DMA maps. 334 */ 335 for (i = 0; i < GEM_TXQUEUELEN; i++) { 336 struct gem_txsoft *txs; 337 338 txs = &sc->sc_txsoft[i]; 339 txs->txs_mbuf = NULL; 340 if ((error = bus_dmamap_create(sc->sc_dmatag, 341 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 342 ETHER_MAX_LEN_JUMBO, 0, 0, 343 &txs->txs_dmamap)) != 0) { 344 aprint_error_dev(sc->sc_dev, 345 "unable to create tx DMA map %d, error = %d\n", 346 i, error); 347 gem_partial_detach(sc, GEM_ATT_6); 348 return; 349 } 350 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 351 } 352 353 /* 354 * Create the receive buffer DMA maps. 355 */ 356 for (i = 0; i < GEM_NRXDESC; i++) { 357 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 358 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 359 aprint_error_dev(sc->sc_dev, 360 "unable to create rx DMA map %d, error = %d\n", 361 i, error); 362 gem_partial_detach(sc, GEM_ATT_7); 363 return; 364 } 365 sc->sc_rxsoft[i].rxs_mbuf = NULL; 366 } 367 368 /* Initialize ifmedia structures and MII info */ 369 mii->mii_ifp = ifp; 370 mii->mii_readreg = gem_mii_readreg; 371 mii->mii_writereg = gem_mii_writereg; 372 mii->mii_statchg = gem_mii_statchg; 373 374 sc->sc_ethercom.ec_mii = mii; 375 376 /* 377 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 378 * Section 3.2.1 `Initialization Sequence'. 379 * However, we can't assume SERDES or Serialink if neither 380 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 381 * being set, as both are set on Sun X1141A (with SERDES). So, 382 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 383 * Also, for variants that report 2 PHY's, we prefer the external 384 * PHY over the internal PHY, so we look for that first. 385 */ 386 gem_mifinit(sc); 387 388 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 389 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 390 ether_mediastatus); 391 /* Look for external PHY */ 392 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 393 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 394 bus_space_write_4(t, h, GEM_MIF_CONFIG, 395 sc->sc_mif_config); 396 switch (sc->sc_variant) { 397 case GEM_SUN_ERI: 398 phyaddr = GEM_PHYAD_EXTERNAL; 399 break; 400 default: 401 phyaddr = MII_PHY_ANY; 402 break; 403 } 404 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 405 MII_OFFSET_ANY, MIIF_FORCEANEG); 406 } 407 #ifdef GEM_DEBUG 408 else 409 aprint_debug_dev(sc->sc_dev, "using external PHY\n"); 410 #endif 411 /* Look for internal PHY if no external PHY was found */ 412 if (LIST_EMPTY(&mii->mii_phys) && 413 ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI0) || 414 (sc->sc_variant == GEM_APPLE_K2_GMAC))) { 415 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 416 bus_space_write_4(t, h, GEM_MIF_CONFIG, 417 sc->sc_mif_config); 418 switch (sc->sc_variant) { 419 case GEM_SUN_ERI: 420 case GEM_APPLE_K2_GMAC: 421 phyaddr = GEM_PHYAD_INTERNAL; 422 break; 423 case GEM_APPLE_GMAC: 424 phyaddr = GEM_PHYAD_EXTERNAL; 425 break; 426 default: 427 phyaddr = MII_PHY_ANY; 428 break; 429 } 430 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 431 MII_OFFSET_ANY, MIIF_FORCEANEG); 432 #ifdef GEM_DEBUG 433 if (!LIST_EMPTY(&mii->mii_phys)) 434 aprint_debug_dev(sc->sc_dev, 435 "using internal PHY\n"); 436 #endif 437 } 438 if (LIST_EMPTY(&mii->mii_phys)) { 439 /* No PHY attached */ 440 aprint_error_dev(sc->sc_dev, 441 "PHY probe failed\n"); 442 gem_partial_detach(sc, GEM_ATT_MII); 443 return; 444 } else { 445 struct mii_softc *child; 446 447 /* 448 * Walk along the list of attached MII devices and 449 * establish an `MII instance' to `PHY number' 450 * mapping. 451 */ 452 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 453 /* 454 * Note: we support just one PHY: the internal 455 * or external MII is already selected for us 456 * by the GEM_MIF_CONFIG register. 457 */ 458 if (child->mii_phy > 1 || child->mii_inst > 0) { 459 aprint_error_dev(sc->sc_dev, 460 "cannot accommodate MII device" 461 " %s at PHY %d, instance %d\n", 462 device_xname(child->mii_dev), 463 child->mii_phy, child->mii_inst); 464 continue; 465 } 466 sc->sc_phys[child->mii_inst] = child->mii_phy; 467 } 468 469 if (sc->sc_variant != GEM_SUN_ERI) 470 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 471 GEM_MII_DATAPATH_MII); 472 473 /* 474 * XXX - we can really do the following ONLY if the 475 * PHY indeed has the auto negotiation capability!! 476 */ 477 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 478 } 479 } else { 480 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 481 gem_ser_mediastatus); 482 /* SERDES or Serialink */ 483 if (sc->sc_flags & GEM_SERDES) { 484 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 485 GEM_MII_DATAPATH_SERDES); 486 } else { 487 sc->sc_flags |= GEM_SERIAL; 488 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 489 GEM_MII_DATAPATH_SERIAL); 490 } 491 492 aprint_normal_dev(sc->sc_dev, "using external PCS %s: ", 493 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 494 495 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_AUTO, 0, NULL); 496 /* Check for FDX and HDX capabilities */ 497 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 498 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 499 ifmedia_add(&mii->mii_media, IFM_ETHER | 500 IFM_1000_SX | IFM_MANUAL | IFM_FDX, 0, NULL); 501 aprint_normal("1000baseSX-FDX, "); 502 } 503 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 504 ifmedia_add(&mii->mii_media, IFM_ETHER | 505 IFM_1000_SX | IFM_MANUAL | IFM_HDX, 0, NULL); 506 aprint_normal("1000baseSX-HDX, "); 507 } 508 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 509 sc->sc_mii_media = IFM_AUTO; 510 aprint_normal("auto\n"); 511 512 gem_pcs_stop(sc, 1); 513 } 514 515 /* 516 * From this point forward, the attachment cannot fail. A failure 517 * before this point releases all resources that may have been 518 * allocated. 519 */ 520 521 /* Announce ourselves. */ 522 aprint_normal_dev(sc->sc_dev, "Ethernet address %s", 523 ether_sprintf(enaddr)); 524 525 /* Get RX FIFO size */ 526 sc->sc_rxfifosize = 64 * 527 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 528 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 529 530 /* Get TX FIFO size */ 531 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 532 aprint_normal(", %uKB TX fifo\n", v / 16); 533 534 /* Initialize ifnet structure. */ 535 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 536 ifp->if_softc = sc; 537 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 538 sc->sc_if_flags = ifp->if_flags; 539 #if 0 540 /* 541 * The GEM hardware supports basic TCP checksum offloading only. 542 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 543 * have bugs in the receive checksum, so don't enable it for now. 544 */ 545 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 546 (GEM_IS_APPLE(sc) && 547 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 548 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 549 #endif 550 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 551 ifp->if_start = gem_start; 552 ifp->if_ioctl = gem_ioctl; 553 ifp->if_watchdog = gem_watchdog; 554 ifp->if_stop = gem_stop; 555 ifp->if_init = gem_init; 556 IFQ_SET_READY(&ifp->if_snd); 557 558 /* 559 * If we support GigE media, we support jumbo frames too. 560 * Unless we are Apple. 561 */ 562 TAILQ_FOREACH(ife, &mii->mii_media.ifm_list, ifm_list) { 563 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T || 564 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_SX || 565 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_LX || 566 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_CX) { 567 if (!GEM_IS_APPLE(sc)) 568 sc->sc_ethercom.ec_capabilities 569 |= ETHERCAP_JUMBO_MTU; 570 sc->sc_flags |= GEM_GIGABIT; 571 break; 572 } 573 } 574 575 /* claim 802.1q capability */ 576 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 577 578 /* Attach the interface. */ 579 if_attach(ifp); 580 if_deferred_start_init(ifp, NULL); 581 ether_ifattach(ifp, enaddr); 582 ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb); 583 584 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 585 RND_TYPE_NET, RND_FLAG_DEFAULT); 586 587 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 588 NULL, device_xname(sc->sc_dev), "interrupts"); 589 #ifdef GEM_COUNTERS 590 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 591 &sc->sc_ev_intr, device_xname(sc->sc_dev), "tx interrupts"); 592 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 593 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rx interrupts"); 594 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 595 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx ring full"); 596 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 597 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx malloc failure"); 598 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 599 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 0desc"); 600 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 601 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 1desc"); 602 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 603 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 2desc"); 604 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 605 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 3desc"); 606 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 607 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >3desc"); 608 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 609 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >7desc"); 610 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 611 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >15desc"); 612 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 613 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >31desc"); 614 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 615 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >63desc"); 616 #endif 617 618 callout_init(&sc->sc_tick_ch, 0); 619 callout_setfunc(&sc->sc_tick_ch, gem_tick, sc); 620 621 callout_init(&sc->sc_rx_watchdog, 0); 622 callout_setfunc(&sc->sc_rx_watchdog, gem_rx_watchdog, sc); 623 624 sc->sc_att_stage = GEM_ATT_FINISHED; 625 626 return; 627 } 628 629 void 630 gem_tick(void *arg) 631 { 632 struct gem_softc *sc = arg; 633 int s; 634 635 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 636 /* 637 * We have to reset everything if we failed to get a 638 * PCS interrupt. Restarting the callout is handled 639 * in gem_pcs_start(). 640 */ 641 gem_init(&sc->sc_ethercom.ec_if); 642 } else { 643 s = splnet(); 644 mii_tick(&sc->sc_mii); 645 splx(s); 646 callout_schedule(&sc->sc_tick_ch, hz); 647 } 648 } 649 650 static int 651 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, uint32_t clr, 652 uint32_t set) 653 { 654 int i; 655 uint32_t reg; 656 657 for (i = TRIES; i--; DELAY(100)) { 658 reg = bus_space_read_4(sc->sc_bustag, h, r); 659 if ((reg & clr) == 0 && (reg & set) == set) 660 return (1); 661 } 662 return (0); 663 } 664 665 void 666 gem_reset(struct gem_softc *sc) 667 { 668 bus_space_tag_t t = sc->sc_bustag; 669 bus_space_handle_t h = sc->sc_h2; 670 int s; 671 672 s = splnet(); 673 DPRINTF(sc, ("%s: gem_reset\n", device_xname(sc->sc_dev))); 674 gem_reset_rx(sc); 675 gem_reset_tx(sc); 676 677 /* Do a full reset */ 678 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 679 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 680 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 681 splx(s); 682 } 683 684 685 /* 686 * gem_rxdrain: 687 * 688 * Drain the receive queue. 689 */ 690 static void 691 gem_rxdrain(struct gem_softc *sc) 692 { 693 struct gem_rxsoft *rxs; 694 int i; 695 696 for (i = 0; i < GEM_NRXDESC; i++) { 697 rxs = &sc->sc_rxsoft[i]; 698 if (rxs->rxs_mbuf != NULL) { 699 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 700 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 701 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 702 m_freem(rxs->rxs_mbuf); 703 rxs->rxs_mbuf = NULL; 704 } 705 } 706 } 707 708 /* 709 * Reset the whole thing. 710 */ 711 static void 712 gem_stop(struct ifnet *ifp, int disable) 713 { 714 struct gem_softc *sc = ifp->if_softc; 715 struct gem_txsoft *txs; 716 717 DPRINTF(sc, ("%s: gem_stop\n", device_xname(sc->sc_dev))); 718 719 callout_halt(&sc->sc_tick_ch, NULL); 720 callout_halt(&sc->sc_rx_watchdog, NULL); 721 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 722 gem_pcs_stop(sc, disable); 723 else 724 mii_down(&sc->sc_mii); 725 726 /* XXX - Should we reset these instead? */ 727 gem_disable_tx(sc); 728 gem_disable_rx(sc); 729 730 /* 731 * Release any queued transmit buffers. 732 */ 733 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 734 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 735 if (txs->txs_mbuf != NULL) { 736 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 737 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 738 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 739 m_freem(txs->txs_mbuf); 740 txs->txs_mbuf = NULL; 741 } 742 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 743 } 744 745 /* 746 * Mark the interface down and cancel the watchdog timer. 747 */ 748 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 749 sc->sc_if_flags = ifp->if_flags; 750 ifp->if_timer = 0; 751 752 if (disable) 753 gem_rxdrain(sc); 754 } 755 756 757 /* 758 * Reset the receiver 759 */ 760 int 761 gem_reset_rx(struct gem_softc *sc) 762 { 763 bus_space_tag_t t = sc->sc_bustag; 764 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 765 766 /* 767 * Resetting while DMA is in progress can cause a bus hang, so we 768 * disable DMA first. 769 */ 770 gem_disable_rx(sc); 771 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 772 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 773 /* Wait till it finishes */ 774 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 775 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 776 /* Wait 5ms extra. */ 777 delay(5000); 778 779 /* Finally, reset the ERX */ 780 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 781 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 782 /* Wait till it finishes */ 783 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 784 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 785 return (1); 786 } 787 return (0); 788 } 789 790 791 /* 792 * Reset the receiver DMA engine. 793 * 794 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 795 * etc in order to reset the receiver DMA engine only and not do a full 796 * reset which amongst others also downs the link and clears the FIFOs. 797 */ 798 static void 799 gem_reset_rxdma(struct gem_softc *sc) 800 { 801 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 802 bus_space_tag_t t = sc->sc_bustag; 803 bus_space_handle_t h = sc->sc_h1; 804 int i; 805 806 if (gem_reset_rx(sc) != 0) { 807 gem_init(ifp); 808 return; 809 } 810 for (i = 0; i < GEM_NRXDESC; i++) 811 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 812 GEM_UPDATE_RXDESC(sc, i); 813 sc->sc_rxptr = 0; 814 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 815 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 816 817 /* Reprogram Descriptor Ring Base Addresses */ 818 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 819 ((uint64_t)GEM_CDRXADDR(sc, 0)) >> 32); 820 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 821 822 /* Redo ERX Configuration */ 823 gem_rx_common(sc); 824 825 /* Give the receiver a swift kick */ 826 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 827 } 828 829 /* 830 * Common RX configuration for gem_init() and gem_reset_rxdma(). 831 */ 832 static void 833 gem_rx_common(struct gem_softc *sc) 834 { 835 bus_space_tag_t t = sc->sc_bustag; 836 bus_space_handle_t h = sc->sc_h1; 837 uint32_t v; 838 839 /* Encode Receive Descriptor ring size: four possible values */ 840 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 841 842 /* Set receive h/w checksum offset */ 843 #ifdef INET 844 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 845 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 846 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 847 #endif 848 849 /* Enable RX DMA */ 850 bus_space_write_4(t, h, GEM_RX_CONFIG, 851 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 852 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 853 854 /* 855 * The following value is for an OFF Threshold of about 3/4 full 856 * and an ON Threshold of 1/4 full. 857 */ 858 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 859 (3 * sc->sc_rxfifosize / 256) | 860 ((sc->sc_rxfifosize / 256) << 12)); 861 bus_space_write_4(t, h, GEM_RX_BLANKING, 862 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 8); 863 } 864 865 /* 866 * Reset the transmitter 867 */ 868 int 869 gem_reset_tx(struct gem_softc *sc) 870 { 871 bus_space_tag_t t = sc->sc_bustag; 872 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 873 874 /* 875 * Resetting while DMA is in progress can cause a bus hang, so we 876 * disable DMA first. 877 */ 878 gem_disable_tx(sc); 879 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 880 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 881 /* Wait till it finishes */ 882 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 883 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); /* OpenBSD 1.34 */ 884 /* Wait 5ms extra. */ 885 delay(5000); 886 887 /* Finally, reset the ETX */ 888 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 889 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 890 /* Wait till it finishes */ 891 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 892 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); /* OpenBSD 1.34 */ 893 return (1); 894 } 895 return (0); 896 } 897 898 /* 899 * disable receiver. 900 */ 901 int 902 gem_disable_rx(struct gem_softc *sc) 903 { 904 bus_space_tag_t t = sc->sc_bustag; 905 bus_space_handle_t h = sc->sc_h1; 906 uint32_t cfg; 907 908 /* Flip the enable bit */ 909 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 910 cfg &= ~GEM_MAC_RX_ENABLE; 911 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 912 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 913 /* Wait for it to finish */ 914 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 915 } 916 917 /* 918 * disable transmitter. 919 */ 920 int 921 gem_disable_tx(struct gem_softc *sc) 922 { 923 bus_space_tag_t t = sc->sc_bustag; 924 bus_space_handle_t h = sc->sc_h1; 925 uint32_t cfg; 926 927 /* Flip the enable bit */ 928 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 929 cfg &= ~GEM_MAC_TX_ENABLE; 930 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 931 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 932 /* Wait for it to finish */ 933 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 934 } 935 936 /* 937 * Initialize interface. 938 */ 939 int 940 gem_meminit(struct gem_softc *sc) 941 { 942 struct gem_rxsoft *rxs; 943 int i, error; 944 945 /* 946 * Initialize the transmit descriptor ring. 947 */ 948 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 949 for (i = 0; i < GEM_NTXDESC; i++) { 950 sc->sc_txdescs[i].gd_flags = 0; 951 sc->sc_txdescs[i].gd_addr = 0; 952 } 953 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 954 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 955 sc->sc_txfree = GEM_NTXDESC-1; 956 sc->sc_txnext = 0; 957 sc->sc_txwin = 0; 958 959 /* 960 * Initialize the receive descriptor and receive job 961 * descriptor rings. 962 */ 963 for (i = 0; i < GEM_NRXDESC; i++) { 964 rxs = &sc->sc_rxsoft[i]; 965 if (rxs->rxs_mbuf == NULL) { 966 if ((error = gem_add_rxbuf(sc, i)) != 0) { 967 aprint_error_dev(sc->sc_dev, 968 "unable to allocate or map rx " 969 "buffer %d, error = %d\n", 970 i, error); 971 /* 972 * XXX Should attempt to run with fewer receive 973 * XXX buffers instead of just failing. 974 */ 975 gem_rxdrain(sc); 976 return (1); 977 } 978 } else 979 GEM_INIT_RXDESC(sc, i); 980 } 981 sc->sc_rxptr = 0; 982 sc->sc_meminited = 1; 983 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 984 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 985 986 return (0); 987 } 988 989 static int 990 gem_ringsize(int sz) 991 { 992 switch (sz) { 993 case 32: 994 return GEM_RING_SZ_32; 995 case 64: 996 return GEM_RING_SZ_64; 997 case 128: 998 return GEM_RING_SZ_128; 999 case 256: 1000 return GEM_RING_SZ_256; 1001 case 512: 1002 return GEM_RING_SZ_512; 1003 case 1024: 1004 return GEM_RING_SZ_1024; 1005 case 2048: 1006 return GEM_RING_SZ_2048; 1007 case 4096: 1008 return GEM_RING_SZ_4096; 1009 case 8192: 1010 return GEM_RING_SZ_8192; 1011 default: 1012 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 1013 return GEM_RING_SZ_32; 1014 } 1015 } 1016 1017 1018 /* 1019 * Start PCS 1020 */ 1021 void 1022 gem_pcs_start(struct gem_softc *sc) 1023 { 1024 bus_space_tag_t t = sc->sc_bustag; 1025 bus_space_handle_t h = sc->sc_h1; 1026 uint32_t v; 1027 1028 #ifdef GEM_DEBUG 1029 aprint_debug_dev(sc->sc_dev, "gem_pcs_start()\n"); 1030 #endif 1031 1032 /* 1033 * Set up. We must disable the MII before modifying the 1034 * GEM_MII_ANAR register 1035 */ 1036 if (sc->sc_flags & GEM_SERDES) { 1037 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1038 GEM_MII_DATAPATH_SERDES); 1039 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1040 GEM_MII_SLINK_LOOPBACK); 1041 } else { 1042 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1043 GEM_MII_DATAPATH_SERIAL); 1044 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 1045 } 1046 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1047 v = bus_space_read_4(t, h, GEM_MII_ANAR); 1048 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 1049 if (IFM_SUBTYPE(sc->sc_mii_media) == IFM_AUTO) 1050 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 1051 else if ((IFM_OPTIONS(sc->sc_mii_media) & IFM_FDX) != 0) { 1052 v |= GEM_MII_ANEG_FUL_DUPLX; 1053 v &= ~GEM_MII_ANEG_HLF_DUPLX; 1054 } else if ((IFM_OPTIONS(sc->sc_mii_media) & IFM_HDX) != 0) { 1055 v &= ~GEM_MII_ANEG_FUL_DUPLX; 1056 v |= GEM_MII_ANEG_HLF_DUPLX; 1057 } 1058 1059 /* Configure link. */ 1060 bus_space_write_4(t, h, GEM_MII_ANAR, v); 1061 bus_space_write_4(t, h, GEM_MII_CONTROL, 1062 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1063 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 1064 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 1065 1066 /* Start the 10 second timer */ 1067 callout_schedule(&sc->sc_tick_ch, hz * 10); 1068 } 1069 1070 /* 1071 * Stop PCS 1072 */ 1073 void 1074 gem_pcs_stop(struct gem_softc *sc, int disable) 1075 { 1076 bus_space_tag_t t = sc->sc_bustag; 1077 bus_space_handle_t h = sc->sc_h1; 1078 1079 #ifdef GEM_DEBUG 1080 aprint_debug_dev(sc->sc_dev, "gem_pcs_stop()\n"); 1081 #endif 1082 1083 /* Tell link partner that we're going away */ 1084 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1085 1086 /* 1087 * Disable PCS MII. The documentation suggests that setting 1088 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1089 * negotiation will shut down the link. However, it appears 1090 * that we also need to unset the datapath mode. 1091 */ 1092 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1093 bus_space_write_4(t, h, GEM_MII_CONTROL, 1094 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1095 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1096 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1097 1098 if (disable) { 1099 if (sc->sc_flags & GEM_SERDES) 1100 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1101 GEM_MII_SLINK_POWER_OFF); 1102 else 1103 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1104 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1105 } 1106 1107 sc->sc_flags &= ~GEM_LINK; 1108 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1109 sc->sc_mii.mii_media_status = IFM_AVALID; 1110 } 1111 1112 1113 /* 1114 * Initialization of interface; set up initialization block 1115 * and transmit/receive descriptor rings. 1116 */ 1117 int 1118 gem_init(struct ifnet *ifp) 1119 { 1120 struct gem_softc *sc = ifp->if_softc; 1121 bus_space_tag_t t = sc->sc_bustag; 1122 bus_space_handle_t h = sc->sc_h1; 1123 int rc = 0, s; 1124 u_int max_frame_size; 1125 uint32_t v; 1126 1127 s = splnet(); 1128 1129 DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(sc->sc_dev))); 1130 /* 1131 * Initialization sequence. The numbered steps below correspond 1132 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1133 * Channel Engine manual (part of the PCIO manual). 1134 * See also the STP2002-STQ document from Sun Microsystems. 1135 */ 1136 1137 /* step 1 & 2. Reset the Ethernet Channel */ 1138 gem_stop(ifp, 0); 1139 gem_reset(sc); 1140 DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(sc->sc_dev))); 1141 1142 /* Re-initialize the MIF */ 1143 gem_mifinit(sc); 1144 1145 /* Set up correct datapath for non-SERDES/Serialink */ 1146 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1147 sc->sc_variant != GEM_SUN_ERI) 1148 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1149 GEM_MII_DATAPATH_MII); 1150 1151 /* Call MI reset function if any */ 1152 if (sc->sc_hwreset) 1153 (*sc->sc_hwreset)(sc); 1154 1155 /* step 3. Setup data structures in host memory */ 1156 if (gem_meminit(sc) != 0) { 1157 splx(s); 1158 return 1; 1159 } 1160 1161 /* step 4. TX MAC registers & counters */ 1162 gem_init_regs(sc); 1163 max_frame_size = uimax(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1164 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1165 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1166 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1167 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1168 max_frame_size|/* burst size */(0x2000<<16)); 1169 1170 /* step 5. RX MAC registers & counters */ 1171 gem_setladrf(sc); 1172 1173 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1174 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 1175 ((uint64_t)GEM_CDTXADDR(sc, 0)) >> 32); 1176 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1177 1178 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 1179 ((uint64_t)GEM_CDRXADDR(sc, 0)) >> 32); 1180 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1181 1182 /* step 8. Global Configuration & Interrupt Mask */ 1183 gem_inten(sc); 1184 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1185 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1186 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1187 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1188 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1189 1190 /* step 9. ETX Configuration: use mostly default values */ 1191 1192 /* Enable TX DMA */ 1193 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1194 bus_space_write_4(t, h, GEM_TX_CONFIG, 1195 v | GEM_TX_CONFIG_TXDMA_EN | 1196 (((sc->sc_flags & GEM_GIGABIT ? 0x4FF : 0x100) << 10) & 1197 GEM_TX_CONFIG_TXFIFO_TH)); 1198 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1199 1200 /* step 10. ERX Configuration */ 1201 gem_rx_common(sc); 1202 1203 /* step 11. Configure Media */ 1204 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1205 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1206 goto out; 1207 1208 /* step 12. RX_MAC Configuration Register */ 1209 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1210 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1211 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1212 1213 /* step 14. Issue Transmit Pending command */ 1214 1215 /* Call MI initialization function if any */ 1216 if (sc->sc_hwinit) 1217 (*sc->sc_hwinit)(sc); 1218 1219 /* step 15. Give the receiver a swift kick */ 1220 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1221 1222 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1223 /* Configure PCS */ 1224 gem_pcs_start(sc); 1225 else 1226 /* Start the one second timer. */ 1227 callout_schedule(&sc->sc_tick_ch, hz); 1228 1229 sc->sc_flags &= ~GEM_LINK; 1230 ifp->if_flags |= IFF_RUNNING; 1231 ifp->if_flags &= ~IFF_OACTIVE; 1232 ifp->if_timer = 0; 1233 sc->sc_if_flags = ifp->if_flags; 1234 out: 1235 splx(s); 1236 1237 return (0); 1238 } 1239 1240 void 1241 gem_init_regs(struct gem_softc *sc) 1242 { 1243 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1244 bus_space_tag_t t = sc->sc_bustag; 1245 bus_space_handle_t h = sc->sc_h1; 1246 const u_char *laddr = CLLADDR(ifp->if_sadl); 1247 uint32_t v; 1248 1249 /* These regs are not cleared on reset */ 1250 if (!sc->sc_inited) { 1251 1252 /* Load recommended values */ 1253 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1254 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1255 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1256 1257 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1258 /* Max frame and max burst size */ 1259 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1260 ETHER_MAX_LEN | (0x2000<<16)); 1261 1262 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1263 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1264 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1265 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1266 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1267 ((laddr[5]<<8)|laddr[4])&0x3ff); 1268 1269 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1270 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1271 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1272 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1273 1274 /* MAC control addr set to 01:80:c2:00:00:01 */ 1275 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1276 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1277 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1278 1279 /* MAC filter addr set to 0:0:0:0:0:0 */ 1280 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1281 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1282 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1283 1284 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1285 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1286 1287 sc->sc_inited = 1; 1288 } 1289 1290 /* Counters need to be zeroed */ 1291 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1292 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1293 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1294 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1295 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1296 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1297 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1298 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1299 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1300 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1301 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1302 1303 /* Set XOFF PAUSE time. */ 1304 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1305 1306 /* 1307 * Set the internal arbitration to "infinite" bursts of the 1308 * maximum length of 31 * 64 bytes so DMA transfers aren't 1309 * split up in cache line size chunks. This greatly improves 1310 * especially RX performance. 1311 * Enable silicon bug workarounds for the Apple variants. 1312 */ 1313 bus_space_write_4(t, h, GEM_CONFIG, 1314 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1315 ((sc->sc_flags & GEM_PCI) ? 1316 GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1317 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1318 1319 /* 1320 * Set the station address. 1321 */ 1322 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1323 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1324 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1325 1326 /* 1327 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1328 */ 1329 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1330 v = GEM_MAC_XIF_TX_MII_ENA; 1331 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1332 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1333 v |= GEM_MAC_XIF_FDPLX_LED; 1334 if (sc->sc_flags & GEM_GIGABIT) 1335 v |= GEM_MAC_XIF_GMII_MODE; 1336 } 1337 } else { 1338 v |= GEM_MAC_XIF_GMII_MODE; 1339 } 1340 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1341 } 1342 1343 #ifdef GEM_DEBUG 1344 static void 1345 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1346 { 1347 int i; 1348 1349 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1350 printf("descriptor %d:\t", i); 1351 printf("gd_flags: 0x%016" PRIx64 "\t", 1352 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1353 printf("gd_addr: 0x%016" PRIx64 "\n", 1354 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1355 if (i == lastdesc) 1356 break; 1357 } 1358 } 1359 #endif 1360 1361 static void 1362 gem_start(struct ifnet *ifp) 1363 { 1364 struct gem_softc *sc = ifp->if_softc; 1365 struct mbuf *m0, *m; 1366 struct gem_txsoft *txs; 1367 bus_dmamap_t dmamap; 1368 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1369 #ifdef GEM_DEBUG 1370 int otxnext; 1371 #endif 1372 uint64_t flags = 0; 1373 1374 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1375 return; 1376 1377 /* 1378 * Remember the previous number of free descriptors and 1379 * the first descriptor we'll use. 1380 */ 1381 ofree = sc->sc_txfree; 1382 #ifdef GEM_DEBUG 1383 otxnext = sc->sc_txnext; 1384 #endif 1385 1386 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1387 device_xname(sc->sc_dev), ofree, otxnext)); 1388 1389 /* 1390 * Loop through the send queue, setting up transmit descriptors 1391 * until we drain the queue, or use up all available transmit 1392 * descriptors. 1393 */ 1394 #ifdef INET 1395 next: 1396 #endif 1397 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1398 sc->sc_txfree != 0) { 1399 /* 1400 * Grab a packet off the queue. 1401 */ 1402 IFQ_POLL(&ifp->if_snd, m0); 1403 if (m0 == NULL) 1404 break; 1405 m = NULL; 1406 1407 dmamap = txs->txs_dmamap; 1408 1409 /* 1410 * Load the DMA map. If this fails, the packet either 1411 * didn't fit in the alloted number of segments, or we were 1412 * short on resources. In this case, we'll copy and try 1413 * again. 1414 */ 1415 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1416 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0 || 1417 (m0->m_pkthdr.len < ETHER_MIN_TX && 1418 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1419 if (m0->m_pkthdr.len > MCLBYTES) { 1420 aprint_error_dev(sc->sc_dev, 1421 "unable to allocate jumbo Tx cluster\n"); 1422 IFQ_DEQUEUE(&ifp->if_snd, m0); 1423 m_freem(m0); 1424 continue; 1425 } 1426 MGETHDR(m, M_DONTWAIT, MT_DATA); 1427 if (m == NULL) { 1428 aprint_error_dev(sc->sc_dev, 1429 "unable to allocate Tx mbuf\n"); 1430 break; 1431 } 1432 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1433 if (m0->m_pkthdr.len > MHLEN) { 1434 MCLGET(m, M_DONTWAIT); 1435 if ((m->m_flags & M_EXT) == 0) { 1436 aprint_error_dev(sc->sc_dev, 1437 "unable to allocate Tx cluster\n"); 1438 m_freem(m); 1439 break; 1440 } 1441 } 1442 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1443 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1444 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1445 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1446 if (error) { 1447 aprint_error_dev(sc->sc_dev, 1448 "unable to load Tx buffer, error = %d\n", 1449 error); 1450 break; 1451 } 1452 } 1453 1454 /* 1455 * Ensure we have enough descriptors free to describe 1456 * the packet. 1457 */ 1458 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1459 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1460 /* 1461 * Not enough free descriptors to transmit this 1462 * packet. We haven't committed to anything yet, 1463 * so just unload the DMA map, put the packet 1464 * back on the queue, and punt. Notify the upper 1465 * layer that there are no more slots left. 1466 * 1467 * XXX We could allocate an mbuf and copy, but 1468 * XXX it is worth it? 1469 */ 1470 ifp->if_flags |= IFF_OACTIVE; 1471 sc->sc_if_flags = ifp->if_flags; 1472 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1473 if (m != NULL) 1474 m_freem(m); 1475 break; 1476 } 1477 1478 IFQ_DEQUEUE(&ifp->if_snd, m0); 1479 if (m != NULL) { 1480 m_freem(m0); 1481 m0 = m; 1482 } 1483 1484 /* 1485 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1486 */ 1487 1488 /* Sync the DMA map. */ 1489 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1490 BUS_DMASYNC_PREWRITE); 1491 1492 /* 1493 * Initialize the transmit descriptors. 1494 */ 1495 firsttx = sc->sc_txnext; 1496 for (nexttx = firsttx, seg = 0; 1497 seg < dmamap->dm_nsegs; 1498 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1499 1500 /* 1501 * If this is the first descriptor we're 1502 * enqueueing, set the start of packet flag, 1503 * and the checksum stuff if we want the hardware 1504 * to do it. 1505 */ 1506 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1507 if (nexttx == firsttx) { 1508 flags |= GEM_TD_START_OF_PACKET; 1509 #ifdef INET 1510 /* h/w checksum */ 1511 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1512 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1513 struct ether_header *eh; 1514 uint16_t offset, start; 1515 1516 eh = mtod(m0, struct ether_header *); 1517 switch (ntohs(eh->ether_type)) { 1518 case ETHERTYPE_IP: 1519 start = ETHER_HDR_LEN; 1520 break; 1521 case ETHERTYPE_VLAN: 1522 start = ETHER_HDR_LEN + 1523 ETHER_VLAN_ENCAP_LEN; 1524 break; 1525 default: 1526 /* unsupported, drop it */ 1527 bus_dmamap_unload(sc->sc_dmatag, 1528 dmamap); 1529 m_freem(m0); 1530 goto next; 1531 } 1532 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1533 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1534 flags |= (start << 1535 GEM_TD_CXSUM_STARTSHFT) | 1536 (offset << 1537 GEM_TD_CXSUM_STUFFSHFT) | 1538 GEM_TD_CXSUM_ENABLE; 1539 } 1540 #endif 1541 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1542 sc->sc_txwin = 0; 1543 flags |= GEM_TD_INTERRUPT_ME; 1544 } 1545 } 1546 sc->sc_txdescs[nexttx].gd_addr = 1547 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1548 if (seg == dmamap->dm_nsegs - 1) { 1549 flags |= GEM_TD_END_OF_PACKET; 1550 } else { 1551 /* last flag set outside of loop */ 1552 sc->sc_txdescs[nexttx].gd_flags = 1553 GEM_DMA_WRITE(sc, flags); 1554 } 1555 lasttx = nexttx; 1556 } 1557 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1558 /* add padding buffer at end of chain */ 1559 flags &= ~GEM_TD_END_OF_PACKET; 1560 sc->sc_txdescs[lasttx].gd_flags = 1561 GEM_DMA_WRITE(sc, flags); 1562 1563 sc->sc_txdescs[nexttx].gd_addr = 1564 GEM_DMA_WRITE(sc, 1565 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1566 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1567 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1568 lasttx = nexttx; 1569 nexttx = GEM_NEXTTX(nexttx); 1570 seg++; 1571 } 1572 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1573 1574 KASSERT(lasttx != -1); 1575 1576 /* 1577 * Store a pointer to the packet so we can free it later, 1578 * and remember what txdirty will be once the packet is 1579 * done. 1580 */ 1581 txs->txs_mbuf = m0; 1582 txs->txs_firstdesc = sc->sc_txnext; 1583 txs->txs_lastdesc = lasttx; 1584 txs->txs_ndescs = seg; 1585 1586 #ifdef GEM_DEBUG 1587 if (ifp->if_flags & IFF_DEBUG) { 1588 printf(" gem_start %p transmit chain:\n", txs); 1589 gem_txsoft_print(sc, txs->txs_firstdesc, 1590 txs->txs_lastdesc); 1591 } 1592 #endif 1593 1594 /* Sync the descriptors we're using. */ 1595 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1596 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1597 1598 /* Advance the tx pointer. */ 1599 sc->sc_txfree -= txs->txs_ndescs; 1600 sc->sc_txnext = nexttx; 1601 1602 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1603 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1604 1605 /* 1606 * Pass the packet to any BPF listeners. 1607 */ 1608 bpf_mtap(ifp, m0, BPF_D_OUT); 1609 } 1610 1611 if (txs == NULL || sc->sc_txfree == 0) { 1612 /* No more slots left; notify upper layer. */ 1613 ifp->if_flags |= IFF_OACTIVE; 1614 sc->sc_if_flags = ifp->if_flags; 1615 } 1616 1617 if (sc->sc_txfree != ofree) { 1618 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1619 device_xname(sc->sc_dev), lasttx, otxnext)); 1620 /* 1621 * The entire packet chain is set up. 1622 * Kick the transmitter. 1623 */ 1624 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1625 device_xname(sc->sc_dev), nexttx)); 1626 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1627 sc->sc_txnext); 1628 1629 /* Set a watchdog timer in case the chip flakes out. */ 1630 ifp->if_timer = 5; 1631 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1632 device_xname(sc->sc_dev), ifp->if_timer)); 1633 } 1634 } 1635 1636 /* 1637 * Transmit interrupt. 1638 */ 1639 int 1640 gem_tint(struct gem_softc *sc) 1641 { 1642 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1643 bus_space_tag_t t = sc->sc_bustag; 1644 bus_space_handle_t mac = sc->sc_h1; 1645 struct gem_txsoft *txs; 1646 int txlast; 1647 int progress = 0; 1648 uint32_t v; 1649 1650 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1651 1652 DPRINTF(sc, ("%s: gem_tint\n", device_xname(sc->sc_dev))); 1653 1654 /* Unload collision counters ... */ 1655 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1656 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1657 if_statadd_ref(nsr, if_collisions, v + 1658 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1659 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT)); 1660 if_statadd_ref(nsr, if_oerrors, v); 1661 1662 /* ... then clear the hardware counters. */ 1663 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1664 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1665 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1666 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1667 1668 /* 1669 * Go through our Tx list and free mbufs for those 1670 * frames that have been transmitted. 1671 */ 1672 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1673 /* 1674 * In theory, we could harvest some descriptors before 1675 * the ring is empty, but that's a bit complicated. 1676 * 1677 * GEM_TX_COMPLETION points to the last descriptor 1678 * processed +1. 1679 * 1680 * Let's assume that the NIC writes back to the Tx 1681 * descriptors before it updates the completion 1682 * register. If the NIC has posted writes to the 1683 * Tx descriptors, PCI ordering requires that the 1684 * posted writes flush to RAM before the register-read 1685 * finishes. So let's read the completion register, 1686 * before syncing the descriptors, so that we 1687 * examine Tx descriptors that are at least as 1688 * current as the completion register. 1689 */ 1690 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1691 DPRINTF(sc, 1692 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1693 txs->txs_lastdesc, txlast)); 1694 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1695 if (txlast >= txs->txs_firstdesc && 1696 txlast <= txs->txs_lastdesc) 1697 break; 1698 } else if (txlast >= txs->txs_firstdesc || 1699 txlast <= txs->txs_lastdesc) 1700 break; 1701 1702 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1703 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1704 1705 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1706 if (ifp->if_flags & IFF_DEBUG) { 1707 printf(" txsoft %p transmit chain:\n", txs); 1708 gem_txsoft_print(sc, txs->txs_firstdesc, 1709 txs->txs_lastdesc); 1710 } 1711 #endif 1712 1713 1714 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1715 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1716 1717 sc->sc_txfree += txs->txs_ndescs; 1718 1719 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1720 0, txs->txs_dmamap->dm_mapsize, 1721 BUS_DMASYNC_POSTWRITE); 1722 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1723 if (txs->txs_mbuf != NULL) { 1724 m_freem(txs->txs_mbuf); 1725 txs->txs_mbuf = NULL; 1726 } 1727 1728 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1729 1730 if_statinc_ref(nsr, if_opackets); 1731 progress = 1; 1732 } 1733 1734 IF_STAT_PUTREF(ifp); 1735 1736 #if 0 1737 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1738 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1739 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1740 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1741 GEM_TX_DATA_PTR_HI) << 32) | 1742 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1743 GEM_TX_DATA_PTR_LO), 1744 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1745 #endif 1746 1747 if (progress) { 1748 if (sc->sc_txfree == GEM_NTXDESC - 1) 1749 sc->sc_txwin = 0; 1750 1751 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1752 ifp->if_flags &= ~IFF_OACTIVE; 1753 sc->sc_if_flags = ifp->if_flags; 1754 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1755 if_schedule_deferred_start(ifp); 1756 } 1757 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1758 device_xname(sc->sc_dev), ifp->if_timer)); 1759 1760 return (1); 1761 } 1762 1763 /* 1764 * Receive interrupt. 1765 */ 1766 int 1767 gem_rint(struct gem_softc *sc) 1768 { 1769 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1770 bus_space_tag_t t = sc->sc_bustag; 1771 bus_space_handle_t h = sc->sc_h1; 1772 struct gem_rxsoft *rxs; 1773 struct mbuf *m; 1774 uint64_t rxstat; 1775 uint32_t rxcomp; 1776 int i, len, progress = 0; 1777 1778 DPRINTF(sc, ("%s: gem_rint\n", device_xname(sc->sc_dev))); 1779 1780 /* 1781 * Ignore spurious interrupt that sometimes occurs before 1782 * we are set up when we network boot. 1783 */ 1784 if (!sc->sc_meminited) 1785 return 1; 1786 1787 /* 1788 * Read the completion register once. This limits 1789 * how long the following loop can execute. 1790 */ 1791 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1792 1793 /* 1794 * XXX Read the lastrx only once at the top for speed. 1795 */ 1796 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1797 sc->sc_rxptr, rxcomp)); 1798 1799 /* 1800 * Go into the loop at least once. 1801 */ 1802 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1803 i = GEM_NEXTRX(i)) { 1804 rxs = &sc->sc_rxsoft[i]; 1805 1806 GEM_CDRXSYNC(sc, i, 1807 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1808 1809 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1810 1811 if (rxstat & GEM_RD_OWN) { 1812 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1813 /* 1814 * We have processed all of the receive buffers. 1815 */ 1816 break; 1817 } 1818 1819 progress++; 1820 1821 if (rxstat & GEM_RD_BAD_CRC) { 1822 if_statinc(ifp, if_ierrors); 1823 aprint_error_dev(sc->sc_dev, 1824 "receive error: CRC error\n"); 1825 GEM_INIT_RXDESC(sc, i); 1826 continue; 1827 } 1828 1829 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1830 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1831 #ifdef GEM_DEBUG 1832 if (ifp->if_flags & IFF_DEBUG) { 1833 printf(" rxsoft %p descriptor %d: ", rxs, i); 1834 printf("gd_flags: 0x%016llx\t", (long long) 1835 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1836 printf("gd_addr: 0x%016llx\n", (long long) 1837 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1838 } 1839 #endif 1840 1841 /* No errors; receive the packet. */ 1842 len = GEM_RD_BUFLEN(rxstat); 1843 1844 /* 1845 * Allocate a new mbuf cluster. If that fails, we are 1846 * out of memory, and must drop the packet and recycle 1847 * the buffer that's already attached to this descriptor. 1848 */ 1849 m = rxs->rxs_mbuf; 1850 if (gem_add_rxbuf(sc, i) != 0) { 1851 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1852 if_statinc(ifp, if_ierrors); 1853 aprint_error_dev(sc->sc_dev, 1854 "receive error: RX no buffer space\n"); 1855 GEM_INIT_RXDESC(sc, i); 1856 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1857 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1858 continue; 1859 } 1860 m->m_data += 2; /* We're already off by two */ 1861 1862 m_set_rcvif(m, ifp); 1863 m->m_pkthdr.len = m->m_len = len; 1864 1865 #ifdef INET 1866 /* hardware checksum */ 1867 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1868 struct ether_header *eh; 1869 struct ip *ip; 1870 int32_t hlen, pktlen; 1871 1872 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1873 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1874 ETHER_VLAN_ENCAP_LEN; 1875 eh = (struct ether_header *) (mtod(m, char *) + 1876 ETHER_VLAN_ENCAP_LEN); 1877 } else { 1878 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1879 eh = mtod(m, struct ether_header *); 1880 } 1881 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1882 goto swcsum; 1883 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1884 1885 /* IPv4 only */ 1886 if (ip->ip_v != IPVERSION) 1887 goto swcsum; 1888 1889 hlen = ip->ip_hl << 2; 1890 if (hlen < sizeof(struct ip)) 1891 goto swcsum; 1892 1893 /* 1894 * bail if too short, has random trailing garbage, 1895 * truncated, fragment, or has ethernet pad. 1896 */ 1897 if ((ntohs(ip->ip_len) < hlen) || 1898 (ntohs(ip->ip_len) != pktlen) || 1899 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1900 goto swcsum; 1901 1902 switch (ip->ip_p) { 1903 case IPPROTO_TCP: 1904 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1905 goto swcsum; 1906 if (pktlen < (hlen + sizeof(struct tcphdr))) 1907 goto swcsum; 1908 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1909 break; 1910 case IPPROTO_UDP: 1911 /* FALLTHROUGH */ 1912 default: 1913 goto swcsum; 1914 } 1915 1916 /* the uncomplemented sum is expected */ 1917 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1918 1919 /* if the pkt had ip options, we have to deduct them */ 1920 if (hlen > sizeof(struct ip)) { 1921 uint16_t *opts; 1922 uint32_t optsum, temp; 1923 1924 optsum = 0; 1925 temp = hlen - sizeof(struct ip); 1926 opts = (uint16_t *) ((char *) ip + 1927 sizeof(struct ip)); 1928 1929 while (temp > 1) { 1930 optsum += ntohs(*opts++); 1931 temp -= 2; 1932 } 1933 while (optsum >> 16) 1934 optsum = (optsum >> 16) + 1935 (optsum & 0xffff); 1936 1937 /* Deduct ip opts sum from hwsum. */ 1938 m->m_pkthdr.csum_data += (uint16_t)~optsum; 1939 1940 while (m->m_pkthdr.csum_data >> 16) 1941 m->m_pkthdr.csum_data = 1942 (m->m_pkthdr.csum_data >> 16) + 1943 (m->m_pkthdr.csum_data & 1944 0xffff); 1945 } 1946 1947 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1948 M_CSUM_NO_PSEUDOHDR; 1949 } else 1950 swcsum: 1951 m->m_pkthdr.csum_flags = 0; 1952 #endif 1953 /* Pass it on. */ 1954 if_percpuq_enqueue(ifp->if_percpuq, m); 1955 } 1956 1957 if (progress) { 1958 /* Update the receive pointer. */ 1959 if (i == sc->sc_rxptr) { 1960 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1961 #ifdef GEM_DEBUG 1962 if (ifp->if_flags & IFF_DEBUG) 1963 printf("%s: rint: ring wrap\n", 1964 device_xname(sc->sc_dev)); 1965 #endif 1966 } 1967 sc->sc_rxptr = i; 1968 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1969 } 1970 #ifdef GEM_COUNTERS 1971 if (progress <= 4) { 1972 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1973 } else if (progress < 32) { 1974 if (progress < 16) 1975 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1976 else 1977 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1978 1979 } else { 1980 if (progress < 64) 1981 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1982 else 1983 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1984 } 1985 #endif 1986 1987 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1988 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1989 1990 /* Read error counters ... */ 1991 if_statadd(ifp, if_ierrors, 1992 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1993 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1994 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1995 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL)); 1996 1997 /* ... then clear the hardware counters. */ 1998 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1999 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 2000 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 2001 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 2002 2003 return (1); 2004 } 2005 2006 2007 /* 2008 * gem_add_rxbuf: 2009 * 2010 * Add a receive buffer to the indicated descriptor. 2011 */ 2012 int 2013 gem_add_rxbuf(struct gem_softc *sc, int idx) 2014 { 2015 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2016 struct mbuf *m; 2017 int error; 2018 2019 MGETHDR(m, M_DONTWAIT, MT_DATA); 2020 if (m == NULL) 2021 return (ENOBUFS); 2022 2023 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2024 MCLGET(m, M_DONTWAIT); 2025 if ((m->m_flags & M_EXT) == 0) { 2026 m_freem(m); 2027 return (ENOBUFS); 2028 } 2029 2030 #ifdef GEM_DEBUG 2031 /* bzero the packet to check DMA */ 2032 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 2033 #endif 2034 2035 if (rxs->rxs_mbuf != NULL) 2036 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 2037 2038 rxs->rxs_mbuf = m; 2039 2040 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 2041 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2042 BUS_DMA_READ | BUS_DMA_NOWAIT); 2043 if (error) { 2044 aprint_error_dev(sc->sc_dev, 2045 "can't load rx DMA map %d, error = %d\n", idx, error); 2046 panic("gem_add_rxbuf"); /* XXX */ 2047 } 2048 2049 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 2050 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2051 2052 GEM_INIT_RXDESC(sc, idx); 2053 2054 return (0); 2055 } 2056 2057 2058 int 2059 gem_eint(struct gem_softc *sc, u_int status) 2060 { 2061 char bits[128]; 2062 uint32_t r, v; 2063 2064 if ((status & GEM_INTR_MIF) != 0) { 2065 printf("%s: XXXlink status changed\n", device_xname(sc->sc_dev)); 2066 return (1); 2067 } 2068 2069 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 2070 gem_reset_rxdma(sc); 2071 return (1); 2072 } 2073 2074 if (status & GEM_INTR_BERR) { 2075 if (sc->sc_flags & GEM_PCI) 2076 r = GEM_ERROR_STATUS; 2077 else 2078 r = GEM_SBUS_ERROR_STATUS; 2079 bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2080 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2081 aprint_error_dev(sc->sc_dev, "bus error interrupt: 0x%02x\n", 2082 v); 2083 return (1); 2084 } 2085 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2086 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 2087 2088 return (1); 2089 } 2090 2091 2092 /* 2093 * PCS interrupts. 2094 * We should receive these when the link status changes, but sometimes 2095 * we don't receive them for link up. We compensate for this in the 2096 * gem_tick() callout. 2097 */ 2098 int 2099 gem_pint(struct gem_softc *sc) 2100 { 2101 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2102 bus_space_tag_t t = sc->sc_bustag; 2103 bus_space_handle_t h = sc->sc_h1; 2104 uint32_t v, v2; 2105 2106 /* 2107 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2108 * latched, so we have to read it twice. There is only one bit in 2109 * use, so the value is meaningless. 2110 */ 2111 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2112 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2113 2114 if ((ifp->if_flags & IFF_UP) == 0) 2115 return 1; 2116 2117 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2118 return 1; 2119 2120 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2121 /* If we see remote fault, our link partner is probably going away */ 2122 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2123 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2124 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2125 /* Otherwise, we may need to wait after auto-negotiation completes */ 2126 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2127 GEM_MII_STATUS_ANEG_CPT) { 2128 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2129 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2130 } 2131 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2132 if (sc->sc_flags & GEM_LINK) { 2133 return 1; 2134 } 2135 callout_stop(&sc->sc_tick_ch); 2136 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2137 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2138 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2139 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2140 v &= v2; 2141 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2142 sc->sc_mii.mii_media_active |= IFM_FDX; 2143 #ifdef GEM_DEBUG 2144 aprint_debug_dev(sc->sc_dev, "link up: full duplex\n"); 2145 #endif 2146 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2147 sc->sc_mii.mii_media_active |= IFM_HDX; 2148 #ifdef GEM_DEBUG 2149 aprint_debug_dev(sc->sc_dev, "link up: half duplex\n"); 2150 #endif 2151 } else { 2152 #ifdef GEM_DEBUG 2153 aprint_debug_dev(sc->sc_dev, "duplex mismatch\n"); 2154 #endif 2155 } 2156 gem_statuschange(sc); 2157 } else { 2158 if ((sc->sc_flags & GEM_LINK) == 0) { 2159 return 1; 2160 } 2161 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2162 sc->sc_mii.mii_media_status = IFM_AVALID; 2163 #ifdef GEM_DEBUG 2164 aprint_debug_dev(sc->sc_dev, "link down\n"); 2165 #endif 2166 gem_statuschange(sc); 2167 2168 /* Start the 10 second timer */ 2169 callout_schedule(&sc->sc_tick_ch, hz * 10); 2170 } 2171 return 1; 2172 } 2173 2174 2175 2176 int 2177 gem_intr(void *v) 2178 { 2179 struct gem_softc *sc = v; 2180 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2181 bus_space_tag_t t = sc->sc_bustag; 2182 bus_space_handle_t h = sc->sc_h1; 2183 uint32_t status; 2184 int r = 0; 2185 #ifdef GEM_DEBUG 2186 char bits[128]; 2187 #endif 2188 2189 /* XXX We should probably mask out interrupts until we're done */ 2190 2191 sc->sc_ev_intr.ev_count++; 2192 2193 status = bus_space_read_4(t, h, GEM_STATUS); 2194 #ifdef GEM_DEBUG 2195 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2196 #endif 2197 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2198 device_xname(sc->sc_dev), (status >> 19), bits)); 2199 2200 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2201 r |= gem_eint(sc, status); 2202 2203 /* We don't bother with GEM_INTR_TX_DONE */ 2204 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2205 GEM_COUNTER_INCR(sc, sc_ev_txint); 2206 r |= gem_tint(sc); 2207 } 2208 2209 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2210 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2211 r |= gem_rint(sc); 2212 } 2213 2214 /* We should eventually do more than just print out error stats. */ 2215 if (status & GEM_INTR_TX_MAC) { 2216 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2217 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2218 printf("%s: MAC tx fault, status %x\n", 2219 device_xname(sc->sc_dev), txstat); 2220 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2221 gem_init(ifp); 2222 } 2223 if (status & GEM_INTR_RX_MAC) { 2224 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2225 /* 2226 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2227 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2228 * silicon bug so handle them silently. So if we detect 2229 * an RX FIFO overflow, we fire off a timer, and check 2230 * whether we're still making progress by looking at the 2231 * RX FIFO write and read pointers. 2232 */ 2233 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2234 if_statinc(ifp, if_ierrors); 2235 aprint_error_dev(sc->sc_dev, 2236 "receive error: RX overflow sc->rxptr %d, complete %d\n", sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)); 2237 sc->sc_rx_fifo_wr_ptr = 2238 bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 2239 sc->sc_rx_fifo_rd_ptr = 2240 bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 2241 callout_schedule(&sc->sc_rx_watchdog, 400); 2242 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2243 printf("%s: MAC rx fault, status 0x%02x\n", 2244 device_xname(sc->sc_dev), rxstat); 2245 } 2246 if (status & GEM_INTR_PCS) { 2247 r |= gem_pint(sc); 2248 } 2249 2250 /* Do we need to do anything with these? 2251 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2252 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2253 if ((status2 & GEM_MAC_PAUSED) != 0) 2254 aprintf_debug_dev(sc->sc_dev, "PAUSE received (%d slots)\n", 2255 GEM_MAC_PAUSE_TIME(status2)); 2256 if ((status2 & GEM_MAC_PAUSE) != 0) 2257 aprintf_debug_dev(sc->sc_dev, "transited to PAUSE state\n"); 2258 if ((status2 & GEM_MAC_RESUME) != 0) 2259 aprintf_debug_dev(sc->sc_dev, "transited to non-PAUSE state\n"); 2260 } 2261 if ((status & GEM_INTR_MIF) != 0) 2262 aprintf_debug_dev(sc->sc_dev, "MIF interrupt\n"); 2263 */ 2264 rnd_add_uint32(&sc->rnd_source, status); 2265 return (r); 2266 } 2267 2268 void 2269 gem_rx_watchdog(void *arg) 2270 { 2271 struct gem_softc *sc = arg; 2272 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2273 bus_space_tag_t t = sc->sc_bustag; 2274 bus_space_handle_t h = sc->sc_h1; 2275 uint32_t rx_fifo_wr_ptr; 2276 uint32_t rx_fifo_rd_ptr; 2277 uint32_t state; 2278 2279 if ((ifp->if_flags & IFF_RUNNING) == 0) { 2280 aprint_error_dev(sc->sc_dev, "receiver not running\n"); 2281 return; 2282 } 2283 2284 rx_fifo_wr_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 2285 rx_fifo_rd_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 2286 state = bus_space_read_4(t, h, GEM_MAC_MAC_STATE); 2287 if ((state & GEM_MAC_STATE_OVERFLOW) == GEM_MAC_STATE_OVERFLOW && 2288 ((rx_fifo_wr_ptr == rx_fifo_rd_ptr) || 2289 ((sc->sc_rx_fifo_wr_ptr == rx_fifo_wr_ptr) && 2290 (sc->sc_rx_fifo_rd_ptr == rx_fifo_rd_ptr)))) 2291 { 2292 /* 2293 * The RX state machine is still in overflow state and 2294 * the RX FIFO write and read pointers seem to be 2295 * stuck. Whack the chip over the head to get things 2296 * going again. 2297 */ 2298 aprint_error_dev(sc->sc_dev, 2299 "receiver stuck in overflow, resetting\n"); 2300 gem_init(ifp); 2301 } else { 2302 if ((state & GEM_MAC_STATE_OVERFLOW) != GEM_MAC_STATE_OVERFLOW) { 2303 aprint_error_dev(sc->sc_dev, 2304 "rx_watchdog: not in overflow state: 0x%x\n", 2305 state); 2306 } 2307 if (rx_fifo_wr_ptr != rx_fifo_rd_ptr) { 2308 aprint_error_dev(sc->sc_dev, 2309 "rx_watchdog: wr & rd ptr different\n"); 2310 } 2311 if (sc->sc_rx_fifo_wr_ptr != rx_fifo_wr_ptr) { 2312 aprint_error_dev(sc->sc_dev, 2313 "rx_watchdog: wr pointer != saved\n"); 2314 } 2315 if (sc->sc_rx_fifo_rd_ptr != rx_fifo_rd_ptr) { 2316 aprint_error_dev(sc->sc_dev, 2317 "rx_watchdog: rd pointer != saved\n"); 2318 } 2319 aprint_error_dev(sc->sc_dev, "resetting anyway\n"); 2320 gem_init(ifp); 2321 } 2322 } 2323 2324 void 2325 gem_watchdog(struct ifnet *ifp) 2326 { 2327 struct gem_softc *sc = ifp->if_softc; 2328 2329 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2330 "GEM_MAC_RX_CONFIG %x\n", 2331 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2332 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2333 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2334 2335 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 2336 if_statinc(ifp, if_oerrors); 2337 2338 /* Try to get more packets going. */ 2339 gem_init(ifp); 2340 gem_start(ifp); 2341 } 2342 2343 /* 2344 * Initialize the MII Management Interface 2345 */ 2346 void 2347 gem_mifinit(struct gem_softc *sc) 2348 { 2349 bus_space_tag_t t = sc->sc_bustag; 2350 bus_space_handle_t mif = sc->sc_h1; 2351 2352 /* Configure the MIF in frame mode */ 2353 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2354 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2355 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2356 } 2357 2358 /* 2359 * MII interface 2360 * 2361 * The GEM MII interface supports at least three different operating modes: 2362 * 2363 * Bitbang mode is implemented using data, clock and output enable registers. 2364 * 2365 * Frame mode is implemented by loading a complete frame into the frame 2366 * register and polling the valid bit for completion. 2367 * 2368 * Polling mode uses the frame register but completion is indicated by 2369 * an interrupt. 2370 * 2371 */ 2372 static int 2373 gem_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 2374 { 2375 struct gem_softc *sc = device_private(self); 2376 bus_space_tag_t t = sc->sc_bustag; 2377 bus_space_handle_t mif = sc->sc_h1; 2378 int n; 2379 uint32_t v; 2380 2381 #ifdef GEM_DEBUG1 2382 if (sc->sc_debug) 2383 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2384 #endif 2385 2386 /* Construct the frame command */ 2387 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2388 GEM_MIF_FRAME_READ; 2389 2390 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2391 for (n = 0; n < 100; n++) { 2392 DELAY(1); 2393 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2394 if (v & GEM_MIF_FRAME_TA0) { 2395 *val = v & GEM_MIF_FRAME_DATA; 2396 return 0; 2397 } 2398 } 2399 2400 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 2401 return ETIMEDOUT; 2402 } 2403 2404 static int 2405 gem_mii_writereg(device_t self, int phy, int reg, uint16_t val) 2406 { 2407 struct gem_softc *sc = device_private(self); 2408 bus_space_tag_t t = sc->sc_bustag; 2409 bus_space_handle_t mif = sc->sc_h1; 2410 int n; 2411 uint32_t v; 2412 2413 #ifdef GEM_DEBUG1 2414 if (sc->sc_debug) 2415 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2416 phy, reg, val); 2417 #endif 2418 2419 /* Construct the frame command */ 2420 v = GEM_MIF_FRAME_WRITE | 2421 (phy << GEM_MIF_PHY_SHIFT) | 2422 (reg << GEM_MIF_REG_SHIFT) | 2423 (val & GEM_MIF_FRAME_DATA); 2424 2425 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2426 for (n = 0; n < 100; n++) { 2427 DELAY(1); 2428 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2429 if (v & GEM_MIF_FRAME_TA0) 2430 return 0; 2431 } 2432 2433 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 2434 return ETIMEDOUT; 2435 } 2436 2437 static void 2438 gem_mii_statchg(struct ifnet *ifp) 2439 { 2440 struct gem_softc *sc = ifp->if_softc; 2441 #ifdef GEM_DEBUG 2442 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2443 #endif 2444 2445 #ifdef GEM_DEBUG 2446 if (sc->sc_debug) 2447 printf("gem_mii_statchg: status change: phy = %d\n", 2448 sc->sc_phys[instance]); 2449 #endif 2450 gem_statuschange(sc); 2451 } 2452 2453 /* 2454 * Common status change for gem_mii_statchg() and gem_pint() 2455 */ 2456 void 2457 gem_statuschange(struct gem_softc* sc) 2458 { 2459 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2460 bus_space_tag_t t = sc->sc_bustag; 2461 bus_space_handle_t mac = sc->sc_h1; 2462 int gigabit; 2463 uint32_t rxcfg, txcfg, v; 2464 2465 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2466 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2467 sc->sc_flags |= GEM_LINK; 2468 else 2469 sc->sc_flags &= ~GEM_LINK; 2470 2471 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2472 gigabit = 1; 2473 else 2474 gigabit = 0; 2475 2476 /* 2477 * The configuration done here corresponds to the steps F) and 2478 * G) and as far as enabling of RX and TX MAC goes also step H) 2479 * of the initialization sequence outlined in section 3.2.1 of 2480 * the GEM Gigabit Ethernet ASIC Specification. 2481 */ 2482 2483 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2484 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2485 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2486 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2487 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2488 else if (gigabit) { 2489 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2490 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2491 } 2492 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2493 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2494 BUS_SPACE_BARRIER_WRITE); 2495 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2496 aprint_normal_dev(sc->sc_dev, "cannot disable TX MAC\n"); 2497 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2498 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2499 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2500 BUS_SPACE_BARRIER_WRITE); 2501 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2502 aprint_normal_dev(sc->sc_dev, "cannot disable RX MAC\n"); 2503 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2504 2505 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2506 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2507 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2508 2509 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2510 gigabit != 0) 2511 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2512 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2513 else 2514 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2515 GEM_MAC_SLOT_TIME_NORMAL); 2516 2517 /* XIF Configuration */ 2518 if (sc->sc_flags & GEM_LINK) 2519 v = GEM_MAC_XIF_LINK_LED; 2520 else 2521 v = 0; 2522 v |= GEM_MAC_XIF_TX_MII_ENA; 2523 2524 /* If an external transceiver is connected, enable its MII drivers */ 2525 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2526 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2527 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2528 if (gigabit) 2529 v |= GEM_MAC_XIF_GMII_MODE; 2530 else 2531 v &= ~GEM_MAC_XIF_GMII_MODE; 2532 } else 2533 /* Internal MII needs buf enable */ 2534 v |= GEM_MAC_XIF_MII_BUF_ENA; 2535 /* MII needs echo disable if half duplex. */ 2536 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2537 /* turn on full duplex LED */ 2538 v |= GEM_MAC_XIF_FDPLX_LED; 2539 else 2540 /* half duplex -- disable echo */ 2541 v |= GEM_MAC_XIF_ECHO_DISABL; 2542 } else { 2543 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2544 v |= GEM_MAC_XIF_FDPLX_LED; 2545 v |= GEM_MAC_XIF_GMII_MODE; 2546 } 2547 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2548 2549 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2550 (sc->sc_flags & GEM_LINK) != 0) { 2551 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2552 txcfg | GEM_MAC_TX_ENABLE); 2553 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2554 rxcfg | GEM_MAC_RX_ENABLE); 2555 } 2556 } 2557 2558 int 2559 gem_ser_mediachange(struct ifnet *ifp) 2560 { 2561 struct gem_softc *sc = ifp->if_softc; 2562 u_int s, t; 2563 2564 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2565 return EINVAL; 2566 2567 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2568 if (s == IFM_AUTO) { 2569 if (sc->sc_mii_media != s) { 2570 #ifdef GEM_DEBUG 2571 aprint_debug_dev(sc->sc_dev, "setting media to auto\n"); 2572 #endif 2573 sc->sc_mii_media = s; 2574 if (ifp->if_flags & IFF_UP) { 2575 gem_pcs_stop(sc, 0); 2576 gem_pcs_start(sc); 2577 } 2578 } 2579 return 0; 2580 } 2581 if (s == IFM_1000_SX) { 2582 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media) 2583 & (IFM_FDX | IFM_HDX); 2584 if ((sc->sc_mii_media & (IFM_FDX | IFM_HDX)) != t) { 2585 sc->sc_mii_media &= ~(IFM_FDX | IFM_HDX); 2586 sc->sc_mii_media |= t; 2587 #ifdef GEM_DEBUG 2588 aprint_debug_dev(sc->sc_dev, 2589 "setting media to 1000baseSX-%s\n", 2590 t == IFM_FDX ? "FDX" : "HDX"); 2591 #endif 2592 if (ifp->if_flags & IFF_UP) { 2593 gem_pcs_stop(sc, 0); 2594 gem_pcs_start(sc); 2595 } 2596 } 2597 return 0; 2598 } 2599 return EINVAL; 2600 } 2601 2602 void 2603 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2604 { 2605 struct gem_softc *sc = ifp->if_softc; 2606 2607 if ((ifp->if_flags & IFF_UP) == 0) 2608 return; 2609 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2610 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2611 } 2612 2613 static int 2614 gem_ifflags_cb(struct ethercom *ec) 2615 { 2616 struct ifnet *ifp = &ec->ec_if; 2617 struct gem_softc *sc = ifp->if_softc; 2618 u_short change = ifp->if_flags ^ sc->sc_if_flags; 2619 2620 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 2621 return ENETRESET; 2622 else if ((change & IFF_PROMISC) != 0) 2623 gem_setladrf(sc); 2624 return 0; 2625 } 2626 2627 /* 2628 * Process an ioctl request. 2629 */ 2630 int 2631 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 2632 { 2633 struct gem_softc *sc = ifp->if_softc; 2634 int s, error = 0; 2635 2636 s = splnet(); 2637 2638 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2639 error = 0; 2640 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2641 ; 2642 else if (ifp->if_flags & IFF_RUNNING) { 2643 /* 2644 * Multicast list has changed; set the hardware filter 2645 * accordingly. 2646 */ 2647 gem_setladrf(sc); 2648 } 2649 } 2650 2651 /* Try to get things going again */ 2652 if (ifp->if_flags & IFF_UP) 2653 gem_start(ifp); 2654 splx(s); 2655 return (error); 2656 } 2657 2658 static void 2659 gem_inten(struct gem_softc *sc) 2660 { 2661 bus_space_tag_t t = sc->sc_bustag; 2662 bus_space_handle_t h = sc->sc_h1; 2663 uint32_t v; 2664 2665 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 2666 v = GEM_INTR_PCS; 2667 else 2668 v = GEM_INTR_MIF; 2669 bus_space_write_4(t, h, GEM_INTMASK, 2670 ~(GEM_INTR_TX_INTME | 2671 GEM_INTR_TX_EMPTY | 2672 GEM_INTR_TX_MAC | 2673 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF | 2674 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL | 2675 GEM_INTR_BERR | v)); 2676 } 2677 2678 bool 2679 gem_resume(device_t self, const pmf_qual_t *qual) 2680 { 2681 struct gem_softc *sc = device_private(self); 2682 2683 gem_inten(sc); 2684 2685 return true; 2686 } 2687 2688 bool 2689 gem_suspend(device_t self, const pmf_qual_t *qual) 2690 { 2691 struct gem_softc *sc = device_private(self); 2692 bus_space_tag_t t = sc->sc_bustag; 2693 bus_space_handle_t h = sc->sc_h1; 2694 2695 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 2696 2697 return true; 2698 } 2699 2700 bool 2701 gem_shutdown(device_t self, int howto) 2702 { 2703 struct gem_softc *sc = device_private(self); 2704 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2705 2706 gem_stop(ifp, 1); 2707 2708 return true; 2709 } 2710 2711 /* 2712 * Set up the logical address filter. 2713 */ 2714 void 2715 gem_setladrf(struct gem_softc *sc) 2716 { 2717 struct ethercom *ec = &sc->sc_ethercom; 2718 struct ifnet *ifp = &ec->ec_if; 2719 struct ether_multi *enm; 2720 struct ether_multistep step; 2721 bus_space_tag_t t = sc->sc_bustag; 2722 bus_space_handle_t h = sc->sc_h1; 2723 uint32_t crc; 2724 uint32_t hash[16]; 2725 uint32_t v; 2726 int i; 2727 2728 /* Get current RX configuration */ 2729 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2730 2731 /* 2732 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2733 * and hash filter. Depending on the case, the right bit will be 2734 * enabled. 2735 */ 2736 v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_HASH_FILTER | 2737 GEM_MAC_RX_PROMISC_GRP); 2738 2739 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2740 /* Turn on promiscuous mode */ 2741 v |= GEM_MAC_RX_PROMISCUOUS; 2742 ifp->if_flags |= IFF_ALLMULTI; 2743 goto chipit; 2744 } 2745 2746 /* 2747 * Set up multicast address filter by passing all multicast addresses 2748 * through a crc generator, and then using the high order 8 bits as an 2749 * index into the 256 bit logical address filter. The high order 4 2750 * bits selects the word, while the other 4 bits select the bit within 2751 * the word (where bit 0 is the MSB). 2752 */ 2753 2754 /* Clear hash table */ 2755 memset(hash, 0, sizeof(hash)); 2756 2757 ETHER_LOCK(ec); 2758 ETHER_FIRST_MULTI(step, ec, enm); 2759 while (enm != NULL) { 2760 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2761 /* 2762 * We must listen to a range of multicast addresses. 2763 * For now, just accept all multicasts, rather than 2764 * trying to set only those filter bits needed to match 2765 * the range. (At this time, the only use of address 2766 * ranges is for IP multicast routing, for which the 2767 * range is big enough to require all bits set.) 2768 * XXX should use the address filters for this 2769 */ 2770 ifp->if_flags |= IFF_ALLMULTI; 2771 v |= GEM_MAC_RX_PROMISC_GRP; 2772 ETHER_UNLOCK(ec); 2773 goto chipit; 2774 } 2775 2776 /* Get the LE CRC32 of the address */ 2777 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2778 2779 /* Just want the 8 most significant bits. */ 2780 crc >>= 24; 2781 2782 /* Set the corresponding bit in the filter. */ 2783 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2784 2785 ETHER_NEXT_MULTI(step, enm); 2786 } 2787 ETHER_UNLOCK(ec); 2788 2789 v |= GEM_MAC_RX_HASH_FILTER; 2790 ifp->if_flags &= ~IFF_ALLMULTI; 2791 2792 /* Now load the hash table into the chip (if we are using it) */ 2793 for (i = 0; i < 16; i++) { 2794 bus_space_write_4(t, h, 2795 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2796 hash[i]); 2797 } 2798 2799 chipit: 2800 sc->sc_if_flags = ifp->if_flags; 2801 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2802 } 2803