1 /* $NetBSD: gem.c,v 1.134 2021/03/10 18:26:16 christos Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.134 2021/03/10 18:26:16 christos Exp $"); 41 42 #include "opt_inet.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/callout.h> 47 #include <sys/mbuf.h> 48 #include <sys/syslog.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/device.h> 55 56 #include <machine/endian.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #include <net/bpf.h> 73 74 #include <sys/bus.h> 75 #include <sys/intr.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/ic/gemreg.h> 82 #include <dev/ic/gemvar.h> 83 84 #define TRIES 10000 85 86 static void gem_inten(struct gem_softc *); 87 static void gem_start(struct ifnet *); 88 static void gem_stop(struct ifnet *, int); 89 int gem_ioctl(struct ifnet *, u_long, void *); 90 void gem_tick(void *); 91 void gem_watchdog(struct ifnet *); 92 void gem_rx_watchdog(void *); 93 void gem_pcs_start(struct gem_softc *sc); 94 void gem_pcs_stop(struct gem_softc *sc, int); 95 int gem_init(struct ifnet *); 96 void gem_init_regs(struct gem_softc *sc); 97 static int gem_ringsize(int sz); 98 static int gem_meminit(struct gem_softc *); 99 void gem_mifinit(struct gem_softc *); 100 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 101 uint32_t, uint32_t); 102 void gem_reset(struct gem_softc *); 103 int gem_reset_rx(struct gem_softc *sc); 104 static void gem_reset_rxdma(struct gem_softc *sc); 105 static void gem_rx_common(struct gem_softc *sc); 106 int gem_reset_tx(struct gem_softc *sc); 107 int gem_disable_rx(struct gem_softc *sc); 108 int gem_disable_tx(struct gem_softc *sc); 109 static void gem_rxdrain(struct gem_softc *sc); 110 int gem_add_rxbuf(struct gem_softc *sc, int idx); 111 void gem_setladrf(struct gem_softc *); 112 113 /* MII methods & callbacks */ 114 static int gem_mii_readreg(device_t, int, int, uint16_t *); 115 static int gem_mii_writereg(device_t, int, int, uint16_t); 116 static void gem_mii_statchg(struct ifnet *); 117 118 static int gem_ifflags_cb(struct ethercom *); 119 120 void gem_statuschange(struct gem_softc *); 121 122 int gem_ser_mediachange(struct ifnet *); 123 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 124 125 static void gem_partial_detach(struct gem_softc *, enum gem_attach_stage); 126 127 struct mbuf *gem_get(struct gem_softc *, int, int); 128 int gem_put(struct gem_softc *, int, struct mbuf *); 129 void gem_read(struct gem_softc *, int, int); 130 int gem_pint(struct gem_softc *); 131 int gem_eint(struct gem_softc *, u_int); 132 int gem_rint(struct gem_softc *); 133 int gem_tint(struct gem_softc *); 134 void gem_power(int, void *); 135 136 #ifdef GEM_DEBUG 137 static void gem_txsoft_print(const struct gem_softc *, int, int); 138 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 139 printf x 140 #else 141 #define DPRINTF(sc, x) /* nothing */ 142 #endif 143 144 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 145 146 int 147 gem_detach(struct gem_softc *sc, int flags) 148 { 149 int i; 150 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 151 bus_space_tag_t t = sc->sc_bustag; 152 bus_space_handle_t h = sc->sc_h1; 153 154 /* 155 * Free any resources we've allocated during the attach. 156 * Do this in reverse order and fall through. 157 */ 158 switch (sc->sc_att_stage) { 159 case GEM_ATT_BACKEND_2: 160 case GEM_ATT_BACKEND_1: 161 case GEM_ATT_FINISHED: 162 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 163 gem_stop(&sc->sc_ethercom.ec_if, 1); 164 165 #ifdef GEM_COUNTERS 166 for (i = __arraycount(sc->sc_ev_rxhist); --i >= 0; ) 167 evcnt_detach(&sc->sc_ev_rxhist[i]); 168 evcnt_detach(&sc->sc_ev_rxnobuf); 169 evcnt_detach(&sc->sc_ev_rxfull); 170 evcnt_detach(&sc->sc_ev_rxint); 171 evcnt_detach(&sc->sc_ev_txint); 172 evcnt_detach(&sc->sc_ev_rxoverflow); 173 #endif 174 evcnt_detach(&sc->sc_ev_intr); 175 176 rnd_detach_source(&sc->rnd_source); 177 ether_ifdetach(ifp); 178 if_detach(ifp); 179 180 callout_destroy(&sc->sc_tick_ch); 181 callout_destroy(&sc->sc_rx_watchdog); 182 183 /*FALLTHROUGH*/ 184 case GEM_ATT_MII: 185 sc->sc_att_stage = GEM_ATT_MII; 186 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 187 ifmedia_fini(&sc->sc_mii.mii_media); 188 189 /*FALLTHROUGH*/ 190 case GEM_ATT_7: 191 for (i = 0; i < GEM_NRXDESC; i++) { 192 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 193 bus_dmamap_destroy(sc->sc_dmatag, 194 sc->sc_rxsoft[i].rxs_dmamap); 195 } 196 /*FALLTHROUGH*/ 197 case GEM_ATT_6: 198 for (i = 0; i < GEM_TXQUEUELEN; i++) { 199 if (sc->sc_txsoft[i].txs_dmamap != NULL) 200 bus_dmamap_destroy(sc->sc_dmatag, 201 sc->sc_txsoft[i].txs_dmamap); 202 } 203 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 204 /*FALLTHROUGH*/ 205 case GEM_ATT_5: 206 bus_dmamap_unload(sc->sc_dmatag, sc->sc_nulldmamap); 207 /*FALLTHROUGH*/ 208 case GEM_ATT_4: 209 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 210 /*FALLTHROUGH*/ 211 case GEM_ATT_3: 212 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 213 /*FALLTHROUGH*/ 214 case GEM_ATT_2: 215 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 216 sizeof(struct gem_control_data)); 217 /*FALLTHROUGH*/ 218 case GEM_ATT_1: 219 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 220 /*FALLTHROUGH*/ 221 case GEM_ATT_0: 222 sc->sc_att_stage = GEM_ATT_0; 223 /*FALLTHROUGH*/ 224 case GEM_ATT_BACKEND_0: 225 break; 226 } 227 return 0; 228 } 229 230 static void 231 gem_partial_detach(struct gem_softc *sc, enum gem_attach_stage stage) 232 { 233 cfattach_t ca = device_cfattach(sc->sc_dev); 234 235 sc->sc_att_stage = stage; 236 (*ca->ca_detach)(sc->sc_dev, 0); 237 } 238 239 /* 240 * gem_attach: 241 * 242 * Attach a Gem interface to the system. 243 */ 244 void 245 gem_attach(struct gem_softc *sc, const uint8_t *enaddr) 246 { 247 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 248 struct mii_data *mii = &sc->sc_mii; 249 bus_space_tag_t t = sc->sc_bustag; 250 bus_space_handle_t h = sc->sc_h1; 251 struct ifmedia_entry *ife; 252 int i, error, phyaddr; 253 uint32_t v; 254 char *nullbuf; 255 256 /* Make sure the chip is stopped. */ 257 ifp->if_softc = sc; 258 gem_reset(sc); 259 260 /* 261 * Allocate the control data structures, and create and load the 262 * DMA map for it. gem_control_data is 9216 bytes, we have space for 263 * the padding buffer in the bus_dmamem_alloc()'d memory. 264 */ 265 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 266 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 267 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 268 aprint_error_dev(sc->sc_dev, 269 "unable to allocate control data, error = %d\n", 270 error); 271 gem_partial_detach(sc, GEM_ATT_0); 272 return; 273 } 274 275 /* XXX should map this in with correct endianness */ 276 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 277 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 278 BUS_DMA_COHERENT)) != 0) { 279 aprint_error_dev(sc->sc_dev, 280 "unable to map control data, error = %d\n", error); 281 gem_partial_detach(sc, GEM_ATT_1); 282 return; 283 } 284 285 nullbuf = 286 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 287 288 if ((error = bus_dmamap_create(sc->sc_dmatag, 289 sizeof(struct gem_control_data), 1, 290 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 291 aprint_error_dev(sc->sc_dev, 292 "unable to create control data DMA map, error = %d\n", 293 error); 294 gem_partial_detach(sc, GEM_ATT_2); 295 return; 296 } 297 298 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 299 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 300 0)) != 0) { 301 aprint_error_dev(sc->sc_dev, 302 "unable to load control data DMA map, error = %d\n", 303 error); 304 gem_partial_detach(sc, GEM_ATT_3); 305 return; 306 } 307 308 memset(nullbuf, 0, ETHER_MIN_TX); 309 if ((error = bus_dmamap_create(sc->sc_dmatag, 310 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 311 aprint_error_dev(sc->sc_dev, 312 "unable to create padding DMA map, error = %d\n", error); 313 gem_partial_detach(sc, GEM_ATT_4); 314 return; 315 } 316 317 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 318 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 319 aprint_error_dev(sc->sc_dev, 320 "unable to load padding DMA map, error = %d\n", error); 321 gem_partial_detach(sc, GEM_ATT_5); 322 return; 323 } 324 325 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 326 BUS_DMASYNC_PREWRITE); 327 328 /* 329 * Initialize the transmit job descriptors. 330 */ 331 SIMPLEQ_INIT(&sc->sc_txfreeq); 332 SIMPLEQ_INIT(&sc->sc_txdirtyq); 333 334 /* 335 * Create the transmit buffer DMA maps. 336 */ 337 for (i = 0; i < GEM_TXQUEUELEN; i++) { 338 struct gem_txsoft *txs; 339 340 txs = &sc->sc_txsoft[i]; 341 txs->txs_mbuf = NULL; 342 if ((error = bus_dmamap_create(sc->sc_dmatag, 343 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 344 ETHER_MAX_LEN_JUMBO, 0, 0, 345 &txs->txs_dmamap)) != 0) { 346 aprint_error_dev(sc->sc_dev, 347 "unable to create tx DMA map %d, error = %d\n", 348 i, error); 349 gem_partial_detach(sc, GEM_ATT_6); 350 return; 351 } 352 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 353 } 354 355 /* 356 * Create the receive buffer DMA maps. 357 */ 358 for (i = 0; i < GEM_NRXDESC; i++) { 359 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 360 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 361 aprint_error_dev(sc->sc_dev, 362 "unable to create rx DMA map %d, error = %d\n", 363 i, error); 364 gem_partial_detach(sc, GEM_ATT_7); 365 return; 366 } 367 sc->sc_rxsoft[i].rxs_mbuf = NULL; 368 } 369 370 /* Initialize ifmedia structures and MII info */ 371 mii->mii_ifp = ifp; 372 mii->mii_readreg = gem_mii_readreg; 373 mii->mii_writereg = gem_mii_writereg; 374 mii->mii_statchg = gem_mii_statchg; 375 376 sc->sc_ethercom.ec_mii = mii; 377 378 /* 379 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 380 * Section 3.2.1 `Initialization Sequence'. 381 * However, we can't assume SERDES or Serialink if neither 382 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 383 * being set, as both are set on Sun X1141A (with SERDES). So, 384 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 385 * Also, for variants that report 2 PHY's, we prefer the external 386 * PHY over the internal PHY, so we look for that first. 387 */ 388 gem_mifinit(sc); 389 390 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 391 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 392 ether_mediastatus); 393 /* Look for external PHY */ 394 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 395 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 396 bus_space_write_4(t, h, GEM_MIF_CONFIG, 397 sc->sc_mif_config); 398 switch (sc->sc_variant) { 399 case GEM_SUN_ERI: 400 phyaddr = GEM_PHYAD_EXTERNAL; 401 break; 402 default: 403 phyaddr = MII_PHY_ANY; 404 break; 405 } 406 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 407 MII_OFFSET_ANY, MIIF_FORCEANEG); 408 } 409 #ifdef GEM_DEBUG 410 else 411 aprint_debug_dev(sc->sc_dev, "using external PHY\n"); 412 #endif 413 /* Look for internal PHY if no external PHY was found */ 414 if (LIST_EMPTY(&mii->mii_phys) && 415 ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI0) || 416 (sc->sc_variant == GEM_APPLE_K2_GMAC))) { 417 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 418 bus_space_write_4(t, h, GEM_MIF_CONFIG, 419 sc->sc_mif_config); 420 switch (sc->sc_variant) { 421 case GEM_SUN_ERI: 422 case GEM_APPLE_K2_GMAC: 423 phyaddr = GEM_PHYAD_INTERNAL; 424 break; 425 case GEM_APPLE_GMAC: 426 phyaddr = GEM_PHYAD_EXTERNAL; 427 break; 428 default: 429 phyaddr = MII_PHY_ANY; 430 break; 431 } 432 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 433 MII_OFFSET_ANY, MIIF_FORCEANEG); 434 #ifdef GEM_DEBUG 435 if (!LIST_EMPTY(&mii->mii_phys)) 436 aprint_debug_dev(sc->sc_dev, 437 "using internal PHY\n"); 438 #endif 439 } 440 if (LIST_EMPTY(&mii->mii_phys)) { 441 /* No PHY attached */ 442 aprint_error_dev(sc->sc_dev, 443 "PHY probe failed\n"); 444 gem_partial_detach(sc, GEM_ATT_MII); 445 return; 446 } else { 447 struct mii_softc *child; 448 449 /* 450 * Walk along the list of attached MII devices and 451 * establish an `MII instance' to `PHY number' 452 * mapping. 453 */ 454 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 455 /* 456 * Note: we support just one PHY: the internal 457 * or external MII is already selected for us 458 * by the GEM_MIF_CONFIG register. 459 */ 460 if (child->mii_phy > 1 || child->mii_inst > 0) { 461 aprint_error_dev(sc->sc_dev, 462 "cannot accommodate MII device" 463 " %s at PHY %d, instance %d\n", 464 device_xname(child->mii_dev), 465 child->mii_phy, child->mii_inst); 466 continue; 467 } 468 sc->sc_phys[child->mii_inst] = child->mii_phy; 469 } 470 471 if (sc->sc_variant != GEM_SUN_ERI) 472 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 473 GEM_MII_DATAPATH_MII); 474 475 /* 476 * XXX - we can really do the following ONLY if the 477 * PHY indeed has the auto negotiation capability!! 478 */ 479 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 480 } 481 } else { 482 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 483 gem_ser_mediastatus); 484 /* SERDES or Serialink */ 485 if (sc->sc_flags & GEM_SERDES) { 486 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 487 GEM_MII_DATAPATH_SERDES); 488 } else { 489 sc->sc_flags |= GEM_SERIAL; 490 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 491 GEM_MII_DATAPATH_SERIAL); 492 } 493 494 aprint_normal_dev(sc->sc_dev, "using external PCS %s: ", 495 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 496 497 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_AUTO, 0, NULL); 498 /* Check for FDX and HDX capabilities */ 499 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 500 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 501 ifmedia_add(&mii->mii_media, IFM_ETHER | 502 IFM_1000_SX | IFM_MANUAL | IFM_FDX, 0, NULL); 503 aprint_normal("1000baseSX-FDX, "); 504 } 505 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 506 ifmedia_add(&mii->mii_media, IFM_ETHER | 507 IFM_1000_SX | IFM_MANUAL | IFM_HDX, 0, NULL); 508 aprint_normal("1000baseSX-HDX, "); 509 } 510 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 511 sc->sc_mii_media = IFM_AUTO; 512 aprint_normal("auto\n"); 513 514 gem_pcs_stop(sc, 1); 515 } 516 517 /* 518 * From this point forward, the attachment cannot fail. A failure 519 * before this point releases all resources that may have been 520 * allocated. 521 */ 522 523 /* Announce ourselves. */ 524 aprint_normal_dev(sc->sc_dev, "Ethernet address %s", 525 ether_sprintf(enaddr)); 526 527 /* Get RX FIFO size */ 528 sc->sc_rxfifosize = 64 * 529 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 530 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 531 532 /* Get TX FIFO size */ 533 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 534 aprint_normal(", %uKB TX fifo\n", v / 16); 535 536 /* Initialize ifnet structure. */ 537 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 538 ifp->if_softc = sc; 539 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 540 sc->sc_if_flags = ifp->if_flags; 541 #if 0 542 /* 543 * The GEM hardware supports basic TCP checksum offloading only. 544 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 545 * have bugs in the receive checksum, so don't enable it for now. 546 */ 547 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 548 (GEM_IS_APPLE(sc) && 549 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 550 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 551 #endif 552 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 553 ifp->if_start = gem_start; 554 ifp->if_ioctl = gem_ioctl; 555 ifp->if_watchdog = gem_watchdog; 556 ifp->if_stop = gem_stop; 557 ifp->if_init = gem_init; 558 IFQ_SET_READY(&ifp->if_snd); 559 560 /* 561 * If we support GigE media, we support jumbo frames too. 562 * Unless we are Apple. 563 */ 564 TAILQ_FOREACH(ife, &mii->mii_media.ifm_list, ifm_list) { 565 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T || 566 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_SX || 567 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_LX || 568 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_CX) { 569 if (!GEM_IS_APPLE(sc)) 570 sc->sc_ethercom.ec_capabilities 571 |= ETHERCAP_JUMBO_MTU; 572 sc->sc_flags |= GEM_GIGABIT; 573 break; 574 } 575 } 576 577 /* claim 802.1q capability */ 578 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 579 580 /* Attach the interface. */ 581 if_attach(ifp); 582 if_deferred_start_init(ifp, NULL); 583 ether_ifattach(ifp, enaddr); 584 ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb); 585 586 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 587 RND_TYPE_NET, RND_FLAG_DEFAULT); 588 589 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 590 NULL, device_xname(sc->sc_dev), "interrupts"); 591 #ifdef GEM_COUNTERS 592 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 593 &sc->sc_ev_intr, device_xname(sc->sc_dev), "tx interrupts"); 594 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 595 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rx interrupts"); 596 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 597 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx ring full"); 598 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 599 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx malloc failure"); 600 evcnt_attach_dynamic(&sc->sc_ev_rxoverflow, EVCNT_TYPE_INTR, 601 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx overflow"); 602 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 603 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 0desc"); 604 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 605 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 1desc"); 606 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 607 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 2desc"); 608 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 609 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 3desc"); 610 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 611 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >3desc"); 612 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 613 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >7desc"); 614 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 615 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >15desc"); 616 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 617 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >31desc"); 618 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 619 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >63desc"); 620 #endif 621 622 callout_init(&sc->sc_tick_ch, 0); 623 callout_setfunc(&sc->sc_tick_ch, gem_tick, sc); 624 625 callout_init(&sc->sc_rx_watchdog, 0); 626 callout_setfunc(&sc->sc_rx_watchdog, gem_rx_watchdog, sc); 627 628 sc->sc_att_stage = GEM_ATT_FINISHED; 629 630 return; 631 } 632 633 void 634 gem_tick(void *arg) 635 { 636 struct gem_softc *sc = arg; 637 int s; 638 639 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 640 /* 641 * We have to reset everything if we failed to get a 642 * PCS interrupt. Restarting the callout is handled 643 * in gem_pcs_start(). 644 */ 645 gem_init(&sc->sc_ethercom.ec_if); 646 } else { 647 s = splnet(); 648 mii_tick(&sc->sc_mii); 649 splx(s); 650 callout_schedule(&sc->sc_tick_ch, hz); 651 } 652 } 653 654 static int 655 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, uint32_t clr, 656 uint32_t set) 657 { 658 int i; 659 uint32_t reg; 660 661 for (i = TRIES; i--; DELAY(100)) { 662 reg = bus_space_read_4(sc->sc_bustag, h, r); 663 if ((reg & clr) == 0 && (reg & set) == set) 664 return (1); 665 } 666 return (0); 667 } 668 669 void 670 gem_reset(struct gem_softc *sc) 671 { 672 bus_space_tag_t t = sc->sc_bustag; 673 bus_space_handle_t h = sc->sc_h2; 674 int s; 675 676 s = splnet(); 677 DPRINTF(sc, ("%s: gem_reset\n", device_xname(sc->sc_dev))); 678 gem_reset_rx(sc); 679 gem_reset_tx(sc); 680 681 /* Do a full reset */ 682 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 683 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 684 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 685 splx(s); 686 } 687 688 689 /* 690 * gem_rxdrain: 691 * 692 * Drain the receive queue. 693 */ 694 static void 695 gem_rxdrain(struct gem_softc *sc) 696 { 697 struct gem_rxsoft *rxs; 698 int i; 699 700 for (i = 0; i < GEM_NRXDESC; i++) { 701 rxs = &sc->sc_rxsoft[i]; 702 if (rxs->rxs_mbuf != NULL) { 703 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 704 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 705 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 706 m_freem(rxs->rxs_mbuf); 707 rxs->rxs_mbuf = NULL; 708 } 709 } 710 } 711 712 /* 713 * Reset the whole thing. 714 */ 715 static void 716 gem_stop(struct ifnet *ifp, int disable) 717 { 718 struct gem_softc *sc = ifp->if_softc; 719 struct gem_txsoft *txs; 720 721 DPRINTF(sc, ("%s: gem_stop\n", device_xname(sc->sc_dev))); 722 723 callout_halt(&sc->sc_tick_ch, NULL); 724 callout_halt(&sc->sc_rx_watchdog, NULL); 725 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 726 gem_pcs_stop(sc, disable); 727 else 728 mii_down(&sc->sc_mii); 729 730 /* XXX - Should we reset these instead? */ 731 gem_disable_tx(sc); 732 gem_disable_rx(sc); 733 734 /* 735 * Release any queued transmit buffers. 736 */ 737 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 738 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 739 if (txs->txs_mbuf != NULL) { 740 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 741 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 742 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 743 m_freem(txs->txs_mbuf); 744 txs->txs_mbuf = NULL; 745 } 746 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 747 } 748 749 /* 750 * Mark the interface down and cancel the watchdog timer. 751 */ 752 ifp->if_flags &= ~IFF_RUNNING; 753 sc->sc_if_flags = ifp->if_flags; 754 ifp->if_timer = 0; 755 756 if (disable) 757 gem_rxdrain(sc); 758 } 759 760 761 /* 762 * Reset the receiver 763 */ 764 int 765 gem_reset_rx(struct gem_softc *sc) 766 { 767 bus_space_tag_t t = sc->sc_bustag; 768 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 769 770 /* 771 * Resetting while DMA is in progress can cause a bus hang, so we 772 * disable DMA first. 773 */ 774 gem_disable_rx(sc); 775 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 776 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 777 /* Wait till it finishes */ 778 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 779 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 780 /* Wait 5ms extra. */ 781 delay(5000); 782 783 /* Finally, reset the ERX */ 784 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 785 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 786 /* Wait till it finishes */ 787 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 788 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 789 return (1); 790 } 791 return (0); 792 } 793 794 795 /* 796 * Reset the receiver DMA engine. 797 * 798 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 799 * etc in order to reset the receiver DMA engine only and not do a full 800 * reset which amongst others also downs the link and clears the FIFOs. 801 */ 802 static void 803 gem_reset_rxdma(struct gem_softc *sc) 804 { 805 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 806 bus_space_tag_t t = sc->sc_bustag; 807 bus_space_handle_t h = sc->sc_h1; 808 int i; 809 810 if (gem_reset_rx(sc) != 0) { 811 gem_init(ifp); 812 return; 813 } 814 for (i = 0; i < GEM_NRXDESC; i++) 815 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 816 GEM_UPDATE_RXDESC(sc, i); 817 sc->sc_rxptr = 0; 818 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 819 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 820 821 /* Reprogram Descriptor Ring Base Addresses */ 822 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 823 ((uint64_t)GEM_CDRXADDR(sc, 0)) >> 32); 824 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 825 826 /* Redo ERX Configuration */ 827 gem_rx_common(sc); 828 829 /* Give the receiver a swift kick */ 830 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 831 } 832 833 /* 834 * Common RX configuration for gem_init() and gem_reset_rxdma(). 835 */ 836 static void 837 gem_rx_common(struct gem_softc *sc) 838 { 839 bus_space_tag_t t = sc->sc_bustag; 840 bus_space_handle_t h = sc->sc_h1; 841 uint32_t v; 842 843 /* Encode Receive Descriptor ring size: four possible values */ 844 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 845 846 /* Set receive h/w checksum offset */ 847 #ifdef INET 848 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 849 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 850 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 851 #endif 852 853 /* Enable RX DMA */ 854 bus_space_write_4(t, h, GEM_RX_CONFIG, 855 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 856 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 857 858 /* 859 * The following value is for an OFF Threshold of about 3/4 full 860 * and an ON Threshold of 1/4 full. 861 */ 862 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 863 (3 * sc->sc_rxfifosize / 256) | 864 ((sc->sc_rxfifosize / 256) << 12)); 865 bus_space_write_4(t, h, GEM_RX_BLANKING, 866 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 8); 867 } 868 869 /* 870 * Reset the transmitter 871 */ 872 int 873 gem_reset_tx(struct gem_softc *sc) 874 { 875 bus_space_tag_t t = sc->sc_bustag; 876 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 877 878 /* 879 * Resetting while DMA is in progress can cause a bus hang, so we 880 * disable DMA first. 881 */ 882 gem_disable_tx(sc); 883 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 884 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 885 /* Wait till it finishes */ 886 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 887 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); 888 /* Wait 5ms extra. */ 889 delay(5000); 890 891 /* Finally, reset the ETX */ 892 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 893 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 894 /* Wait till it finishes */ 895 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 896 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); 897 return (1); 898 } 899 return (0); 900 } 901 902 /* 903 * disable receiver. 904 */ 905 int 906 gem_disable_rx(struct gem_softc *sc) 907 { 908 bus_space_tag_t t = sc->sc_bustag; 909 bus_space_handle_t h = sc->sc_h1; 910 uint32_t cfg; 911 912 /* Flip the enable bit */ 913 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 914 cfg &= ~GEM_MAC_RX_ENABLE; 915 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 916 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 917 /* Wait for it to finish */ 918 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 919 } 920 921 /* 922 * disable transmitter. 923 */ 924 int 925 gem_disable_tx(struct gem_softc *sc) 926 { 927 bus_space_tag_t t = sc->sc_bustag; 928 bus_space_handle_t h = sc->sc_h1; 929 uint32_t cfg; 930 931 /* Flip the enable bit */ 932 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 933 cfg &= ~GEM_MAC_TX_ENABLE; 934 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 935 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 936 /* Wait for it to finish */ 937 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 938 } 939 940 /* 941 * Initialize interface. 942 */ 943 int 944 gem_meminit(struct gem_softc *sc) 945 { 946 struct gem_rxsoft *rxs; 947 int i, error; 948 949 /* 950 * Initialize the transmit descriptor ring. 951 */ 952 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 953 for (i = 0; i < GEM_NTXDESC; i++) { 954 sc->sc_txdescs[i].gd_flags = 0; 955 sc->sc_txdescs[i].gd_addr = 0; 956 } 957 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 958 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 959 sc->sc_txfree = GEM_NTXDESC-1; 960 sc->sc_txnext = 0; 961 sc->sc_txwin = 0; 962 963 /* 964 * Initialize the receive descriptor and receive job 965 * descriptor rings. 966 */ 967 for (i = 0; i < GEM_NRXDESC; i++) { 968 rxs = &sc->sc_rxsoft[i]; 969 if (rxs->rxs_mbuf == NULL) { 970 if ((error = gem_add_rxbuf(sc, i)) != 0) { 971 aprint_error_dev(sc->sc_dev, 972 "unable to allocate or map rx " 973 "buffer %d, error = %d\n", 974 i, error); 975 /* 976 * XXX Should attempt to run with fewer receive 977 * XXX buffers instead of just failing. 978 */ 979 gem_rxdrain(sc); 980 return (1); 981 } 982 } else 983 GEM_INIT_RXDESC(sc, i); 984 } 985 sc->sc_rxptr = 0; 986 sc->sc_meminited = 1; 987 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 988 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 989 990 return (0); 991 } 992 993 static int 994 gem_ringsize(int sz) 995 { 996 switch (sz) { 997 case 32: 998 return GEM_RING_SZ_32; 999 case 64: 1000 return GEM_RING_SZ_64; 1001 case 128: 1002 return GEM_RING_SZ_128; 1003 case 256: 1004 return GEM_RING_SZ_256; 1005 case 512: 1006 return GEM_RING_SZ_512; 1007 case 1024: 1008 return GEM_RING_SZ_1024; 1009 case 2048: 1010 return GEM_RING_SZ_2048; 1011 case 4096: 1012 return GEM_RING_SZ_4096; 1013 case 8192: 1014 return GEM_RING_SZ_8192; 1015 default: 1016 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 1017 return GEM_RING_SZ_32; 1018 } 1019 } 1020 1021 1022 /* 1023 * Start PCS 1024 */ 1025 void 1026 gem_pcs_start(struct gem_softc *sc) 1027 { 1028 bus_space_tag_t t = sc->sc_bustag; 1029 bus_space_handle_t h = sc->sc_h1; 1030 uint32_t v; 1031 1032 #ifdef GEM_DEBUG 1033 aprint_debug_dev(sc->sc_dev, "gem_pcs_start()\n"); 1034 #endif 1035 1036 /* 1037 * Set up. We must disable the MII before modifying the 1038 * GEM_MII_ANAR register 1039 */ 1040 if (sc->sc_flags & GEM_SERDES) { 1041 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1042 GEM_MII_DATAPATH_SERDES); 1043 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1044 GEM_MII_SLINK_LOOPBACK); 1045 } else { 1046 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1047 GEM_MII_DATAPATH_SERIAL); 1048 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 1049 } 1050 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1051 v = bus_space_read_4(t, h, GEM_MII_ANAR); 1052 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 1053 if (IFM_SUBTYPE(sc->sc_mii_media) == IFM_AUTO) 1054 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 1055 else if ((IFM_OPTIONS(sc->sc_mii_media) & IFM_FDX) != 0) { 1056 v |= GEM_MII_ANEG_FUL_DUPLX; 1057 v &= ~GEM_MII_ANEG_HLF_DUPLX; 1058 } else if ((IFM_OPTIONS(sc->sc_mii_media) & IFM_HDX) != 0) { 1059 v &= ~GEM_MII_ANEG_FUL_DUPLX; 1060 v |= GEM_MII_ANEG_HLF_DUPLX; 1061 } 1062 1063 /* Configure link. */ 1064 bus_space_write_4(t, h, GEM_MII_ANAR, v); 1065 bus_space_write_4(t, h, GEM_MII_CONTROL, 1066 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1067 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 1068 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 1069 1070 /* Start the 10 second timer */ 1071 callout_schedule(&sc->sc_tick_ch, hz * 10); 1072 } 1073 1074 /* 1075 * Stop PCS 1076 */ 1077 void 1078 gem_pcs_stop(struct gem_softc *sc, int disable) 1079 { 1080 bus_space_tag_t t = sc->sc_bustag; 1081 bus_space_handle_t h = sc->sc_h1; 1082 1083 #ifdef GEM_DEBUG 1084 aprint_debug_dev(sc->sc_dev, "gem_pcs_stop()\n"); 1085 #endif 1086 1087 /* Tell link partner that we're going away */ 1088 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1089 1090 /* 1091 * Disable PCS MII. The documentation suggests that setting 1092 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1093 * negotiation will shut down the link. However, it appears 1094 * that we also need to unset the datapath mode. 1095 */ 1096 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1097 bus_space_write_4(t, h, GEM_MII_CONTROL, 1098 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1099 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1100 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1101 1102 if (disable) { 1103 if (sc->sc_flags & GEM_SERDES) 1104 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1105 GEM_MII_SLINK_POWER_OFF); 1106 else 1107 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1108 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1109 } 1110 1111 sc->sc_flags &= ~GEM_LINK; 1112 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1113 sc->sc_mii.mii_media_status = IFM_AVALID; 1114 } 1115 1116 1117 /* 1118 * Initialization of interface; set up initialization block 1119 * and transmit/receive descriptor rings. 1120 */ 1121 int 1122 gem_init(struct ifnet *ifp) 1123 { 1124 struct gem_softc *sc = ifp->if_softc; 1125 bus_space_tag_t t = sc->sc_bustag; 1126 bus_space_handle_t h = sc->sc_h1; 1127 int rc = 0, s; 1128 u_int max_frame_size; 1129 uint32_t v; 1130 1131 s = splnet(); 1132 1133 DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(sc->sc_dev))); 1134 /* 1135 * Initialization sequence. The numbered steps below correspond 1136 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1137 * Channel Engine manual (part of the PCIO manual). 1138 * See also the STP2002-STQ document from Sun Microsystems. 1139 */ 1140 1141 /* step 1 & 2. Reset the Ethernet Channel */ 1142 gem_stop(ifp, 0); 1143 gem_reset(sc); 1144 DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(sc->sc_dev))); 1145 1146 /* Re-initialize the MIF */ 1147 gem_mifinit(sc); 1148 1149 /* Set up correct datapath for non-SERDES/Serialink */ 1150 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1151 sc->sc_variant != GEM_SUN_ERI) 1152 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1153 GEM_MII_DATAPATH_MII); 1154 1155 /* Call MI reset function if any */ 1156 if (sc->sc_hwreset) 1157 (*sc->sc_hwreset)(sc); 1158 1159 /* step 3. Setup data structures in host memory */ 1160 if (gem_meminit(sc) != 0) { 1161 splx(s); 1162 return 1; 1163 } 1164 1165 /* step 4. TX MAC registers & counters */ 1166 gem_init_regs(sc); 1167 max_frame_size = uimax(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1168 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1169 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1170 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1171 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1172 max_frame_size|/* burst size */(0x2000<<16)); 1173 1174 /* step 5. RX MAC registers & counters */ 1175 gem_setladrf(sc); 1176 1177 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1178 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 1179 ((uint64_t)GEM_CDTXADDR(sc, 0)) >> 32); 1180 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1181 1182 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 1183 ((uint64_t)GEM_CDRXADDR(sc, 0)) >> 32); 1184 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1185 1186 /* step 8. Global Configuration & Interrupt Mask */ 1187 gem_inten(sc); 1188 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1189 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1190 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1191 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1192 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1193 1194 /* step 9. ETX Configuration: use mostly default values */ 1195 1196 /* Enable TX DMA */ 1197 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1198 bus_space_write_4(t, h, GEM_TX_CONFIG, 1199 v | GEM_TX_CONFIG_TXDMA_EN | 1200 (((sc->sc_flags & GEM_GIGABIT ? 0x4FF : 0x100) << 10) & 1201 GEM_TX_CONFIG_TXFIFO_TH)); 1202 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1203 1204 /* step 10. ERX Configuration */ 1205 gem_rx_common(sc); 1206 1207 /* step 11. Configure Media */ 1208 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1209 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1210 goto out; 1211 1212 /* step 12. RX_MAC Configuration Register */ 1213 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1214 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1215 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1216 1217 /* step 14. Issue Transmit Pending command */ 1218 1219 /* Call MI initialization function if any */ 1220 if (sc->sc_hwinit) 1221 (*sc->sc_hwinit)(sc); 1222 1223 /* step 15. Give the receiver a swift kick */ 1224 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1225 1226 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1227 /* Configure PCS */ 1228 gem_pcs_start(sc); 1229 else 1230 /* Start the one second timer. */ 1231 callout_schedule(&sc->sc_tick_ch, hz); 1232 1233 sc->sc_flags &= ~GEM_LINK; 1234 ifp->if_flags |= IFF_RUNNING; 1235 ifp->if_timer = 0; 1236 sc->sc_if_flags = ifp->if_flags; 1237 out: 1238 splx(s); 1239 1240 return (0); 1241 } 1242 1243 void 1244 gem_init_regs(struct gem_softc *sc) 1245 { 1246 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1247 bus_space_tag_t t = sc->sc_bustag; 1248 bus_space_handle_t h = sc->sc_h1; 1249 const u_char *laddr = CLLADDR(ifp->if_sadl); 1250 uint32_t v; 1251 1252 /* These regs are not cleared on reset */ 1253 if (!sc->sc_inited) { 1254 1255 /* Load recommended values */ 1256 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1257 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1258 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1259 1260 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1261 /* Max frame and max burst size */ 1262 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1263 ETHER_MAX_LEN | (0x2000<<16)); 1264 1265 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1266 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1267 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1268 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1269 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1270 ((laddr[5]<<8)|laddr[4])&0x3ff); 1271 1272 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1273 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1274 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1275 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1276 1277 /* MAC control addr set to 01:80:c2:00:00:01 */ 1278 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1279 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1280 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1281 1282 /* MAC filter addr set to 0:0:0:0:0:0 */ 1283 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1284 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1285 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1286 1287 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1288 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1289 1290 sc->sc_inited = 1; 1291 } 1292 1293 /* Counters need to be zeroed */ 1294 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1295 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1296 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1297 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1298 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1299 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1300 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1301 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1302 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1303 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1304 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1305 1306 /* Set XOFF PAUSE time. */ 1307 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1308 1309 /* 1310 * Set the internal arbitration to "infinite" bursts of the 1311 * maximum length of 31 * 64 bytes so DMA transfers aren't 1312 * split up in cache line size chunks. This greatly improves 1313 * especially RX performance. 1314 * Enable silicon bug workarounds for the Apple variants. 1315 */ 1316 bus_space_write_4(t, h, GEM_CONFIG, 1317 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1318 ((sc->sc_flags & GEM_PCI) ? 1319 GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1320 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1321 1322 /* 1323 * Set the station address. 1324 */ 1325 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1326 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1327 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1328 1329 /* 1330 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1331 */ 1332 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1333 v = GEM_MAC_XIF_TX_MII_ENA; 1334 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1335 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1336 v |= GEM_MAC_XIF_FDPLX_LED; 1337 if (sc->sc_flags & GEM_GIGABIT) 1338 v |= GEM_MAC_XIF_GMII_MODE; 1339 } 1340 } else { 1341 v |= GEM_MAC_XIF_GMII_MODE; 1342 } 1343 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1344 } 1345 1346 #ifdef GEM_DEBUG 1347 static void 1348 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1349 { 1350 int i; 1351 1352 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1353 printf("descriptor %d:\t", i); 1354 printf("gd_flags: 0x%016" PRIx64 "\t", 1355 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1356 printf("gd_addr: 0x%016" PRIx64 "\n", 1357 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1358 if (i == lastdesc) 1359 break; 1360 } 1361 } 1362 #endif 1363 1364 static void 1365 gem_start(struct ifnet *ifp) 1366 { 1367 struct gem_softc *sc = ifp->if_softc; 1368 struct mbuf *m0, *m; 1369 struct gem_txsoft *txs; 1370 bus_dmamap_t dmamap; 1371 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1372 #ifdef GEM_DEBUG 1373 int otxnext; 1374 #endif 1375 uint64_t flags = 0; 1376 1377 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING) 1378 return; 1379 1380 /* 1381 * Remember the previous number of free descriptors and 1382 * the first descriptor we'll use. 1383 */ 1384 ofree = sc->sc_txfree; 1385 #ifdef GEM_DEBUG 1386 otxnext = sc->sc_txnext; 1387 #endif 1388 1389 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1390 device_xname(sc->sc_dev), ofree, otxnext)); 1391 1392 /* 1393 * Loop through the send queue, setting up transmit descriptors 1394 * until we drain the queue, or use up all available transmit 1395 * descriptors. 1396 */ 1397 #ifdef INET 1398 next: 1399 #endif 1400 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1401 sc->sc_txfree != 0) { 1402 /* 1403 * Grab a packet off the queue. 1404 */ 1405 IFQ_POLL(&ifp->if_snd, m0); 1406 if (m0 == NULL) 1407 break; 1408 m = NULL; 1409 1410 dmamap = txs->txs_dmamap; 1411 1412 /* 1413 * Load the DMA map. If this fails, the packet either 1414 * didn't fit in the alloted number of segments, or we were 1415 * short on resources. In this case, we'll copy and try 1416 * again. 1417 */ 1418 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1419 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0 || 1420 (m0->m_pkthdr.len < ETHER_MIN_TX && 1421 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1422 if (m0->m_pkthdr.len > MCLBYTES) { 1423 aprint_error_dev(sc->sc_dev, 1424 "unable to allocate jumbo Tx cluster\n"); 1425 IFQ_DEQUEUE(&ifp->if_snd, m0); 1426 m_freem(m0); 1427 continue; 1428 } 1429 MGETHDR(m, M_DONTWAIT, MT_DATA); 1430 if (m == NULL) { 1431 aprint_error_dev(sc->sc_dev, 1432 "unable to allocate Tx mbuf\n"); 1433 break; 1434 } 1435 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1436 if (m0->m_pkthdr.len > MHLEN) { 1437 MCLGET(m, M_DONTWAIT); 1438 if ((m->m_flags & M_EXT) == 0) { 1439 aprint_error_dev(sc->sc_dev, 1440 "unable to allocate Tx cluster\n"); 1441 m_freem(m); 1442 break; 1443 } 1444 } 1445 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1446 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1447 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1448 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1449 if (error) { 1450 aprint_error_dev(sc->sc_dev, 1451 "unable to load Tx buffer, error = %d\n", 1452 error); 1453 break; 1454 } 1455 } 1456 1457 /* 1458 * Ensure we have enough descriptors free to describe 1459 * the packet. 1460 */ 1461 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1462 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1463 /* 1464 * Not enough free descriptors to transmit this 1465 * packet. 1466 */ 1467 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1468 if (m != NULL) 1469 m_freem(m); 1470 break; 1471 } 1472 1473 IFQ_DEQUEUE(&ifp->if_snd, m0); 1474 if (m != NULL) { 1475 m_freem(m0); 1476 m0 = m; 1477 } 1478 1479 /* 1480 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1481 */ 1482 1483 /* Sync the DMA map. */ 1484 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1485 BUS_DMASYNC_PREWRITE); 1486 1487 /* 1488 * Initialize the transmit descriptors. 1489 */ 1490 firsttx = sc->sc_txnext; 1491 for (nexttx = firsttx, seg = 0; 1492 seg < dmamap->dm_nsegs; 1493 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1494 1495 /* 1496 * If this is the first descriptor we're 1497 * enqueueing, set the start of packet flag, 1498 * and the checksum stuff if we want the hardware 1499 * to do it. 1500 */ 1501 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1502 if (nexttx == firsttx) { 1503 flags |= GEM_TD_START_OF_PACKET; 1504 #ifdef INET 1505 /* h/w checksum */ 1506 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1507 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1508 struct ether_header *eh; 1509 uint16_t offset, start; 1510 1511 eh = mtod(m0, struct ether_header *); 1512 switch (ntohs(eh->ether_type)) { 1513 case ETHERTYPE_IP: 1514 start = ETHER_HDR_LEN; 1515 break; 1516 case ETHERTYPE_VLAN: 1517 start = ETHER_HDR_LEN + 1518 ETHER_VLAN_ENCAP_LEN; 1519 break; 1520 default: 1521 /* unsupported, drop it */ 1522 bus_dmamap_unload(sc->sc_dmatag, 1523 dmamap); 1524 m_freem(m0); 1525 goto next; 1526 } 1527 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1528 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1529 flags |= (start << 1530 GEM_TD_CXSUM_STARTSHFT) | 1531 (offset << 1532 GEM_TD_CXSUM_STUFFSHFT) | 1533 GEM_TD_CXSUM_ENABLE; 1534 } 1535 #endif 1536 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1537 sc->sc_txwin = 0; 1538 flags |= GEM_TD_INTERRUPT_ME; 1539 } 1540 } 1541 sc->sc_txdescs[nexttx].gd_addr = 1542 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1543 if (seg == dmamap->dm_nsegs - 1) { 1544 flags |= GEM_TD_END_OF_PACKET; 1545 } else { 1546 /* last flag set outside of loop */ 1547 sc->sc_txdescs[nexttx].gd_flags = 1548 GEM_DMA_WRITE(sc, flags); 1549 } 1550 lasttx = nexttx; 1551 } 1552 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1553 /* add padding buffer at end of chain */ 1554 flags &= ~GEM_TD_END_OF_PACKET; 1555 sc->sc_txdescs[lasttx].gd_flags = 1556 GEM_DMA_WRITE(sc, flags); 1557 1558 sc->sc_txdescs[nexttx].gd_addr = 1559 GEM_DMA_WRITE(sc, 1560 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1561 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1562 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1563 lasttx = nexttx; 1564 nexttx = GEM_NEXTTX(nexttx); 1565 seg++; 1566 } 1567 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1568 1569 KASSERT(lasttx != -1); 1570 1571 /* 1572 * Store a pointer to the packet so we can free it later, 1573 * and remember what txdirty will be once the packet is 1574 * done. 1575 */ 1576 txs->txs_mbuf = m0; 1577 txs->txs_firstdesc = sc->sc_txnext; 1578 txs->txs_lastdesc = lasttx; 1579 txs->txs_ndescs = seg; 1580 1581 #ifdef GEM_DEBUG 1582 if (ifp->if_flags & IFF_DEBUG) { 1583 printf(" gem_start %p transmit chain:\n", txs); 1584 gem_txsoft_print(sc, txs->txs_firstdesc, 1585 txs->txs_lastdesc); 1586 } 1587 #endif 1588 1589 /* Sync the descriptors we're using. */ 1590 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1591 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1592 1593 /* Advance the tx pointer. */ 1594 sc->sc_txfree -= txs->txs_ndescs; 1595 sc->sc_txnext = nexttx; 1596 1597 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1598 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1599 1600 /* 1601 * Pass the packet to any BPF listeners. 1602 */ 1603 bpf_mtap(ifp, m0, BPF_D_OUT); 1604 } 1605 1606 if (sc->sc_txfree != ofree) { 1607 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1608 device_xname(sc->sc_dev), lasttx, otxnext)); 1609 /* 1610 * The entire packet chain is set up. 1611 * Kick the transmitter. 1612 */ 1613 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1614 device_xname(sc->sc_dev), nexttx)); 1615 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1616 sc->sc_txnext); 1617 1618 /* Set a watchdog timer in case the chip flakes out. */ 1619 ifp->if_timer = 5; 1620 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1621 device_xname(sc->sc_dev), ifp->if_timer)); 1622 } 1623 } 1624 1625 /* 1626 * Transmit interrupt. 1627 */ 1628 int 1629 gem_tint(struct gem_softc *sc) 1630 { 1631 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1632 bus_space_tag_t t = sc->sc_bustag; 1633 bus_space_handle_t mac = sc->sc_h1; 1634 struct gem_txsoft *txs; 1635 int txlast; 1636 int progress = 0; 1637 uint32_t v; 1638 1639 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1640 1641 DPRINTF(sc, ("%s: gem_tint\n", device_xname(sc->sc_dev))); 1642 1643 /* Unload collision counters ... */ 1644 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1645 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1646 if_statadd_ref(nsr, if_collisions, v + 1647 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1648 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT)); 1649 if_statadd_ref(nsr, if_oerrors, v); 1650 1651 /* ... then clear the hardware counters. */ 1652 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1653 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1654 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1655 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1656 1657 /* 1658 * Go through our Tx list and free mbufs for those 1659 * frames that have been transmitted. 1660 */ 1661 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1662 /* 1663 * In theory, we could harvest some descriptors before 1664 * the ring is empty, but that's a bit complicated. 1665 * 1666 * GEM_TX_COMPLETION points to the last descriptor 1667 * processed +1. 1668 * 1669 * Let's assume that the NIC writes back to the Tx 1670 * descriptors before it updates the completion 1671 * register. If the NIC has posted writes to the 1672 * Tx descriptors, PCI ordering requires that the 1673 * posted writes flush to RAM before the register-read 1674 * finishes. So let's read the completion register, 1675 * before syncing the descriptors, so that we 1676 * examine Tx descriptors that are at least as 1677 * current as the completion register. 1678 */ 1679 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1680 DPRINTF(sc, 1681 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1682 txs->txs_lastdesc, txlast)); 1683 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1684 if (txlast >= txs->txs_firstdesc && 1685 txlast <= txs->txs_lastdesc) 1686 break; 1687 } else if (txlast >= txs->txs_firstdesc || 1688 txlast <= txs->txs_lastdesc) 1689 break; 1690 1691 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1692 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1693 1694 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1695 if (ifp->if_flags & IFF_DEBUG) { 1696 printf(" txsoft %p transmit chain:\n", txs); 1697 gem_txsoft_print(sc, txs->txs_firstdesc, 1698 txs->txs_lastdesc); 1699 } 1700 #endif 1701 1702 1703 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1704 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1705 1706 sc->sc_txfree += txs->txs_ndescs; 1707 1708 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1709 0, txs->txs_dmamap->dm_mapsize, 1710 BUS_DMASYNC_POSTWRITE); 1711 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1712 if (txs->txs_mbuf != NULL) { 1713 m_freem(txs->txs_mbuf); 1714 txs->txs_mbuf = NULL; 1715 } 1716 1717 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1718 1719 if_statinc_ref(nsr, if_opackets); 1720 progress = 1; 1721 } 1722 1723 IF_STAT_PUTREF(ifp); 1724 1725 #if 0 1726 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1727 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1728 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1729 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1730 GEM_TX_DATA_PTR_HI) << 32) | 1731 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1732 GEM_TX_DATA_PTR_LO), 1733 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1734 #endif 1735 1736 if (progress) { 1737 if (sc->sc_txfree == GEM_NTXDESC - 1) 1738 sc->sc_txwin = 0; 1739 1740 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1741 if_schedule_deferred_start(ifp); 1742 } 1743 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1744 device_xname(sc->sc_dev), ifp->if_timer)); 1745 1746 return (1); 1747 } 1748 1749 /* 1750 * Receive interrupt. 1751 */ 1752 int 1753 gem_rint(struct gem_softc *sc) 1754 { 1755 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1756 bus_space_tag_t t = sc->sc_bustag; 1757 bus_space_handle_t h = sc->sc_h1; 1758 struct gem_rxsoft *rxs; 1759 struct mbuf *m; 1760 uint64_t rxstat; 1761 uint32_t rxcomp; 1762 int i, len, progress = 0; 1763 1764 DPRINTF(sc, ("%s: gem_rint\n", device_xname(sc->sc_dev))); 1765 1766 /* 1767 * Ignore spurious interrupt that sometimes occurs before 1768 * we are set up when we network boot. 1769 */ 1770 if (!sc->sc_meminited) 1771 return 1; 1772 1773 /* 1774 * Read the completion register once. This limits 1775 * how long the following loop can execute. 1776 */ 1777 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1778 1779 /* 1780 * XXX Read the lastrx only once at the top for speed. 1781 */ 1782 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1783 sc->sc_rxptr, rxcomp)); 1784 1785 /* 1786 * Go into the loop at least once. 1787 */ 1788 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1789 i = GEM_NEXTRX(i)) { 1790 rxs = &sc->sc_rxsoft[i]; 1791 1792 GEM_CDRXSYNC(sc, i, 1793 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1794 1795 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1796 1797 if (rxstat & GEM_RD_OWN) { 1798 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1799 /* 1800 * We have processed all of the receive buffers. 1801 */ 1802 break; 1803 } 1804 1805 progress++; 1806 1807 if (rxstat & GEM_RD_BAD_CRC) { 1808 if_statinc(ifp, if_ierrors); 1809 DPRINTF(sc, ("%s: receive error: CRC error\n", 1810 device_xname(sc->sc_dev))); 1811 GEM_INIT_RXDESC(sc, i); 1812 continue; 1813 } 1814 1815 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1816 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1817 #ifdef GEM_DEBUG 1818 if (ifp->if_flags & IFF_DEBUG) { 1819 printf(" rxsoft %p descriptor %d: ", rxs, i); 1820 printf("gd_flags: 0x%016llx\t", (long long) 1821 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1822 printf("gd_addr: 0x%016llx\n", (long long) 1823 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1824 } 1825 #endif 1826 1827 /* No errors; receive the packet. */ 1828 len = GEM_RD_BUFLEN(rxstat); 1829 1830 /* 1831 * Allocate a new mbuf cluster. If that fails, we are 1832 * out of memory, and must drop the packet and recycle 1833 * the buffer that's already attached to this descriptor. 1834 */ 1835 m = rxs->rxs_mbuf; 1836 if (gem_add_rxbuf(sc, i) != 0) { 1837 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1838 if_statinc(ifp, if_ierrors); 1839 aprint_error_dev(sc->sc_dev, 1840 "receive error: RX no buffer space\n"); 1841 GEM_INIT_RXDESC(sc, i); 1842 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1843 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1844 continue; 1845 } 1846 m->m_data += 2; /* We're already off by two */ 1847 1848 m_set_rcvif(m, ifp); 1849 m->m_pkthdr.len = m->m_len = len; 1850 1851 #ifdef INET 1852 /* hardware checksum */ 1853 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1854 struct ether_header *eh; 1855 struct ip *ip; 1856 int32_t hlen, pktlen; 1857 1858 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1859 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1860 ETHER_VLAN_ENCAP_LEN; 1861 eh = (struct ether_header *) (mtod(m, char *) + 1862 ETHER_VLAN_ENCAP_LEN); 1863 } else { 1864 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1865 eh = mtod(m, struct ether_header *); 1866 } 1867 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1868 goto swcsum; 1869 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1870 1871 /* IPv4 only */ 1872 if (ip->ip_v != IPVERSION) 1873 goto swcsum; 1874 1875 hlen = ip->ip_hl << 2; 1876 if (hlen < sizeof(struct ip)) 1877 goto swcsum; 1878 1879 /* 1880 * bail if too short, has random trailing garbage, 1881 * truncated, fragment, or has ethernet pad. 1882 */ 1883 if ((ntohs(ip->ip_len) < hlen) || 1884 (ntohs(ip->ip_len) != pktlen) || 1885 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1886 goto swcsum; 1887 1888 switch (ip->ip_p) { 1889 case IPPROTO_TCP: 1890 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1891 goto swcsum; 1892 if (pktlen < (hlen + sizeof(struct tcphdr))) 1893 goto swcsum; 1894 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1895 break; 1896 case IPPROTO_UDP: 1897 /* FALLTHROUGH */ 1898 default: 1899 goto swcsum; 1900 } 1901 1902 /* the uncomplemented sum is expected */ 1903 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1904 1905 /* if the pkt had ip options, we have to deduct them */ 1906 if (hlen > sizeof(struct ip)) { 1907 uint16_t *opts; 1908 uint32_t optsum, temp; 1909 1910 optsum = 0; 1911 temp = hlen - sizeof(struct ip); 1912 opts = (uint16_t *) ((char *) ip + 1913 sizeof(struct ip)); 1914 1915 while (temp > 1) { 1916 optsum += ntohs(*opts++); 1917 temp -= 2; 1918 } 1919 while (optsum >> 16) 1920 optsum = (optsum >> 16) + 1921 (optsum & 0xffff); 1922 1923 /* Deduct ip opts sum from hwsum. */ 1924 m->m_pkthdr.csum_data += (uint16_t)~optsum; 1925 1926 while (m->m_pkthdr.csum_data >> 16) 1927 m->m_pkthdr.csum_data = 1928 (m->m_pkthdr.csum_data >> 16) + 1929 (m->m_pkthdr.csum_data & 1930 0xffff); 1931 } 1932 1933 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1934 M_CSUM_NO_PSEUDOHDR; 1935 } else 1936 swcsum: 1937 m->m_pkthdr.csum_flags = 0; 1938 #endif 1939 /* Pass it on. */ 1940 if_percpuq_enqueue(ifp->if_percpuq, m); 1941 } 1942 1943 if (progress) { 1944 /* Update the receive pointer. */ 1945 if (i == sc->sc_rxptr) { 1946 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1947 #ifdef GEM_DEBUG 1948 if (ifp->if_flags & IFF_DEBUG) 1949 printf("%s: rint: ring wrap\n", 1950 device_xname(sc->sc_dev)); 1951 #endif 1952 } 1953 sc->sc_rxptr = i; 1954 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1955 } 1956 #ifdef GEM_COUNTERS 1957 if (progress <= 4) { 1958 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1959 } else if (progress < 32) { 1960 if (progress < 16) 1961 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1962 else 1963 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1964 1965 } else { 1966 if (progress < 64) 1967 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1968 else 1969 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1970 } 1971 #endif 1972 1973 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1974 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1975 1976 /* Read error counters ... */ 1977 if_statadd(ifp, if_ierrors, 1978 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1979 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1980 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1981 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL)); 1982 1983 /* ... then clear the hardware counters. */ 1984 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1985 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1986 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1987 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1988 1989 return (1); 1990 } 1991 1992 1993 /* 1994 * gem_add_rxbuf: 1995 * 1996 * Add a receive buffer to the indicated descriptor. 1997 */ 1998 int 1999 gem_add_rxbuf(struct gem_softc *sc, int idx) 2000 { 2001 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2002 struct mbuf *m; 2003 int error; 2004 2005 MGETHDR(m, M_DONTWAIT, MT_DATA); 2006 if (m == NULL) 2007 return (ENOBUFS); 2008 2009 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2010 MCLGET(m, M_DONTWAIT); 2011 if ((m->m_flags & M_EXT) == 0) { 2012 m_freem(m); 2013 return (ENOBUFS); 2014 } 2015 2016 #ifdef GEM_DEBUG 2017 /* bzero the packet to check DMA */ 2018 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 2019 #endif 2020 2021 if (rxs->rxs_mbuf != NULL) 2022 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 2023 2024 rxs->rxs_mbuf = m; 2025 2026 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 2027 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2028 BUS_DMA_READ | BUS_DMA_NOWAIT); 2029 if (error) { 2030 aprint_error_dev(sc->sc_dev, 2031 "can't load rx DMA map %d, error = %d\n", idx, error); 2032 panic("gem_add_rxbuf"); /* XXX */ 2033 } 2034 2035 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 2036 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2037 2038 GEM_INIT_RXDESC(sc, idx); 2039 2040 return (0); 2041 } 2042 2043 2044 int 2045 gem_eint(struct gem_softc *sc, u_int status) 2046 { 2047 char bits[128]; 2048 uint32_t r, v; 2049 2050 if ((status & GEM_INTR_MIF) != 0) { 2051 printf("%s: XXXlink status changed\n", device_xname(sc->sc_dev)); 2052 return (1); 2053 } 2054 2055 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 2056 gem_reset_rxdma(sc); 2057 return (1); 2058 } 2059 2060 if (status & GEM_INTR_BERR) { 2061 if (sc->sc_flags & GEM_PCI) 2062 r = GEM_ERROR_STATUS; 2063 else 2064 r = GEM_SBUS_ERROR_STATUS; 2065 bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2066 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2067 aprint_error_dev(sc->sc_dev, "bus error interrupt: 0x%02x\n", 2068 v); 2069 return (1); 2070 } 2071 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2072 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 2073 2074 return (1); 2075 } 2076 2077 2078 /* 2079 * PCS interrupts. 2080 * We should receive these when the link status changes, but sometimes 2081 * we don't receive them for link up. We compensate for this in the 2082 * gem_tick() callout. 2083 */ 2084 int 2085 gem_pint(struct gem_softc *sc) 2086 { 2087 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2088 bus_space_tag_t t = sc->sc_bustag; 2089 bus_space_handle_t h = sc->sc_h1; 2090 uint32_t v, v2; 2091 2092 /* 2093 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2094 * latched, so we have to read it twice. There is only one bit in 2095 * use, so the value is meaningless. 2096 */ 2097 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2098 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2099 2100 if ((ifp->if_flags & IFF_UP) == 0) 2101 return 1; 2102 2103 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2104 return 1; 2105 2106 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2107 /* If we see remote fault, our link partner is probably going away */ 2108 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2109 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2110 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2111 /* Otherwise, we may need to wait after auto-negotiation completes */ 2112 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2113 GEM_MII_STATUS_ANEG_CPT) { 2114 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2115 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2116 } 2117 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2118 if (sc->sc_flags & GEM_LINK) { 2119 return 1; 2120 } 2121 callout_stop(&sc->sc_tick_ch); 2122 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2123 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2124 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2125 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2126 v &= v2; 2127 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2128 sc->sc_mii.mii_media_active |= IFM_FDX; 2129 #ifdef GEM_DEBUG 2130 aprint_debug_dev(sc->sc_dev, "link up: full duplex\n"); 2131 #endif 2132 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2133 sc->sc_mii.mii_media_active |= IFM_HDX; 2134 #ifdef GEM_DEBUG 2135 aprint_debug_dev(sc->sc_dev, "link up: half duplex\n"); 2136 #endif 2137 } else { 2138 #ifdef GEM_DEBUG 2139 aprint_debug_dev(sc->sc_dev, "duplex mismatch\n"); 2140 #endif 2141 } 2142 gem_statuschange(sc); 2143 } else { 2144 if ((sc->sc_flags & GEM_LINK) == 0) { 2145 return 1; 2146 } 2147 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2148 sc->sc_mii.mii_media_status = IFM_AVALID; 2149 #ifdef GEM_DEBUG 2150 aprint_debug_dev(sc->sc_dev, "link down\n"); 2151 #endif 2152 gem_statuschange(sc); 2153 2154 /* Start the 10 second timer */ 2155 callout_schedule(&sc->sc_tick_ch, hz * 10); 2156 } 2157 return 1; 2158 } 2159 2160 2161 2162 int 2163 gem_intr(void *v) 2164 { 2165 struct gem_softc *sc = v; 2166 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2167 bus_space_tag_t t = sc->sc_bustag; 2168 bus_space_handle_t h = sc->sc_h1; 2169 uint32_t status; 2170 int r = 0; 2171 #ifdef GEM_DEBUG 2172 char bits[128]; 2173 #endif 2174 2175 /* XXX We should probably mask out interrupts until we're done */ 2176 2177 sc->sc_ev_intr.ev_count++; 2178 2179 status = bus_space_read_4(t, h, GEM_STATUS); 2180 #ifdef GEM_DEBUG 2181 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2182 #endif 2183 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2184 device_xname(sc->sc_dev), (status >> 19), bits)); 2185 2186 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2187 r |= gem_eint(sc, status); 2188 2189 /* We don't bother with GEM_INTR_TX_DONE */ 2190 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2191 GEM_COUNTER_INCR(sc, sc_ev_txint); 2192 r |= gem_tint(sc); 2193 } 2194 2195 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2196 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2197 r |= gem_rint(sc); 2198 } 2199 2200 /* We should eventually do more than just print out error stats. */ 2201 if (status & GEM_INTR_TX_MAC) { 2202 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2203 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2204 printf("%s: MAC tx fault, status %x\n", 2205 device_xname(sc->sc_dev), txstat); 2206 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2207 gem_init(ifp); 2208 } 2209 if (status & GEM_INTR_RX_MAC) { 2210 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2211 /* 2212 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2213 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2214 * silicon bug so handle them silently. So if we detect 2215 * an RX FIFO overflow, we fire off a timer, and check 2216 * whether we're still making progress by looking at the 2217 * RX FIFO write and read pointers. 2218 */ 2219 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2220 if_statinc(ifp, if_ierrors); 2221 GEM_COUNTER_INCR(sc, sc_ev_rxoverflow); 2222 #ifdef GEM_DEBUG 2223 aprint_error_dev(sc->sc_dev, 2224 "receive error: RX overflow sc->rxptr %d, complete %d\n", sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)); 2225 #endif 2226 sc->sc_rx_fifo_wr_ptr = 2227 bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 2228 sc->sc_rx_fifo_rd_ptr = 2229 bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 2230 callout_schedule(&sc->sc_rx_watchdog, 400); 2231 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2232 printf("%s: MAC rx fault, status 0x%02x\n", 2233 device_xname(sc->sc_dev), rxstat); 2234 } 2235 if (status & GEM_INTR_PCS) { 2236 r |= gem_pint(sc); 2237 } 2238 2239 /* Do we need to do anything with these? 2240 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2241 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2242 if ((status2 & GEM_MAC_PAUSED) != 0) 2243 aprintf_debug_dev(sc->sc_dev, "PAUSE received (%d slots)\n", 2244 GEM_MAC_PAUSE_TIME(status2)); 2245 if ((status2 & GEM_MAC_PAUSE) != 0) 2246 aprintf_debug_dev(sc->sc_dev, "transited to PAUSE state\n"); 2247 if ((status2 & GEM_MAC_RESUME) != 0) 2248 aprintf_debug_dev(sc->sc_dev, "transited to non-PAUSE state\n"); 2249 } 2250 if ((status & GEM_INTR_MIF) != 0) 2251 aprintf_debug_dev(sc->sc_dev, "MIF interrupt\n"); 2252 */ 2253 rnd_add_uint32(&sc->rnd_source, status); 2254 return (r); 2255 } 2256 2257 void 2258 gem_rx_watchdog(void *arg) 2259 { 2260 struct gem_softc *sc = arg; 2261 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2262 bus_space_tag_t t = sc->sc_bustag; 2263 bus_space_handle_t h = sc->sc_h1; 2264 uint32_t rx_fifo_wr_ptr; 2265 uint32_t rx_fifo_rd_ptr; 2266 uint32_t state; 2267 2268 if ((ifp->if_flags & IFF_RUNNING) == 0) { 2269 aprint_error_dev(sc->sc_dev, "receiver not running\n"); 2270 return; 2271 } 2272 2273 rx_fifo_wr_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 2274 rx_fifo_rd_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 2275 state = bus_space_read_4(t, h, GEM_MAC_MAC_STATE); 2276 if ((state & GEM_MAC_STATE_OVERFLOW) == GEM_MAC_STATE_OVERFLOW && 2277 ((rx_fifo_wr_ptr == rx_fifo_rd_ptr) || 2278 ((sc->sc_rx_fifo_wr_ptr == rx_fifo_wr_ptr) && 2279 (sc->sc_rx_fifo_rd_ptr == rx_fifo_rd_ptr)))) 2280 { 2281 /* 2282 * The RX state machine is still in overflow state and 2283 * the RX FIFO write and read pointers seem to be 2284 * stuck. Whack the chip over the head to get things 2285 * going again. 2286 */ 2287 aprint_error_dev(sc->sc_dev, 2288 "receiver stuck in overflow, resetting\n"); 2289 gem_init(ifp); 2290 } else { 2291 int needreset = 1; 2292 if ((state & GEM_MAC_STATE_OVERFLOW) != GEM_MAC_STATE_OVERFLOW) { 2293 DPRINTF(sc, 2294 ("%s: rx_watchdog: not in overflow state: 0x%x\n", 2295 device_xname(sc->sc_dev), state)); 2296 } 2297 if (rx_fifo_wr_ptr != rx_fifo_rd_ptr) { 2298 DPRINTF(sc, 2299 ("%s: rx_watchdog: wr & rd ptr different\n", 2300 device_xname(sc->sc_dev))); 2301 needreset = 0; 2302 } 2303 if (sc->sc_rx_fifo_wr_ptr != rx_fifo_wr_ptr) { 2304 DPRINTF(sc, ("%s: rx_watchdog: wr pointer != saved\n", 2305 device_xname(sc->sc_dev))); 2306 needreset = 0; 2307 } 2308 if (sc->sc_rx_fifo_rd_ptr != rx_fifo_rd_ptr) { 2309 DPRINTF(sc, ("%s: rx_watchdog: rd pointer != saved\n", 2310 device_xname(sc->sc_dev))); 2311 needreset = 0; 2312 } 2313 if (needreset) { 2314 aprint_error_dev(sc->sc_dev, 2315 "rx_watchdog: resetting anyway\n"); 2316 gem_init(ifp); 2317 } 2318 } 2319 } 2320 2321 void 2322 gem_watchdog(struct ifnet *ifp) 2323 { 2324 struct gem_softc *sc = ifp->if_softc; 2325 2326 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2327 "GEM_MAC_RX_CONFIG %x\n", 2328 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2329 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2330 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2331 2332 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 2333 if_statinc(ifp, if_oerrors); 2334 2335 /* Try to get more packets going. */ 2336 gem_init(ifp); 2337 gem_start(ifp); 2338 } 2339 2340 /* 2341 * Initialize the MII Management Interface 2342 */ 2343 void 2344 gem_mifinit(struct gem_softc *sc) 2345 { 2346 bus_space_tag_t t = sc->sc_bustag; 2347 bus_space_handle_t mif = sc->sc_h1; 2348 2349 /* Configure the MIF in frame mode */ 2350 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2351 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2352 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2353 } 2354 2355 /* 2356 * MII interface 2357 * 2358 * The GEM MII interface supports at least three different operating modes: 2359 * 2360 * Bitbang mode is implemented using data, clock and output enable registers. 2361 * 2362 * Frame mode is implemented by loading a complete frame into the frame 2363 * register and polling the valid bit for completion. 2364 * 2365 * Polling mode uses the frame register but completion is indicated by 2366 * an interrupt. 2367 * 2368 */ 2369 static int 2370 gem_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 2371 { 2372 struct gem_softc *sc = device_private(self); 2373 bus_space_tag_t t = sc->sc_bustag; 2374 bus_space_handle_t mif = sc->sc_h1; 2375 int n; 2376 uint32_t v; 2377 2378 #ifdef GEM_DEBUG1 2379 if (sc->sc_debug) 2380 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2381 #endif 2382 2383 /* Construct the frame command */ 2384 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2385 GEM_MIF_FRAME_READ; 2386 2387 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2388 for (n = 0; n < 100; n++) { 2389 DELAY(1); 2390 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2391 if (v & GEM_MIF_FRAME_TA0) { 2392 *val = v & GEM_MIF_FRAME_DATA; 2393 return 0; 2394 } 2395 } 2396 2397 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 2398 return ETIMEDOUT; 2399 } 2400 2401 static int 2402 gem_mii_writereg(device_t self, int phy, int reg, uint16_t val) 2403 { 2404 struct gem_softc *sc = device_private(self); 2405 bus_space_tag_t t = sc->sc_bustag; 2406 bus_space_handle_t mif = sc->sc_h1; 2407 int n; 2408 uint32_t v; 2409 2410 #ifdef GEM_DEBUG1 2411 if (sc->sc_debug) 2412 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2413 phy, reg, val); 2414 #endif 2415 2416 /* Construct the frame command */ 2417 v = GEM_MIF_FRAME_WRITE | 2418 (phy << GEM_MIF_PHY_SHIFT) | 2419 (reg << GEM_MIF_REG_SHIFT) | 2420 (val & GEM_MIF_FRAME_DATA); 2421 2422 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2423 for (n = 0; n < 100; n++) { 2424 DELAY(1); 2425 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2426 if (v & GEM_MIF_FRAME_TA0) 2427 return 0; 2428 } 2429 2430 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 2431 return ETIMEDOUT; 2432 } 2433 2434 static void 2435 gem_mii_statchg(struct ifnet *ifp) 2436 { 2437 struct gem_softc *sc = ifp->if_softc; 2438 #ifdef GEM_DEBUG 2439 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2440 #endif 2441 2442 #ifdef GEM_DEBUG 2443 if (sc->sc_debug) 2444 printf("gem_mii_statchg: status change: phy = %d\n", 2445 sc->sc_phys[instance]); 2446 #endif 2447 gem_statuschange(sc); 2448 } 2449 2450 /* 2451 * Common status change for gem_mii_statchg() and gem_pint() 2452 */ 2453 void 2454 gem_statuschange(struct gem_softc* sc) 2455 { 2456 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2457 bus_space_tag_t t = sc->sc_bustag; 2458 bus_space_handle_t mac = sc->sc_h1; 2459 int gigabit; 2460 uint32_t rxcfg, txcfg, v; 2461 2462 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2463 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2464 sc->sc_flags |= GEM_LINK; 2465 else 2466 sc->sc_flags &= ~GEM_LINK; 2467 2468 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2469 gigabit = 1; 2470 else 2471 gigabit = 0; 2472 2473 /* 2474 * The configuration done here corresponds to the steps F) and 2475 * G) and as far as enabling of RX and TX MAC goes also step H) 2476 * of the initialization sequence outlined in section 3.2.1 of 2477 * the GEM Gigabit Ethernet ASIC Specification. 2478 */ 2479 2480 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2481 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2482 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2483 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2484 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2485 else if (gigabit) { 2486 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2487 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2488 } 2489 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2490 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2491 BUS_SPACE_BARRIER_WRITE); 2492 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2493 aprint_normal_dev(sc->sc_dev, "cannot disable TX MAC\n"); 2494 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2495 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2496 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2497 BUS_SPACE_BARRIER_WRITE); 2498 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2499 aprint_normal_dev(sc->sc_dev, "cannot disable RX MAC\n"); 2500 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2501 2502 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2503 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2504 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2505 2506 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2507 gigabit != 0) 2508 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2509 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2510 else 2511 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2512 GEM_MAC_SLOT_TIME_NORMAL); 2513 2514 /* XIF Configuration */ 2515 if (sc->sc_flags & GEM_LINK) 2516 v = GEM_MAC_XIF_LINK_LED; 2517 else 2518 v = 0; 2519 v |= GEM_MAC_XIF_TX_MII_ENA; 2520 2521 /* If an external transceiver is connected, enable its MII drivers */ 2522 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2523 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2524 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2525 if (gigabit) 2526 v |= GEM_MAC_XIF_GMII_MODE; 2527 else 2528 v &= ~GEM_MAC_XIF_GMII_MODE; 2529 } else 2530 /* Internal MII needs buf enable */ 2531 v |= GEM_MAC_XIF_MII_BUF_ENA; 2532 /* MII needs echo disable if half duplex. */ 2533 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2534 /* turn on full duplex LED */ 2535 v |= GEM_MAC_XIF_FDPLX_LED; 2536 else 2537 /* half duplex -- disable echo */ 2538 v |= GEM_MAC_XIF_ECHO_DISABL; 2539 } else { 2540 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2541 v |= GEM_MAC_XIF_FDPLX_LED; 2542 v |= GEM_MAC_XIF_GMII_MODE; 2543 } 2544 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2545 2546 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2547 (sc->sc_flags & GEM_LINK) != 0) { 2548 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2549 txcfg | GEM_MAC_TX_ENABLE); 2550 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2551 rxcfg | GEM_MAC_RX_ENABLE); 2552 } 2553 } 2554 2555 int 2556 gem_ser_mediachange(struct ifnet *ifp) 2557 { 2558 struct gem_softc *sc = ifp->if_softc; 2559 u_int s, t; 2560 2561 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2562 return EINVAL; 2563 2564 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2565 if (s == IFM_AUTO) { 2566 if (sc->sc_mii_media != s) { 2567 #ifdef GEM_DEBUG 2568 aprint_debug_dev(sc->sc_dev, "setting media to auto\n"); 2569 #endif 2570 sc->sc_mii_media = s; 2571 if (ifp->if_flags & IFF_UP) { 2572 gem_pcs_stop(sc, 0); 2573 gem_pcs_start(sc); 2574 } 2575 } 2576 return 0; 2577 } 2578 if (s == IFM_1000_SX) { 2579 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media) 2580 & (IFM_FDX | IFM_HDX); 2581 if ((sc->sc_mii_media & (IFM_FDX | IFM_HDX)) != t) { 2582 sc->sc_mii_media &= ~(IFM_FDX | IFM_HDX); 2583 sc->sc_mii_media |= t; 2584 #ifdef GEM_DEBUG 2585 aprint_debug_dev(sc->sc_dev, 2586 "setting media to 1000baseSX-%s\n", 2587 t == IFM_FDX ? "FDX" : "HDX"); 2588 #endif 2589 if (ifp->if_flags & IFF_UP) { 2590 gem_pcs_stop(sc, 0); 2591 gem_pcs_start(sc); 2592 } 2593 } 2594 return 0; 2595 } 2596 return EINVAL; 2597 } 2598 2599 void 2600 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2601 { 2602 struct gem_softc *sc = ifp->if_softc; 2603 2604 if ((ifp->if_flags & IFF_UP) == 0) 2605 return; 2606 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2607 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2608 } 2609 2610 static int 2611 gem_ifflags_cb(struct ethercom *ec) 2612 { 2613 struct ifnet *ifp = &ec->ec_if; 2614 struct gem_softc *sc = ifp->if_softc; 2615 u_short change = ifp->if_flags ^ sc->sc_if_flags; 2616 2617 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 2618 return ENETRESET; 2619 else if ((change & IFF_PROMISC) != 0) 2620 gem_setladrf(sc); 2621 return 0; 2622 } 2623 2624 /* 2625 * Process an ioctl request. 2626 */ 2627 int 2628 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 2629 { 2630 struct gem_softc *sc = ifp->if_softc; 2631 int s, error = 0; 2632 2633 s = splnet(); 2634 2635 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2636 error = 0; 2637 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2638 ; 2639 else if (ifp->if_flags & IFF_RUNNING) { 2640 /* 2641 * Multicast list has changed; set the hardware filter 2642 * accordingly. 2643 */ 2644 gem_setladrf(sc); 2645 } 2646 } 2647 2648 /* Try to get things going again */ 2649 if (ifp->if_flags & IFF_UP) 2650 gem_start(ifp); 2651 splx(s); 2652 return (error); 2653 } 2654 2655 static void 2656 gem_inten(struct gem_softc *sc) 2657 { 2658 bus_space_tag_t t = sc->sc_bustag; 2659 bus_space_handle_t h = sc->sc_h1; 2660 uint32_t v; 2661 2662 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 2663 v = GEM_INTR_PCS; 2664 else 2665 v = GEM_INTR_MIF; 2666 bus_space_write_4(t, h, GEM_INTMASK, 2667 ~(GEM_INTR_TX_INTME | 2668 GEM_INTR_TX_EMPTY | 2669 GEM_INTR_TX_MAC | 2670 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF | 2671 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL | 2672 GEM_INTR_BERR | v)); 2673 } 2674 2675 bool 2676 gem_resume(device_t self, const pmf_qual_t *qual) 2677 { 2678 struct gem_softc *sc = device_private(self); 2679 2680 gem_inten(sc); 2681 2682 return true; 2683 } 2684 2685 bool 2686 gem_suspend(device_t self, const pmf_qual_t *qual) 2687 { 2688 struct gem_softc *sc = device_private(self); 2689 bus_space_tag_t t = sc->sc_bustag; 2690 bus_space_handle_t h = sc->sc_h1; 2691 2692 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 2693 2694 return true; 2695 } 2696 2697 bool 2698 gem_shutdown(device_t self, int howto) 2699 { 2700 struct gem_softc *sc = device_private(self); 2701 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2702 2703 gem_stop(ifp, 1); 2704 2705 return true; 2706 } 2707 2708 /* 2709 * Set up the logical address filter. 2710 */ 2711 void 2712 gem_setladrf(struct gem_softc *sc) 2713 { 2714 struct ethercom *ec = &sc->sc_ethercom; 2715 struct ifnet *ifp = &ec->ec_if; 2716 struct ether_multi *enm; 2717 struct ether_multistep step; 2718 bus_space_tag_t t = sc->sc_bustag; 2719 bus_space_handle_t h = sc->sc_h1; 2720 uint32_t crc; 2721 uint32_t hash[16]; 2722 uint32_t v; 2723 int i; 2724 2725 /* Get current RX configuration */ 2726 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2727 2728 /* 2729 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2730 * and hash filter. Depending on the case, the right bit will be 2731 * enabled. 2732 */ 2733 v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_HASH_FILTER | 2734 GEM_MAC_RX_PROMISC_GRP); 2735 2736 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2737 /* Turn on promiscuous mode */ 2738 v |= GEM_MAC_RX_PROMISCUOUS; 2739 ifp->if_flags |= IFF_ALLMULTI; 2740 goto chipit; 2741 } 2742 2743 /* 2744 * Set up multicast address filter by passing all multicast addresses 2745 * through a crc generator, and then using the high order 8 bits as an 2746 * index into the 256 bit logical address filter. The high order 4 2747 * bits selects the word, while the other 4 bits select the bit within 2748 * the word (where bit 0 is the MSB). 2749 */ 2750 2751 /* Clear hash table */ 2752 memset(hash, 0, sizeof(hash)); 2753 2754 ETHER_LOCK(ec); 2755 ETHER_FIRST_MULTI(step, ec, enm); 2756 while (enm != NULL) { 2757 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2758 /* 2759 * We must listen to a range of multicast addresses. 2760 * For now, just accept all multicasts, rather than 2761 * trying to set only those filter bits needed to match 2762 * the range. (At this time, the only use of address 2763 * ranges is for IP multicast routing, for which the 2764 * range is big enough to require all bits set.) 2765 * XXX should use the address filters for this 2766 */ 2767 ifp->if_flags |= IFF_ALLMULTI; 2768 v |= GEM_MAC_RX_PROMISC_GRP; 2769 ETHER_UNLOCK(ec); 2770 goto chipit; 2771 } 2772 2773 /* Get the LE CRC32 of the address */ 2774 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2775 2776 /* Just want the 8 most significant bits. */ 2777 crc >>= 24; 2778 2779 /* Set the corresponding bit in the filter. */ 2780 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2781 2782 ETHER_NEXT_MULTI(step, enm); 2783 } 2784 ETHER_UNLOCK(ec); 2785 2786 v |= GEM_MAC_RX_HASH_FILTER; 2787 ifp->if_flags &= ~IFF_ALLMULTI; 2788 2789 /* Now load the hash table into the chip (if we are using it) */ 2790 for (i = 0; i < 16; i++) { 2791 bus_space_write_4(t, h, 2792 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2793 hash[i]); 2794 } 2795 2796 chipit: 2797 sc->sc_if_flags = ifp->if_flags; 2798 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2799 } 2800