1 /* $NetBSD: gem.c,v 1.47 2006/08/05 21:26:49 sanjayl Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.47 2006/08/05 21:26:49 sanjayl Exp $"); 38 39 #include "opt_inet.h" 40 #include "bpfilter.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/syslog.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 54 #include <machine/endian.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #endif 75 76 #include <machine/bus.h> 77 #include <machine/intr.h> 78 79 #include <dev/mii/mii.h> 80 #include <dev/mii/miivar.h> 81 #include <dev/mii/mii_bitbang.h> 82 83 #include <dev/ic/gemreg.h> 84 #include <dev/ic/gemvar.h> 85 86 #define TRIES 10000 87 88 static void gem_start(struct ifnet *); 89 static void gem_stop(struct ifnet *, int); 90 int gem_ioctl(struct ifnet *, u_long, caddr_t); 91 void gem_tick(void *); 92 void gem_watchdog(struct ifnet *); 93 void gem_shutdown(void *); 94 int gem_init(struct ifnet *); 95 void gem_init_regs(struct gem_softc *sc); 96 static int gem_ringsize(int sz); 97 static int gem_meminit(struct gem_softc *); 98 void gem_mifinit(struct gem_softc *); 99 static int gem_bitwait(struct gem_softc *sc, int, u_int32_t, u_int32_t); 100 void gem_reset(struct gem_softc *); 101 int gem_reset_rx(struct gem_softc *sc); 102 int gem_reset_tx(struct gem_softc *sc); 103 int gem_disable_rx(struct gem_softc *sc); 104 int gem_disable_tx(struct gem_softc *sc); 105 static void gem_rxdrain(struct gem_softc *sc); 106 int gem_add_rxbuf(struct gem_softc *sc, int idx); 107 void gem_setladrf(struct gem_softc *); 108 109 /* MII methods & callbacks */ 110 static int gem_mii_readreg(struct device *, int, int); 111 static void gem_mii_writereg(struct device *, int, int, int); 112 static void gem_mii_statchg(struct device *); 113 114 int gem_mediachange(struct ifnet *); 115 void gem_mediastatus(struct ifnet *, struct ifmediareq *); 116 117 struct mbuf *gem_get(struct gem_softc *, int, int); 118 int gem_put(struct gem_softc *, int, struct mbuf *); 119 void gem_read(struct gem_softc *, int, int); 120 int gem_eint(struct gem_softc *, u_int); 121 int gem_rint(struct gem_softc *); 122 int gem_tint(struct gem_softc *); 123 void gem_power(int, void *); 124 125 #ifdef GEM_DEBUG 126 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 127 printf x 128 #else 129 #define DPRINTF(sc, x) /* nothing */ 130 #endif 131 132 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 133 134 135 /* 136 * gem_attach: 137 * 138 * Attach a Gem interface to the system. 139 */ 140 void 141 gem_attach(sc, enaddr) 142 struct gem_softc *sc; 143 const uint8_t *enaddr; 144 { 145 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 146 struct mii_data *mii = &sc->sc_mii; 147 struct mii_softc *child; 148 struct ifmedia_entry *ifm; 149 int i, error; 150 u_int32_t v; 151 char *nullbuf; 152 153 /* Make sure the chip is stopped. */ 154 ifp->if_softc = sc; 155 gem_reset(sc); 156 157 /* 158 * Allocate the control data structures, and create and load the 159 * DMA map for it. gem_control_data is 9216 bytes, we have space for 160 * the padding buffer in the bus_dmamem_alloc()'d memory. 161 */ 162 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 163 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 164 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 165 aprint_error( 166 "%s: unable to allocate control data, error = %d\n", 167 sc->sc_dev.dv_xname, error); 168 goto fail_0; 169 } 170 171 /* XXX should map this in with correct endianness */ 172 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 173 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 174 BUS_DMA_COHERENT)) != 0) { 175 aprint_error("%s: unable to map control data, error = %d\n", 176 sc->sc_dev.dv_xname, error); 177 goto fail_1; 178 } 179 180 nullbuf = 181 (caddr_t)sc->sc_control_data + sizeof(struct gem_control_data); 182 183 if ((error = bus_dmamap_create(sc->sc_dmatag, 184 sizeof(struct gem_control_data), 1, 185 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 186 aprint_error("%s: unable to create control data DMA map, " 187 "error = %d\n", sc->sc_dev.dv_xname, error); 188 goto fail_2; 189 } 190 191 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 192 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 193 0)) != 0) { 194 aprint_error( 195 "%s: unable to load control data DMA map, error = %d\n", 196 sc->sc_dev.dv_xname, error); 197 goto fail_3; 198 } 199 200 memset(nullbuf, 0, ETHER_MIN_TX); 201 if ((error = bus_dmamap_create(sc->sc_dmatag, 202 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 203 aprint_error("%s: unable to create padding DMA map, " 204 "error = %d\n", sc->sc_dev.dv_xname, error); 205 goto fail_4; 206 } 207 208 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 209 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 210 aprint_error( 211 "%s: unable to load padding DMA map, error = %d\n", 212 sc->sc_dev.dv_xname, error); 213 goto fail_5; 214 } 215 216 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 217 BUS_DMASYNC_PREWRITE); 218 219 /* 220 * Initialize the transmit job descriptors. 221 */ 222 SIMPLEQ_INIT(&sc->sc_txfreeq); 223 SIMPLEQ_INIT(&sc->sc_txdirtyq); 224 225 /* 226 * Create the transmit buffer DMA maps. 227 */ 228 for (i = 0; i < GEM_TXQUEUELEN; i++) { 229 struct gem_txsoft *txs; 230 231 txs = &sc->sc_txsoft[i]; 232 txs->txs_mbuf = NULL; 233 if ((error = bus_dmamap_create(sc->sc_dmatag, 234 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 235 ETHER_MAX_LEN_JUMBO, 0, 0, 236 &txs->txs_dmamap)) != 0) { 237 aprint_error("%s: unable to create tx DMA map %d, " 238 "error = %d\n", sc->sc_dev.dv_xname, i, error); 239 goto fail_6; 240 } 241 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 242 } 243 244 /* 245 * Create the receive buffer DMA maps. 246 */ 247 for (i = 0; i < GEM_NRXDESC; i++) { 248 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 249 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 250 aprint_error("%s: unable to create rx DMA map %d, " 251 "error = %d\n", sc->sc_dev.dv_xname, i, error); 252 goto fail_7; 253 } 254 sc->sc_rxsoft[i].rxs_mbuf = NULL; 255 } 256 257 /* 258 * From this point forward, the attachment cannot fail. A failure 259 * before this point releases all resources that may have been 260 * allocated. 261 */ 262 263 /* Announce ourselves. */ 264 aprint_normal("%s: Ethernet address %s", sc->sc_dev.dv_xname, 265 ether_sprintf(enaddr)); 266 267 /* Get RX FIFO size */ 268 sc->sc_rxfifosize = 64 * 269 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 270 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 271 272 /* Get TX FIFO size */ 273 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 274 aprint_normal(", %uKB TX fifo\n", v / 16); 275 276 /* Initialize ifnet structure. */ 277 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 278 ifp->if_softc = sc; 279 ifp->if_flags = 280 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 281 sc->sc_if_flags = ifp->if_flags; 282 ifp->if_capabilities |= 283 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 284 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 285 ifp->if_start = gem_start; 286 ifp->if_ioctl = gem_ioctl; 287 ifp->if_watchdog = gem_watchdog; 288 ifp->if_stop = gem_stop; 289 ifp->if_init = gem_init; 290 IFQ_SET_READY(&ifp->if_snd); 291 292 /* Initialize ifmedia structures and MII info */ 293 mii->mii_ifp = ifp; 294 mii->mii_readreg = gem_mii_readreg; 295 mii->mii_writereg = gem_mii_writereg; 296 mii->mii_statchg = gem_mii_statchg; 297 298 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_mediachange, gem_mediastatus); 299 300 gem_mifinit(sc); 301 302 #if defined (PMAC_G5) 303 mii_attach(&sc->sc_dev, mii, 0xffffffff, 304 1, MII_OFFSET_ANY, MIIF_FORCEANEG); 305 #else 306 mii_attach(&sc->sc_dev, mii, 0xffffffff, 307 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 308 #endif 309 310 child = LIST_FIRST(&mii->mii_phys); 311 if (child == NULL) { 312 /* No PHY attached */ 313 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 314 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 315 } else { 316 /* 317 * Walk along the list of attached MII devices and 318 * establish an `MII instance' to `phy number' 319 * mapping. We'll use this mapping in media change 320 * requests to determine which phy to use to program 321 * the MIF configuration register. 322 */ 323 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 324 /* 325 * Note: we support just two PHYs: the built-in 326 * internal device and an external on the MII 327 * connector. 328 */ 329 if (child->mii_phy > 1 || child->mii_inst > 1) { 330 aprint_error( 331 "%s: cannot accomodate MII device %s" 332 " at phy %d, instance %d\n", 333 sc->sc_dev.dv_xname, 334 child->mii_dev.dv_xname, 335 child->mii_phy, child->mii_inst); 336 continue; 337 } 338 339 sc->sc_phys[child->mii_inst] = child->mii_phy; 340 } 341 342 /* 343 * Now select and activate the PHY we will use. 344 * 345 * The order of preference is External (MDI1), 346 * Internal (MDI0), Serial Link (no MII). 347 */ 348 if (sc->sc_phys[1]) { 349 #ifdef GEM_DEBUG 350 aprint_debug("using external phy\n"); 351 #endif 352 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 353 } else { 354 #ifdef GEM_DEBUG 355 aprint_debug("using internal phy\n"); 356 #endif 357 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 358 } 359 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 360 sc->sc_mif_config); 361 362 /* 363 * XXX - we can really do the following ONLY if the 364 * phy indeed has the auto negotiation capability!! 365 */ 366 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 367 } 368 369 /* 370 * If we support GigE media, we support jumbo frames too. 371 * Unless we are Apple. 372 */ 373 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 374 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 375 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 376 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 377 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 378 if (sc->sc_variant != GEM_APPLE_GMAC) 379 sc->sc_ethercom.ec_capabilities 380 |= ETHERCAP_JUMBO_MTU; 381 382 sc->sc_flags |= GEM_GIGABIT; 383 break; 384 } 385 } 386 387 /* claim 802.1q capability */ 388 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 389 390 /* Attach the interface. */ 391 if_attach(ifp); 392 ether_ifattach(ifp, enaddr); 393 394 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 395 if (sc->sc_sh == NULL) 396 panic("gem_config: can't establish shutdownhook"); 397 398 #if NRND > 0 399 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 400 RND_TYPE_NET, 0); 401 #endif 402 403 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 404 NULL, sc->sc_dev.dv_xname, "interrupts"); 405 #ifdef GEM_COUNTERS 406 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 407 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "tx interrupts"); 408 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 409 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "rx interrupts"); 410 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 411 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx ring full"); 412 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 413 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx malloc failure"); 414 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 415 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 0desc"); 416 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 417 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 1desc"); 418 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 419 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 2desc"); 420 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 421 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 3desc"); 422 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 423 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >3desc"); 424 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 425 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >7desc"); 426 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 427 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >15desc"); 428 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 429 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >31desc"); 430 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 431 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >63desc"); 432 #endif 433 434 #if notyet 435 /* 436 * Add a suspend hook to make sure we come back up after a 437 * resume. 438 */ 439 sc->sc_powerhook = powerhook_establish(gem_power, sc); 440 if (sc->sc_powerhook == NULL) 441 aprint_error("%s: WARNING: unable to establish power hook\n", 442 sc->sc_dev.dv_xname); 443 #endif 444 445 callout_init(&sc->sc_tick_ch); 446 return; 447 448 /* 449 * Free any resources we've allocated during the failed attach 450 * attempt. Do this in reverse order and fall through. 451 */ 452 fail_7: 453 for (i = 0; i < GEM_NRXDESC; i++) { 454 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 455 bus_dmamap_destroy(sc->sc_dmatag, 456 sc->sc_rxsoft[i].rxs_dmamap); 457 } 458 fail_6: 459 for (i = 0; i < GEM_TXQUEUELEN; i++) { 460 if (sc->sc_txsoft[i].txs_dmamap != NULL) 461 bus_dmamap_destroy(sc->sc_dmatag, 462 sc->sc_txsoft[i].txs_dmamap); 463 } 464 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 465 fail_5: 466 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 467 fail_4: 468 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)nullbuf, ETHER_MIN_TX); 469 fail_3: 470 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 471 fail_2: 472 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 473 sizeof(struct gem_control_data)); 474 fail_1: 475 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 476 fail_0: 477 return; 478 } 479 480 481 void 482 gem_tick(arg) 483 void *arg; 484 { 485 struct gem_softc *sc = arg; 486 int s; 487 488 s = splnet(); 489 mii_tick(&sc->sc_mii); 490 splx(s); 491 492 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 493 494 } 495 496 static int 497 gem_bitwait(sc, r, clr, set) 498 struct gem_softc *sc; 499 int r; 500 u_int32_t clr; 501 u_int32_t set; 502 { 503 int i; 504 u_int32_t reg; 505 506 for (i = TRIES; i--; DELAY(100)) { 507 reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r); 508 if ((r & clr) == 0 && (r & set) == set) 509 return (1); 510 } 511 return (0); 512 } 513 514 void 515 gem_reset(sc) 516 struct gem_softc *sc; 517 { 518 bus_space_tag_t t = sc->sc_bustag; 519 bus_space_handle_t h = sc->sc_h; 520 int s; 521 522 s = splnet(); 523 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 524 gem_reset_rx(sc); 525 gem_reset_tx(sc); 526 527 /* Do a full reset */ 528 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 529 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 530 printf("%s: cannot reset device\n", sc->sc_dev.dv_xname); 531 splx(s); 532 } 533 534 535 /* 536 * gem_rxdrain: 537 * 538 * Drain the receive queue. 539 */ 540 static void 541 gem_rxdrain(struct gem_softc *sc) 542 { 543 struct gem_rxsoft *rxs; 544 int i; 545 546 for (i = 0; i < GEM_NRXDESC; i++) { 547 rxs = &sc->sc_rxsoft[i]; 548 if (rxs->rxs_mbuf != NULL) { 549 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 550 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 551 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 552 m_freem(rxs->rxs_mbuf); 553 rxs->rxs_mbuf = NULL; 554 } 555 } 556 } 557 558 /* 559 * Reset the whole thing. 560 */ 561 static void 562 gem_stop(struct ifnet *ifp, int disable) 563 { 564 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 565 struct gem_txsoft *txs; 566 567 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 568 569 callout_stop(&sc->sc_tick_ch); 570 mii_down(&sc->sc_mii); 571 572 /* XXX - Should we reset these instead? */ 573 gem_disable_rx(sc); 574 gem_disable_tx(sc); 575 576 /* 577 * Release any queued transmit buffers. 578 */ 579 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 580 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 581 if (txs->txs_mbuf != NULL) { 582 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 583 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 584 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 585 m_freem(txs->txs_mbuf); 586 txs->txs_mbuf = NULL; 587 } 588 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 589 } 590 591 if (disable) { 592 gem_rxdrain(sc); 593 } 594 595 /* 596 * Mark the interface down and cancel the watchdog timer. 597 */ 598 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 599 sc->sc_if_flags = ifp->if_flags; 600 ifp->if_timer = 0; 601 } 602 603 604 /* 605 * Reset the receiver 606 */ 607 int 608 gem_reset_rx(struct gem_softc *sc) 609 { 610 bus_space_tag_t t = sc->sc_bustag; 611 bus_space_handle_t h = sc->sc_h; 612 613 /* 614 * Resetting while DMA is in progress can cause a bus hang, so we 615 * disable DMA first. 616 */ 617 gem_disable_rx(sc); 618 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 619 /* Wait till it finishes */ 620 if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0)) 621 printf("%s: cannot disable read dma\n", sc->sc_dev.dv_xname); 622 /* Wait 5ms extra. */ 623 delay(5000); 624 625 /* Finally, reset the ERX */ 626 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 627 /* Wait till it finishes */ 628 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 629 printf("%s: cannot reset receiver\n", sc->sc_dev.dv_xname); 630 return (1); 631 } 632 return (0); 633 } 634 635 636 /* 637 * Reset the transmitter 638 */ 639 int 640 gem_reset_tx(struct gem_softc *sc) 641 { 642 bus_space_tag_t t = sc->sc_bustag; 643 bus_space_handle_t h = sc->sc_h; 644 645 /* 646 * Resetting while DMA is in progress can cause a bus hang, so we 647 * disable DMA first. 648 */ 649 gem_disable_tx(sc); 650 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 651 /* Wait till it finishes */ 652 if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0)) 653 printf("%s: cannot disable read dma\n", sc->sc_dev.dv_xname); 654 /* Wait 5ms extra. */ 655 delay(5000); 656 657 /* Finally, reset the ETX */ 658 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 659 /* Wait till it finishes */ 660 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 661 printf("%s: cannot reset receiver\n", 662 sc->sc_dev.dv_xname); 663 return (1); 664 } 665 return (0); 666 } 667 668 /* 669 * disable receiver. 670 */ 671 int 672 gem_disable_rx(struct gem_softc *sc) 673 { 674 bus_space_tag_t t = sc->sc_bustag; 675 bus_space_handle_t h = sc->sc_h; 676 u_int32_t cfg; 677 678 /* Flip the enable bit */ 679 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 680 cfg &= ~GEM_MAC_RX_ENABLE; 681 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 682 683 /* Wait for it to finish */ 684 return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 685 } 686 687 /* 688 * disable transmitter. 689 */ 690 int 691 gem_disable_tx(struct gem_softc *sc) 692 { 693 bus_space_tag_t t = sc->sc_bustag; 694 bus_space_handle_t h = sc->sc_h; 695 u_int32_t cfg; 696 697 /* Flip the enable bit */ 698 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 699 cfg &= ~GEM_MAC_TX_ENABLE; 700 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 701 702 /* Wait for it to finish */ 703 return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 704 } 705 706 /* 707 * Initialize interface. 708 */ 709 int 710 gem_meminit(struct gem_softc *sc) 711 { 712 struct gem_rxsoft *rxs; 713 int i, error; 714 715 /* 716 * Initialize the transmit descriptor ring. 717 */ 718 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 719 for (i = 0; i < GEM_NTXDESC; i++) { 720 sc->sc_txdescs[i].gd_flags = 0; 721 sc->sc_txdescs[i].gd_addr = 0; 722 } 723 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 724 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 725 sc->sc_txfree = GEM_NTXDESC-1; 726 sc->sc_txnext = 0; 727 sc->sc_txwin = 0; 728 729 /* 730 * Initialize the receive descriptor and receive job 731 * descriptor rings. 732 */ 733 for (i = 0; i < GEM_NRXDESC; i++) { 734 rxs = &sc->sc_rxsoft[i]; 735 if (rxs->rxs_mbuf == NULL) { 736 if ((error = gem_add_rxbuf(sc, i)) != 0) { 737 printf("%s: unable to allocate or map rx " 738 "buffer %d, error = %d\n", 739 sc->sc_dev.dv_xname, i, error); 740 /* 741 * XXX Should attempt to run with fewer receive 742 * XXX buffers instead of just failing. 743 */ 744 gem_rxdrain(sc); 745 return (1); 746 } 747 } else 748 GEM_INIT_RXDESC(sc, i); 749 } 750 sc->sc_rxptr = 0; 751 752 return (0); 753 } 754 755 static int 756 gem_ringsize(int sz) 757 { 758 switch (sz) { 759 case 32: 760 return GEM_RING_SZ_32; 761 case 64: 762 return GEM_RING_SZ_64; 763 case 128: 764 return GEM_RING_SZ_128; 765 case 256: 766 return GEM_RING_SZ_256; 767 case 512: 768 return GEM_RING_SZ_512; 769 case 1024: 770 return GEM_RING_SZ_1024; 771 case 2048: 772 return GEM_RING_SZ_2048; 773 case 4096: 774 return GEM_RING_SZ_4096; 775 case 8192: 776 return GEM_RING_SZ_8192; 777 default: 778 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 779 return GEM_RING_SZ_32; 780 } 781 } 782 783 /* 784 * Initialization of interface; set up initialization block 785 * and transmit/receive descriptor rings. 786 */ 787 int 788 gem_init(struct ifnet *ifp) 789 { 790 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 791 bus_space_tag_t t = sc->sc_bustag; 792 bus_space_handle_t h = sc->sc_h; 793 int s; 794 u_int max_frame_size; 795 u_int32_t v; 796 797 s = splnet(); 798 799 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 800 /* 801 * Initialization sequence. The numbered steps below correspond 802 * to the sequence outlined in section 6.3.5.1 in the Ethernet 803 * Channel Engine manual (part of the PCIO manual). 804 * See also the STP2002-STQ document from Sun Microsystems. 805 */ 806 807 /* step 1 & 2. Reset the Ethernet Channel */ 808 gem_stop(ifp, 0); 809 gem_reset(sc); 810 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 811 812 /* Re-initialize the MIF */ 813 gem_mifinit(sc); 814 815 /* Call MI reset function if any */ 816 if (sc->sc_hwreset) 817 (*sc->sc_hwreset)(sc); 818 819 /* step 3. Setup data structures in host memory */ 820 gem_meminit(sc); 821 822 /* step 4. TX MAC registers & counters */ 823 gem_init_regs(sc); 824 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 825 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 826 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 827 max_frame_size += ETHER_VLAN_ENCAP_LEN; 828 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 829 max_frame_size|/* burst size */(0x2000<<16)); 830 831 /* step 5. RX MAC registers & counters */ 832 gem_setladrf(sc); 833 834 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 835 /* NOTE: we use only 32-bit DMA addresses here. */ 836 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 837 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 838 839 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 840 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 841 842 /* step 8. Global Configuration & Interrupt Mask */ 843 bus_space_write_4(t, h, GEM_INTMASK, 844 ~(GEM_INTR_TX_INTME| 845 GEM_INTR_TX_EMPTY| 846 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 847 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 848 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 849 GEM_INTR_BERR)); 850 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 851 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 852 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 853 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 854 855 /* step 9. ETX Configuration: use mostly default values */ 856 857 /* Enable DMA */ 858 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 859 bus_space_write_4(t, h, GEM_TX_CONFIG, 860 v|GEM_TX_CONFIG_TXDMA_EN| 861 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 862 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 863 864 /* step 10. ERX Configuration */ 865 866 /* Encode Receive Descriptor ring size: four possible values */ 867 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 868 869 /* Set receive h/w checksum offset */ 870 #ifdef INET 871 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 872 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 873 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 874 #endif 875 876 /* Enable DMA */ 877 bus_space_write_4(t, h, GEM_RX_CONFIG, 878 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 879 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN); 880 881 /* 882 * The following value is for an OFF Threshold of about 3/4 full 883 * and an ON Threshold of 1/4 full. 884 */ 885 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 886 (3 * sc->sc_rxfifosize / 256) | 887 ( (sc->sc_rxfifosize / 256) << 12)); 888 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 889 890 /* step 11. Configure Media */ 891 mii_mediachg(&sc->sc_mii); 892 893 /* XXXX Serial link needs a whole different setup. */ 894 895 896 /* step 12. RX_MAC Configuration Register */ 897 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 898 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 899 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 900 901 /* step 14. Issue Transmit Pending command */ 902 903 /* Call MI initialization function if any */ 904 if (sc->sc_hwinit) 905 (*sc->sc_hwinit)(sc); 906 907 908 /* step 15. Give the reciever a swift kick */ 909 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 910 911 /* Start the one second timer. */ 912 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 913 914 ifp->if_flags |= IFF_RUNNING; 915 ifp->if_flags &= ~IFF_OACTIVE; 916 ifp->if_timer = 0; 917 sc->sc_if_flags = ifp->if_flags; 918 splx(s); 919 920 return (0); 921 } 922 923 void 924 gem_init_regs(struct gem_softc *sc) 925 { 926 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 927 bus_space_tag_t t = sc->sc_bustag; 928 bus_space_handle_t h = sc->sc_h; 929 const u_char *laddr = LLADDR(ifp->if_sadl); 930 u_int32_t v; 931 932 /* These regs are not cleared on reset */ 933 if (!sc->sc_inited) { 934 935 /* Wooo. Magic values. */ 936 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 937 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 938 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 939 940 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 941 /* Max frame and max burst size */ 942 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 943 ETHER_MAX_LEN | (0x2000<<16)); 944 945 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 946 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 947 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 948 /* Dunno.... */ 949 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 950 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 951 ((laddr[5]<<8)|laddr[4])&0x3ff); 952 953 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 954 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 955 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 956 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 957 958 /* MAC control addr set to 01:80:c2:00:00:01 */ 959 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 960 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 961 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 962 963 /* MAC filter addr set to 0:0:0:0:0:0 */ 964 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 965 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 966 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 967 968 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 969 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 970 971 sc->sc_inited = 1; 972 } 973 974 /* Counters need to be zeroed */ 975 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 976 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 977 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 978 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 979 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 980 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 981 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 982 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 983 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 984 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 985 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 986 987 /* Un-pause stuff */ 988 #if 0 989 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 990 #else 991 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 992 #endif 993 994 /* 995 * Set the station address. 996 */ 997 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 998 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 999 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1000 1001 #if 0 1002 if (sc->sc_variant != APPLE_GMAC) 1003 return; 1004 #endif 1005 1006 /* 1007 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1008 */ 1009 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1010 v = GEM_MAC_XIF_TX_MII_ENA; 1011 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1012 v |= GEM_MAC_XIF_FDPLX_LED; 1013 if (sc->sc_flags & GEM_GIGABIT) 1014 v |= GEM_MAC_XIF_GMII_MODE; 1015 } 1016 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1017 } 1018 1019 static void 1020 gem_start(ifp) 1021 struct ifnet *ifp; 1022 { 1023 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1024 struct mbuf *m0, *m; 1025 struct gem_txsoft *txs, *last_txs; 1026 bus_dmamap_t dmamap; 1027 int error, firsttx, nexttx, lasttx = -1, ofree, seg; 1028 uint64_t flags = 0; 1029 1030 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1031 return; 1032 1033 /* 1034 * Remember the previous number of free descriptors and 1035 * the first descriptor we'll use. 1036 */ 1037 ofree = sc->sc_txfree; 1038 firsttx = sc->sc_txnext; 1039 1040 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1041 sc->sc_dev.dv_xname, ofree, firsttx)); 1042 1043 /* 1044 * Loop through the send queue, setting up transmit descriptors 1045 * until we drain the queue, or use up all available transmit 1046 * descriptors. 1047 */ 1048 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1049 sc->sc_txfree != 0) { 1050 /* 1051 * Grab a packet off the queue. 1052 */ 1053 IFQ_POLL(&ifp->if_snd, m0); 1054 if (m0 == NULL) 1055 break; 1056 m = NULL; 1057 1058 dmamap = txs->txs_dmamap; 1059 1060 /* 1061 * Load the DMA map. If this fails, the packet either 1062 * didn't fit in the alloted number of segments, or we were 1063 * short on resources. In this case, we'll copy and try 1064 * again. 1065 */ 1066 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1067 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1068 (m0->m_pkthdr.len < ETHER_MIN_TX && 1069 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1070 if (m0->m_pkthdr.len > MCLBYTES) { 1071 printf("%s: unable to allocate jumbo Tx " 1072 "cluster\n", sc->sc_dev.dv_xname); 1073 IFQ_DEQUEUE(&ifp->if_snd, m0); 1074 m_freem(m0); 1075 continue; 1076 } 1077 MGETHDR(m, M_DONTWAIT, MT_DATA); 1078 if (m == NULL) { 1079 printf("%s: unable to allocate Tx mbuf\n", 1080 sc->sc_dev.dv_xname); 1081 break; 1082 } 1083 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1084 if (m0->m_pkthdr.len > MHLEN) { 1085 MCLGET(m, M_DONTWAIT); 1086 if ((m->m_flags & M_EXT) == 0) { 1087 printf("%s: unable to allocate Tx " 1088 "cluster\n", sc->sc_dev.dv_xname); 1089 m_freem(m); 1090 break; 1091 } 1092 } 1093 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1094 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1095 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1096 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1097 if (error) { 1098 printf("%s: unable to load Tx buffer, " 1099 "error = %d\n", sc->sc_dev.dv_xname, error); 1100 break; 1101 } 1102 } 1103 1104 /* 1105 * Ensure we have enough descriptors free to describe 1106 * the packet. 1107 */ 1108 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1109 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1110 /* 1111 * Not enough free descriptors to transmit this 1112 * packet. We haven't committed to anything yet, 1113 * so just unload the DMA map, put the packet 1114 * back on the queue, and punt. Notify the upper 1115 * layer that there are no more slots left. 1116 * 1117 * XXX We could allocate an mbuf and copy, but 1118 * XXX it is worth it? 1119 */ 1120 ifp->if_flags |= IFF_OACTIVE; 1121 sc->sc_if_flags = ifp->if_flags; 1122 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1123 if (m != NULL) 1124 m_freem(m); 1125 break; 1126 } 1127 1128 IFQ_DEQUEUE(&ifp->if_snd, m0); 1129 if (m != NULL) { 1130 m_freem(m0); 1131 m0 = m; 1132 } 1133 1134 /* 1135 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1136 */ 1137 1138 /* Sync the DMA map. */ 1139 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1140 BUS_DMASYNC_PREWRITE); 1141 1142 /* 1143 * Initialize the transmit descriptors. 1144 */ 1145 for (nexttx = sc->sc_txnext, seg = 0; 1146 seg < dmamap->dm_nsegs; 1147 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1148 1149 /* 1150 * If this is the first descriptor we're 1151 * enqueueing, set the start of packet flag, 1152 * and the checksum stuff if we want the hardware 1153 * to do it. 1154 */ 1155 sc->sc_txdescs[nexttx].gd_addr = 1156 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1157 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1158 if (nexttx == firsttx) { 1159 flags |= GEM_TD_START_OF_PACKET; 1160 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1161 sc->sc_txwin = 0; 1162 flags |= GEM_TD_INTERRUPT_ME; 1163 } 1164 1165 #ifdef INET 1166 /* h/w checksum */ 1167 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | 1168 M_CSUM_UDPv4) && m0->m_pkthdr.csum_flags & 1169 (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1170 struct ether_header *eh; 1171 uint16_t offset, start; 1172 1173 eh = mtod(m0, struct ether_header *); 1174 switch (ntohs(eh->ether_type)) { 1175 case ETHERTYPE_IP: 1176 start = ETHER_HDR_LEN; 1177 break; 1178 case ETHERTYPE_VLAN: 1179 start = ETHER_HDR_LEN + 1180 ETHER_VLAN_ENCAP_LEN; 1181 break; 1182 default: 1183 /* unsupported, drop it */ 1184 m_free(m0); 1185 continue; 1186 } 1187 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1188 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1189 flags |= (start << 1190 GEM_TD_CXSUM_STARTSHFT) | 1191 (offset << 1192 GEM_TD_CXSUM_STUFFSHFT) | 1193 GEM_TD_CXSUM_ENABLE; 1194 } 1195 #endif 1196 } 1197 if (seg == dmamap->dm_nsegs - 1) { 1198 flags |= GEM_TD_END_OF_PACKET; 1199 } else { 1200 /* last flag set outside of loop */ 1201 sc->sc_txdescs[nexttx].gd_flags = 1202 GEM_DMA_WRITE(sc, flags); 1203 } 1204 lasttx = nexttx; 1205 } 1206 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1207 /* add padding buffer at end of chain */ 1208 flags &= ~GEM_TD_END_OF_PACKET; 1209 sc->sc_txdescs[lasttx].gd_flags = 1210 GEM_DMA_WRITE(sc, flags); 1211 1212 sc->sc_txdescs[nexttx].gd_addr = 1213 GEM_DMA_WRITE(sc, 1214 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1215 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1216 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1217 lasttx = nexttx; 1218 nexttx = GEM_NEXTTX(nexttx); 1219 seg++; 1220 } 1221 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1222 1223 KASSERT(lasttx != -1); 1224 1225 /* 1226 * Store a pointer to the packet so we can free it later, 1227 * and remember what txdirty will be once the packet is 1228 * done. 1229 */ 1230 txs->txs_mbuf = m0; 1231 txs->txs_firstdesc = sc->sc_txnext; 1232 txs->txs_lastdesc = lasttx; 1233 txs->txs_ndescs = seg; 1234 1235 #ifdef GEM_DEBUG 1236 if (ifp->if_flags & IFF_DEBUG) { 1237 printf(" gem_start %p transmit chain:\n", txs); 1238 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1239 printf("descriptor %d:\t", seg); 1240 printf("gd_flags: 0x%016llx\t", (long long) 1241 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1242 printf("gd_addr: 0x%016llx\n", (long long) 1243 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1244 if (seg == lasttx) 1245 break; 1246 } 1247 } 1248 #endif 1249 1250 /* Sync the descriptors we're using. */ 1251 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1252 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1253 1254 /* Advance the tx pointer. */ 1255 sc->sc_txfree -= txs->txs_ndescs; 1256 sc->sc_txnext = nexttx; 1257 1258 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1259 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1260 1261 last_txs = txs; 1262 1263 #if NBPFILTER > 0 1264 /* 1265 * Pass the packet to any BPF listeners. 1266 */ 1267 if (ifp->if_bpf) 1268 bpf_mtap(ifp->if_bpf, m0); 1269 #endif /* NBPFILTER > 0 */ 1270 } 1271 1272 if (txs == NULL || sc->sc_txfree == 0) { 1273 /* No more slots left; notify upper layer. */ 1274 ifp->if_flags |= IFF_OACTIVE; 1275 sc->sc_if_flags = ifp->if_flags; 1276 } 1277 1278 if (sc->sc_txfree != ofree) { 1279 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1280 sc->sc_dev.dv_xname, lasttx, firsttx)); 1281 /* 1282 * The entire packet chain is set up. 1283 * Kick the transmitter. 1284 */ 1285 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1286 sc->sc_dev.dv_xname, nexttx)); 1287 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1288 sc->sc_txnext); 1289 1290 /* Set a watchdog timer in case the chip flakes out. */ 1291 ifp->if_timer = 5; 1292 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1293 sc->sc_dev.dv_xname, ifp->if_timer)); 1294 } 1295 } 1296 1297 /* 1298 * Transmit interrupt. 1299 */ 1300 int 1301 gem_tint(sc) 1302 struct gem_softc *sc; 1303 { 1304 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1305 bus_space_tag_t t = sc->sc_bustag; 1306 bus_space_handle_t mac = sc->sc_h; 1307 struct gem_txsoft *txs; 1308 int txlast; 1309 int progress = 0; 1310 1311 1312 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1313 1314 /* 1315 * Unload collision counters 1316 */ 1317 ifp->if_collisions += 1318 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1319 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1320 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1321 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1322 1323 /* 1324 * then clear the hardware counters. 1325 */ 1326 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1327 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1328 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1329 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1330 1331 /* 1332 * Go through our Tx list and free mbufs for those 1333 * frames that have been transmitted. 1334 */ 1335 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1336 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1337 txs->txs_ndescs, 1338 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1339 1340 #ifdef GEM_DEBUG 1341 if (ifp->if_flags & IFF_DEBUG) { 1342 int i; 1343 printf(" txsoft %p transmit chain:\n", txs); 1344 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1345 printf("descriptor %d: ", i); 1346 printf("gd_flags: 0x%016llx\t", (long long) 1347 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1348 printf("gd_addr: 0x%016llx\n", (long long) 1349 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1350 if (i == txs->txs_lastdesc) 1351 break; 1352 } 1353 } 1354 #endif 1355 1356 /* 1357 * In theory, we could harveast some descriptors before 1358 * the ring is empty, but that's a bit complicated. 1359 * 1360 * GEM_TX_COMPLETION points to the last descriptor 1361 * processed +1. 1362 */ 1363 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1364 DPRINTF(sc, 1365 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1366 txs->txs_lastdesc, txlast)); 1367 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1368 if ((txlast >= txs->txs_firstdesc) && 1369 (txlast <= txs->txs_lastdesc)) 1370 break; 1371 } else { 1372 /* Ick -- this command wraps */ 1373 if ((txlast >= txs->txs_firstdesc) || 1374 (txlast <= txs->txs_lastdesc)) 1375 break; 1376 } 1377 1378 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1379 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1380 1381 sc->sc_txfree += txs->txs_ndescs; 1382 1383 if (txs->txs_mbuf == NULL) { 1384 #ifdef DIAGNOSTIC 1385 panic("gem_txintr: null mbuf"); 1386 #endif 1387 } 1388 1389 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1390 0, txs->txs_dmamap->dm_mapsize, 1391 BUS_DMASYNC_POSTWRITE); 1392 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1393 m_freem(txs->txs_mbuf); 1394 txs->txs_mbuf = NULL; 1395 1396 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1397 1398 ifp->if_opackets++; 1399 progress = 1; 1400 } 1401 1402 #if 0 1403 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1404 "GEM_TX_DATA_PTR %llx " 1405 "GEM_TX_COMPLETION %x\n", 1406 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1407 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1408 GEM_TX_DATA_PTR_HI) << 32) | 1409 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1410 GEM_TX_DATA_PTR_LO), 1411 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1412 #endif 1413 1414 if (progress) { 1415 if (sc->sc_txfree == GEM_NTXDESC - 1) 1416 sc->sc_txwin = 0; 1417 1418 ifp->if_flags &= ~IFF_OACTIVE; 1419 sc->sc_if_flags = ifp->if_flags; 1420 gem_start(ifp); 1421 1422 if (SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) 1423 ifp->if_timer = 0; 1424 } 1425 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1426 sc->sc_dev.dv_xname, ifp->if_timer)); 1427 1428 return (1); 1429 } 1430 1431 /* 1432 * Receive interrupt. 1433 */ 1434 int 1435 gem_rint(sc) 1436 struct gem_softc *sc; 1437 { 1438 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1439 bus_space_tag_t t = sc->sc_bustag; 1440 bus_space_handle_t h = sc->sc_h; 1441 struct gem_rxsoft *rxs; 1442 struct mbuf *m; 1443 u_int64_t rxstat; 1444 u_int32_t rxcomp; 1445 int i, len, progress = 0; 1446 1447 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1448 1449 /* 1450 * Read the completion register once. This limits 1451 * how long the following loop can execute. 1452 */ 1453 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1454 1455 /* 1456 * XXXX Read the lastrx only once at the top for speed. 1457 */ 1458 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1459 sc->sc_rxptr, rxcomp)); 1460 1461 /* 1462 * Go into the loop at least once. 1463 */ 1464 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1465 i = GEM_NEXTRX(i)) { 1466 rxs = &sc->sc_rxsoft[i]; 1467 1468 GEM_CDRXSYNC(sc, i, 1469 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1470 1471 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1472 1473 if (rxstat & GEM_RD_OWN) { 1474 /* 1475 * We have processed all of the receive buffers. 1476 */ 1477 break; 1478 } 1479 1480 progress++; 1481 ifp->if_ipackets++; 1482 1483 if (rxstat & GEM_RD_BAD_CRC) { 1484 ifp->if_ierrors++; 1485 printf("%s: receive error: CRC error\n", 1486 sc->sc_dev.dv_xname); 1487 GEM_INIT_RXDESC(sc, i); 1488 continue; 1489 } 1490 1491 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1492 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1493 #ifdef GEM_DEBUG 1494 if (ifp->if_flags & IFF_DEBUG) { 1495 printf(" rxsoft %p descriptor %d: ", rxs, i); 1496 printf("gd_flags: 0x%016llx\t", (long long) 1497 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1498 printf("gd_addr: 0x%016llx\n", (long long) 1499 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1500 } 1501 #endif 1502 1503 /* No errors; receive the packet. */ 1504 len = GEM_RD_BUFLEN(rxstat); 1505 1506 /* 1507 * Allocate a new mbuf cluster. If that fails, we are 1508 * out of memory, and must drop the packet and recycle 1509 * the buffer that's already attached to this descriptor. 1510 */ 1511 m = rxs->rxs_mbuf; 1512 if (gem_add_rxbuf(sc, i) != 0) { 1513 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1514 ifp->if_ierrors++; 1515 GEM_INIT_RXDESC(sc, i); 1516 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1517 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1518 continue; 1519 } 1520 m->m_data += 2; /* We're already off by two */ 1521 1522 m->m_pkthdr.rcvif = ifp; 1523 m->m_pkthdr.len = m->m_len = len; 1524 1525 #if NBPFILTER > 0 1526 /* 1527 * Pass this up to any BPF listeners, but only 1528 * pass it up the stack if its for us. 1529 */ 1530 if (ifp->if_bpf) 1531 bpf_mtap(ifp->if_bpf, m); 1532 #endif /* NPBFILTER > 0 */ 1533 1534 #ifdef INET 1535 /* hardware checksum */ 1536 if (ifp->if_csum_flags_rx & (M_CSUM_UDPv4 | M_CSUM_TCPv4)) { 1537 struct ether_header *eh; 1538 struct ip *ip; 1539 struct udphdr *uh; 1540 int32_t hlen, pktlen; 1541 1542 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1543 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1544 ETHER_VLAN_ENCAP_LEN; 1545 eh = (struct ether_header *) mtod(m, caddr_t) + 1546 ETHER_VLAN_ENCAP_LEN; 1547 } else { 1548 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1549 eh = mtod(m, struct ether_header *); 1550 } 1551 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1552 goto swcsum; 1553 ip = (struct ip *) ((caddr_t)eh + ETHER_HDR_LEN); 1554 1555 /* IPv4 only */ 1556 if (ip->ip_v != IPVERSION) 1557 goto swcsum; 1558 1559 hlen = ip->ip_hl << 2; 1560 if (hlen < sizeof(struct ip)) 1561 goto swcsum; 1562 1563 /* 1564 * bail if too short, has random trailing garbage, 1565 * truncated, fragment, or has ethernet pad. 1566 */ 1567 if ((ntohs(ip->ip_len) < hlen) || 1568 (ntohs(ip->ip_len) != pktlen) || 1569 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1570 goto swcsum; 1571 1572 switch (ip->ip_p) { 1573 case IPPROTO_TCP: 1574 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1575 goto swcsum; 1576 if (pktlen < (hlen + sizeof(struct tcphdr))) 1577 goto swcsum; 1578 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1579 break; 1580 case IPPROTO_UDP: 1581 if (! (ifp->if_csum_flags_rx & M_CSUM_UDPv4)) 1582 goto swcsum; 1583 if (pktlen < (hlen + sizeof(struct udphdr))) 1584 goto swcsum; 1585 uh = (struct udphdr *)((caddr_t)ip + hlen); 1586 /* no checksum */ 1587 if (uh->uh_sum == 0) 1588 goto swcsum; 1589 m->m_pkthdr.csum_flags = M_CSUM_UDPv4; 1590 break; 1591 default: 1592 goto swcsum; 1593 } 1594 1595 /* the uncomplemented sum is expected */ 1596 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1597 1598 /* if the pkt had ip options, we have to deduct them */ 1599 if (hlen > sizeof(struct ip)) { 1600 uint16_t *opts; 1601 uint32_t optsum, temp; 1602 1603 optsum = 0; 1604 temp = hlen - sizeof(struct ip); 1605 opts = (uint16_t *) ((caddr_t) ip + 1606 sizeof(struct ip)); 1607 1608 while (temp > 1) { 1609 optsum += ntohs(*opts++); 1610 temp -= 2; 1611 } 1612 while (optsum >> 16) 1613 optsum = (optsum >> 16) + 1614 (optsum & 0xffff); 1615 1616 /* Deduct ip opts sum from hwsum (rfc 1624). */ 1617 m->m_pkthdr.csum_data = 1618 ~((~m->m_pkthdr.csum_data) - ~optsum); 1619 1620 while (m->m_pkthdr.csum_data >> 16) 1621 m->m_pkthdr.csum_data = 1622 (m->m_pkthdr.csum_data >> 16) + 1623 (m->m_pkthdr.csum_data & 1624 0xffff); 1625 } 1626 1627 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1628 M_CSUM_NO_PSEUDOHDR; 1629 } else 1630 swcsum: 1631 m->m_pkthdr.csum_flags = 0; 1632 #endif 1633 /* Pass it on. */ 1634 (*ifp->if_input)(ifp, m); 1635 } 1636 1637 if (progress) { 1638 /* Update the receive pointer. */ 1639 if (i == sc->sc_rxptr) { 1640 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1641 #ifdef GEM_DEBUG 1642 if (ifp->if_flags & IFF_DEBUG) 1643 printf("%s: rint: ring wrap\n", 1644 sc->sc_dev.dv_xname); 1645 #endif 1646 } 1647 sc->sc_rxptr = i; 1648 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1649 } 1650 #ifdef GEM_COUNTERS 1651 if (progress <= 4) { 1652 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1653 } else if (progress < 32) { 1654 if (progress < 16) 1655 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1656 else 1657 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1658 1659 } else { 1660 if (progress < 64) 1661 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1662 else 1663 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1664 } 1665 #endif 1666 1667 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1668 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1669 1670 return (1); 1671 } 1672 1673 1674 /* 1675 * gem_add_rxbuf: 1676 * 1677 * Add a receive buffer to the indicated descriptor. 1678 */ 1679 int 1680 gem_add_rxbuf(struct gem_softc *sc, int idx) 1681 { 1682 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1683 struct mbuf *m; 1684 int error; 1685 1686 MGETHDR(m, M_DONTWAIT, MT_DATA); 1687 if (m == NULL) 1688 return (ENOBUFS); 1689 1690 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1691 MCLGET(m, M_DONTWAIT); 1692 if ((m->m_flags & M_EXT) == 0) { 1693 m_freem(m); 1694 return (ENOBUFS); 1695 } 1696 1697 #ifdef GEM_DEBUG 1698 /* bzero the packet to check DMA */ 1699 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1700 #endif 1701 1702 if (rxs->rxs_mbuf != NULL) 1703 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1704 1705 rxs->rxs_mbuf = m; 1706 1707 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1708 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1709 BUS_DMA_READ|BUS_DMA_NOWAIT); 1710 if (error) { 1711 printf("%s: can't load rx DMA map %d, error = %d\n", 1712 sc->sc_dev.dv_xname, idx, error); 1713 panic("gem_add_rxbuf"); /* XXX */ 1714 } 1715 1716 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1717 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1718 1719 GEM_INIT_RXDESC(sc, idx); 1720 1721 return (0); 1722 } 1723 1724 1725 int 1726 gem_eint(sc, status) 1727 struct gem_softc *sc; 1728 u_int status; 1729 { 1730 char bits[128]; 1731 1732 if ((status & GEM_INTR_MIF) != 0) { 1733 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1734 return (1); 1735 } 1736 1737 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1738 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1739 return (1); 1740 } 1741 1742 1743 int 1744 gem_intr(v) 1745 void *v; 1746 { 1747 struct gem_softc *sc = (struct gem_softc *)v; 1748 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1749 bus_space_tag_t t = sc->sc_bustag; 1750 bus_space_handle_t seb = sc->sc_h; 1751 u_int32_t status; 1752 int r = 0; 1753 #ifdef GEM_DEBUG 1754 char bits[128]; 1755 #endif 1756 1757 sc->sc_ev_intr.ev_count++; 1758 1759 status = bus_space_read_4(t, seb, GEM_STATUS); 1760 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 1761 sc->sc_dev.dv_xname, (status >> 19), 1762 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1763 1764 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1765 r |= gem_eint(sc, status); 1766 1767 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 1768 GEM_COUNTER_INCR(sc, sc_ev_txint); 1769 r |= gem_tint(sc); 1770 } 1771 1772 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 1773 GEM_COUNTER_INCR(sc, sc_ev_rxint); 1774 r |= gem_rint(sc); 1775 } 1776 1777 /* We should eventually do more than just print out error stats. */ 1778 if (status & GEM_INTR_TX_MAC) { 1779 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1780 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1781 printf("%s: MAC tx fault, status %x\n", 1782 sc->sc_dev.dv_xname, txstat); 1783 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 1784 gem_init(ifp); 1785 } 1786 if (status & GEM_INTR_RX_MAC) { 1787 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1788 if (rxstat & ~GEM_MAC_RX_DONE) 1789 printf("%s: MAC rx fault, status %x\n", 1790 sc->sc_dev.dv_xname, rxstat); 1791 /* 1792 * On some chip revisions GEM_MAC_RX_OVERFLOW happen often 1793 * due to a silicon bug so handle them silently. 1794 */ 1795 if (rxstat & GEM_MAC_RX_OVERFLOW) 1796 gem_init(ifp); 1797 else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 1798 printf("%s: MAC rx fault, status %x\n", 1799 sc->sc_dev.dv_xname, rxstat); 1800 } 1801 #if NRND > 0 1802 rnd_add_uint32(&sc->rnd_source, status); 1803 #endif 1804 return (r); 1805 } 1806 1807 1808 void 1809 gem_watchdog(ifp) 1810 struct ifnet *ifp; 1811 { 1812 struct gem_softc *sc = ifp->if_softc; 1813 1814 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1815 "GEM_MAC_RX_CONFIG %x\n", 1816 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1817 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1818 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1819 1820 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1821 ++ifp->if_oerrors; 1822 1823 /* Try to get more packets going. */ 1824 gem_start(ifp); 1825 } 1826 1827 /* 1828 * Initialize the MII Management Interface 1829 */ 1830 void 1831 gem_mifinit(sc) 1832 struct gem_softc *sc; 1833 { 1834 bus_space_tag_t t = sc->sc_bustag; 1835 bus_space_handle_t mif = sc->sc_h; 1836 1837 /* Configure the MIF in frame mode */ 1838 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1839 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1840 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1841 } 1842 1843 /* 1844 * MII interface 1845 * 1846 * The GEM MII interface supports at least three different operating modes: 1847 * 1848 * Bitbang mode is implemented using data, clock and output enable registers. 1849 * 1850 * Frame mode is implemented by loading a complete frame into the frame 1851 * register and polling the valid bit for completion. 1852 * 1853 * Polling mode uses the frame register but completion is indicated by 1854 * an interrupt. 1855 * 1856 */ 1857 static int 1858 gem_mii_readreg(self, phy, reg) 1859 struct device *self; 1860 int phy, reg; 1861 { 1862 struct gem_softc *sc = (void *)self; 1863 bus_space_tag_t t = sc->sc_bustag; 1864 bus_space_handle_t mif = sc->sc_h; 1865 int n; 1866 u_int32_t v; 1867 1868 #ifdef GEM_DEBUG1 1869 if (sc->sc_debug) 1870 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1871 #endif 1872 1873 #if 0 1874 /* Select the desired PHY in the MIF configuration register */ 1875 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1876 /* Clear PHY select bit */ 1877 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1878 if (phy == GEM_PHYAD_EXTERNAL) 1879 /* Set PHY select bit to get at external device */ 1880 v |= GEM_MIF_CONFIG_PHY_SEL; 1881 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1882 #endif 1883 1884 /* Construct the frame command */ 1885 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1886 GEM_MIF_FRAME_READ; 1887 1888 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1889 for (n = 0; n < 100; n++) { 1890 DELAY(1); 1891 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1892 if (v & GEM_MIF_FRAME_TA0) 1893 return (v & GEM_MIF_FRAME_DATA); 1894 } 1895 1896 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1897 return (0); 1898 } 1899 1900 static void 1901 gem_mii_writereg(self, phy, reg, val) 1902 struct device *self; 1903 int phy, reg, val; 1904 { 1905 struct gem_softc *sc = (void *)self; 1906 bus_space_tag_t t = sc->sc_bustag; 1907 bus_space_handle_t mif = sc->sc_h; 1908 int n; 1909 u_int32_t v; 1910 1911 #ifdef GEM_DEBUG1 1912 if (sc->sc_debug) 1913 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1914 phy, reg, val); 1915 #endif 1916 1917 #if 0 1918 /* Select the desired PHY in the MIF configuration register */ 1919 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1920 /* Clear PHY select bit */ 1921 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1922 if (phy == GEM_PHYAD_EXTERNAL) 1923 /* Set PHY select bit to get at external device */ 1924 v |= GEM_MIF_CONFIG_PHY_SEL; 1925 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1926 #endif 1927 /* Construct the frame command */ 1928 v = GEM_MIF_FRAME_WRITE | 1929 (phy << GEM_MIF_PHY_SHIFT) | 1930 (reg << GEM_MIF_REG_SHIFT) | 1931 (val & GEM_MIF_FRAME_DATA); 1932 1933 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1934 for (n = 0; n < 100; n++) { 1935 DELAY(1); 1936 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1937 if (v & GEM_MIF_FRAME_TA0) 1938 return; 1939 } 1940 1941 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1942 } 1943 1944 static void 1945 gem_mii_statchg(dev) 1946 struct device *dev; 1947 { 1948 struct gem_softc *sc = (void *)dev; 1949 #ifdef GEM_DEBUG 1950 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1951 #endif 1952 bus_space_tag_t t = sc->sc_bustag; 1953 bus_space_handle_t mac = sc->sc_h; 1954 u_int32_t v; 1955 1956 #ifdef GEM_DEBUG 1957 if (sc->sc_debug) 1958 printf("gem_mii_statchg: status change: phy = %d\n", 1959 sc->sc_phys[instance]); 1960 #endif 1961 1962 1963 /* Set tx full duplex options */ 1964 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1965 delay(10000); /* reg must be cleared and delay before changing. */ 1966 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1967 GEM_MAC_TX_ENABLE; 1968 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1969 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1970 } 1971 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1972 1973 /* XIF Configuration */ 1974 /* We should really calculate all this rather than rely on defaults */ 1975 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1976 v = GEM_MAC_XIF_LINK_LED; 1977 v |= GEM_MAC_XIF_TX_MII_ENA; 1978 1979 /* If an external transceiver is connected, enable its MII drivers */ 1980 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1981 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1982 /* External MII needs echo disable if half duplex. */ 1983 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1984 /* turn on full duplex LED */ 1985 v |= GEM_MAC_XIF_FDPLX_LED; 1986 else 1987 /* half duplex -- disable echo */ 1988 v |= GEM_MAC_XIF_ECHO_DISABL; 1989 1990 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 1991 v |= GEM_MAC_XIF_GMII_MODE; 1992 else 1993 v &= ~GEM_MAC_XIF_GMII_MODE; 1994 } else 1995 /* Internal MII needs buf enable */ 1996 v |= GEM_MAC_XIF_MII_BUF_ENA; 1997 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1998 } 1999 2000 int 2001 gem_mediachange(ifp) 2002 struct ifnet *ifp; 2003 { 2004 struct gem_softc *sc = ifp->if_softc; 2005 2006 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 2007 return (EINVAL); 2008 2009 return (mii_mediachg(&sc->sc_mii)); 2010 } 2011 2012 void 2013 gem_mediastatus(ifp, ifmr) 2014 struct ifnet *ifp; 2015 struct ifmediareq *ifmr; 2016 { 2017 struct gem_softc *sc = ifp->if_softc; 2018 2019 if ((ifp->if_flags & IFF_UP) == 0) 2020 return; 2021 2022 mii_pollstat(&sc->sc_mii); 2023 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2024 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2025 } 2026 2027 /* 2028 * Process an ioctl request. 2029 */ 2030 int 2031 gem_ioctl(ifp, cmd, data) 2032 struct ifnet *ifp; 2033 u_long cmd; 2034 caddr_t data; 2035 { 2036 struct gem_softc *sc = ifp->if_softc; 2037 struct ifreq *ifr = (struct ifreq *)data; 2038 int s, error = 0; 2039 2040 s = splnet(); 2041 2042 switch (cmd) { 2043 case SIOCGIFMEDIA: 2044 case SIOCSIFMEDIA: 2045 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 2046 break; 2047 case SIOCSIFFLAGS: 2048 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 2049 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 2050 == (IFF_UP|IFF_RUNNING)) 2051 && ((ifp->if_flags & (~RESETIGN)) 2052 == (sc->sc_if_flags & (~RESETIGN)))) { 2053 gem_setladrf(sc); 2054 break; 2055 } 2056 #undef RESETIGN 2057 /*FALLTHROUGH*/ 2058 default: 2059 error = ether_ioctl(ifp, cmd, data); 2060 if (error == ENETRESET) { 2061 /* 2062 * Multicast list has changed; set the hardware filter 2063 * accordingly. 2064 */ 2065 if (ifp->if_flags & IFF_RUNNING) 2066 gem_setladrf(sc); 2067 error = 0; 2068 } 2069 break; 2070 } 2071 2072 /* Try to get things going again */ 2073 if (ifp->if_flags & IFF_UP) 2074 gem_start(ifp); 2075 splx(s); 2076 return (error); 2077 } 2078 2079 2080 void 2081 gem_shutdown(arg) 2082 void *arg; 2083 { 2084 struct gem_softc *sc = (struct gem_softc *)arg; 2085 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2086 2087 gem_stop(ifp, 1); 2088 } 2089 2090 /* 2091 * Set up the logical address filter. 2092 */ 2093 void 2094 gem_setladrf(sc) 2095 struct gem_softc *sc; 2096 { 2097 struct ethercom *ec = &sc->sc_ethercom; 2098 struct ifnet *ifp = &ec->ec_if; 2099 struct ether_multi *enm; 2100 struct ether_multistep step; 2101 bus_space_tag_t t = sc->sc_bustag; 2102 bus_space_handle_t h = sc->sc_h; 2103 u_int32_t crc; 2104 u_int32_t hash[16]; 2105 u_int32_t v; 2106 int i; 2107 2108 /* Get current RX configuration */ 2109 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2110 2111 /* 2112 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2113 * and hash filter. Depending on the case, the right bit will be 2114 * enabled. 2115 */ 2116 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2117 GEM_MAC_RX_PROMISC_GRP); 2118 2119 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2120 /* Turn on promiscuous mode */ 2121 v |= GEM_MAC_RX_PROMISCUOUS; 2122 ifp->if_flags |= IFF_ALLMULTI; 2123 goto chipit; 2124 } 2125 2126 /* 2127 * Set up multicast address filter by passing all multicast addresses 2128 * through a crc generator, and then using the high order 8 bits as an 2129 * index into the 256 bit logical address filter. The high order 4 2130 * bits selects the word, while the other 4 bits select the bit within 2131 * the word (where bit 0 is the MSB). 2132 */ 2133 2134 /* Clear hash table */ 2135 memset(hash, 0, sizeof(hash)); 2136 2137 ETHER_FIRST_MULTI(step, ec, enm); 2138 while (enm != NULL) { 2139 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2140 /* 2141 * We must listen to a range of multicast addresses. 2142 * For now, just accept all multicasts, rather than 2143 * trying to set only those filter bits needed to match 2144 * the range. (At this time, the only use of address 2145 * ranges is for IP multicast routing, for which the 2146 * range is big enough to require all bits set.) 2147 * XXX use the addr filter for this 2148 */ 2149 ifp->if_flags |= IFF_ALLMULTI; 2150 v |= GEM_MAC_RX_PROMISC_GRP; 2151 goto chipit; 2152 } 2153 2154 /* Get the LE CRC32 of the address */ 2155 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2156 2157 /* Just want the 8 most significant bits. */ 2158 crc >>= 24; 2159 2160 /* Set the corresponding bit in the filter. */ 2161 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2162 2163 ETHER_NEXT_MULTI(step, enm); 2164 } 2165 2166 v |= GEM_MAC_RX_HASH_FILTER; 2167 ifp->if_flags &= ~IFF_ALLMULTI; 2168 2169 /* Now load the hash table into the chip (if we are using it) */ 2170 for (i = 0; i < 16; i++) { 2171 bus_space_write_4(t, h, 2172 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2173 hash[i]); 2174 } 2175 2176 chipit: 2177 sc->sc_if_flags = ifp->if_flags; 2178 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2179 } 2180 2181 #if notyet 2182 2183 /* 2184 * gem_power: 2185 * 2186 * Power management (suspend/resume) hook. 2187 */ 2188 void 2189 gem_power(why, arg) 2190 int why; 2191 void *arg; 2192 { 2193 struct gem_softc *sc = arg; 2194 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2195 int s; 2196 2197 s = splnet(); 2198 switch (why) { 2199 case PWR_SUSPEND: 2200 case PWR_STANDBY: 2201 gem_stop(ifp, 1); 2202 if (sc->sc_power != NULL) 2203 (*sc->sc_power)(sc, why); 2204 break; 2205 case PWR_RESUME: 2206 if (ifp->if_flags & IFF_UP) { 2207 if (sc->sc_power != NULL) 2208 (*sc->sc_power)(sc, why); 2209 gem_init(ifp); 2210 } 2211 break; 2212 case PWR_SOFTSUSPEND: 2213 case PWR_SOFTSTANDBY: 2214 case PWR_SOFTRESUME: 2215 break; 2216 } 2217 splx(s); 2218 } 2219 #endif 2220