1 /* $NetBSD: gem.c,v 1.132 2020/09/15 08:33:40 mrg Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.132 2020/09/15 08:33:40 mrg Exp $"); 41 42 #include "opt_inet.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/callout.h> 47 #include <sys/mbuf.h> 48 #include <sys/syslog.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/device.h> 55 56 #include <machine/endian.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #include <net/bpf.h> 73 74 #include <sys/bus.h> 75 #include <sys/intr.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/ic/gemreg.h> 82 #include <dev/ic/gemvar.h> 83 84 #define TRIES 10000 85 86 static void gem_inten(struct gem_softc *); 87 static void gem_start(struct ifnet *); 88 static void gem_stop(struct ifnet *, int); 89 int gem_ioctl(struct ifnet *, u_long, void *); 90 void gem_tick(void *); 91 void gem_watchdog(struct ifnet *); 92 void gem_rx_watchdog(void *); 93 void gem_pcs_start(struct gem_softc *sc); 94 void gem_pcs_stop(struct gem_softc *sc, int); 95 int gem_init(struct ifnet *); 96 void gem_init_regs(struct gem_softc *sc); 97 static int gem_ringsize(int sz); 98 static int gem_meminit(struct gem_softc *); 99 void gem_mifinit(struct gem_softc *); 100 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 101 uint32_t, uint32_t); 102 void gem_reset(struct gem_softc *); 103 int gem_reset_rx(struct gem_softc *sc); 104 static void gem_reset_rxdma(struct gem_softc *sc); 105 static void gem_rx_common(struct gem_softc *sc); 106 int gem_reset_tx(struct gem_softc *sc); 107 int gem_disable_rx(struct gem_softc *sc); 108 int gem_disable_tx(struct gem_softc *sc); 109 static void gem_rxdrain(struct gem_softc *sc); 110 int gem_add_rxbuf(struct gem_softc *sc, int idx); 111 void gem_setladrf(struct gem_softc *); 112 113 /* MII methods & callbacks */ 114 static int gem_mii_readreg(device_t, int, int, uint16_t *); 115 static int gem_mii_writereg(device_t, int, int, uint16_t); 116 static void gem_mii_statchg(struct ifnet *); 117 118 static int gem_ifflags_cb(struct ethercom *); 119 120 void gem_statuschange(struct gem_softc *); 121 122 int gem_ser_mediachange(struct ifnet *); 123 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 124 125 static void gem_partial_detach(struct gem_softc *, enum gem_attach_stage); 126 127 struct mbuf *gem_get(struct gem_softc *, int, int); 128 int gem_put(struct gem_softc *, int, struct mbuf *); 129 void gem_read(struct gem_softc *, int, int); 130 int gem_pint(struct gem_softc *); 131 int gem_eint(struct gem_softc *, u_int); 132 int gem_rint(struct gem_softc *); 133 int gem_tint(struct gem_softc *); 134 void gem_power(int, void *); 135 136 #ifdef GEM_DEBUG 137 static void gem_txsoft_print(const struct gem_softc *, int, int); 138 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 139 printf x 140 #else 141 #define DPRINTF(sc, x) /* nothing */ 142 #endif 143 144 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 145 146 int 147 gem_detach(struct gem_softc *sc, int flags) 148 { 149 int i; 150 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 151 bus_space_tag_t t = sc->sc_bustag; 152 bus_space_handle_t h = sc->sc_h1; 153 154 /* 155 * Free any resources we've allocated during the attach. 156 * Do this in reverse order and fall through. 157 */ 158 switch (sc->sc_att_stage) { 159 case GEM_ATT_BACKEND_2: 160 case GEM_ATT_BACKEND_1: 161 case GEM_ATT_FINISHED: 162 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 163 gem_stop(&sc->sc_ethercom.ec_if, 1); 164 165 #ifdef GEM_COUNTERS 166 for (i = __arraycount(sc->sc_ev_rxhist); --i >= 0; ) 167 evcnt_detach(&sc->sc_ev_rxhist[i]); 168 evcnt_detach(&sc->sc_ev_rxnobuf); 169 evcnt_detach(&sc->sc_ev_rxfull); 170 evcnt_detach(&sc->sc_ev_rxint); 171 evcnt_detach(&sc->sc_ev_txint); 172 #endif 173 evcnt_detach(&sc->sc_ev_intr); 174 175 rnd_detach_source(&sc->rnd_source); 176 ether_ifdetach(ifp); 177 if_detach(ifp); 178 179 callout_destroy(&sc->sc_tick_ch); 180 callout_destroy(&sc->sc_rx_watchdog); 181 182 /*FALLTHROUGH*/ 183 case GEM_ATT_MII: 184 sc->sc_att_stage = GEM_ATT_MII; 185 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 186 ifmedia_fini(&sc->sc_mii.mii_media); 187 188 /*FALLTHROUGH*/ 189 case GEM_ATT_7: 190 for (i = 0; i < GEM_NRXDESC; i++) { 191 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 192 bus_dmamap_destroy(sc->sc_dmatag, 193 sc->sc_rxsoft[i].rxs_dmamap); 194 } 195 /*FALLTHROUGH*/ 196 case GEM_ATT_6: 197 for (i = 0; i < GEM_TXQUEUELEN; i++) { 198 if (sc->sc_txsoft[i].txs_dmamap != NULL) 199 bus_dmamap_destroy(sc->sc_dmatag, 200 sc->sc_txsoft[i].txs_dmamap); 201 } 202 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 203 /*FALLTHROUGH*/ 204 case GEM_ATT_5: 205 bus_dmamap_unload(sc->sc_dmatag, sc->sc_nulldmamap); 206 /*FALLTHROUGH*/ 207 case GEM_ATT_4: 208 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 209 /*FALLTHROUGH*/ 210 case GEM_ATT_3: 211 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 212 /*FALLTHROUGH*/ 213 case GEM_ATT_2: 214 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 215 sizeof(struct gem_control_data)); 216 /*FALLTHROUGH*/ 217 case GEM_ATT_1: 218 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 219 /*FALLTHROUGH*/ 220 case GEM_ATT_0: 221 sc->sc_att_stage = GEM_ATT_0; 222 /*FALLTHROUGH*/ 223 case GEM_ATT_BACKEND_0: 224 break; 225 } 226 return 0; 227 } 228 229 static void 230 gem_partial_detach(struct gem_softc *sc, enum gem_attach_stage stage) 231 { 232 cfattach_t ca = device_cfattach(sc->sc_dev); 233 234 sc->sc_att_stage = stage; 235 (*ca->ca_detach)(sc->sc_dev, 0); 236 } 237 238 /* 239 * gem_attach: 240 * 241 * Attach a Gem interface to the system. 242 */ 243 void 244 gem_attach(struct gem_softc *sc, const uint8_t *enaddr) 245 { 246 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 247 struct mii_data *mii = &sc->sc_mii; 248 bus_space_tag_t t = sc->sc_bustag; 249 bus_space_handle_t h = sc->sc_h1; 250 struct ifmedia_entry *ife; 251 int i, error, phyaddr; 252 uint32_t v; 253 char *nullbuf; 254 255 /* Make sure the chip is stopped. */ 256 ifp->if_softc = sc; 257 gem_reset(sc); 258 259 /* 260 * Allocate the control data structures, and create and load the 261 * DMA map for it. gem_control_data is 9216 bytes, we have space for 262 * the padding buffer in the bus_dmamem_alloc()'d memory. 263 */ 264 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 265 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 266 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 267 aprint_error_dev(sc->sc_dev, 268 "unable to allocate control data, error = %d\n", 269 error); 270 gem_partial_detach(sc, GEM_ATT_0); 271 return; 272 } 273 274 /* XXX should map this in with correct endianness */ 275 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 276 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 277 BUS_DMA_COHERENT)) != 0) { 278 aprint_error_dev(sc->sc_dev, 279 "unable to map control data, error = %d\n", error); 280 gem_partial_detach(sc, GEM_ATT_1); 281 return; 282 } 283 284 nullbuf = 285 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 286 287 if ((error = bus_dmamap_create(sc->sc_dmatag, 288 sizeof(struct gem_control_data), 1, 289 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 290 aprint_error_dev(sc->sc_dev, 291 "unable to create control data DMA map, error = %d\n", 292 error); 293 gem_partial_detach(sc, GEM_ATT_2); 294 return; 295 } 296 297 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 298 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 299 0)) != 0) { 300 aprint_error_dev(sc->sc_dev, 301 "unable to load control data DMA map, error = %d\n", 302 error); 303 gem_partial_detach(sc, GEM_ATT_3); 304 return; 305 } 306 307 memset(nullbuf, 0, ETHER_MIN_TX); 308 if ((error = bus_dmamap_create(sc->sc_dmatag, 309 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 310 aprint_error_dev(sc->sc_dev, 311 "unable to create padding DMA map, error = %d\n", error); 312 gem_partial_detach(sc, GEM_ATT_4); 313 return; 314 } 315 316 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 317 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 318 aprint_error_dev(sc->sc_dev, 319 "unable to load padding DMA map, error = %d\n", error); 320 gem_partial_detach(sc, GEM_ATT_5); 321 return; 322 } 323 324 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 325 BUS_DMASYNC_PREWRITE); 326 327 /* 328 * Initialize the transmit job descriptors. 329 */ 330 SIMPLEQ_INIT(&sc->sc_txfreeq); 331 SIMPLEQ_INIT(&sc->sc_txdirtyq); 332 333 /* 334 * Create the transmit buffer DMA maps. 335 */ 336 for (i = 0; i < GEM_TXQUEUELEN; i++) { 337 struct gem_txsoft *txs; 338 339 txs = &sc->sc_txsoft[i]; 340 txs->txs_mbuf = NULL; 341 if ((error = bus_dmamap_create(sc->sc_dmatag, 342 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 343 ETHER_MAX_LEN_JUMBO, 0, 0, 344 &txs->txs_dmamap)) != 0) { 345 aprint_error_dev(sc->sc_dev, 346 "unable to create tx DMA map %d, error = %d\n", 347 i, error); 348 gem_partial_detach(sc, GEM_ATT_6); 349 return; 350 } 351 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 352 } 353 354 /* 355 * Create the receive buffer DMA maps. 356 */ 357 for (i = 0; i < GEM_NRXDESC; i++) { 358 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 359 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 360 aprint_error_dev(sc->sc_dev, 361 "unable to create rx DMA map %d, error = %d\n", 362 i, error); 363 gem_partial_detach(sc, GEM_ATT_7); 364 return; 365 } 366 sc->sc_rxsoft[i].rxs_mbuf = NULL; 367 } 368 369 /* Initialize ifmedia structures and MII info */ 370 mii->mii_ifp = ifp; 371 mii->mii_readreg = gem_mii_readreg; 372 mii->mii_writereg = gem_mii_writereg; 373 mii->mii_statchg = gem_mii_statchg; 374 375 sc->sc_ethercom.ec_mii = mii; 376 377 /* 378 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 379 * Section 3.2.1 `Initialization Sequence'. 380 * However, we can't assume SERDES or Serialink if neither 381 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 382 * being set, as both are set on Sun X1141A (with SERDES). So, 383 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 384 * Also, for variants that report 2 PHY's, we prefer the external 385 * PHY over the internal PHY, so we look for that first. 386 */ 387 gem_mifinit(sc); 388 389 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 390 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 391 ether_mediastatus); 392 /* Look for external PHY */ 393 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 394 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 395 bus_space_write_4(t, h, GEM_MIF_CONFIG, 396 sc->sc_mif_config); 397 switch (sc->sc_variant) { 398 case GEM_SUN_ERI: 399 phyaddr = GEM_PHYAD_EXTERNAL; 400 break; 401 default: 402 phyaddr = MII_PHY_ANY; 403 break; 404 } 405 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 406 MII_OFFSET_ANY, MIIF_FORCEANEG); 407 } 408 #ifdef GEM_DEBUG 409 else 410 aprint_debug_dev(sc->sc_dev, "using external PHY\n"); 411 #endif 412 /* Look for internal PHY if no external PHY was found */ 413 if (LIST_EMPTY(&mii->mii_phys) && 414 ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI0) || 415 (sc->sc_variant == GEM_APPLE_K2_GMAC))) { 416 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 417 bus_space_write_4(t, h, GEM_MIF_CONFIG, 418 sc->sc_mif_config); 419 switch (sc->sc_variant) { 420 case GEM_SUN_ERI: 421 case GEM_APPLE_K2_GMAC: 422 phyaddr = GEM_PHYAD_INTERNAL; 423 break; 424 case GEM_APPLE_GMAC: 425 phyaddr = GEM_PHYAD_EXTERNAL; 426 break; 427 default: 428 phyaddr = MII_PHY_ANY; 429 break; 430 } 431 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 432 MII_OFFSET_ANY, MIIF_FORCEANEG); 433 #ifdef GEM_DEBUG 434 if (!LIST_EMPTY(&mii->mii_phys)) 435 aprint_debug_dev(sc->sc_dev, 436 "using internal PHY\n"); 437 #endif 438 } 439 if (LIST_EMPTY(&mii->mii_phys)) { 440 /* No PHY attached */ 441 aprint_error_dev(sc->sc_dev, 442 "PHY probe failed\n"); 443 gem_partial_detach(sc, GEM_ATT_MII); 444 return; 445 } else { 446 struct mii_softc *child; 447 448 /* 449 * Walk along the list of attached MII devices and 450 * establish an `MII instance' to `PHY number' 451 * mapping. 452 */ 453 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 454 /* 455 * Note: we support just one PHY: the internal 456 * or external MII is already selected for us 457 * by the GEM_MIF_CONFIG register. 458 */ 459 if (child->mii_phy > 1 || child->mii_inst > 0) { 460 aprint_error_dev(sc->sc_dev, 461 "cannot accommodate MII device" 462 " %s at PHY %d, instance %d\n", 463 device_xname(child->mii_dev), 464 child->mii_phy, child->mii_inst); 465 continue; 466 } 467 sc->sc_phys[child->mii_inst] = child->mii_phy; 468 } 469 470 if (sc->sc_variant != GEM_SUN_ERI) 471 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 472 GEM_MII_DATAPATH_MII); 473 474 /* 475 * XXX - we can really do the following ONLY if the 476 * PHY indeed has the auto negotiation capability!! 477 */ 478 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 479 } 480 } else { 481 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 482 gem_ser_mediastatus); 483 /* SERDES or Serialink */ 484 if (sc->sc_flags & GEM_SERDES) { 485 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 486 GEM_MII_DATAPATH_SERDES); 487 } else { 488 sc->sc_flags |= GEM_SERIAL; 489 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 490 GEM_MII_DATAPATH_SERIAL); 491 } 492 493 aprint_normal_dev(sc->sc_dev, "using external PCS %s: ", 494 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 495 496 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_AUTO, 0, NULL); 497 /* Check for FDX and HDX capabilities */ 498 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 499 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 500 ifmedia_add(&mii->mii_media, IFM_ETHER | 501 IFM_1000_SX | IFM_MANUAL | IFM_FDX, 0, NULL); 502 aprint_normal("1000baseSX-FDX, "); 503 } 504 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 505 ifmedia_add(&mii->mii_media, IFM_ETHER | 506 IFM_1000_SX | IFM_MANUAL | IFM_HDX, 0, NULL); 507 aprint_normal("1000baseSX-HDX, "); 508 } 509 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 510 sc->sc_mii_media = IFM_AUTO; 511 aprint_normal("auto\n"); 512 513 gem_pcs_stop(sc, 1); 514 } 515 516 /* 517 * From this point forward, the attachment cannot fail. A failure 518 * before this point releases all resources that may have been 519 * allocated. 520 */ 521 522 /* Announce ourselves. */ 523 aprint_normal_dev(sc->sc_dev, "Ethernet address %s", 524 ether_sprintf(enaddr)); 525 526 /* Get RX FIFO size */ 527 sc->sc_rxfifosize = 64 * 528 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 529 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 530 531 /* Get TX FIFO size */ 532 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 533 aprint_normal(", %uKB TX fifo\n", v / 16); 534 535 /* Initialize ifnet structure. */ 536 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 537 ifp->if_softc = sc; 538 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 539 sc->sc_if_flags = ifp->if_flags; 540 #if 0 541 /* 542 * The GEM hardware supports basic TCP checksum offloading only. 543 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 544 * have bugs in the receive checksum, so don't enable it for now. 545 */ 546 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 547 (GEM_IS_APPLE(sc) && 548 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 549 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 550 #endif 551 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 552 ifp->if_start = gem_start; 553 ifp->if_ioctl = gem_ioctl; 554 ifp->if_watchdog = gem_watchdog; 555 ifp->if_stop = gem_stop; 556 ifp->if_init = gem_init; 557 IFQ_SET_READY(&ifp->if_snd); 558 559 /* 560 * If we support GigE media, we support jumbo frames too. 561 * Unless we are Apple. 562 */ 563 TAILQ_FOREACH(ife, &mii->mii_media.ifm_list, ifm_list) { 564 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T || 565 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_SX || 566 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_LX || 567 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_CX) { 568 if (!GEM_IS_APPLE(sc)) 569 sc->sc_ethercom.ec_capabilities 570 |= ETHERCAP_JUMBO_MTU; 571 sc->sc_flags |= GEM_GIGABIT; 572 break; 573 } 574 } 575 576 /* claim 802.1q capability */ 577 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 578 579 /* Attach the interface. */ 580 if_attach(ifp); 581 if_deferred_start_init(ifp, NULL); 582 ether_ifattach(ifp, enaddr); 583 ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb); 584 585 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 586 RND_TYPE_NET, RND_FLAG_DEFAULT); 587 588 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 589 NULL, device_xname(sc->sc_dev), "interrupts"); 590 #ifdef GEM_COUNTERS 591 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 592 &sc->sc_ev_intr, device_xname(sc->sc_dev), "tx interrupts"); 593 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 594 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rx interrupts"); 595 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 596 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx ring full"); 597 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 598 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx malloc failure"); 599 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 600 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 0desc"); 601 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 602 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 1desc"); 603 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 604 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 2desc"); 605 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 606 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 3desc"); 607 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 608 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >3desc"); 609 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 610 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >7desc"); 611 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 612 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >15desc"); 613 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 614 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >31desc"); 615 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 616 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >63desc"); 617 #endif 618 619 callout_init(&sc->sc_tick_ch, 0); 620 callout_setfunc(&sc->sc_tick_ch, gem_tick, sc); 621 622 callout_init(&sc->sc_rx_watchdog, 0); 623 callout_setfunc(&sc->sc_rx_watchdog, gem_rx_watchdog, sc); 624 625 sc->sc_att_stage = GEM_ATT_FINISHED; 626 627 return; 628 } 629 630 void 631 gem_tick(void *arg) 632 { 633 struct gem_softc *sc = arg; 634 int s; 635 636 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 637 /* 638 * We have to reset everything if we failed to get a 639 * PCS interrupt. Restarting the callout is handled 640 * in gem_pcs_start(). 641 */ 642 gem_init(&sc->sc_ethercom.ec_if); 643 } else { 644 s = splnet(); 645 mii_tick(&sc->sc_mii); 646 splx(s); 647 callout_schedule(&sc->sc_tick_ch, hz); 648 } 649 } 650 651 static int 652 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, uint32_t clr, 653 uint32_t set) 654 { 655 int i; 656 uint32_t reg; 657 658 for (i = TRIES; i--; DELAY(100)) { 659 reg = bus_space_read_4(sc->sc_bustag, h, r); 660 if ((reg & clr) == 0 && (reg & set) == set) 661 return (1); 662 } 663 return (0); 664 } 665 666 void 667 gem_reset(struct gem_softc *sc) 668 { 669 bus_space_tag_t t = sc->sc_bustag; 670 bus_space_handle_t h = sc->sc_h2; 671 int s; 672 673 s = splnet(); 674 DPRINTF(sc, ("%s: gem_reset\n", device_xname(sc->sc_dev))); 675 gem_reset_rx(sc); 676 gem_reset_tx(sc); 677 678 /* Do a full reset */ 679 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 680 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 681 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 682 splx(s); 683 } 684 685 686 /* 687 * gem_rxdrain: 688 * 689 * Drain the receive queue. 690 */ 691 static void 692 gem_rxdrain(struct gem_softc *sc) 693 { 694 struct gem_rxsoft *rxs; 695 int i; 696 697 for (i = 0; i < GEM_NRXDESC; i++) { 698 rxs = &sc->sc_rxsoft[i]; 699 if (rxs->rxs_mbuf != NULL) { 700 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 701 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 702 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 703 m_freem(rxs->rxs_mbuf); 704 rxs->rxs_mbuf = NULL; 705 } 706 } 707 } 708 709 /* 710 * Reset the whole thing. 711 */ 712 static void 713 gem_stop(struct ifnet *ifp, int disable) 714 { 715 struct gem_softc *sc = ifp->if_softc; 716 struct gem_txsoft *txs; 717 718 DPRINTF(sc, ("%s: gem_stop\n", device_xname(sc->sc_dev))); 719 720 callout_halt(&sc->sc_tick_ch, NULL); 721 callout_halt(&sc->sc_rx_watchdog, NULL); 722 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 723 gem_pcs_stop(sc, disable); 724 else 725 mii_down(&sc->sc_mii); 726 727 /* XXX - Should we reset these instead? */ 728 gem_disable_tx(sc); 729 gem_disable_rx(sc); 730 731 /* 732 * Release any queued transmit buffers. 733 */ 734 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 735 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 736 if (txs->txs_mbuf != NULL) { 737 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 738 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 739 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 740 m_freem(txs->txs_mbuf); 741 txs->txs_mbuf = NULL; 742 } 743 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 744 } 745 746 /* 747 * Mark the interface down and cancel the watchdog timer. 748 */ 749 ifp->if_flags &= ~IFF_RUNNING; 750 sc->sc_if_flags = ifp->if_flags; 751 ifp->if_timer = 0; 752 753 if (disable) 754 gem_rxdrain(sc); 755 } 756 757 758 /* 759 * Reset the receiver 760 */ 761 int 762 gem_reset_rx(struct gem_softc *sc) 763 { 764 bus_space_tag_t t = sc->sc_bustag; 765 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 766 767 /* 768 * Resetting while DMA is in progress can cause a bus hang, so we 769 * disable DMA first. 770 */ 771 gem_disable_rx(sc); 772 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 773 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 774 /* Wait till it finishes */ 775 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 776 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 777 /* Wait 5ms extra. */ 778 delay(5000); 779 780 /* Finally, reset the ERX */ 781 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 782 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 783 /* Wait till it finishes */ 784 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 785 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 786 return (1); 787 } 788 return (0); 789 } 790 791 792 /* 793 * Reset the receiver DMA engine. 794 * 795 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 796 * etc in order to reset the receiver DMA engine only and not do a full 797 * reset which amongst others also downs the link and clears the FIFOs. 798 */ 799 static void 800 gem_reset_rxdma(struct gem_softc *sc) 801 { 802 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 803 bus_space_tag_t t = sc->sc_bustag; 804 bus_space_handle_t h = sc->sc_h1; 805 int i; 806 807 if (gem_reset_rx(sc) != 0) { 808 gem_init(ifp); 809 return; 810 } 811 for (i = 0; i < GEM_NRXDESC; i++) 812 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 813 GEM_UPDATE_RXDESC(sc, i); 814 sc->sc_rxptr = 0; 815 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 816 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 817 818 /* Reprogram Descriptor Ring Base Addresses */ 819 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 820 ((uint64_t)GEM_CDRXADDR(sc, 0)) >> 32); 821 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 822 823 /* Redo ERX Configuration */ 824 gem_rx_common(sc); 825 826 /* Give the receiver a swift kick */ 827 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 828 } 829 830 /* 831 * Common RX configuration for gem_init() and gem_reset_rxdma(). 832 */ 833 static void 834 gem_rx_common(struct gem_softc *sc) 835 { 836 bus_space_tag_t t = sc->sc_bustag; 837 bus_space_handle_t h = sc->sc_h1; 838 uint32_t v; 839 840 /* Encode Receive Descriptor ring size: four possible values */ 841 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 842 843 /* Set receive h/w checksum offset */ 844 #ifdef INET 845 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 846 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 847 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 848 #endif 849 850 /* Enable RX DMA */ 851 bus_space_write_4(t, h, GEM_RX_CONFIG, 852 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 853 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 854 855 /* 856 * The following value is for an OFF Threshold of about 3/4 full 857 * and an ON Threshold of 1/4 full. 858 */ 859 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 860 (3 * sc->sc_rxfifosize / 256) | 861 ((sc->sc_rxfifosize / 256) << 12)); 862 bus_space_write_4(t, h, GEM_RX_BLANKING, 863 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 8); 864 } 865 866 /* 867 * Reset the transmitter 868 */ 869 int 870 gem_reset_tx(struct gem_softc *sc) 871 { 872 bus_space_tag_t t = sc->sc_bustag; 873 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 874 875 /* 876 * Resetting while DMA is in progress can cause a bus hang, so we 877 * disable DMA first. 878 */ 879 gem_disable_tx(sc); 880 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 881 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 882 /* Wait till it finishes */ 883 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 884 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); 885 /* Wait 5ms extra. */ 886 delay(5000); 887 888 /* Finally, reset the ETX */ 889 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 890 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 891 /* Wait till it finishes */ 892 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 893 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); 894 return (1); 895 } 896 return (0); 897 } 898 899 /* 900 * disable receiver. 901 */ 902 int 903 gem_disable_rx(struct gem_softc *sc) 904 { 905 bus_space_tag_t t = sc->sc_bustag; 906 bus_space_handle_t h = sc->sc_h1; 907 uint32_t cfg; 908 909 /* Flip the enable bit */ 910 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 911 cfg &= ~GEM_MAC_RX_ENABLE; 912 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 913 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 914 /* Wait for it to finish */ 915 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 916 } 917 918 /* 919 * disable transmitter. 920 */ 921 int 922 gem_disable_tx(struct gem_softc *sc) 923 { 924 bus_space_tag_t t = sc->sc_bustag; 925 bus_space_handle_t h = sc->sc_h1; 926 uint32_t cfg; 927 928 /* Flip the enable bit */ 929 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 930 cfg &= ~GEM_MAC_TX_ENABLE; 931 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 932 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 933 /* Wait for it to finish */ 934 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 935 } 936 937 /* 938 * Initialize interface. 939 */ 940 int 941 gem_meminit(struct gem_softc *sc) 942 { 943 struct gem_rxsoft *rxs; 944 int i, error; 945 946 /* 947 * Initialize the transmit descriptor ring. 948 */ 949 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 950 for (i = 0; i < GEM_NTXDESC; i++) { 951 sc->sc_txdescs[i].gd_flags = 0; 952 sc->sc_txdescs[i].gd_addr = 0; 953 } 954 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 955 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 956 sc->sc_txfree = GEM_NTXDESC-1; 957 sc->sc_txnext = 0; 958 sc->sc_txwin = 0; 959 960 /* 961 * Initialize the receive descriptor and receive job 962 * descriptor rings. 963 */ 964 for (i = 0; i < GEM_NRXDESC; i++) { 965 rxs = &sc->sc_rxsoft[i]; 966 if (rxs->rxs_mbuf == NULL) { 967 if ((error = gem_add_rxbuf(sc, i)) != 0) { 968 aprint_error_dev(sc->sc_dev, 969 "unable to allocate or map rx " 970 "buffer %d, error = %d\n", 971 i, error); 972 /* 973 * XXX Should attempt to run with fewer receive 974 * XXX buffers instead of just failing. 975 */ 976 gem_rxdrain(sc); 977 return (1); 978 } 979 } else 980 GEM_INIT_RXDESC(sc, i); 981 } 982 sc->sc_rxptr = 0; 983 sc->sc_meminited = 1; 984 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 985 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 986 987 return (0); 988 } 989 990 static int 991 gem_ringsize(int sz) 992 { 993 switch (sz) { 994 case 32: 995 return GEM_RING_SZ_32; 996 case 64: 997 return GEM_RING_SZ_64; 998 case 128: 999 return GEM_RING_SZ_128; 1000 case 256: 1001 return GEM_RING_SZ_256; 1002 case 512: 1003 return GEM_RING_SZ_512; 1004 case 1024: 1005 return GEM_RING_SZ_1024; 1006 case 2048: 1007 return GEM_RING_SZ_2048; 1008 case 4096: 1009 return GEM_RING_SZ_4096; 1010 case 8192: 1011 return GEM_RING_SZ_8192; 1012 default: 1013 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 1014 return GEM_RING_SZ_32; 1015 } 1016 } 1017 1018 1019 /* 1020 * Start PCS 1021 */ 1022 void 1023 gem_pcs_start(struct gem_softc *sc) 1024 { 1025 bus_space_tag_t t = sc->sc_bustag; 1026 bus_space_handle_t h = sc->sc_h1; 1027 uint32_t v; 1028 1029 #ifdef GEM_DEBUG 1030 aprint_debug_dev(sc->sc_dev, "gem_pcs_start()\n"); 1031 #endif 1032 1033 /* 1034 * Set up. We must disable the MII before modifying the 1035 * GEM_MII_ANAR register 1036 */ 1037 if (sc->sc_flags & GEM_SERDES) { 1038 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1039 GEM_MII_DATAPATH_SERDES); 1040 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1041 GEM_MII_SLINK_LOOPBACK); 1042 } else { 1043 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1044 GEM_MII_DATAPATH_SERIAL); 1045 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 1046 } 1047 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1048 v = bus_space_read_4(t, h, GEM_MII_ANAR); 1049 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 1050 if (IFM_SUBTYPE(sc->sc_mii_media) == IFM_AUTO) 1051 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 1052 else if ((IFM_OPTIONS(sc->sc_mii_media) & IFM_FDX) != 0) { 1053 v |= GEM_MII_ANEG_FUL_DUPLX; 1054 v &= ~GEM_MII_ANEG_HLF_DUPLX; 1055 } else if ((IFM_OPTIONS(sc->sc_mii_media) & IFM_HDX) != 0) { 1056 v &= ~GEM_MII_ANEG_FUL_DUPLX; 1057 v |= GEM_MII_ANEG_HLF_DUPLX; 1058 } 1059 1060 /* Configure link. */ 1061 bus_space_write_4(t, h, GEM_MII_ANAR, v); 1062 bus_space_write_4(t, h, GEM_MII_CONTROL, 1063 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1064 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 1065 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 1066 1067 /* Start the 10 second timer */ 1068 callout_schedule(&sc->sc_tick_ch, hz * 10); 1069 } 1070 1071 /* 1072 * Stop PCS 1073 */ 1074 void 1075 gem_pcs_stop(struct gem_softc *sc, int disable) 1076 { 1077 bus_space_tag_t t = sc->sc_bustag; 1078 bus_space_handle_t h = sc->sc_h1; 1079 1080 #ifdef GEM_DEBUG 1081 aprint_debug_dev(sc->sc_dev, "gem_pcs_stop()\n"); 1082 #endif 1083 1084 /* Tell link partner that we're going away */ 1085 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1086 1087 /* 1088 * Disable PCS MII. The documentation suggests that setting 1089 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1090 * negotiation will shut down the link. However, it appears 1091 * that we also need to unset the datapath mode. 1092 */ 1093 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1094 bus_space_write_4(t, h, GEM_MII_CONTROL, 1095 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1096 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1097 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1098 1099 if (disable) { 1100 if (sc->sc_flags & GEM_SERDES) 1101 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1102 GEM_MII_SLINK_POWER_OFF); 1103 else 1104 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1105 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1106 } 1107 1108 sc->sc_flags &= ~GEM_LINK; 1109 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1110 sc->sc_mii.mii_media_status = IFM_AVALID; 1111 } 1112 1113 1114 /* 1115 * Initialization of interface; set up initialization block 1116 * and transmit/receive descriptor rings. 1117 */ 1118 int 1119 gem_init(struct ifnet *ifp) 1120 { 1121 struct gem_softc *sc = ifp->if_softc; 1122 bus_space_tag_t t = sc->sc_bustag; 1123 bus_space_handle_t h = sc->sc_h1; 1124 int rc = 0, s; 1125 u_int max_frame_size; 1126 uint32_t v; 1127 1128 s = splnet(); 1129 1130 DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(sc->sc_dev))); 1131 /* 1132 * Initialization sequence. The numbered steps below correspond 1133 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1134 * Channel Engine manual (part of the PCIO manual). 1135 * See also the STP2002-STQ document from Sun Microsystems. 1136 */ 1137 1138 /* step 1 & 2. Reset the Ethernet Channel */ 1139 gem_stop(ifp, 0); 1140 gem_reset(sc); 1141 DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(sc->sc_dev))); 1142 1143 /* Re-initialize the MIF */ 1144 gem_mifinit(sc); 1145 1146 /* Set up correct datapath for non-SERDES/Serialink */ 1147 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1148 sc->sc_variant != GEM_SUN_ERI) 1149 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1150 GEM_MII_DATAPATH_MII); 1151 1152 /* Call MI reset function if any */ 1153 if (sc->sc_hwreset) 1154 (*sc->sc_hwreset)(sc); 1155 1156 /* step 3. Setup data structures in host memory */ 1157 if (gem_meminit(sc) != 0) { 1158 splx(s); 1159 return 1; 1160 } 1161 1162 /* step 4. TX MAC registers & counters */ 1163 gem_init_regs(sc); 1164 max_frame_size = uimax(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1165 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1166 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1167 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1168 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1169 max_frame_size|/* burst size */(0x2000<<16)); 1170 1171 /* step 5. RX MAC registers & counters */ 1172 gem_setladrf(sc); 1173 1174 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1175 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 1176 ((uint64_t)GEM_CDTXADDR(sc, 0)) >> 32); 1177 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1178 1179 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 1180 ((uint64_t)GEM_CDRXADDR(sc, 0)) >> 32); 1181 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1182 1183 /* step 8. Global Configuration & Interrupt Mask */ 1184 gem_inten(sc); 1185 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1186 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1187 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1188 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1189 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1190 1191 /* step 9. ETX Configuration: use mostly default values */ 1192 1193 /* Enable TX DMA */ 1194 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1195 bus_space_write_4(t, h, GEM_TX_CONFIG, 1196 v | GEM_TX_CONFIG_TXDMA_EN | 1197 (((sc->sc_flags & GEM_GIGABIT ? 0x4FF : 0x100) << 10) & 1198 GEM_TX_CONFIG_TXFIFO_TH)); 1199 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1200 1201 /* step 10. ERX Configuration */ 1202 gem_rx_common(sc); 1203 1204 /* step 11. Configure Media */ 1205 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1206 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1207 goto out; 1208 1209 /* step 12. RX_MAC Configuration Register */ 1210 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1211 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1212 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1213 1214 /* step 14. Issue Transmit Pending command */ 1215 1216 /* Call MI initialization function if any */ 1217 if (sc->sc_hwinit) 1218 (*sc->sc_hwinit)(sc); 1219 1220 /* step 15. Give the receiver a swift kick */ 1221 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1222 1223 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1224 /* Configure PCS */ 1225 gem_pcs_start(sc); 1226 else 1227 /* Start the one second timer. */ 1228 callout_schedule(&sc->sc_tick_ch, hz); 1229 1230 sc->sc_flags &= ~GEM_LINK; 1231 ifp->if_flags |= IFF_RUNNING; 1232 ifp->if_timer = 0; 1233 sc->sc_if_flags = ifp->if_flags; 1234 out: 1235 splx(s); 1236 1237 return (0); 1238 } 1239 1240 void 1241 gem_init_regs(struct gem_softc *sc) 1242 { 1243 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1244 bus_space_tag_t t = sc->sc_bustag; 1245 bus_space_handle_t h = sc->sc_h1; 1246 const u_char *laddr = CLLADDR(ifp->if_sadl); 1247 uint32_t v; 1248 1249 /* These regs are not cleared on reset */ 1250 if (!sc->sc_inited) { 1251 1252 /* Load recommended values */ 1253 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1254 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1255 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1256 1257 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1258 /* Max frame and max burst size */ 1259 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1260 ETHER_MAX_LEN | (0x2000<<16)); 1261 1262 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1263 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1264 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1265 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1266 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1267 ((laddr[5]<<8)|laddr[4])&0x3ff); 1268 1269 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1270 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1271 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1272 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1273 1274 /* MAC control addr set to 01:80:c2:00:00:01 */ 1275 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1276 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1277 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1278 1279 /* MAC filter addr set to 0:0:0:0:0:0 */ 1280 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1281 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1282 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1283 1284 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1285 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1286 1287 sc->sc_inited = 1; 1288 } 1289 1290 /* Counters need to be zeroed */ 1291 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1292 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1293 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1294 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1295 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1296 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1297 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1298 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1299 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1300 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1301 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1302 1303 /* Set XOFF PAUSE time. */ 1304 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1305 1306 /* 1307 * Set the internal arbitration to "infinite" bursts of the 1308 * maximum length of 31 * 64 bytes so DMA transfers aren't 1309 * split up in cache line size chunks. This greatly improves 1310 * especially RX performance. 1311 * Enable silicon bug workarounds for the Apple variants. 1312 */ 1313 bus_space_write_4(t, h, GEM_CONFIG, 1314 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1315 ((sc->sc_flags & GEM_PCI) ? 1316 GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1317 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1318 1319 /* 1320 * Set the station address. 1321 */ 1322 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1323 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1324 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1325 1326 /* 1327 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1328 */ 1329 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1330 v = GEM_MAC_XIF_TX_MII_ENA; 1331 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1332 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1333 v |= GEM_MAC_XIF_FDPLX_LED; 1334 if (sc->sc_flags & GEM_GIGABIT) 1335 v |= GEM_MAC_XIF_GMII_MODE; 1336 } 1337 } else { 1338 v |= GEM_MAC_XIF_GMII_MODE; 1339 } 1340 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1341 } 1342 1343 #ifdef GEM_DEBUG 1344 static void 1345 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1346 { 1347 int i; 1348 1349 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1350 printf("descriptor %d:\t", i); 1351 printf("gd_flags: 0x%016" PRIx64 "\t", 1352 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1353 printf("gd_addr: 0x%016" PRIx64 "\n", 1354 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1355 if (i == lastdesc) 1356 break; 1357 } 1358 } 1359 #endif 1360 1361 static void 1362 gem_start(struct ifnet *ifp) 1363 { 1364 struct gem_softc *sc = ifp->if_softc; 1365 struct mbuf *m0, *m; 1366 struct gem_txsoft *txs; 1367 bus_dmamap_t dmamap; 1368 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1369 #ifdef GEM_DEBUG 1370 int otxnext; 1371 #endif 1372 uint64_t flags = 0; 1373 1374 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING) 1375 return; 1376 1377 /* 1378 * Remember the previous number of free descriptors and 1379 * the first descriptor we'll use. 1380 */ 1381 ofree = sc->sc_txfree; 1382 #ifdef GEM_DEBUG 1383 otxnext = sc->sc_txnext; 1384 #endif 1385 1386 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1387 device_xname(sc->sc_dev), ofree, otxnext)); 1388 1389 /* 1390 * Loop through the send queue, setting up transmit descriptors 1391 * until we drain the queue, or use up all available transmit 1392 * descriptors. 1393 */ 1394 #ifdef INET 1395 next: 1396 #endif 1397 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1398 sc->sc_txfree != 0) { 1399 /* 1400 * Grab a packet off the queue. 1401 */ 1402 IFQ_POLL(&ifp->if_snd, m0); 1403 if (m0 == NULL) 1404 break; 1405 m = NULL; 1406 1407 dmamap = txs->txs_dmamap; 1408 1409 /* 1410 * Load the DMA map. If this fails, the packet either 1411 * didn't fit in the alloted number of segments, or we were 1412 * short on resources. In this case, we'll copy and try 1413 * again. 1414 */ 1415 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1416 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0 || 1417 (m0->m_pkthdr.len < ETHER_MIN_TX && 1418 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1419 if (m0->m_pkthdr.len > MCLBYTES) { 1420 aprint_error_dev(sc->sc_dev, 1421 "unable to allocate jumbo Tx cluster\n"); 1422 IFQ_DEQUEUE(&ifp->if_snd, m0); 1423 m_freem(m0); 1424 continue; 1425 } 1426 MGETHDR(m, M_DONTWAIT, MT_DATA); 1427 if (m == NULL) { 1428 aprint_error_dev(sc->sc_dev, 1429 "unable to allocate Tx mbuf\n"); 1430 break; 1431 } 1432 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1433 if (m0->m_pkthdr.len > MHLEN) { 1434 MCLGET(m, M_DONTWAIT); 1435 if ((m->m_flags & M_EXT) == 0) { 1436 aprint_error_dev(sc->sc_dev, 1437 "unable to allocate Tx cluster\n"); 1438 m_freem(m); 1439 break; 1440 } 1441 } 1442 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1443 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1444 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1445 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1446 if (error) { 1447 aprint_error_dev(sc->sc_dev, 1448 "unable to load Tx buffer, error = %d\n", 1449 error); 1450 break; 1451 } 1452 } 1453 1454 /* 1455 * Ensure we have enough descriptors free to describe 1456 * the packet. 1457 */ 1458 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1459 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1460 /* 1461 * Not enough free descriptors to transmit this 1462 * packet. 1463 */ 1464 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1465 if (m != NULL) 1466 m_freem(m); 1467 break; 1468 } 1469 1470 IFQ_DEQUEUE(&ifp->if_snd, m0); 1471 if (m != NULL) { 1472 m_freem(m0); 1473 m0 = m; 1474 } 1475 1476 /* 1477 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1478 */ 1479 1480 /* Sync the DMA map. */ 1481 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1482 BUS_DMASYNC_PREWRITE); 1483 1484 /* 1485 * Initialize the transmit descriptors. 1486 */ 1487 firsttx = sc->sc_txnext; 1488 for (nexttx = firsttx, seg = 0; 1489 seg < dmamap->dm_nsegs; 1490 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1491 1492 /* 1493 * If this is the first descriptor we're 1494 * enqueueing, set the start of packet flag, 1495 * and the checksum stuff if we want the hardware 1496 * to do it. 1497 */ 1498 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1499 if (nexttx == firsttx) { 1500 flags |= GEM_TD_START_OF_PACKET; 1501 #ifdef INET 1502 /* h/w checksum */ 1503 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1504 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1505 struct ether_header *eh; 1506 uint16_t offset, start; 1507 1508 eh = mtod(m0, struct ether_header *); 1509 switch (ntohs(eh->ether_type)) { 1510 case ETHERTYPE_IP: 1511 start = ETHER_HDR_LEN; 1512 break; 1513 case ETHERTYPE_VLAN: 1514 start = ETHER_HDR_LEN + 1515 ETHER_VLAN_ENCAP_LEN; 1516 break; 1517 default: 1518 /* unsupported, drop it */ 1519 bus_dmamap_unload(sc->sc_dmatag, 1520 dmamap); 1521 m_freem(m0); 1522 goto next; 1523 } 1524 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1525 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1526 flags |= (start << 1527 GEM_TD_CXSUM_STARTSHFT) | 1528 (offset << 1529 GEM_TD_CXSUM_STUFFSHFT) | 1530 GEM_TD_CXSUM_ENABLE; 1531 } 1532 #endif 1533 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1534 sc->sc_txwin = 0; 1535 flags |= GEM_TD_INTERRUPT_ME; 1536 } 1537 } 1538 sc->sc_txdescs[nexttx].gd_addr = 1539 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1540 if (seg == dmamap->dm_nsegs - 1) { 1541 flags |= GEM_TD_END_OF_PACKET; 1542 } else { 1543 /* last flag set outside of loop */ 1544 sc->sc_txdescs[nexttx].gd_flags = 1545 GEM_DMA_WRITE(sc, flags); 1546 } 1547 lasttx = nexttx; 1548 } 1549 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1550 /* add padding buffer at end of chain */ 1551 flags &= ~GEM_TD_END_OF_PACKET; 1552 sc->sc_txdescs[lasttx].gd_flags = 1553 GEM_DMA_WRITE(sc, flags); 1554 1555 sc->sc_txdescs[nexttx].gd_addr = 1556 GEM_DMA_WRITE(sc, 1557 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1558 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1559 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1560 lasttx = nexttx; 1561 nexttx = GEM_NEXTTX(nexttx); 1562 seg++; 1563 } 1564 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1565 1566 KASSERT(lasttx != -1); 1567 1568 /* 1569 * Store a pointer to the packet so we can free it later, 1570 * and remember what txdirty will be once the packet is 1571 * done. 1572 */ 1573 txs->txs_mbuf = m0; 1574 txs->txs_firstdesc = sc->sc_txnext; 1575 txs->txs_lastdesc = lasttx; 1576 txs->txs_ndescs = seg; 1577 1578 #ifdef GEM_DEBUG 1579 if (ifp->if_flags & IFF_DEBUG) { 1580 printf(" gem_start %p transmit chain:\n", txs); 1581 gem_txsoft_print(sc, txs->txs_firstdesc, 1582 txs->txs_lastdesc); 1583 } 1584 #endif 1585 1586 /* Sync the descriptors we're using. */ 1587 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1588 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1589 1590 /* Advance the tx pointer. */ 1591 sc->sc_txfree -= txs->txs_ndescs; 1592 sc->sc_txnext = nexttx; 1593 1594 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1595 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1596 1597 /* 1598 * Pass the packet to any BPF listeners. 1599 */ 1600 bpf_mtap(ifp, m0, BPF_D_OUT); 1601 } 1602 1603 if (sc->sc_txfree != ofree) { 1604 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1605 device_xname(sc->sc_dev), lasttx, otxnext)); 1606 /* 1607 * The entire packet chain is set up. 1608 * Kick the transmitter. 1609 */ 1610 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1611 device_xname(sc->sc_dev), nexttx)); 1612 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1613 sc->sc_txnext); 1614 1615 /* Set a watchdog timer in case the chip flakes out. */ 1616 ifp->if_timer = 5; 1617 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1618 device_xname(sc->sc_dev), ifp->if_timer)); 1619 } 1620 } 1621 1622 /* 1623 * Transmit interrupt. 1624 */ 1625 int 1626 gem_tint(struct gem_softc *sc) 1627 { 1628 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1629 bus_space_tag_t t = sc->sc_bustag; 1630 bus_space_handle_t mac = sc->sc_h1; 1631 struct gem_txsoft *txs; 1632 int txlast; 1633 int progress = 0; 1634 uint32_t v; 1635 1636 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1637 1638 DPRINTF(sc, ("%s: gem_tint\n", device_xname(sc->sc_dev))); 1639 1640 /* Unload collision counters ... */ 1641 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1642 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1643 if_statadd_ref(nsr, if_collisions, v + 1644 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1645 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT)); 1646 if_statadd_ref(nsr, if_oerrors, v); 1647 1648 /* ... then clear the hardware counters. */ 1649 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1650 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1651 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1652 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1653 1654 /* 1655 * Go through our Tx list and free mbufs for those 1656 * frames that have been transmitted. 1657 */ 1658 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1659 /* 1660 * In theory, we could harvest some descriptors before 1661 * the ring is empty, but that's a bit complicated. 1662 * 1663 * GEM_TX_COMPLETION points to the last descriptor 1664 * processed +1. 1665 * 1666 * Let's assume that the NIC writes back to the Tx 1667 * descriptors before it updates the completion 1668 * register. If the NIC has posted writes to the 1669 * Tx descriptors, PCI ordering requires that the 1670 * posted writes flush to RAM before the register-read 1671 * finishes. So let's read the completion register, 1672 * before syncing the descriptors, so that we 1673 * examine Tx descriptors that are at least as 1674 * current as the completion register. 1675 */ 1676 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1677 DPRINTF(sc, 1678 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1679 txs->txs_lastdesc, txlast)); 1680 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1681 if (txlast >= txs->txs_firstdesc && 1682 txlast <= txs->txs_lastdesc) 1683 break; 1684 } else if (txlast >= txs->txs_firstdesc || 1685 txlast <= txs->txs_lastdesc) 1686 break; 1687 1688 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1689 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1690 1691 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1692 if (ifp->if_flags & IFF_DEBUG) { 1693 printf(" txsoft %p transmit chain:\n", txs); 1694 gem_txsoft_print(sc, txs->txs_firstdesc, 1695 txs->txs_lastdesc); 1696 } 1697 #endif 1698 1699 1700 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1701 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1702 1703 sc->sc_txfree += txs->txs_ndescs; 1704 1705 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1706 0, txs->txs_dmamap->dm_mapsize, 1707 BUS_DMASYNC_POSTWRITE); 1708 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1709 if (txs->txs_mbuf != NULL) { 1710 m_freem(txs->txs_mbuf); 1711 txs->txs_mbuf = NULL; 1712 } 1713 1714 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1715 1716 if_statinc_ref(nsr, if_opackets); 1717 progress = 1; 1718 } 1719 1720 IF_STAT_PUTREF(ifp); 1721 1722 #if 0 1723 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1724 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1725 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1726 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1727 GEM_TX_DATA_PTR_HI) << 32) | 1728 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1729 GEM_TX_DATA_PTR_LO), 1730 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1731 #endif 1732 1733 if (progress) { 1734 if (sc->sc_txfree == GEM_NTXDESC - 1) 1735 sc->sc_txwin = 0; 1736 1737 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1738 if_schedule_deferred_start(ifp); 1739 } 1740 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1741 device_xname(sc->sc_dev), ifp->if_timer)); 1742 1743 return (1); 1744 } 1745 1746 /* 1747 * Receive interrupt. 1748 */ 1749 int 1750 gem_rint(struct gem_softc *sc) 1751 { 1752 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1753 bus_space_tag_t t = sc->sc_bustag; 1754 bus_space_handle_t h = sc->sc_h1; 1755 struct gem_rxsoft *rxs; 1756 struct mbuf *m; 1757 uint64_t rxstat; 1758 uint32_t rxcomp; 1759 int i, len, progress = 0; 1760 1761 DPRINTF(sc, ("%s: gem_rint\n", device_xname(sc->sc_dev))); 1762 1763 /* 1764 * Ignore spurious interrupt that sometimes occurs before 1765 * we are set up when we network boot. 1766 */ 1767 if (!sc->sc_meminited) 1768 return 1; 1769 1770 /* 1771 * Read the completion register once. This limits 1772 * how long the following loop can execute. 1773 */ 1774 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1775 1776 /* 1777 * XXX Read the lastrx only once at the top for speed. 1778 */ 1779 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1780 sc->sc_rxptr, rxcomp)); 1781 1782 /* 1783 * Go into the loop at least once. 1784 */ 1785 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1786 i = GEM_NEXTRX(i)) { 1787 rxs = &sc->sc_rxsoft[i]; 1788 1789 GEM_CDRXSYNC(sc, i, 1790 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1791 1792 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1793 1794 if (rxstat & GEM_RD_OWN) { 1795 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1796 /* 1797 * We have processed all of the receive buffers. 1798 */ 1799 break; 1800 } 1801 1802 progress++; 1803 1804 if (rxstat & GEM_RD_BAD_CRC) { 1805 if_statinc(ifp, if_ierrors); 1806 aprint_error_dev(sc->sc_dev, 1807 "receive error: CRC error\n"); 1808 GEM_INIT_RXDESC(sc, i); 1809 continue; 1810 } 1811 1812 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1813 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1814 #ifdef GEM_DEBUG 1815 if (ifp->if_flags & IFF_DEBUG) { 1816 printf(" rxsoft %p descriptor %d: ", rxs, i); 1817 printf("gd_flags: 0x%016llx\t", (long long) 1818 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1819 printf("gd_addr: 0x%016llx\n", (long long) 1820 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1821 } 1822 #endif 1823 1824 /* No errors; receive the packet. */ 1825 len = GEM_RD_BUFLEN(rxstat); 1826 1827 /* 1828 * Allocate a new mbuf cluster. If that fails, we are 1829 * out of memory, and must drop the packet and recycle 1830 * the buffer that's already attached to this descriptor. 1831 */ 1832 m = rxs->rxs_mbuf; 1833 if (gem_add_rxbuf(sc, i) != 0) { 1834 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1835 if_statinc(ifp, if_ierrors); 1836 aprint_error_dev(sc->sc_dev, 1837 "receive error: RX no buffer space\n"); 1838 GEM_INIT_RXDESC(sc, i); 1839 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1840 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1841 continue; 1842 } 1843 m->m_data += 2; /* We're already off by two */ 1844 1845 m_set_rcvif(m, ifp); 1846 m->m_pkthdr.len = m->m_len = len; 1847 1848 #ifdef INET 1849 /* hardware checksum */ 1850 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1851 struct ether_header *eh; 1852 struct ip *ip; 1853 int32_t hlen, pktlen; 1854 1855 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1856 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1857 ETHER_VLAN_ENCAP_LEN; 1858 eh = (struct ether_header *) (mtod(m, char *) + 1859 ETHER_VLAN_ENCAP_LEN); 1860 } else { 1861 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1862 eh = mtod(m, struct ether_header *); 1863 } 1864 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1865 goto swcsum; 1866 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1867 1868 /* IPv4 only */ 1869 if (ip->ip_v != IPVERSION) 1870 goto swcsum; 1871 1872 hlen = ip->ip_hl << 2; 1873 if (hlen < sizeof(struct ip)) 1874 goto swcsum; 1875 1876 /* 1877 * bail if too short, has random trailing garbage, 1878 * truncated, fragment, or has ethernet pad. 1879 */ 1880 if ((ntohs(ip->ip_len) < hlen) || 1881 (ntohs(ip->ip_len) != pktlen) || 1882 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1883 goto swcsum; 1884 1885 switch (ip->ip_p) { 1886 case IPPROTO_TCP: 1887 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1888 goto swcsum; 1889 if (pktlen < (hlen + sizeof(struct tcphdr))) 1890 goto swcsum; 1891 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1892 break; 1893 case IPPROTO_UDP: 1894 /* FALLTHROUGH */ 1895 default: 1896 goto swcsum; 1897 } 1898 1899 /* the uncomplemented sum is expected */ 1900 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1901 1902 /* if the pkt had ip options, we have to deduct them */ 1903 if (hlen > sizeof(struct ip)) { 1904 uint16_t *opts; 1905 uint32_t optsum, temp; 1906 1907 optsum = 0; 1908 temp = hlen - sizeof(struct ip); 1909 opts = (uint16_t *) ((char *) ip + 1910 sizeof(struct ip)); 1911 1912 while (temp > 1) { 1913 optsum += ntohs(*opts++); 1914 temp -= 2; 1915 } 1916 while (optsum >> 16) 1917 optsum = (optsum >> 16) + 1918 (optsum & 0xffff); 1919 1920 /* Deduct ip opts sum from hwsum. */ 1921 m->m_pkthdr.csum_data += (uint16_t)~optsum; 1922 1923 while (m->m_pkthdr.csum_data >> 16) 1924 m->m_pkthdr.csum_data = 1925 (m->m_pkthdr.csum_data >> 16) + 1926 (m->m_pkthdr.csum_data & 1927 0xffff); 1928 } 1929 1930 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1931 M_CSUM_NO_PSEUDOHDR; 1932 } else 1933 swcsum: 1934 m->m_pkthdr.csum_flags = 0; 1935 #endif 1936 /* Pass it on. */ 1937 if_percpuq_enqueue(ifp->if_percpuq, m); 1938 } 1939 1940 if (progress) { 1941 /* Update the receive pointer. */ 1942 if (i == sc->sc_rxptr) { 1943 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1944 #ifdef GEM_DEBUG 1945 if (ifp->if_flags & IFF_DEBUG) 1946 printf("%s: rint: ring wrap\n", 1947 device_xname(sc->sc_dev)); 1948 #endif 1949 } 1950 sc->sc_rxptr = i; 1951 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1952 } 1953 #ifdef GEM_COUNTERS 1954 if (progress <= 4) { 1955 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1956 } else if (progress < 32) { 1957 if (progress < 16) 1958 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1959 else 1960 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1961 1962 } else { 1963 if (progress < 64) 1964 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1965 else 1966 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1967 } 1968 #endif 1969 1970 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1971 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1972 1973 /* Read error counters ... */ 1974 if_statadd(ifp, if_ierrors, 1975 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1976 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1977 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1978 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL)); 1979 1980 /* ... then clear the hardware counters. */ 1981 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1982 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1983 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1984 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1985 1986 return (1); 1987 } 1988 1989 1990 /* 1991 * gem_add_rxbuf: 1992 * 1993 * Add a receive buffer to the indicated descriptor. 1994 */ 1995 int 1996 gem_add_rxbuf(struct gem_softc *sc, int idx) 1997 { 1998 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1999 struct mbuf *m; 2000 int error; 2001 2002 MGETHDR(m, M_DONTWAIT, MT_DATA); 2003 if (m == NULL) 2004 return (ENOBUFS); 2005 2006 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2007 MCLGET(m, M_DONTWAIT); 2008 if ((m->m_flags & M_EXT) == 0) { 2009 m_freem(m); 2010 return (ENOBUFS); 2011 } 2012 2013 #ifdef GEM_DEBUG 2014 /* bzero the packet to check DMA */ 2015 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 2016 #endif 2017 2018 if (rxs->rxs_mbuf != NULL) 2019 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 2020 2021 rxs->rxs_mbuf = m; 2022 2023 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 2024 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2025 BUS_DMA_READ | BUS_DMA_NOWAIT); 2026 if (error) { 2027 aprint_error_dev(sc->sc_dev, 2028 "can't load rx DMA map %d, error = %d\n", idx, error); 2029 panic("gem_add_rxbuf"); /* XXX */ 2030 } 2031 2032 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 2033 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2034 2035 GEM_INIT_RXDESC(sc, idx); 2036 2037 return (0); 2038 } 2039 2040 2041 int 2042 gem_eint(struct gem_softc *sc, u_int status) 2043 { 2044 char bits[128]; 2045 uint32_t r, v; 2046 2047 if ((status & GEM_INTR_MIF) != 0) { 2048 printf("%s: XXXlink status changed\n", device_xname(sc->sc_dev)); 2049 return (1); 2050 } 2051 2052 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 2053 gem_reset_rxdma(sc); 2054 return (1); 2055 } 2056 2057 if (status & GEM_INTR_BERR) { 2058 if (sc->sc_flags & GEM_PCI) 2059 r = GEM_ERROR_STATUS; 2060 else 2061 r = GEM_SBUS_ERROR_STATUS; 2062 bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2063 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2064 aprint_error_dev(sc->sc_dev, "bus error interrupt: 0x%02x\n", 2065 v); 2066 return (1); 2067 } 2068 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2069 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 2070 2071 return (1); 2072 } 2073 2074 2075 /* 2076 * PCS interrupts. 2077 * We should receive these when the link status changes, but sometimes 2078 * we don't receive them for link up. We compensate for this in the 2079 * gem_tick() callout. 2080 */ 2081 int 2082 gem_pint(struct gem_softc *sc) 2083 { 2084 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2085 bus_space_tag_t t = sc->sc_bustag; 2086 bus_space_handle_t h = sc->sc_h1; 2087 uint32_t v, v2; 2088 2089 /* 2090 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2091 * latched, so we have to read it twice. There is only one bit in 2092 * use, so the value is meaningless. 2093 */ 2094 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2095 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2096 2097 if ((ifp->if_flags & IFF_UP) == 0) 2098 return 1; 2099 2100 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2101 return 1; 2102 2103 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2104 /* If we see remote fault, our link partner is probably going away */ 2105 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2106 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2107 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2108 /* Otherwise, we may need to wait after auto-negotiation completes */ 2109 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2110 GEM_MII_STATUS_ANEG_CPT) { 2111 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2112 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2113 } 2114 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2115 if (sc->sc_flags & GEM_LINK) { 2116 return 1; 2117 } 2118 callout_stop(&sc->sc_tick_ch); 2119 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2120 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2121 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2122 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2123 v &= v2; 2124 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2125 sc->sc_mii.mii_media_active |= IFM_FDX; 2126 #ifdef GEM_DEBUG 2127 aprint_debug_dev(sc->sc_dev, "link up: full duplex\n"); 2128 #endif 2129 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2130 sc->sc_mii.mii_media_active |= IFM_HDX; 2131 #ifdef GEM_DEBUG 2132 aprint_debug_dev(sc->sc_dev, "link up: half duplex\n"); 2133 #endif 2134 } else { 2135 #ifdef GEM_DEBUG 2136 aprint_debug_dev(sc->sc_dev, "duplex mismatch\n"); 2137 #endif 2138 } 2139 gem_statuschange(sc); 2140 } else { 2141 if ((sc->sc_flags & GEM_LINK) == 0) { 2142 return 1; 2143 } 2144 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2145 sc->sc_mii.mii_media_status = IFM_AVALID; 2146 #ifdef GEM_DEBUG 2147 aprint_debug_dev(sc->sc_dev, "link down\n"); 2148 #endif 2149 gem_statuschange(sc); 2150 2151 /* Start the 10 second timer */ 2152 callout_schedule(&sc->sc_tick_ch, hz * 10); 2153 } 2154 return 1; 2155 } 2156 2157 2158 2159 int 2160 gem_intr(void *v) 2161 { 2162 struct gem_softc *sc = v; 2163 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2164 bus_space_tag_t t = sc->sc_bustag; 2165 bus_space_handle_t h = sc->sc_h1; 2166 uint32_t status; 2167 int r = 0; 2168 #ifdef GEM_DEBUG 2169 char bits[128]; 2170 #endif 2171 2172 /* XXX We should probably mask out interrupts until we're done */ 2173 2174 sc->sc_ev_intr.ev_count++; 2175 2176 status = bus_space_read_4(t, h, GEM_STATUS); 2177 #ifdef GEM_DEBUG 2178 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2179 #endif 2180 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2181 device_xname(sc->sc_dev), (status >> 19), bits)); 2182 2183 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2184 r |= gem_eint(sc, status); 2185 2186 /* We don't bother with GEM_INTR_TX_DONE */ 2187 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2188 GEM_COUNTER_INCR(sc, sc_ev_txint); 2189 r |= gem_tint(sc); 2190 } 2191 2192 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2193 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2194 r |= gem_rint(sc); 2195 } 2196 2197 /* We should eventually do more than just print out error stats. */ 2198 if (status & GEM_INTR_TX_MAC) { 2199 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2200 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2201 printf("%s: MAC tx fault, status %x\n", 2202 device_xname(sc->sc_dev), txstat); 2203 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2204 gem_init(ifp); 2205 } 2206 if (status & GEM_INTR_RX_MAC) { 2207 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2208 /* 2209 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2210 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2211 * silicon bug so handle them silently. So if we detect 2212 * an RX FIFO overflow, we fire off a timer, and check 2213 * whether we're still making progress by looking at the 2214 * RX FIFO write and read pointers. 2215 */ 2216 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2217 if_statinc(ifp, if_ierrors); 2218 aprint_error_dev(sc->sc_dev, 2219 "receive error: RX overflow sc->rxptr %d, complete %d\n", sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)); 2220 sc->sc_rx_fifo_wr_ptr = 2221 bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 2222 sc->sc_rx_fifo_rd_ptr = 2223 bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 2224 callout_schedule(&sc->sc_rx_watchdog, 400); 2225 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2226 printf("%s: MAC rx fault, status 0x%02x\n", 2227 device_xname(sc->sc_dev), rxstat); 2228 } 2229 if (status & GEM_INTR_PCS) { 2230 r |= gem_pint(sc); 2231 } 2232 2233 /* Do we need to do anything with these? 2234 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2235 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2236 if ((status2 & GEM_MAC_PAUSED) != 0) 2237 aprintf_debug_dev(sc->sc_dev, "PAUSE received (%d slots)\n", 2238 GEM_MAC_PAUSE_TIME(status2)); 2239 if ((status2 & GEM_MAC_PAUSE) != 0) 2240 aprintf_debug_dev(sc->sc_dev, "transited to PAUSE state\n"); 2241 if ((status2 & GEM_MAC_RESUME) != 0) 2242 aprintf_debug_dev(sc->sc_dev, "transited to non-PAUSE state\n"); 2243 } 2244 if ((status & GEM_INTR_MIF) != 0) 2245 aprintf_debug_dev(sc->sc_dev, "MIF interrupt\n"); 2246 */ 2247 rnd_add_uint32(&sc->rnd_source, status); 2248 return (r); 2249 } 2250 2251 void 2252 gem_rx_watchdog(void *arg) 2253 { 2254 struct gem_softc *sc = arg; 2255 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2256 bus_space_tag_t t = sc->sc_bustag; 2257 bus_space_handle_t h = sc->sc_h1; 2258 uint32_t rx_fifo_wr_ptr; 2259 uint32_t rx_fifo_rd_ptr; 2260 uint32_t state; 2261 2262 if ((ifp->if_flags & IFF_RUNNING) == 0) { 2263 aprint_error_dev(sc->sc_dev, "receiver not running\n"); 2264 return; 2265 } 2266 2267 rx_fifo_wr_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 2268 rx_fifo_rd_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 2269 state = bus_space_read_4(t, h, GEM_MAC_MAC_STATE); 2270 if ((state & GEM_MAC_STATE_OVERFLOW) == GEM_MAC_STATE_OVERFLOW && 2271 ((rx_fifo_wr_ptr == rx_fifo_rd_ptr) || 2272 ((sc->sc_rx_fifo_wr_ptr == rx_fifo_wr_ptr) && 2273 (sc->sc_rx_fifo_rd_ptr == rx_fifo_rd_ptr)))) 2274 { 2275 /* 2276 * The RX state machine is still in overflow state and 2277 * the RX FIFO write and read pointers seem to be 2278 * stuck. Whack the chip over the head to get things 2279 * going again. 2280 */ 2281 aprint_error_dev(sc->sc_dev, 2282 "receiver stuck in overflow, resetting\n"); 2283 gem_init(ifp); 2284 } else { 2285 if ((state & GEM_MAC_STATE_OVERFLOW) != GEM_MAC_STATE_OVERFLOW) { 2286 aprint_error_dev(sc->sc_dev, 2287 "rx_watchdog: not in overflow state: 0x%x\n", 2288 state); 2289 } 2290 if (rx_fifo_wr_ptr != rx_fifo_rd_ptr) { 2291 aprint_error_dev(sc->sc_dev, 2292 "rx_watchdog: wr & rd ptr different\n"); 2293 } 2294 if (sc->sc_rx_fifo_wr_ptr != rx_fifo_wr_ptr) { 2295 aprint_error_dev(sc->sc_dev, 2296 "rx_watchdog: wr pointer != saved\n"); 2297 } 2298 if (sc->sc_rx_fifo_rd_ptr != rx_fifo_rd_ptr) { 2299 aprint_error_dev(sc->sc_dev, 2300 "rx_watchdog: rd pointer != saved\n"); 2301 } 2302 aprint_error_dev(sc->sc_dev, "resetting anyway\n"); 2303 gem_init(ifp); 2304 } 2305 } 2306 2307 void 2308 gem_watchdog(struct ifnet *ifp) 2309 { 2310 struct gem_softc *sc = ifp->if_softc; 2311 2312 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2313 "GEM_MAC_RX_CONFIG %x\n", 2314 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2315 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2316 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2317 2318 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 2319 if_statinc(ifp, if_oerrors); 2320 2321 /* Try to get more packets going. */ 2322 gem_init(ifp); 2323 gem_start(ifp); 2324 } 2325 2326 /* 2327 * Initialize the MII Management Interface 2328 */ 2329 void 2330 gem_mifinit(struct gem_softc *sc) 2331 { 2332 bus_space_tag_t t = sc->sc_bustag; 2333 bus_space_handle_t mif = sc->sc_h1; 2334 2335 /* Configure the MIF in frame mode */ 2336 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2337 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2338 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2339 } 2340 2341 /* 2342 * MII interface 2343 * 2344 * The GEM MII interface supports at least three different operating modes: 2345 * 2346 * Bitbang mode is implemented using data, clock and output enable registers. 2347 * 2348 * Frame mode is implemented by loading a complete frame into the frame 2349 * register and polling the valid bit for completion. 2350 * 2351 * Polling mode uses the frame register but completion is indicated by 2352 * an interrupt. 2353 * 2354 */ 2355 static int 2356 gem_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 2357 { 2358 struct gem_softc *sc = device_private(self); 2359 bus_space_tag_t t = sc->sc_bustag; 2360 bus_space_handle_t mif = sc->sc_h1; 2361 int n; 2362 uint32_t v; 2363 2364 #ifdef GEM_DEBUG1 2365 if (sc->sc_debug) 2366 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2367 #endif 2368 2369 /* Construct the frame command */ 2370 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2371 GEM_MIF_FRAME_READ; 2372 2373 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2374 for (n = 0; n < 100; n++) { 2375 DELAY(1); 2376 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2377 if (v & GEM_MIF_FRAME_TA0) { 2378 *val = v & GEM_MIF_FRAME_DATA; 2379 return 0; 2380 } 2381 } 2382 2383 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 2384 return ETIMEDOUT; 2385 } 2386 2387 static int 2388 gem_mii_writereg(device_t self, int phy, int reg, uint16_t val) 2389 { 2390 struct gem_softc *sc = device_private(self); 2391 bus_space_tag_t t = sc->sc_bustag; 2392 bus_space_handle_t mif = sc->sc_h1; 2393 int n; 2394 uint32_t v; 2395 2396 #ifdef GEM_DEBUG1 2397 if (sc->sc_debug) 2398 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2399 phy, reg, val); 2400 #endif 2401 2402 /* Construct the frame command */ 2403 v = GEM_MIF_FRAME_WRITE | 2404 (phy << GEM_MIF_PHY_SHIFT) | 2405 (reg << GEM_MIF_REG_SHIFT) | 2406 (val & GEM_MIF_FRAME_DATA); 2407 2408 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2409 for (n = 0; n < 100; n++) { 2410 DELAY(1); 2411 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2412 if (v & GEM_MIF_FRAME_TA0) 2413 return 0; 2414 } 2415 2416 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 2417 return ETIMEDOUT; 2418 } 2419 2420 static void 2421 gem_mii_statchg(struct ifnet *ifp) 2422 { 2423 struct gem_softc *sc = ifp->if_softc; 2424 #ifdef GEM_DEBUG 2425 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2426 #endif 2427 2428 #ifdef GEM_DEBUG 2429 if (sc->sc_debug) 2430 printf("gem_mii_statchg: status change: phy = %d\n", 2431 sc->sc_phys[instance]); 2432 #endif 2433 gem_statuschange(sc); 2434 } 2435 2436 /* 2437 * Common status change for gem_mii_statchg() and gem_pint() 2438 */ 2439 void 2440 gem_statuschange(struct gem_softc* sc) 2441 { 2442 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2443 bus_space_tag_t t = sc->sc_bustag; 2444 bus_space_handle_t mac = sc->sc_h1; 2445 int gigabit; 2446 uint32_t rxcfg, txcfg, v; 2447 2448 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2449 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2450 sc->sc_flags |= GEM_LINK; 2451 else 2452 sc->sc_flags &= ~GEM_LINK; 2453 2454 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2455 gigabit = 1; 2456 else 2457 gigabit = 0; 2458 2459 /* 2460 * The configuration done here corresponds to the steps F) and 2461 * G) and as far as enabling of RX and TX MAC goes also step H) 2462 * of the initialization sequence outlined in section 3.2.1 of 2463 * the GEM Gigabit Ethernet ASIC Specification. 2464 */ 2465 2466 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2467 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2468 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2469 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2470 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2471 else if (gigabit) { 2472 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2473 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2474 } 2475 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2476 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2477 BUS_SPACE_BARRIER_WRITE); 2478 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2479 aprint_normal_dev(sc->sc_dev, "cannot disable TX MAC\n"); 2480 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2481 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2482 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2483 BUS_SPACE_BARRIER_WRITE); 2484 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2485 aprint_normal_dev(sc->sc_dev, "cannot disable RX MAC\n"); 2486 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2487 2488 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2489 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2490 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2491 2492 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2493 gigabit != 0) 2494 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2495 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2496 else 2497 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2498 GEM_MAC_SLOT_TIME_NORMAL); 2499 2500 /* XIF Configuration */ 2501 if (sc->sc_flags & GEM_LINK) 2502 v = GEM_MAC_XIF_LINK_LED; 2503 else 2504 v = 0; 2505 v |= GEM_MAC_XIF_TX_MII_ENA; 2506 2507 /* If an external transceiver is connected, enable its MII drivers */ 2508 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2509 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2510 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2511 if (gigabit) 2512 v |= GEM_MAC_XIF_GMII_MODE; 2513 else 2514 v &= ~GEM_MAC_XIF_GMII_MODE; 2515 } else 2516 /* Internal MII needs buf enable */ 2517 v |= GEM_MAC_XIF_MII_BUF_ENA; 2518 /* MII needs echo disable if half duplex. */ 2519 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2520 /* turn on full duplex LED */ 2521 v |= GEM_MAC_XIF_FDPLX_LED; 2522 else 2523 /* half duplex -- disable echo */ 2524 v |= GEM_MAC_XIF_ECHO_DISABL; 2525 } else { 2526 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2527 v |= GEM_MAC_XIF_FDPLX_LED; 2528 v |= GEM_MAC_XIF_GMII_MODE; 2529 } 2530 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2531 2532 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2533 (sc->sc_flags & GEM_LINK) != 0) { 2534 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2535 txcfg | GEM_MAC_TX_ENABLE); 2536 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2537 rxcfg | GEM_MAC_RX_ENABLE); 2538 } 2539 } 2540 2541 int 2542 gem_ser_mediachange(struct ifnet *ifp) 2543 { 2544 struct gem_softc *sc = ifp->if_softc; 2545 u_int s, t; 2546 2547 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2548 return EINVAL; 2549 2550 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2551 if (s == IFM_AUTO) { 2552 if (sc->sc_mii_media != s) { 2553 #ifdef GEM_DEBUG 2554 aprint_debug_dev(sc->sc_dev, "setting media to auto\n"); 2555 #endif 2556 sc->sc_mii_media = s; 2557 if (ifp->if_flags & IFF_UP) { 2558 gem_pcs_stop(sc, 0); 2559 gem_pcs_start(sc); 2560 } 2561 } 2562 return 0; 2563 } 2564 if (s == IFM_1000_SX) { 2565 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media) 2566 & (IFM_FDX | IFM_HDX); 2567 if ((sc->sc_mii_media & (IFM_FDX | IFM_HDX)) != t) { 2568 sc->sc_mii_media &= ~(IFM_FDX | IFM_HDX); 2569 sc->sc_mii_media |= t; 2570 #ifdef GEM_DEBUG 2571 aprint_debug_dev(sc->sc_dev, 2572 "setting media to 1000baseSX-%s\n", 2573 t == IFM_FDX ? "FDX" : "HDX"); 2574 #endif 2575 if (ifp->if_flags & IFF_UP) { 2576 gem_pcs_stop(sc, 0); 2577 gem_pcs_start(sc); 2578 } 2579 } 2580 return 0; 2581 } 2582 return EINVAL; 2583 } 2584 2585 void 2586 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2587 { 2588 struct gem_softc *sc = ifp->if_softc; 2589 2590 if ((ifp->if_flags & IFF_UP) == 0) 2591 return; 2592 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2593 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2594 } 2595 2596 static int 2597 gem_ifflags_cb(struct ethercom *ec) 2598 { 2599 struct ifnet *ifp = &ec->ec_if; 2600 struct gem_softc *sc = ifp->if_softc; 2601 u_short change = ifp->if_flags ^ sc->sc_if_flags; 2602 2603 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 2604 return ENETRESET; 2605 else if ((change & IFF_PROMISC) != 0) 2606 gem_setladrf(sc); 2607 return 0; 2608 } 2609 2610 /* 2611 * Process an ioctl request. 2612 */ 2613 int 2614 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 2615 { 2616 struct gem_softc *sc = ifp->if_softc; 2617 int s, error = 0; 2618 2619 s = splnet(); 2620 2621 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2622 error = 0; 2623 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2624 ; 2625 else if (ifp->if_flags & IFF_RUNNING) { 2626 /* 2627 * Multicast list has changed; set the hardware filter 2628 * accordingly. 2629 */ 2630 gem_setladrf(sc); 2631 } 2632 } 2633 2634 /* Try to get things going again */ 2635 if (ifp->if_flags & IFF_UP) 2636 gem_start(ifp); 2637 splx(s); 2638 return (error); 2639 } 2640 2641 static void 2642 gem_inten(struct gem_softc *sc) 2643 { 2644 bus_space_tag_t t = sc->sc_bustag; 2645 bus_space_handle_t h = sc->sc_h1; 2646 uint32_t v; 2647 2648 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 2649 v = GEM_INTR_PCS; 2650 else 2651 v = GEM_INTR_MIF; 2652 bus_space_write_4(t, h, GEM_INTMASK, 2653 ~(GEM_INTR_TX_INTME | 2654 GEM_INTR_TX_EMPTY | 2655 GEM_INTR_TX_MAC | 2656 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF | 2657 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL | 2658 GEM_INTR_BERR | v)); 2659 } 2660 2661 bool 2662 gem_resume(device_t self, const pmf_qual_t *qual) 2663 { 2664 struct gem_softc *sc = device_private(self); 2665 2666 gem_inten(sc); 2667 2668 return true; 2669 } 2670 2671 bool 2672 gem_suspend(device_t self, const pmf_qual_t *qual) 2673 { 2674 struct gem_softc *sc = device_private(self); 2675 bus_space_tag_t t = sc->sc_bustag; 2676 bus_space_handle_t h = sc->sc_h1; 2677 2678 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 2679 2680 return true; 2681 } 2682 2683 bool 2684 gem_shutdown(device_t self, int howto) 2685 { 2686 struct gem_softc *sc = device_private(self); 2687 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2688 2689 gem_stop(ifp, 1); 2690 2691 return true; 2692 } 2693 2694 /* 2695 * Set up the logical address filter. 2696 */ 2697 void 2698 gem_setladrf(struct gem_softc *sc) 2699 { 2700 struct ethercom *ec = &sc->sc_ethercom; 2701 struct ifnet *ifp = &ec->ec_if; 2702 struct ether_multi *enm; 2703 struct ether_multistep step; 2704 bus_space_tag_t t = sc->sc_bustag; 2705 bus_space_handle_t h = sc->sc_h1; 2706 uint32_t crc; 2707 uint32_t hash[16]; 2708 uint32_t v; 2709 int i; 2710 2711 /* Get current RX configuration */ 2712 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2713 2714 /* 2715 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2716 * and hash filter. Depending on the case, the right bit will be 2717 * enabled. 2718 */ 2719 v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_HASH_FILTER | 2720 GEM_MAC_RX_PROMISC_GRP); 2721 2722 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2723 /* Turn on promiscuous mode */ 2724 v |= GEM_MAC_RX_PROMISCUOUS; 2725 ifp->if_flags |= IFF_ALLMULTI; 2726 goto chipit; 2727 } 2728 2729 /* 2730 * Set up multicast address filter by passing all multicast addresses 2731 * through a crc generator, and then using the high order 8 bits as an 2732 * index into the 256 bit logical address filter. The high order 4 2733 * bits selects the word, while the other 4 bits select the bit within 2734 * the word (where bit 0 is the MSB). 2735 */ 2736 2737 /* Clear hash table */ 2738 memset(hash, 0, sizeof(hash)); 2739 2740 ETHER_LOCK(ec); 2741 ETHER_FIRST_MULTI(step, ec, enm); 2742 while (enm != NULL) { 2743 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2744 /* 2745 * We must listen to a range of multicast addresses. 2746 * For now, just accept all multicasts, rather than 2747 * trying to set only those filter bits needed to match 2748 * the range. (At this time, the only use of address 2749 * ranges is for IP multicast routing, for which the 2750 * range is big enough to require all bits set.) 2751 * XXX should use the address filters for this 2752 */ 2753 ifp->if_flags |= IFF_ALLMULTI; 2754 v |= GEM_MAC_RX_PROMISC_GRP; 2755 ETHER_UNLOCK(ec); 2756 goto chipit; 2757 } 2758 2759 /* Get the LE CRC32 of the address */ 2760 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2761 2762 /* Just want the 8 most significant bits. */ 2763 crc >>= 24; 2764 2765 /* Set the corresponding bit in the filter. */ 2766 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2767 2768 ETHER_NEXT_MULTI(step, enm); 2769 } 2770 ETHER_UNLOCK(ec); 2771 2772 v |= GEM_MAC_RX_HASH_FILTER; 2773 ifp->if_flags &= ~IFF_ALLMULTI; 2774 2775 /* Now load the hash table into the chip (if we are using it) */ 2776 for (i = 0; i < 16; i++) { 2777 bus_space_write_4(t, h, 2778 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2779 hash[i]); 2780 } 2781 2782 chipit: 2783 sc->sc_if_flags = ifp->if_flags; 2784 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2785 } 2786