1 /* $NetBSD: gem.c,v 1.4 2001/10/18 03:33:33 thorpej Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include "bpfilter.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/callout.h> 41 #include <sys/mbuf.h> 42 #include <sys/syslog.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/ioctl.h> 47 #include <sys/errno.h> 48 #include <sys/device.h> 49 50 #include <machine/endian.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_ether.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 #include <dev/mii/mii_bitbang.h> 69 70 #include <dev/ic/gemreg.h> 71 #include <dev/ic/gemvar.h> 72 73 #define TRIES 10000 74 75 void gem_start __P((struct ifnet *)); 76 void gem_stop __P((struct ifnet *, int)); 77 int gem_ioctl __P((struct ifnet *, u_long, caddr_t)); 78 void gem_tick __P((void *)); 79 void gem_watchdog __P((struct ifnet *)); 80 void gem_shutdown __P((void *)); 81 int gem_init __P((struct ifnet *)); 82 void gem_init_regs(struct gem_softc *sc); 83 static int gem_ringsize(int sz); 84 int gem_meminit __P((struct gem_softc *)); 85 void gem_mifinit __P((struct gem_softc *)); 86 void gem_reset __P((struct gem_softc *)); 87 int gem_reset_rx(struct gem_softc *sc); 88 int gem_reset_tx(struct gem_softc *sc); 89 int gem_disable_rx(struct gem_softc *sc); 90 int gem_disable_tx(struct gem_softc *sc); 91 void gem_rxdrain(struct gem_softc *sc); 92 int gem_add_rxbuf(struct gem_softc *sc, int idx); 93 void gem_setladrf __P((struct gem_softc *)); 94 95 /* MII methods & callbacks */ 96 static int gem_mii_readreg __P((struct device *, int, int)); 97 static void gem_mii_writereg __P((struct device *, int, int, int)); 98 static void gem_mii_statchg __P((struct device *)); 99 100 int gem_mediachange __P((struct ifnet *)); 101 void gem_mediastatus __P((struct ifnet *, struct ifmediareq *)); 102 103 struct mbuf *gem_get __P((struct gem_softc *, int, int)); 104 int gem_put __P((struct gem_softc *, int, struct mbuf *)); 105 void gem_read __P((struct gem_softc *, int, int)); 106 int gem_eint __P((struct gem_softc *, u_int)); 107 int gem_rint __P((struct gem_softc *)); 108 int gem_tint __P((struct gem_softc *)); 109 void gem_power __P((int, void *)); 110 111 static int ether_cmp __P((u_char *, u_char *)); 112 113 /* Default buffer copy routines */ 114 void gem_copytobuf_contig __P((struct gem_softc *, void *, int, int)); 115 void gem_copyfrombuf_contig __P((struct gem_softc *, void *, int, int)); 116 void gem_zerobuf_contig __P((struct gem_softc *, int, int)); 117 118 119 #ifdef GEM_DEBUG 120 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 121 printf x 122 #else 123 #define DPRINTF(sc, x) /* nothing */ 124 #endif 125 126 127 /* 128 * gem_config: 129 * 130 * Attach a Gem interface to the system. 131 */ 132 void 133 gem_config(sc) 134 struct gem_softc *sc; 135 { 136 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 137 struct mii_data *mii = &sc->sc_mii; 138 struct mii_softc *child; 139 int i, error; 140 141 /* Make sure the chip is stopped. */ 142 ifp->if_softc = sc; 143 gem_reset(sc); 144 145 /* 146 * Allocate the control data structures, and create and load the 147 * DMA map for it. 148 */ 149 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 150 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 151 1, &sc->sc_cdnseg, 0)) != 0) { 152 printf("%s: unable to allocate control data, error = %d\n", 153 sc->sc_dev.dv_xname, error); 154 goto fail_0; 155 } 156 157 /* XXX should map this in with correct endianness */ 158 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 159 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 160 BUS_DMA_COHERENT)) != 0) { 161 printf("%s: unable to map control data, error = %d\n", 162 sc->sc_dev.dv_xname, error); 163 goto fail_1; 164 } 165 166 if ((error = bus_dmamap_create(sc->sc_dmatag, 167 sizeof(struct gem_control_data), 1, 168 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 169 printf("%s: unable to create control data DMA map, " 170 "error = %d\n", sc->sc_dev.dv_xname, error); 171 goto fail_2; 172 } 173 174 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 175 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 176 0)) != 0) { 177 printf("%s: unable to load control data DMA map, error = %d\n", 178 sc->sc_dev.dv_xname, error); 179 goto fail_3; 180 } 181 182 /* 183 * Initialize the transmit job descriptors. 184 */ 185 SIMPLEQ_INIT(&sc->sc_txfreeq); 186 SIMPLEQ_INIT(&sc->sc_txdirtyq); 187 188 /* 189 * Create the transmit buffer DMA maps. 190 */ 191 for (i = 0; i < GEM_TXQUEUELEN; i++) { 192 struct gem_txsoft *txs; 193 194 txs = &sc->sc_txsoft[i]; 195 txs->txs_mbuf = NULL; 196 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 197 GEM_NTXSEGS, MCLBYTES, 0, 0, 198 &txs->txs_dmamap)) != 0) { 199 printf("%s: unable to create tx DMA map %d, " 200 "error = %d\n", sc->sc_dev.dv_xname, i, error); 201 goto fail_4; 202 } 203 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 204 } 205 206 /* 207 * Create the receive buffer DMA maps. 208 */ 209 for (i = 0; i < GEM_NRXDESC; i++) { 210 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 211 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 212 printf("%s: unable to create rx DMA map %d, " 213 "error = %d\n", sc->sc_dev.dv_xname, i, error); 214 goto fail_5; 215 } 216 sc->sc_rxsoft[i].rxs_mbuf = NULL; 217 } 218 219 /* 220 * From this point forward, the attachment cannot fail. A failure 221 * before this point releases all resources that may have been 222 * allocated. 223 */ 224 225 /* Announce ourselves. */ 226 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 227 ether_sprintf(sc->sc_enaddr)); 228 229 /* Initialize ifnet structure. */ 230 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 231 ifp->if_softc = sc; 232 ifp->if_flags = 233 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 234 ifp->if_start = gem_start; 235 ifp->if_ioctl = gem_ioctl; 236 ifp->if_watchdog = gem_watchdog; 237 ifp->if_stop = gem_stop; 238 ifp->if_init = gem_init; 239 IFQ_SET_READY(&ifp->if_snd); 240 241 /* Initialize ifmedia structures and MII info */ 242 mii->mii_ifp = ifp; 243 mii->mii_readreg = gem_mii_readreg; 244 mii->mii_writereg = gem_mii_writereg; 245 mii->mii_statchg = gem_mii_statchg; 246 247 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus); 248 249 gem_mifinit(sc); 250 251 mii_attach(&sc->sc_dev, mii, 0xffffffff, 252 MII_PHY_ANY, MII_OFFSET_ANY, 0); 253 254 child = LIST_FIRST(&mii->mii_phys); 255 if (child == NULL) { 256 /* No PHY attached */ 257 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 258 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 259 } else { 260 /* 261 * Walk along the list of attached MII devices and 262 * establish an `MII instance' to `phy number' 263 * mapping. We'll use this mapping in media change 264 * requests to determine which phy to use to program 265 * the MIF configuration register. 266 */ 267 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 268 /* 269 * Note: we support just two PHYs: the built-in 270 * internal device and an external on the MII 271 * connector. 272 */ 273 if (child->mii_phy > 1 || child->mii_inst > 1) { 274 printf("%s: cannot accomodate MII device %s" 275 " at phy %d, instance %d\n", 276 sc->sc_dev.dv_xname, 277 child->mii_dev.dv_xname, 278 child->mii_phy, child->mii_inst); 279 continue; 280 } 281 282 sc->sc_phys[child->mii_inst] = child->mii_phy; 283 } 284 285 /* 286 * Now select and activate the PHY we will use. 287 * 288 * The order of preference is External (MDI1), 289 * Internal (MDI0), Serial Link (no MII). 290 */ 291 if (sc->sc_phys[1]) { 292 #ifdef DEBUG 293 printf("using external phy\n"); 294 #endif 295 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 296 } else { 297 #ifdef DEBUG 298 printf("using internal phy\n"); 299 #endif 300 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 301 } 302 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 303 sc->sc_mif_config); 304 305 /* 306 * XXX - we can really do the following ONLY if the 307 * phy indeed has the auto negotiation capability!! 308 */ 309 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 310 } 311 312 /* claim 802.1q capability */ 313 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 314 315 /* Attach the interface. */ 316 if_attach(ifp); 317 ether_ifattach(ifp, sc->sc_enaddr); 318 319 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 320 if (sc->sc_sh == NULL) 321 panic("gem_config: can't establish shutdownhook"); 322 323 #if NRND > 0 324 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 325 RND_TYPE_NET, 0); 326 #endif 327 328 329 #if notyet 330 /* 331 * Add a suspend hook to make sure we come back up after a 332 * resume. 333 */ 334 sc->sc_powerhook = powerhook_establish(gem_power, sc); 335 if (sc->sc_powerhook == NULL) 336 printf("%s: WARNING: unable to establish power hook\n", 337 sc->sc_dev.dv_xname); 338 #endif 339 340 callout_init(&sc->sc_tick_ch); 341 return; 342 343 /* 344 * Free any resources we've allocated during the failed attach 345 * attempt. Do this in reverse order and fall through. 346 */ 347 fail_5: 348 for (i = 0; i < GEM_NRXDESC; i++) { 349 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 350 bus_dmamap_destroy(sc->sc_dmatag, 351 sc->sc_rxsoft[i].rxs_dmamap); 352 } 353 fail_4: 354 for (i = 0; i < GEM_TXQUEUELEN; i++) { 355 if (sc->sc_txsoft[i].txs_dmamap != NULL) 356 bus_dmamap_destroy(sc->sc_dmatag, 357 sc->sc_txsoft[i].txs_dmamap); 358 } 359 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 360 fail_3: 361 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 362 fail_2: 363 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 364 sizeof(struct gem_control_data)); 365 fail_1: 366 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 367 fail_0: 368 return; 369 } 370 371 372 void 373 gem_tick(arg) 374 void *arg; 375 { 376 struct gem_softc *sc = arg; 377 int s; 378 379 s = splnet(); 380 mii_tick(&sc->sc_mii); 381 splx(s); 382 383 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 384 385 } 386 387 void 388 gem_reset(sc) 389 struct gem_softc *sc; 390 { 391 bus_space_tag_t t = sc->sc_bustag; 392 bus_space_handle_t h = sc->sc_h; 393 int i; 394 int s; 395 396 s = splnet(); 397 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 398 gem_reset_rx(sc); 399 gem_reset_tx(sc); 400 401 /* Do a full reset */ 402 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 403 for (i=TRIES; i--; delay(100)) 404 if ((bus_space_read_4(t, h, GEM_RESET) & 405 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 406 break; 407 if ((bus_space_read_4(t, h, GEM_RESET) & 408 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 409 printf("%s: cannot reset device\n", 410 sc->sc_dev.dv_xname); 411 } 412 splx(s); 413 } 414 415 416 /* 417 * gem_rxdrain: 418 * 419 * Drain the receive queue. 420 */ 421 void 422 gem_rxdrain(struct gem_softc *sc) 423 { 424 struct gem_rxsoft *rxs; 425 int i; 426 427 for (i = 0; i < GEM_NRXDESC; i++) { 428 rxs = &sc->sc_rxsoft[i]; 429 if (rxs->rxs_mbuf != NULL) { 430 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 431 m_freem(rxs->rxs_mbuf); 432 rxs->rxs_mbuf = NULL; 433 } 434 } 435 } 436 437 /* 438 * Reset the whole thing. 439 */ 440 void 441 gem_stop(struct ifnet *ifp, int disable) 442 { 443 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 444 struct gem_txsoft *txs; 445 446 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 447 448 callout_stop(&sc->sc_tick_ch); 449 mii_down(&sc->sc_mii); 450 451 /* XXX - Should we reset these instead? */ 452 gem_disable_rx(sc); 453 gem_disable_rx(sc); 454 455 /* 456 * Release any queued transmit buffers. 457 */ 458 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 459 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 460 if (txs->txs_mbuf != NULL) { 461 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 462 m_freem(txs->txs_mbuf); 463 txs->txs_mbuf = NULL; 464 } 465 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 466 } 467 468 if (disable) { 469 gem_rxdrain(sc); 470 } 471 472 /* 473 * Mark the interface down and cancel the watchdog timer. 474 */ 475 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 476 ifp->if_timer = 0; 477 } 478 479 480 /* 481 * Reset the receiver 482 */ 483 int 484 gem_reset_rx(struct gem_softc *sc) 485 { 486 bus_space_tag_t t = sc->sc_bustag; 487 bus_space_handle_t h = sc->sc_h; 488 int i; 489 490 491 /* 492 * Resetting while DMA is in progress can cause a bus hang, so we 493 * disable DMA first. 494 */ 495 gem_disable_rx(sc); 496 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 497 /* Wait till it finishes */ 498 for (i=TRIES; i--; delay(100)) 499 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 500 break; 501 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 502 printf("%s: cannot disable read dma\n", 503 sc->sc_dev.dv_xname); 504 505 /* Wait 5ms extra. */ 506 delay(5000); 507 508 /* Finally, reset the ERX */ 509 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 510 /* Wait till it finishes */ 511 for (i=TRIES; i--; delay(100)) 512 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 513 break; 514 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 515 printf("%s: cannot reset receiver\n", 516 sc->sc_dev.dv_xname); 517 return (1); 518 } 519 return (0); 520 } 521 522 523 /* 524 * Reset the transmitter 525 */ 526 int 527 gem_reset_tx(struct gem_softc *sc) 528 { 529 bus_space_tag_t t = sc->sc_bustag; 530 bus_space_handle_t h = sc->sc_h; 531 int i; 532 533 /* 534 * Resetting while DMA is in progress can cause a bus hang, so we 535 * disable DMA first. 536 */ 537 gem_disable_tx(sc); 538 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 539 /* Wait till it finishes */ 540 for (i=TRIES; i--; delay(100)) 541 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 542 break; 543 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 544 printf("%s: cannot disable read dma\n", 545 sc->sc_dev.dv_xname); 546 547 /* Wait 5ms extra. */ 548 delay(5000); 549 550 /* Finally, reset the ETX */ 551 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 552 /* Wait till it finishes */ 553 for (i=TRIES; i--; delay(100)) 554 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 555 break; 556 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 557 printf("%s: cannot reset receiver\n", 558 sc->sc_dev.dv_xname); 559 return (1); 560 } 561 return (0); 562 } 563 564 /* 565 * disable receiver. 566 */ 567 int 568 gem_disable_rx(struct gem_softc *sc) 569 { 570 bus_space_tag_t t = sc->sc_bustag; 571 bus_space_handle_t h = sc->sc_h; 572 int i; 573 u_int32_t cfg; 574 575 /* Flip the enable bit */ 576 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 577 cfg &= ~GEM_MAC_RX_ENABLE; 578 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 579 580 /* Wait for it to finish */ 581 for (i=TRIES; i--; delay(100)) 582 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 583 GEM_MAC_RX_ENABLE) == 0) 584 return (0); 585 return (1); 586 } 587 588 /* 589 * disable transmitter. 590 */ 591 int 592 gem_disable_tx(struct gem_softc *sc) 593 { 594 bus_space_tag_t t = sc->sc_bustag; 595 bus_space_handle_t h = sc->sc_h; 596 int i; 597 u_int32_t cfg; 598 599 /* Flip the enable bit */ 600 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 601 cfg &= ~GEM_MAC_TX_ENABLE; 602 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 603 604 /* Wait for it to finish */ 605 for (i=TRIES; i--; delay(100)) 606 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 607 GEM_MAC_TX_ENABLE) == 0) 608 return (0); 609 return (1); 610 } 611 612 /* 613 * Initialize interface. 614 */ 615 int 616 gem_meminit(struct gem_softc *sc) 617 { 618 struct gem_rxsoft *rxs; 619 int i, error; 620 621 /* 622 * Initialize the transmit descriptor ring. 623 */ 624 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 625 for (i = 0; i < GEM_NTXDESC; i++) { 626 sc->sc_txdescs[i].gd_flags = 0; 627 sc->sc_txdescs[i].gd_addr = 0; 628 } 629 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 630 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 631 sc->sc_txfree = GEM_NTXDESC; 632 sc->sc_txnext = 0; 633 634 /* 635 * Initialize the receive descriptor and receive job 636 * descriptor rings. 637 */ 638 for (i = 0; i < GEM_NRXDESC; i++) { 639 rxs = &sc->sc_rxsoft[i]; 640 if (rxs->rxs_mbuf == NULL) { 641 if ((error = gem_add_rxbuf(sc, i)) != 0) { 642 printf("%s: unable to allocate or map rx " 643 "buffer %d, error = %d\n", 644 sc->sc_dev.dv_xname, i, error); 645 /* 646 * XXX Should attempt to run with fewer receive 647 * XXX buffers instead of just failing. 648 */ 649 gem_rxdrain(sc); 650 return (1); 651 } 652 } else 653 GEM_INIT_RXDESC(sc, i); 654 } 655 sc->sc_rxptr = 0; 656 657 return (0); 658 } 659 660 static int 661 gem_ringsize(int sz) 662 { 663 int v; 664 665 switch (sz) { 666 case 32: 667 v = GEM_RING_SZ_32; 668 break; 669 case 64: 670 v = GEM_RING_SZ_64; 671 break; 672 case 128: 673 v = GEM_RING_SZ_128; 674 break; 675 case 256: 676 v = GEM_RING_SZ_256; 677 break; 678 case 512: 679 v = GEM_RING_SZ_512; 680 break; 681 case 1024: 682 v = GEM_RING_SZ_1024; 683 break; 684 case 2048: 685 v = GEM_RING_SZ_2048; 686 break; 687 case 4096: 688 v = GEM_RING_SZ_4096; 689 break; 690 case 8192: 691 v = GEM_RING_SZ_8192; 692 break; 693 default: 694 printf("gem: invalid Receive Descriptor ring size\n"); 695 break; 696 } 697 return (v); 698 } 699 700 /* 701 * Initialization of interface; set up initialization block 702 * and transmit/receive descriptor rings. 703 */ 704 int 705 gem_init(struct ifnet *ifp) 706 { 707 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 708 bus_space_tag_t t = sc->sc_bustag; 709 bus_space_handle_t h = sc->sc_h; 710 int s; 711 u_int32_t v; 712 713 s = splnet(); 714 715 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 716 /* 717 * Initialization sequence. The numbered steps below correspond 718 * to the sequence outlined in section 6.3.5.1 in the Ethernet 719 * Channel Engine manual (part of the PCIO manual). 720 * See also the STP2002-STQ document from Sun Microsystems. 721 */ 722 723 /* step 1 & 2. Reset the Ethernet Channel */ 724 gem_stop(ifp, 0); 725 gem_reset(sc); 726 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 727 728 /* Re-initialize the MIF */ 729 gem_mifinit(sc); 730 731 /* Call MI reset function if any */ 732 if (sc->sc_hwreset) 733 (*sc->sc_hwreset)(sc); 734 735 /* step 3. Setup data structures in host memory */ 736 gem_meminit(sc); 737 738 /* step 4. TX MAC registers & counters */ 739 gem_init_regs(sc); 740 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 741 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 742 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN + sizeof(struct ether_header): 743 ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16)); 744 745 /* step 5. RX MAC registers & counters */ 746 gem_setladrf(sc); 747 748 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 749 /* NOTE: we use only 32-bit DMA addresses here. */ 750 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 751 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 752 753 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 754 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 755 756 /* step 8. Global Configuration & Interrupt Mask */ 757 bus_space_write_4(t, h, GEM_INTMASK, 758 ~(GEM_INTR_TX_INTME| 759 GEM_INTR_TX_EMPTY| 760 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 761 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 762 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 763 GEM_INTR_BERR)); 764 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 0); /* XXXX */ 765 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 766 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 767 #if 0 768 if (!sc->sc_pci) { 769 /* Config SBus */ 770 switch (sc->sc_burst) { 771 default: 772 v = 0; 773 break; 774 case 16: 775 v = GEM_SEB_CFG_BURST16; 776 break; 777 case 32: 778 v = GEM_SEB_CFG_BURST32; 779 break; 780 case 64: 781 v = GEM_SEB_CFG_BURST64; 782 break; 783 } 784 bus_space_write_4(t, seb, GEM_SEBI_CFG, 785 v|GE_SIOCFG_PARITY|GE_SIOCFG_BMODE64); 786 } 787 #endif 788 /* step 9. ETX Configuration: use mostly default values */ 789 790 /* Enable DMA */ 791 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 792 bus_space_write_4(t, h, GEM_TX_CONFIG, 793 v|GEM_TX_CONFIG_TXDMA_EN| 794 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 795 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 796 797 /* step 10. ERX Configuration */ 798 799 /* Encode Receive Descriptor ring size: four possible values */ 800 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 801 802 /* Enable DMA */ 803 bus_space_write_4(t, h, GEM_RX_CONFIG, 804 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 805 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 806 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 807 /* 808 * The following value is for an OFF Threshold of about 15.5 Kbytes 809 * and an ON Threshold of 4K bytes. 810 */ 811 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 0xf8 | (0x40 << 12)); 812 bus_space_write_4(t, h, GEM_RX_BLANKING, (2<<12)|6); 813 814 /* step 11. Configure Media */ 815 gem_mii_statchg(&sc->sc_dev); 816 817 /* XXXX Serial link needs a whole different setup. */ 818 819 820 /* step 12. RX_MAC Configuration Register */ 821 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 822 v |= GEM_MAC_RX_ENABLE; 823 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 824 825 /* step 14. Issue Transmit Pending command */ 826 827 /* Call MI initialization function if any */ 828 if (sc->sc_hwinit) 829 (*sc->sc_hwinit)(sc); 830 831 832 /* step 15. Give the reciever a swift kick */ 833 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 834 835 /* Start the one second timer. */ 836 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 837 838 ifp->if_flags |= IFF_RUNNING; 839 ifp->if_flags &= ~IFF_OACTIVE; 840 ifp->if_timer = 0; 841 splx(s); 842 843 return (0); 844 } 845 846 /* 847 * Compare two Ether/802 addresses for equality, inlined and unrolled for 848 * speed. 849 */ 850 static __inline__ int 851 ether_cmp(a, b) 852 u_char *a, *b; 853 { 854 855 if (a[5] != b[5] || a[4] != b[4] || a[3] != b[3] || 856 a[2] != b[2] || a[1] != b[1] || a[0] != b[0]) 857 return (0); 858 return (1); 859 } 860 861 862 void 863 gem_init_regs(struct gem_softc *sc) 864 { 865 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 866 bus_space_tag_t t = sc->sc_bustag; 867 bus_space_handle_t h = sc->sc_h; 868 869 /* These regs are not cleared on reset */ 870 sc->sc_inited = 0; 871 if (!sc->sc_inited) { 872 873 /* Wooo. Magic values. */ 874 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 875 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 876 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 877 878 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 879 /* Max frame and max burst size */ 880 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 881 (ifp->if_mtu+18) | (0x2000<<16)/* Burst size */); 882 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 883 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 884 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 885 /* Dunno.... */ 886 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 887 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 888 ((sc->sc_enaddr[5]<<8)|sc->sc_enaddr[4])&0x3ff); 889 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 890 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 891 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 892 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 893 /* MAC control addr set to 0:1:c2:0:1:80 */ 894 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 895 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 896 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 897 898 /* MAC filter addr set to 0:0:0:0:0:0 */ 899 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 900 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 901 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 902 903 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 904 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 905 906 sc->sc_inited = 1; 907 } 908 909 /* Counters need to be zeroed */ 910 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 911 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 912 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 913 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 914 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 915 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 916 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 917 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 918 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 919 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 920 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 921 922 /* Un-pause stuff */ 923 #if 0 924 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 925 #else 926 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 927 #endif 928 929 /* 930 * Set the station address. 931 */ 932 bus_space_write_4(t, h, GEM_MAC_ADDR0, 933 (sc->sc_enaddr[4]<<8) | sc->sc_enaddr[5]); 934 bus_space_write_4(t, h, GEM_MAC_ADDR1, 935 (sc->sc_enaddr[2]<<8) | sc->sc_enaddr[3]); 936 bus_space_write_4(t, h, GEM_MAC_ADDR2, 937 (sc->sc_enaddr[0]<<8) | sc->sc_enaddr[1]); 938 939 } 940 941 942 943 void 944 gem_start(ifp) 945 struct ifnet *ifp; 946 { 947 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 948 struct mbuf *m0, *m; 949 struct gem_txsoft *txs, *last_txs; 950 bus_dmamap_t dmamap; 951 int error, firsttx, nexttx, lasttx, ofree, seg; 952 953 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 954 return; 955 956 /* 957 * Remember the previous number of free descriptors and 958 * the first descriptor we'll use. 959 */ 960 ofree = sc->sc_txfree; 961 firsttx = sc->sc_txnext; 962 963 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 964 sc->sc_dev.dv_xname, ofree, firsttx)); 965 966 /* 967 * Loop through the send queue, setting up transmit descriptors 968 * until we drain the queue, or use up all available transmit 969 * descriptors. 970 */ 971 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 972 sc->sc_txfree != 0) { 973 /* 974 * Grab a packet off the queue. 975 */ 976 IFQ_POLL(&ifp->if_snd, m0); 977 if (m0 == NULL) 978 break; 979 m = NULL; 980 981 dmamap = txs->txs_dmamap; 982 983 /* 984 * Load the DMA map. If this fails, the packet either 985 * didn't fit in the alloted number of segments, or we were 986 * short on resources. In this case, we'll copy and try 987 * again. 988 */ 989 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 990 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 991 MGETHDR(m, M_DONTWAIT, MT_DATA); 992 if (m == NULL) { 993 printf("%s: unable to allocate Tx mbuf\n", 994 sc->sc_dev.dv_xname); 995 break; 996 } 997 if (m0->m_pkthdr.len > MHLEN) { 998 MCLGET(m, M_DONTWAIT); 999 if ((m->m_flags & M_EXT) == 0) { 1000 printf("%s: unable to allocate Tx " 1001 "cluster\n", sc->sc_dev.dv_xname); 1002 m_freem(m); 1003 break; 1004 } 1005 } 1006 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1007 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1008 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1009 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1010 if (error) { 1011 printf("%s: unable to load Tx buffer, " 1012 "error = %d\n", sc->sc_dev.dv_xname, error); 1013 break; 1014 } 1015 } 1016 1017 /* 1018 * Ensure we have enough descriptors free to describe 1019 * the packet. 1020 */ 1021 if (dmamap->dm_nsegs > sc->sc_txfree) { 1022 /* 1023 * Not enough free descriptors to transmit this 1024 * packet. We haven't committed to anything yet, 1025 * so just unload the DMA map, put the packet 1026 * back on the queue, and punt. Notify the upper 1027 * layer that there are no more slots left. 1028 * 1029 * XXX We could allocate an mbuf and copy, but 1030 * XXX it is worth it? 1031 */ 1032 ifp->if_flags |= IFF_OACTIVE; 1033 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1034 if (m != NULL) 1035 m_freem(m); 1036 break; 1037 } 1038 1039 IFQ_DEQUEUE(&ifp->if_snd, m0); 1040 if (m != NULL) { 1041 m_freem(m0); 1042 m0 = m; 1043 } 1044 1045 /* 1046 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1047 */ 1048 1049 /* Sync the DMA map. */ 1050 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1051 BUS_DMASYNC_PREWRITE); 1052 1053 /* 1054 * Initialize the transmit descriptors. 1055 */ 1056 for (nexttx = sc->sc_txnext, seg = 0; 1057 seg < dmamap->dm_nsegs; 1058 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1059 uint64_t flags; 1060 1061 /* 1062 * If this is the first descriptor we're 1063 * enqueueing, set the start of packet flag, 1064 * and the checksum stuff if we want the hardware 1065 * to do it. 1066 */ 1067 sc->sc_txdescs[nexttx].gd_addr = 1068 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1069 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1070 if (nexttx == firsttx) { 1071 flags |= GEM_TD_START_OF_PACKET; 1072 } 1073 if (seg == dmamap->dm_nsegs - 1) { 1074 flags |= GEM_TD_END_OF_PACKET; 1075 } 1076 sc->sc_txdescs[nexttx].gd_flags = 1077 GEM_DMA_WRITE(sc, flags); 1078 lasttx = nexttx; 1079 } 1080 1081 #ifdef GEM_DEBUG 1082 if (ifp->if_flags & IFF_DEBUG) { 1083 printf(" gem_start %p transmit chain:\n", txs); 1084 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1085 printf("descriptor %d:\t", seg); 1086 printf("gd_flags: 0x%016llx\t", (long long) 1087 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1088 printf("gd_addr: 0x%016llx\n", (long long) 1089 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1090 if (seg == lasttx) 1091 break; 1092 } 1093 } 1094 #endif 1095 1096 /* Sync the descriptors we're using. */ 1097 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1098 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1099 1100 /* 1101 * Store a pointer to the packet so we can free it later, 1102 * and remember what txdirty will be once the packet is 1103 * done. 1104 */ 1105 txs->txs_mbuf = m0; 1106 txs->txs_firstdesc = sc->sc_txnext; 1107 txs->txs_lastdesc = lasttx; 1108 txs->txs_ndescs = dmamap->dm_nsegs; 1109 1110 /* Advance the tx pointer. */ 1111 sc->sc_txfree -= dmamap->dm_nsegs; 1112 sc->sc_txnext = nexttx; 1113 1114 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1115 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1116 1117 last_txs = txs; 1118 1119 #if NBPFILTER > 0 1120 /* 1121 * Pass the packet to any BPF listeners. 1122 */ 1123 if (ifp->if_bpf) 1124 bpf_mtap(ifp->if_bpf, m0); 1125 #endif /* NBPFILTER > 0 */ 1126 } 1127 1128 if (txs == NULL || sc->sc_txfree == 0) { 1129 /* No more slots left; notify upper layer. */ 1130 ifp->if_flags |= IFF_OACTIVE; 1131 } 1132 1133 if (sc->sc_txfree != ofree) { 1134 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1135 sc->sc_dev.dv_xname, lasttx, firsttx)); 1136 /* 1137 * The entire packet chain is set up. 1138 * Kick the transmitter. 1139 */ 1140 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1141 sc->sc_dev.dv_xname, nexttx)); 1142 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1143 sc->sc_txnext); 1144 1145 /* Set a watchdog timer in case the chip flakes out. */ 1146 ifp->if_timer = 5; 1147 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1148 sc->sc_dev.dv_xname, ifp->if_timer)); 1149 } 1150 } 1151 1152 /* 1153 * Transmit interrupt. 1154 */ 1155 int 1156 gem_tint(sc) 1157 struct gem_softc *sc; 1158 { 1159 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1160 bus_space_tag_t t = sc->sc_bustag; 1161 bus_space_handle_t mac = sc->sc_h; 1162 struct gem_txsoft *txs; 1163 int txlast; 1164 1165 1166 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1167 1168 /* 1169 * Unload collision counters 1170 */ 1171 ifp->if_collisions += 1172 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1173 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1174 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1175 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1176 1177 /* 1178 * then clear the hardware counters. 1179 */ 1180 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1181 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1182 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1183 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1184 1185 /* 1186 * Go through our Tx list and free mbufs for those 1187 * frames that have been transmitted. 1188 */ 1189 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1190 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1191 txs->txs_ndescs, 1192 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1193 1194 #ifdef GEM_DEBUG 1195 if (ifp->if_flags & IFF_DEBUG) { 1196 int i; 1197 printf(" txsoft %p transmit chain:\n", txs); 1198 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1199 printf("descriptor %d: ", i); 1200 printf("gd_flags: 0x%016llx\t", (long long) 1201 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1202 printf("gd_addr: 0x%016llx\n", (long long) 1203 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1204 if (i == txs->txs_lastdesc) 1205 break; 1206 } 1207 } 1208 #endif 1209 1210 /* 1211 * In theory, we could harveast some descriptors before 1212 * the ring is empty, but that's a bit complicated. 1213 * 1214 * GEM_TX_COMPLETION points to the last descriptor 1215 * processed +1. 1216 */ 1217 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1218 DPRINTF(sc, 1219 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1220 txs->txs_lastdesc, txlast)); 1221 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1222 if ((txlast >= txs->txs_firstdesc) && 1223 (txlast <= txs->txs_lastdesc)) 1224 break; 1225 } else { 1226 /* Ick -- this command wraps */ 1227 if ((txlast >= txs->txs_firstdesc) || 1228 (txlast <= txs->txs_lastdesc)) 1229 break; 1230 } 1231 1232 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1233 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1234 1235 sc->sc_txfree += txs->txs_ndescs; 1236 1237 if (txs->txs_mbuf == NULL) { 1238 #ifdef DIAGNOSTIC 1239 panic("gem_txintr: null mbuf"); 1240 #endif 1241 } 1242 1243 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1244 0, txs->txs_dmamap->dm_mapsize, 1245 BUS_DMASYNC_POSTWRITE); 1246 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1247 m_freem(txs->txs_mbuf); 1248 txs->txs_mbuf = NULL; 1249 1250 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1251 1252 ifp->if_opackets++; 1253 } 1254 1255 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1256 "GEM_TX_DATA_PTR %llx " 1257 "GEM_TX_COMPLETION %x\n", 1258 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1259 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1260 GEM_TX_DATA_PTR_HI) << 32) | 1261 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1262 GEM_TX_DATA_PTR_LO), 1263 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1264 1265 gem_start(ifp); 1266 1267 if (SIMPLEQ_FIRST(&sc->sc_txdirtyq) == NULL) 1268 ifp->if_timer = 0; 1269 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1270 sc->sc_dev.dv_xname, ifp->if_timer)); 1271 1272 return (1); 1273 } 1274 1275 /* 1276 * Receive interrupt. 1277 */ 1278 int 1279 gem_rint(sc) 1280 struct gem_softc *sc; 1281 { 1282 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1283 bus_space_tag_t t = sc->sc_bustag; 1284 bus_space_handle_t h = sc->sc_h; 1285 struct ether_header *eh; 1286 struct gem_rxsoft *rxs; 1287 struct mbuf *m; 1288 u_int64_t rxstat; 1289 int i, len; 1290 1291 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1292 /* 1293 * XXXX Read the lastrx only once at the top for speed. 1294 */ 1295 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1296 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1297 for (i = sc->sc_rxptr; i != bus_space_read_4(t, h, GEM_RX_COMPLETION); 1298 i = GEM_NEXTRX(i)) { 1299 rxs = &sc->sc_rxsoft[i]; 1300 1301 GEM_CDRXSYNC(sc, i, 1302 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1303 1304 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1305 1306 if (rxstat & GEM_RD_OWN) { 1307 printf("gem_rint: completed descriptor " 1308 "still owned %d\n", i); 1309 /* 1310 * We have processed all of the receive buffers. 1311 */ 1312 break; 1313 } 1314 1315 if (rxstat & GEM_RD_BAD_CRC) { 1316 printf("%s: receive error: CRC error\n", 1317 sc->sc_dev.dv_xname); 1318 GEM_INIT_RXDESC(sc, i); 1319 continue; 1320 } 1321 1322 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1323 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1324 #ifdef GEM_DEBUG 1325 if (ifp->if_flags & IFF_DEBUG) { 1326 printf(" rxsoft %p descriptor %d: ", rxs, i); 1327 printf("gd_flags: 0x%016llx\t", (long long) 1328 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1329 printf("gd_addr: 0x%016llx\n", (long long) 1330 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1331 } 1332 #endif 1333 1334 /* 1335 * No errors; receive the packet. Note the Gem 1336 * includes the CRC with every packet. 1337 */ 1338 len = GEM_RD_BUFLEN(rxstat); 1339 1340 /* 1341 * Allocate a new mbuf cluster. If that fails, we are 1342 * out of memory, and must drop the packet and recycle 1343 * the buffer that's already attached to this descriptor. 1344 */ 1345 m = rxs->rxs_mbuf; 1346 if (gem_add_rxbuf(sc, i) != 0) { 1347 ifp->if_ierrors++; 1348 GEM_INIT_RXDESC(sc, i); 1349 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1350 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1351 continue; 1352 } 1353 m->m_data += 2; /* We're already off by two */ 1354 1355 ifp->if_ipackets++; 1356 eh = mtod(m, struct ether_header *); 1357 m->m_flags |= M_HASFCS; 1358 m->m_pkthdr.rcvif = ifp; 1359 m->m_pkthdr.len = m->m_len = len; 1360 1361 #if NBPFILTER > 0 1362 /* 1363 * Pass this up to any BPF listeners, but only 1364 * pass it up the stack if its for us. 1365 */ 1366 if (ifp->if_bpf) 1367 bpf_mtap(ifp->if_bpf, m); 1368 #endif /* NPBFILTER > 0 */ 1369 1370 #if 0 1371 /* 1372 * We sometimes have to run the 21140 in Hash-Only 1373 * mode. If we're in that mode, and not in promiscuous 1374 * mode, and we have a unicast packet that isn't for 1375 * us, then drop it. 1376 */ 1377 if (sc->sc_filtmode == TDCTL_Tx_FT_HASHONLY && 1378 (ifp->if_flags & IFF_PROMISC) == 0 && 1379 ETHER_IS_MULTICAST(eh->ether_dhost) == 0 && 1380 memcmp(LLADDR(ifp->if_sadl), eh->ether_dhost, 1381 ETHER_ADDR_LEN) != 0) { 1382 m_freem(m); 1383 continue; 1384 } 1385 #endif 1386 1387 /* Pass it on. */ 1388 (*ifp->if_input)(ifp, m); 1389 } 1390 1391 /* Update the receive pointer. */ 1392 sc->sc_rxptr = i; 1393 bus_space_write_4(t, h, GEM_RX_KICK, i); 1394 1395 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1396 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1397 1398 return (1); 1399 } 1400 1401 1402 /* 1403 * gem_add_rxbuf: 1404 * 1405 * Add a receive buffer to the indicated descriptor. 1406 */ 1407 int 1408 gem_add_rxbuf(struct gem_softc *sc, int idx) 1409 { 1410 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1411 struct mbuf *m; 1412 int error; 1413 1414 MGETHDR(m, M_DONTWAIT, MT_DATA); 1415 if (m == NULL) 1416 return (ENOBUFS); 1417 1418 MCLGET(m, M_DONTWAIT); 1419 if ((m->m_flags & M_EXT) == 0) { 1420 m_freem(m); 1421 return (ENOBUFS); 1422 } 1423 1424 #ifdef GEM_DEBUG 1425 /* bzero the packet to check dma */ 1426 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1427 #endif 1428 1429 if (rxs->rxs_mbuf != NULL) 1430 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1431 1432 rxs->rxs_mbuf = m; 1433 1434 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1435 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1436 BUS_DMA_READ|BUS_DMA_NOWAIT); 1437 if (error) { 1438 printf("%s: can't load rx DMA map %d, error = %d\n", 1439 sc->sc_dev.dv_xname, idx, error); 1440 panic("gem_add_rxbuf"); /* XXX */ 1441 } 1442 1443 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1444 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1445 1446 GEM_INIT_RXDESC(sc, idx); 1447 1448 return (0); 1449 } 1450 1451 1452 int 1453 gem_eint(sc, status) 1454 struct gem_softc *sc; 1455 u_int status; 1456 { 1457 char bits[128]; 1458 1459 if ((status & GEM_INTR_MIF) != 0) { 1460 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1461 return (1); 1462 } 1463 1464 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1465 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1466 return (1); 1467 } 1468 1469 1470 int 1471 gem_intr(v) 1472 void *v; 1473 { 1474 struct gem_softc *sc = (struct gem_softc *)v; 1475 bus_space_tag_t t = sc->sc_bustag; 1476 bus_space_handle_t seb = sc->sc_h; 1477 u_int32_t status; 1478 int r = 0; 1479 #ifdef GEM_DEBUG 1480 char bits[128]; 1481 #endif 1482 1483 status = bus_space_read_4(t, seb, GEM_STATUS); 1484 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %s\n", 1485 sc->sc_dev.dv_xname, (status>>19), 1486 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1487 1488 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1489 r |= gem_eint(sc, status); 1490 1491 if ((status & 1492 (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) 1493 != 0) 1494 r |= gem_tint(sc); 1495 1496 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1497 r |= gem_rint(sc); 1498 1499 /* We should eventually do more than just print out error stats. */ 1500 if (status & GEM_INTR_TX_MAC) { 1501 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1502 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1503 printf("MAC tx fault, status %x\n", txstat); 1504 } 1505 if (status & GEM_INTR_RX_MAC) { 1506 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1507 if (rxstat & ~GEM_MAC_RX_DONE) 1508 printf("MAC rx fault, status %x\n", rxstat); 1509 } 1510 return (r); 1511 } 1512 1513 1514 void 1515 gem_watchdog(ifp) 1516 struct ifnet *ifp; 1517 { 1518 struct gem_softc *sc = ifp->if_softc; 1519 1520 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1521 "GEM_MAC_RX_CONFIG %x\n", 1522 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1523 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1524 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1525 1526 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1527 ++ifp->if_oerrors; 1528 1529 /* Try to get more packets going. */ 1530 gem_start(ifp); 1531 } 1532 1533 /* 1534 * Initialize the MII Management Interface 1535 */ 1536 void 1537 gem_mifinit(sc) 1538 struct gem_softc *sc; 1539 { 1540 bus_space_tag_t t = sc->sc_bustag; 1541 bus_space_handle_t mif = sc->sc_h; 1542 1543 /* Configure the MIF in frame mode */ 1544 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1545 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1546 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1547 } 1548 1549 /* 1550 * MII interface 1551 * 1552 * The GEM MII interface supports at least three different operating modes: 1553 * 1554 * Bitbang mode is implemented using data, clock and output enable registers. 1555 * 1556 * Frame mode is implemented by loading a complete frame into the frame 1557 * register and polling the valid bit for completion. 1558 * 1559 * Polling mode uses the frame register but completion is indicated by 1560 * an interrupt. 1561 * 1562 */ 1563 static int 1564 gem_mii_readreg(self, phy, reg) 1565 struct device *self; 1566 int phy, reg; 1567 { 1568 struct gem_softc *sc = (void *)self; 1569 bus_space_tag_t t = sc->sc_bustag; 1570 bus_space_handle_t mif = sc->sc_h; 1571 int n; 1572 u_int32_t v; 1573 1574 #ifdef GEM_DEBUG1 1575 if (sc->sc_debug) 1576 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1577 #endif 1578 1579 #if 0 1580 /* Select the desired PHY in the MIF configuration register */ 1581 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1582 /* Clear PHY select bit */ 1583 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1584 if (phy == GEM_PHYAD_EXTERNAL) 1585 /* Set PHY select bit to get at external device */ 1586 v |= GEM_MIF_CONFIG_PHY_SEL; 1587 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1588 #endif 1589 1590 /* Construct the frame command */ 1591 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1592 GEM_MIF_FRAME_READ; 1593 1594 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1595 for (n = 0; n < 100; n++) { 1596 DELAY(1); 1597 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1598 if (v & GEM_MIF_FRAME_TA0) 1599 return (v & GEM_MIF_FRAME_DATA); 1600 } 1601 1602 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1603 return (0); 1604 } 1605 1606 static void 1607 gem_mii_writereg(self, phy, reg, val) 1608 struct device *self; 1609 int phy, reg, val; 1610 { 1611 struct gem_softc *sc = (void *)self; 1612 bus_space_tag_t t = sc->sc_bustag; 1613 bus_space_handle_t mif = sc->sc_h; 1614 int n; 1615 u_int32_t v; 1616 1617 #ifdef GEM_DEBUG1 1618 if (sc->sc_debug) 1619 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1620 phy, reg, val); 1621 #endif 1622 1623 #if 0 1624 /* Select the desired PHY in the MIF configuration register */ 1625 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1626 /* Clear PHY select bit */ 1627 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1628 if (phy == GEM_PHYAD_EXTERNAL) 1629 /* Set PHY select bit to get at external device */ 1630 v |= GEM_MIF_CONFIG_PHY_SEL; 1631 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1632 #endif 1633 /* Construct the frame command */ 1634 v = GEM_MIF_FRAME_WRITE | 1635 (phy << GEM_MIF_PHY_SHIFT) | 1636 (reg << GEM_MIF_REG_SHIFT) | 1637 (val & GEM_MIF_FRAME_DATA); 1638 1639 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1640 for (n = 0; n < 100; n++) { 1641 DELAY(1); 1642 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1643 if (v & GEM_MIF_FRAME_TA0) 1644 return; 1645 } 1646 1647 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1648 } 1649 1650 static void 1651 gem_mii_statchg(dev) 1652 struct device *dev; 1653 { 1654 struct gem_softc *sc = (void *)dev; 1655 #ifdef GEM_DEBUG 1656 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1657 #endif 1658 bus_space_tag_t t = sc->sc_bustag; 1659 bus_space_handle_t mac = sc->sc_h; 1660 u_int32_t v; 1661 1662 #ifdef GEM_DEBUG 1663 if (sc->sc_debug) 1664 printf("gem_mii_statchg: status change: phy = %d\n", 1665 sc->sc_phys[instance];); 1666 #endif 1667 1668 1669 /* Set tx full duplex options */ 1670 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1671 delay(10000); /* reg must be cleared and delay before changing. */ 1672 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1673 GEM_MAC_TX_ENABLE; 1674 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1675 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1676 } 1677 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1678 1679 /* XIF Configuration */ 1680 /* We should really calculate all this rather than rely on defaults */ 1681 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1682 v = GEM_MAC_XIF_LINK_LED; 1683 v |= GEM_MAC_XIF_TX_MII_ENA; 1684 /* If an external transceiver is connected, enable its MII drivers */ 1685 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1686 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1687 /* External MII needs echo disable if half duplex. */ 1688 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1689 /* turn on full duplex LED */ 1690 v |= GEM_MAC_XIF_FDPLX_LED; 1691 else 1692 /* half duplex -- disable echo */ 1693 v |= GEM_MAC_XIF_ECHO_DISABL; 1694 } else 1695 /* Internal MII needs buf enable */ 1696 v |= GEM_MAC_XIF_MII_BUF_ENA; 1697 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1698 } 1699 1700 int 1701 gem_mediachange(ifp) 1702 struct ifnet *ifp; 1703 { 1704 struct gem_softc *sc = ifp->if_softc; 1705 1706 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1707 return (EINVAL); 1708 1709 return (mii_mediachg(&sc->sc_mii)); 1710 } 1711 1712 void 1713 gem_mediastatus(ifp, ifmr) 1714 struct ifnet *ifp; 1715 struct ifmediareq *ifmr; 1716 { 1717 struct gem_softc *sc = ifp->if_softc; 1718 1719 if ((ifp->if_flags & IFF_UP) == 0) 1720 return; 1721 1722 mii_pollstat(&sc->sc_mii); 1723 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1724 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1725 } 1726 1727 int gem_ioctldebug = 0; 1728 /* 1729 * Process an ioctl request. 1730 */ 1731 int 1732 gem_ioctl(ifp, cmd, data) 1733 struct ifnet *ifp; 1734 u_long cmd; 1735 caddr_t data; 1736 { 1737 struct gem_softc *sc = ifp->if_softc; 1738 struct ifreq *ifr = (struct ifreq *)data; 1739 int s, error = 0; 1740 1741 1742 switch (cmd) { 1743 case SIOCGIFMEDIA: 1744 case SIOCSIFMEDIA: 1745 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1746 break; 1747 1748 default: 1749 error = ether_ioctl(ifp, cmd, data); 1750 if (error == ENETRESET) { 1751 /* 1752 * Multicast list has changed; set the hardware filter 1753 * accordingly. 1754 */ 1755 if (gem_ioctldebug) printf("reset1\n"); 1756 gem_init(ifp); 1757 delay(50000); 1758 error = 0; 1759 } 1760 break; 1761 } 1762 1763 /* Try to get things going again */ 1764 if (ifp->if_flags & IFF_UP) { 1765 if (gem_ioctldebug) printf("start\n"); 1766 gem_start(ifp); 1767 } 1768 splx(s); 1769 return (error); 1770 } 1771 1772 1773 void 1774 gem_shutdown(arg) 1775 void *arg; 1776 { 1777 struct gem_softc *sc = (struct gem_softc *)arg; 1778 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1779 1780 gem_stop(ifp, 1); 1781 } 1782 1783 /* 1784 * Set up the logical address filter. 1785 */ 1786 void 1787 gem_setladrf(sc) 1788 struct gem_softc *sc; 1789 { 1790 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1791 struct ether_multi *enm; 1792 struct ether_multistep step; 1793 struct ethercom *ec = &sc->sc_ethercom; 1794 bus_space_tag_t t = sc->sc_bustag; 1795 bus_space_handle_t h = sc->sc_h; 1796 u_char *cp; 1797 u_int32_t crc; 1798 u_int32_t hash[16]; 1799 u_int32_t v; 1800 int len; 1801 1802 /* Clear hash table */ 1803 memset(hash, 0, sizeof(hash)); 1804 1805 /* Get current RX configuration */ 1806 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1807 1808 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1809 /* Turn on promiscuous mode; turn off the hash filter */ 1810 v |= GEM_MAC_RX_PROMISCUOUS; 1811 v &= ~GEM_MAC_RX_HASH_FILTER; 1812 ifp->if_flags |= IFF_ALLMULTI; 1813 goto chipit; 1814 } 1815 1816 /* Turn off promiscuous mode; turn on the hash filter */ 1817 v &= ~GEM_MAC_RX_PROMISCUOUS; 1818 v |= GEM_MAC_RX_HASH_FILTER; 1819 1820 /* 1821 * Set up multicast address filter by passing all multicast addresses 1822 * through a crc generator, and then using the high order 6 bits as an 1823 * index into the 256 bit logical address filter. The high order bit 1824 * selects the word, while the rest of the bits select the bit within 1825 * the word. 1826 */ 1827 1828 ETHER_FIRST_MULTI(step, ec, enm); 1829 while (enm != NULL) { 1830 if (ether_cmp(enm->enm_addrlo, enm->enm_addrhi)) { 1831 /* 1832 * We must listen to a range of multicast addresses. 1833 * For now, just accept all multicasts, rather than 1834 * trying to set only those filter bits needed to match 1835 * the range. (At this time, the only use of address 1836 * ranges is for IP multicast routing, for which the 1837 * range is big enough to require all bits set.) 1838 */ 1839 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1840 ifp->if_flags |= IFF_ALLMULTI; 1841 goto chipit; 1842 } 1843 1844 cp = enm->enm_addrlo; 1845 crc = 0xffffffff; 1846 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1847 int octet = *cp++; 1848 int i; 1849 1850 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1851 for (i = 0; i < 8; i++) { 1852 if ((crc & 1) ^ (octet & 1)) { 1853 crc >>= 1; 1854 crc ^= MC_POLY_LE; 1855 } else { 1856 crc >>= 1; 1857 } 1858 octet >>= 1; 1859 } 1860 } 1861 /* Just want the 8 most significant bits. */ 1862 crc >>= 24; 1863 1864 /* Set the corresponding bit in the filter. */ 1865 hash[crc >> 4] |= 1 << (crc & 0xf); 1866 1867 ETHER_NEXT_MULTI(step, enm); 1868 } 1869 1870 ifp->if_flags &= ~IFF_ALLMULTI; 1871 1872 chipit: 1873 /* Now load the hash table into the chip */ 1874 bus_space_write_4(t, h, GEM_MAC_HASH0, hash[0]); 1875 bus_space_write_4(t, h, GEM_MAC_HASH1, hash[1]); 1876 bus_space_write_4(t, h, GEM_MAC_HASH2, hash[2]); 1877 bus_space_write_4(t, h, GEM_MAC_HASH3, hash[3]); 1878 bus_space_write_4(t, h, GEM_MAC_HASH4, hash[4]); 1879 bus_space_write_4(t, h, GEM_MAC_HASH5, hash[5]); 1880 bus_space_write_4(t, h, GEM_MAC_HASH6, hash[6]); 1881 bus_space_write_4(t, h, GEM_MAC_HASH7, hash[7]); 1882 bus_space_write_4(t, h, GEM_MAC_HASH8, hash[8]); 1883 bus_space_write_4(t, h, GEM_MAC_HASH9, hash[9]); 1884 bus_space_write_4(t, h, GEM_MAC_HASH10, hash[10]); 1885 bus_space_write_4(t, h, GEM_MAC_HASH11, hash[11]); 1886 bus_space_write_4(t, h, GEM_MAC_HASH12, hash[12]); 1887 bus_space_write_4(t, h, GEM_MAC_HASH13, hash[13]); 1888 bus_space_write_4(t, h, GEM_MAC_HASH14, hash[14]); 1889 bus_space_write_4(t, h, GEM_MAC_HASH15, hash[15]); 1890 1891 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1892 } 1893 1894 #if notyet 1895 1896 /* 1897 * gem_power: 1898 * 1899 * Power management (suspend/resume) hook. 1900 */ 1901 void 1902 gem_power(why, arg) 1903 int why; 1904 void *arg; 1905 { 1906 struct gem_softc *sc = arg; 1907 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1908 int s; 1909 1910 s = splnet(); 1911 switch (why) { 1912 case PWR_SUSPEND: 1913 case PWR_STANDBY: 1914 gem_stop(ifp, 1); 1915 if (sc->sc_power != NULL) 1916 (*sc->sc_power)(sc, why); 1917 break; 1918 case PWR_RESUME: 1919 if (ifp->if_flags & IFF_UP) { 1920 if (sc->sc_power != NULL) 1921 (*sc->sc_power)(sc, why); 1922 gem_init(ifp); 1923 } 1924 break; 1925 case PWR_SOFTSUSPEND: 1926 case PWR_SOFTSTANDBY: 1927 case PWR_SOFTRESUME: 1928 break; 1929 } 1930 splx(s); 1931 } 1932 #endif 1933