1 /* $NetBSD: gem.c,v 1.12 2002/01/19 03:16:38 eeh Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.12 2002/01/19 03:16:38 eeh Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/syslog.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <machine/endian.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/bus.h> 67 #include <machine/intr.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/mii/mii_bitbang.h> 72 73 #include <dev/ic/gemreg.h> 74 #include <dev/ic/gemvar.h> 75 76 #define TRIES 10000 77 78 void gem_start __P((struct ifnet *)); 79 void gem_stop __P((struct ifnet *, int)); 80 int gem_ioctl __P((struct ifnet *, u_long, caddr_t)); 81 void gem_tick __P((void *)); 82 void gem_watchdog __P((struct ifnet *)); 83 void gem_shutdown __P((void *)); 84 int gem_init __P((struct ifnet *)); 85 void gem_init_regs(struct gem_softc *sc); 86 static int gem_ringsize(int sz); 87 int gem_meminit __P((struct gem_softc *)); 88 void gem_mifinit __P((struct gem_softc *)); 89 void gem_reset __P((struct gem_softc *)); 90 int gem_reset_rx(struct gem_softc *sc); 91 int gem_reset_tx(struct gem_softc *sc); 92 int gem_disable_rx(struct gem_softc *sc); 93 int gem_disable_tx(struct gem_softc *sc); 94 void gem_rxdrain(struct gem_softc *sc); 95 int gem_add_rxbuf(struct gem_softc *sc, int idx); 96 void gem_setladrf __P((struct gem_softc *)); 97 98 /* MII methods & callbacks */ 99 static int gem_mii_readreg __P((struct device *, int, int)); 100 static void gem_mii_writereg __P((struct device *, int, int, int)); 101 static void gem_mii_statchg __P((struct device *)); 102 103 int gem_mediachange __P((struct ifnet *)); 104 void gem_mediastatus __P((struct ifnet *, struct ifmediareq *)); 105 106 struct mbuf *gem_get __P((struct gem_softc *, int, int)); 107 int gem_put __P((struct gem_softc *, int, struct mbuf *)); 108 void gem_read __P((struct gem_softc *, int, int)); 109 int gem_eint __P((struct gem_softc *, u_int)); 110 int gem_rint __P((struct gem_softc *)); 111 int gem_tint __P((struct gem_softc *)); 112 void gem_power __P((int, void *)); 113 114 #ifdef GEM_DEBUG 115 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 116 printf x 117 #else 118 #define DPRINTF(sc, x) /* nothing */ 119 #endif 120 121 122 /* 123 * gem_attach: 124 * 125 * Attach a Gem interface to the system. 126 */ 127 void 128 gem_attach(sc, enaddr) 129 struct gem_softc *sc; 130 const uint8_t *enaddr; 131 { 132 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 133 struct mii_data *mii = &sc->sc_mii; 134 struct mii_softc *child; 135 int i, error; 136 137 /* Make sure the chip is stopped. */ 138 ifp->if_softc = sc; 139 gem_reset(sc); 140 141 /* 142 * Allocate the control data structures, and create and load the 143 * DMA map for it. 144 */ 145 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 146 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 147 1, &sc->sc_cdnseg, 0)) != 0) { 148 printf("%s: unable to allocate control data, error = %d\n", 149 sc->sc_dev.dv_xname, error); 150 goto fail_0; 151 } 152 153 /* XXX should map this in with correct endianness */ 154 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 155 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 156 BUS_DMA_COHERENT)) != 0) { 157 printf("%s: unable to map control data, error = %d\n", 158 sc->sc_dev.dv_xname, error); 159 goto fail_1; 160 } 161 162 if ((error = bus_dmamap_create(sc->sc_dmatag, 163 sizeof(struct gem_control_data), 1, 164 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 165 printf("%s: unable to create control data DMA map, " 166 "error = %d\n", sc->sc_dev.dv_xname, error); 167 goto fail_2; 168 } 169 170 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 171 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 172 0)) != 0) { 173 printf("%s: unable to load control data DMA map, error = %d\n", 174 sc->sc_dev.dv_xname, error); 175 goto fail_3; 176 } 177 178 /* 179 * Initialize the transmit job descriptors. 180 */ 181 SIMPLEQ_INIT(&sc->sc_txfreeq); 182 SIMPLEQ_INIT(&sc->sc_txdirtyq); 183 184 /* 185 * Create the transmit buffer DMA maps. 186 */ 187 for (i = 0; i < GEM_TXQUEUELEN; i++) { 188 struct gem_txsoft *txs; 189 190 txs = &sc->sc_txsoft[i]; 191 txs->txs_mbuf = NULL; 192 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 193 GEM_NTXSEGS, MCLBYTES, 0, 0, 194 &txs->txs_dmamap)) != 0) { 195 printf("%s: unable to create tx DMA map %d, " 196 "error = %d\n", sc->sc_dev.dv_xname, i, error); 197 goto fail_4; 198 } 199 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 200 } 201 202 /* 203 * Create the receive buffer DMA maps. 204 */ 205 for (i = 0; i < GEM_NRXDESC; i++) { 206 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 207 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 208 printf("%s: unable to create rx DMA map %d, " 209 "error = %d\n", sc->sc_dev.dv_xname, i, error); 210 goto fail_5; 211 } 212 sc->sc_rxsoft[i].rxs_mbuf = NULL; 213 } 214 215 /* 216 * From this point forward, the attachment cannot fail. A failure 217 * before this point releases all resources that may have been 218 * allocated. 219 */ 220 221 /* Announce ourselves. */ 222 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 223 ether_sprintf(enaddr)); 224 225 /* Initialize ifnet structure. */ 226 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 227 ifp->if_softc = sc; 228 ifp->if_flags = 229 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 230 ifp->if_start = gem_start; 231 ifp->if_ioctl = gem_ioctl; 232 ifp->if_watchdog = gem_watchdog; 233 ifp->if_stop = gem_stop; 234 ifp->if_init = gem_init; 235 IFQ_SET_READY(&ifp->if_snd); 236 237 /* Initialize ifmedia structures and MII info */ 238 mii->mii_ifp = ifp; 239 mii->mii_readreg = gem_mii_readreg; 240 mii->mii_writereg = gem_mii_writereg; 241 mii->mii_statchg = gem_mii_statchg; 242 243 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus); 244 245 gem_mifinit(sc); 246 247 mii_attach(&sc->sc_dev, mii, 0xffffffff, 248 MII_PHY_ANY, MII_OFFSET_ANY, 0); 249 250 child = LIST_FIRST(&mii->mii_phys); 251 if (child == NULL) { 252 /* No PHY attached */ 253 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 254 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 255 } else { 256 /* 257 * Walk along the list of attached MII devices and 258 * establish an `MII instance' to `phy number' 259 * mapping. We'll use this mapping in media change 260 * requests to determine which phy to use to program 261 * the MIF configuration register. 262 */ 263 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 264 /* 265 * Note: we support just two PHYs: the built-in 266 * internal device and an external on the MII 267 * connector. 268 */ 269 if (child->mii_phy > 1 || child->mii_inst > 1) { 270 printf("%s: cannot accomodate MII device %s" 271 " at phy %d, instance %d\n", 272 sc->sc_dev.dv_xname, 273 child->mii_dev.dv_xname, 274 child->mii_phy, child->mii_inst); 275 continue; 276 } 277 278 sc->sc_phys[child->mii_inst] = child->mii_phy; 279 } 280 281 /* 282 * Now select and activate the PHY we will use. 283 * 284 * The order of preference is External (MDI1), 285 * Internal (MDI0), Serial Link (no MII). 286 */ 287 if (sc->sc_phys[1]) { 288 #ifdef DEBUG 289 printf("using external phy\n"); 290 #endif 291 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 292 } else { 293 #ifdef DEBUG 294 printf("using internal phy\n"); 295 #endif 296 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 297 } 298 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 299 sc->sc_mif_config); 300 301 /* 302 * XXX - we can really do the following ONLY if the 303 * phy indeed has the auto negotiation capability!! 304 */ 305 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 306 } 307 308 /* claim 802.1q capability */ 309 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 310 311 /* Attach the interface. */ 312 if_attach(ifp); 313 ether_ifattach(ifp, enaddr); 314 315 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 316 if (sc->sc_sh == NULL) 317 panic("gem_config: can't establish shutdownhook"); 318 319 #if NRND > 0 320 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 321 RND_TYPE_NET, 0); 322 #endif 323 324 325 #if notyet 326 /* 327 * Add a suspend hook to make sure we come back up after a 328 * resume. 329 */ 330 sc->sc_powerhook = powerhook_establish(gem_power, sc); 331 if (sc->sc_powerhook == NULL) 332 printf("%s: WARNING: unable to establish power hook\n", 333 sc->sc_dev.dv_xname); 334 #endif 335 336 callout_init(&sc->sc_tick_ch); 337 return; 338 339 /* 340 * Free any resources we've allocated during the failed attach 341 * attempt. Do this in reverse order and fall through. 342 */ 343 fail_5: 344 for (i = 0; i < GEM_NRXDESC; i++) { 345 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 346 bus_dmamap_destroy(sc->sc_dmatag, 347 sc->sc_rxsoft[i].rxs_dmamap); 348 } 349 fail_4: 350 for (i = 0; i < GEM_TXQUEUELEN; i++) { 351 if (sc->sc_txsoft[i].txs_dmamap != NULL) 352 bus_dmamap_destroy(sc->sc_dmatag, 353 sc->sc_txsoft[i].txs_dmamap); 354 } 355 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 356 fail_3: 357 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 358 fail_2: 359 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 360 sizeof(struct gem_control_data)); 361 fail_1: 362 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 363 fail_0: 364 return; 365 } 366 367 368 void 369 gem_tick(arg) 370 void *arg; 371 { 372 struct gem_softc *sc = arg; 373 int s; 374 375 s = splnet(); 376 mii_tick(&sc->sc_mii); 377 splx(s); 378 379 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 380 381 } 382 383 void 384 gem_reset(sc) 385 struct gem_softc *sc; 386 { 387 bus_space_tag_t t = sc->sc_bustag; 388 bus_space_handle_t h = sc->sc_h; 389 int i; 390 int s; 391 392 s = splnet(); 393 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 394 gem_reset_rx(sc); 395 gem_reset_tx(sc); 396 397 /* Do a full reset */ 398 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 399 for (i=TRIES; i--; delay(100)) 400 if ((bus_space_read_4(t, h, GEM_RESET) & 401 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 402 break; 403 if ((bus_space_read_4(t, h, GEM_RESET) & 404 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 405 printf("%s: cannot reset device\n", 406 sc->sc_dev.dv_xname); 407 } 408 splx(s); 409 } 410 411 412 /* 413 * gem_rxdrain: 414 * 415 * Drain the receive queue. 416 */ 417 void 418 gem_rxdrain(struct gem_softc *sc) 419 { 420 struct gem_rxsoft *rxs; 421 int i; 422 423 for (i = 0; i < GEM_NRXDESC; i++) { 424 rxs = &sc->sc_rxsoft[i]; 425 if (rxs->rxs_mbuf != NULL) { 426 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 427 m_freem(rxs->rxs_mbuf); 428 rxs->rxs_mbuf = NULL; 429 } 430 } 431 } 432 433 /* 434 * Reset the whole thing. 435 */ 436 void 437 gem_stop(struct ifnet *ifp, int disable) 438 { 439 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 440 struct gem_txsoft *txs; 441 442 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 443 444 callout_stop(&sc->sc_tick_ch); 445 mii_down(&sc->sc_mii); 446 447 /* XXX - Should we reset these instead? */ 448 gem_disable_rx(sc); 449 gem_disable_rx(sc); 450 451 /* 452 * Release any queued transmit buffers. 453 */ 454 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 455 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 456 if (txs->txs_mbuf != NULL) { 457 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 458 m_freem(txs->txs_mbuf); 459 txs->txs_mbuf = NULL; 460 } 461 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 462 } 463 464 if (disable) { 465 gem_rxdrain(sc); 466 } 467 468 /* 469 * Mark the interface down and cancel the watchdog timer. 470 */ 471 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 472 ifp->if_timer = 0; 473 } 474 475 476 /* 477 * Reset the receiver 478 */ 479 int 480 gem_reset_rx(struct gem_softc *sc) 481 { 482 bus_space_tag_t t = sc->sc_bustag; 483 bus_space_handle_t h = sc->sc_h; 484 int i; 485 486 487 /* 488 * Resetting while DMA is in progress can cause a bus hang, so we 489 * disable DMA first. 490 */ 491 gem_disable_rx(sc); 492 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 493 /* Wait till it finishes */ 494 for (i=TRIES; i--; delay(100)) 495 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 496 break; 497 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 498 printf("%s: cannot disable read dma\n", 499 sc->sc_dev.dv_xname); 500 501 /* Wait 5ms extra. */ 502 delay(5000); 503 504 /* Finally, reset the ERX */ 505 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 506 /* Wait till it finishes */ 507 for (i=TRIES; i--; delay(100)) 508 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 509 break; 510 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 511 printf("%s: cannot reset receiver\n", 512 sc->sc_dev.dv_xname); 513 return (1); 514 } 515 return (0); 516 } 517 518 519 /* 520 * Reset the transmitter 521 */ 522 int 523 gem_reset_tx(struct gem_softc *sc) 524 { 525 bus_space_tag_t t = sc->sc_bustag; 526 bus_space_handle_t h = sc->sc_h; 527 int i; 528 529 /* 530 * Resetting while DMA is in progress can cause a bus hang, so we 531 * disable DMA first. 532 */ 533 gem_disable_tx(sc); 534 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 535 /* Wait till it finishes */ 536 for (i=TRIES; i--; delay(100)) 537 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 538 break; 539 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 540 printf("%s: cannot disable read dma\n", 541 sc->sc_dev.dv_xname); 542 543 /* Wait 5ms extra. */ 544 delay(5000); 545 546 /* Finally, reset the ETX */ 547 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 548 /* Wait till it finishes */ 549 for (i=TRIES; i--; delay(100)) 550 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 551 break; 552 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 553 printf("%s: cannot reset receiver\n", 554 sc->sc_dev.dv_xname); 555 return (1); 556 } 557 return (0); 558 } 559 560 /* 561 * disable receiver. 562 */ 563 int 564 gem_disable_rx(struct gem_softc *sc) 565 { 566 bus_space_tag_t t = sc->sc_bustag; 567 bus_space_handle_t h = sc->sc_h; 568 int i; 569 u_int32_t cfg; 570 571 /* Flip the enable bit */ 572 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 573 cfg &= ~GEM_MAC_RX_ENABLE; 574 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 575 576 /* Wait for it to finish */ 577 for (i=TRIES; i--; delay(100)) 578 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 579 GEM_MAC_RX_ENABLE) == 0) 580 return (0); 581 return (1); 582 } 583 584 /* 585 * disable transmitter. 586 */ 587 int 588 gem_disable_tx(struct gem_softc *sc) 589 { 590 bus_space_tag_t t = sc->sc_bustag; 591 bus_space_handle_t h = sc->sc_h; 592 int i; 593 u_int32_t cfg; 594 595 /* Flip the enable bit */ 596 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 597 cfg &= ~GEM_MAC_TX_ENABLE; 598 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 599 600 /* Wait for it to finish */ 601 for (i=TRIES; i--; delay(100)) 602 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 603 GEM_MAC_TX_ENABLE) == 0) 604 return (0); 605 return (1); 606 } 607 608 /* 609 * Initialize interface. 610 */ 611 int 612 gem_meminit(struct gem_softc *sc) 613 { 614 struct gem_rxsoft *rxs; 615 int i, error; 616 617 /* 618 * Initialize the transmit descriptor ring. 619 */ 620 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 621 for (i = 0; i < GEM_NTXDESC; i++) { 622 sc->sc_txdescs[i].gd_flags = 0; 623 sc->sc_txdescs[i].gd_addr = 0; 624 } 625 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 626 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 627 sc->sc_txfree = GEM_NTXDESC; 628 sc->sc_txnext = 0; 629 630 /* 631 * Initialize the receive descriptor and receive job 632 * descriptor rings. 633 */ 634 for (i = 0; i < GEM_NRXDESC; i++) { 635 rxs = &sc->sc_rxsoft[i]; 636 if (rxs->rxs_mbuf == NULL) { 637 if ((error = gem_add_rxbuf(sc, i)) != 0) { 638 printf("%s: unable to allocate or map rx " 639 "buffer %d, error = %d\n", 640 sc->sc_dev.dv_xname, i, error); 641 /* 642 * XXX Should attempt to run with fewer receive 643 * XXX buffers instead of just failing. 644 */ 645 gem_rxdrain(sc); 646 return (1); 647 } 648 } else 649 GEM_INIT_RXDESC(sc, i); 650 } 651 sc->sc_rxptr = 0; 652 653 return (0); 654 } 655 656 static int 657 gem_ringsize(int sz) 658 { 659 int v; 660 661 switch (sz) { 662 case 32: 663 v = GEM_RING_SZ_32; 664 break; 665 case 64: 666 v = GEM_RING_SZ_64; 667 break; 668 case 128: 669 v = GEM_RING_SZ_128; 670 break; 671 case 256: 672 v = GEM_RING_SZ_256; 673 break; 674 case 512: 675 v = GEM_RING_SZ_512; 676 break; 677 case 1024: 678 v = GEM_RING_SZ_1024; 679 break; 680 case 2048: 681 v = GEM_RING_SZ_2048; 682 break; 683 case 4096: 684 v = GEM_RING_SZ_4096; 685 break; 686 case 8192: 687 v = GEM_RING_SZ_8192; 688 break; 689 default: 690 printf("gem: invalid Receive Descriptor ring size\n"); 691 break; 692 } 693 return (v); 694 } 695 696 /* 697 * Initialization of interface; set up initialization block 698 * and transmit/receive descriptor rings. 699 */ 700 int 701 gem_init(struct ifnet *ifp) 702 { 703 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 704 bus_space_tag_t t = sc->sc_bustag; 705 bus_space_handle_t h = sc->sc_h; 706 int s; 707 u_int32_t v; 708 709 s = splnet(); 710 711 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 712 /* 713 * Initialization sequence. The numbered steps below correspond 714 * to the sequence outlined in section 6.3.5.1 in the Ethernet 715 * Channel Engine manual (part of the PCIO manual). 716 * See also the STP2002-STQ document from Sun Microsystems. 717 */ 718 719 /* step 1 & 2. Reset the Ethernet Channel */ 720 gem_stop(ifp, 0); 721 gem_reset(sc); 722 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 723 724 /* Re-initialize the MIF */ 725 gem_mifinit(sc); 726 727 /* Call MI reset function if any */ 728 if (sc->sc_hwreset) 729 (*sc->sc_hwreset)(sc); 730 731 /* step 3. Setup data structures in host memory */ 732 gem_meminit(sc); 733 734 /* step 4. TX MAC registers & counters */ 735 gem_init_regs(sc); 736 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 737 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 738 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN + sizeof(struct ether_header): 739 ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16)); 740 741 /* step 5. RX MAC registers & counters */ 742 gem_setladrf(sc); 743 744 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 745 /* NOTE: we use only 32-bit DMA addresses here. */ 746 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 747 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 748 749 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 750 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 751 752 /* step 8. Global Configuration & Interrupt Mask */ 753 bus_space_write_4(t, h, GEM_INTMASK, 754 ~(GEM_INTR_TX_INTME| 755 GEM_INTR_TX_EMPTY| 756 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 757 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 758 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 759 GEM_INTR_BERR)); 760 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 0); /* XXXX */ 761 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 762 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 763 764 /* step 9. ETX Configuration: use mostly default values */ 765 766 /* Enable DMA */ 767 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 768 bus_space_write_4(t, h, GEM_TX_CONFIG, 769 v|GEM_TX_CONFIG_TXDMA_EN| 770 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 771 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 772 773 /* step 10. ERX Configuration */ 774 775 /* Encode Receive Descriptor ring size: four possible values */ 776 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 777 778 /* Enable DMA */ 779 bus_space_write_4(t, h, GEM_RX_CONFIG, 780 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 781 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 782 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 783 /* 784 * The following value is for an OFF Threshold of about 15.5 Kbytes 785 * and an ON Threshold of 4K bytes. 786 */ 787 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 0xf8 | (0x40 << 12)); 788 bus_space_write_4(t, h, GEM_RX_BLANKING, (2<<12)|6); 789 790 /* step 11. Configure Media */ 791 gem_mii_statchg(&sc->sc_dev); 792 793 /* XXXX Serial link needs a whole different setup. */ 794 795 796 /* step 12. RX_MAC Configuration Register */ 797 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 798 v |= GEM_MAC_RX_ENABLE; 799 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 800 801 /* step 14. Issue Transmit Pending command */ 802 803 /* Call MI initialization function if any */ 804 if (sc->sc_hwinit) 805 (*sc->sc_hwinit)(sc); 806 807 808 /* step 15. Give the reciever a swift kick */ 809 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 810 811 /* Start the one second timer. */ 812 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 813 814 ifp->if_flags |= IFF_RUNNING; 815 ifp->if_flags &= ~IFF_OACTIVE; 816 ifp->if_timer = 0; 817 splx(s); 818 819 return (0); 820 } 821 822 void 823 gem_init_regs(struct gem_softc *sc) 824 { 825 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 826 bus_space_tag_t t = sc->sc_bustag; 827 bus_space_handle_t h = sc->sc_h; 828 829 /* These regs are not cleared on reset */ 830 if (!sc->sc_inited) { 831 832 /* Wooo. Magic values. */ 833 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 834 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 835 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 836 837 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 838 /* Max frame and max burst size */ 839 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 840 (ifp->if_mtu+18) | (0x2000<<16)/* Burst size */); 841 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 842 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 843 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 844 /* Dunno.... */ 845 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 846 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 847 ((LLADDR(ifp->if_sadl)[5]<<8)| 848 LLADDR(ifp->if_sadl)[4])&0x3ff); 849 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 850 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 851 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 852 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 853 /* MAC control addr set to 0:1:c2:0:1:80 */ 854 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 855 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 856 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 857 858 /* MAC filter addr set to 0:0:0:0:0:0 */ 859 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 860 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 861 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 862 863 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 864 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 865 866 sc->sc_inited = 1; 867 } 868 869 /* Counters need to be zeroed */ 870 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 871 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 872 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 873 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 874 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 875 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 876 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 877 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 878 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 879 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 880 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 881 882 /* Un-pause stuff */ 883 #if 0 884 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 885 #else 886 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 887 #endif 888 889 /* 890 * Set the station address. 891 */ 892 bus_space_write_4(t, h, GEM_MAC_ADDR0, 893 (LLADDR(ifp->if_sadl)[4]<<8) | LLADDR(ifp->if_sadl)[5]); 894 bus_space_write_4(t, h, GEM_MAC_ADDR1, 895 (LLADDR(ifp->if_sadl)[2]<<8) | LLADDR(ifp->if_sadl)[3]); 896 bus_space_write_4(t, h, GEM_MAC_ADDR2, 897 (LLADDR(ifp->if_sadl)[0]<<8) | LLADDR(ifp->if_sadl)[1]); 898 899 } 900 901 902 903 void 904 gem_start(ifp) 905 struct ifnet *ifp; 906 { 907 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 908 struct mbuf *m0, *m; 909 struct gem_txsoft *txs, *last_txs; 910 bus_dmamap_t dmamap; 911 int error, firsttx, nexttx, lasttx, ofree, seg; 912 913 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 914 return; 915 916 /* 917 * Remember the previous number of free descriptors and 918 * the first descriptor we'll use. 919 */ 920 ofree = sc->sc_txfree; 921 firsttx = sc->sc_txnext; 922 923 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 924 sc->sc_dev.dv_xname, ofree, firsttx)); 925 926 /* 927 * Loop through the send queue, setting up transmit descriptors 928 * until we drain the queue, or use up all available transmit 929 * descriptors. 930 */ 931 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 932 sc->sc_txfree != 0) { 933 /* 934 * Grab a packet off the queue. 935 */ 936 IFQ_POLL(&ifp->if_snd, m0); 937 if (m0 == NULL) 938 break; 939 m = NULL; 940 941 dmamap = txs->txs_dmamap; 942 943 /* 944 * Load the DMA map. If this fails, the packet either 945 * didn't fit in the alloted number of segments, or we were 946 * short on resources. In this case, we'll copy and try 947 * again. 948 */ 949 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 950 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 951 MGETHDR(m, M_DONTWAIT, MT_DATA); 952 if (m == NULL) { 953 printf("%s: unable to allocate Tx mbuf\n", 954 sc->sc_dev.dv_xname); 955 break; 956 } 957 if (m0->m_pkthdr.len > MHLEN) { 958 MCLGET(m, M_DONTWAIT); 959 if ((m->m_flags & M_EXT) == 0) { 960 printf("%s: unable to allocate Tx " 961 "cluster\n", sc->sc_dev.dv_xname); 962 m_freem(m); 963 break; 964 } 965 } 966 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 967 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 968 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 969 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 970 if (error) { 971 printf("%s: unable to load Tx buffer, " 972 "error = %d\n", sc->sc_dev.dv_xname, error); 973 break; 974 } 975 } 976 977 /* 978 * Ensure we have enough descriptors free to describe 979 * the packet. 980 */ 981 if (dmamap->dm_nsegs > sc->sc_txfree) { 982 /* 983 * Not enough free descriptors to transmit this 984 * packet. We haven't committed to anything yet, 985 * so just unload the DMA map, put the packet 986 * back on the queue, and punt. Notify the upper 987 * layer that there are no more slots left. 988 * 989 * XXX We could allocate an mbuf and copy, but 990 * XXX it is worth it? 991 */ 992 ifp->if_flags |= IFF_OACTIVE; 993 bus_dmamap_unload(sc->sc_dmatag, dmamap); 994 if (m != NULL) 995 m_freem(m); 996 break; 997 } 998 999 IFQ_DEQUEUE(&ifp->if_snd, m0); 1000 if (m != NULL) { 1001 m_freem(m0); 1002 m0 = m; 1003 } 1004 1005 /* 1006 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1007 */ 1008 1009 /* Sync the DMA map. */ 1010 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1011 BUS_DMASYNC_PREWRITE); 1012 1013 /* 1014 * Initialize the transmit descriptors. 1015 */ 1016 for (nexttx = sc->sc_txnext, seg = 0; 1017 seg < dmamap->dm_nsegs; 1018 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1019 uint64_t flags; 1020 1021 /* 1022 * If this is the first descriptor we're 1023 * enqueueing, set the start of packet flag, 1024 * and the checksum stuff if we want the hardware 1025 * to do it. 1026 */ 1027 sc->sc_txdescs[nexttx].gd_addr = 1028 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1029 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1030 if (nexttx == firsttx) { 1031 flags |= GEM_TD_START_OF_PACKET; 1032 } 1033 if (seg == dmamap->dm_nsegs - 1) { 1034 flags |= GEM_TD_END_OF_PACKET; 1035 } 1036 sc->sc_txdescs[nexttx].gd_flags = 1037 GEM_DMA_WRITE(sc, flags); 1038 lasttx = nexttx; 1039 } 1040 1041 #ifdef GEM_DEBUG 1042 if (ifp->if_flags & IFF_DEBUG) { 1043 printf(" gem_start %p transmit chain:\n", txs); 1044 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1045 printf("descriptor %d:\t", seg); 1046 printf("gd_flags: 0x%016llx\t", (long long) 1047 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1048 printf("gd_addr: 0x%016llx\n", (long long) 1049 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1050 if (seg == lasttx) 1051 break; 1052 } 1053 } 1054 #endif 1055 1056 /* Sync the descriptors we're using. */ 1057 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1058 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1059 1060 /* 1061 * Store a pointer to the packet so we can free it later, 1062 * and remember what txdirty will be once the packet is 1063 * done. 1064 */ 1065 txs->txs_mbuf = m0; 1066 txs->txs_firstdesc = sc->sc_txnext; 1067 txs->txs_lastdesc = lasttx; 1068 txs->txs_ndescs = dmamap->dm_nsegs; 1069 1070 /* Advance the tx pointer. */ 1071 sc->sc_txfree -= dmamap->dm_nsegs; 1072 sc->sc_txnext = nexttx; 1073 1074 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1075 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1076 1077 last_txs = txs; 1078 1079 #if NBPFILTER > 0 1080 /* 1081 * Pass the packet to any BPF listeners. 1082 */ 1083 if (ifp->if_bpf) 1084 bpf_mtap(ifp->if_bpf, m0); 1085 #endif /* NBPFILTER > 0 */ 1086 } 1087 1088 if (txs == NULL || sc->sc_txfree == 0) { 1089 /* No more slots left; notify upper layer. */ 1090 ifp->if_flags |= IFF_OACTIVE; 1091 } 1092 1093 if (sc->sc_txfree != ofree) { 1094 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1095 sc->sc_dev.dv_xname, lasttx, firsttx)); 1096 /* 1097 * The entire packet chain is set up. 1098 * Kick the transmitter. 1099 */ 1100 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1101 sc->sc_dev.dv_xname, nexttx)); 1102 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1103 sc->sc_txnext); 1104 1105 /* Set a watchdog timer in case the chip flakes out. */ 1106 ifp->if_timer = 5; 1107 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1108 sc->sc_dev.dv_xname, ifp->if_timer)); 1109 } 1110 } 1111 1112 /* 1113 * Transmit interrupt. 1114 */ 1115 int 1116 gem_tint(sc) 1117 struct gem_softc *sc; 1118 { 1119 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1120 bus_space_tag_t t = sc->sc_bustag; 1121 bus_space_handle_t mac = sc->sc_h; 1122 struct gem_txsoft *txs; 1123 int txlast; 1124 1125 1126 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1127 1128 /* 1129 * Unload collision counters 1130 */ 1131 ifp->if_collisions += 1132 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1133 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1134 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1135 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1136 1137 /* 1138 * then clear the hardware counters. 1139 */ 1140 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1141 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1142 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1143 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1144 1145 /* 1146 * Go through our Tx list and free mbufs for those 1147 * frames that have been transmitted. 1148 */ 1149 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1150 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1151 txs->txs_ndescs, 1152 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1153 1154 #ifdef GEM_DEBUG 1155 if (ifp->if_flags & IFF_DEBUG) { 1156 int i; 1157 printf(" txsoft %p transmit chain:\n", txs); 1158 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1159 printf("descriptor %d: ", i); 1160 printf("gd_flags: 0x%016llx\t", (long long) 1161 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1162 printf("gd_addr: 0x%016llx\n", (long long) 1163 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1164 if (i == txs->txs_lastdesc) 1165 break; 1166 } 1167 } 1168 #endif 1169 1170 /* 1171 * In theory, we could harveast some descriptors before 1172 * the ring is empty, but that's a bit complicated. 1173 * 1174 * GEM_TX_COMPLETION points to the last descriptor 1175 * processed +1. 1176 */ 1177 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1178 DPRINTF(sc, 1179 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1180 txs->txs_lastdesc, txlast)); 1181 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1182 if ((txlast >= txs->txs_firstdesc) && 1183 (txlast <= txs->txs_lastdesc)) 1184 break; 1185 } else { 1186 /* Ick -- this command wraps */ 1187 if ((txlast >= txs->txs_firstdesc) || 1188 (txlast <= txs->txs_lastdesc)) 1189 break; 1190 } 1191 1192 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1193 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1194 1195 sc->sc_txfree += txs->txs_ndescs; 1196 1197 if (txs->txs_mbuf == NULL) { 1198 #ifdef DIAGNOSTIC 1199 panic("gem_txintr: null mbuf"); 1200 #endif 1201 } 1202 1203 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1204 0, txs->txs_dmamap->dm_mapsize, 1205 BUS_DMASYNC_POSTWRITE); 1206 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1207 m_freem(txs->txs_mbuf); 1208 txs->txs_mbuf = NULL; 1209 1210 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1211 1212 ifp->if_opackets++; 1213 } 1214 1215 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1216 "GEM_TX_DATA_PTR %llx " 1217 "GEM_TX_COMPLETION %x\n", 1218 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1219 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1220 GEM_TX_DATA_PTR_HI) << 32) | 1221 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1222 GEM_TX_DATA_PTR_LO), 1223 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1224 1225 gem_start(ifp); 1226 1227 if (SIMPLEQ_FIRST(&sc->sc_txdirtyq) == NULL) 1228 ifp->if_timer = 0; 1229 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1230 sc->sc_dev.dv_xname, ifp->if_timer)); 1231 1232 return (1); 1233 } 1234 1235 /* 1236 * Receive interrupt. 1237 */ 1238 int 1239 gem_rint(sc) 1240 struct gem_softc *sc; 1241 { 1242 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1243 bus_space_tag_t t = sc->sc_bustag; 1244 bus_space_handle_t h = sc->sc_h; 1245 struct ether_header *eh; 1246 struct gem_rxsoft *rxs; 1247 struct mbuf *m; 1248 u_int64_t rxstat; 1249 int i, len; 1250 1251 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1252 /* 1253 * XXXX Read the lastrx only once at the top for speed. 1254 */ 1255 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1256 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1257 for (i = sc->sc_rxptr; i != bus_space_read_4(t, h, GEM_RX_COMPLETION); 1258 i = GEM_NEXTRX(i)) { 1259 rxs = &sc->sc_rxsoft[i]; 1260 1261 GEM_CDRXSYNC(sc, i, 1262 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1263 1264 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1265 1266 if (rxstat & GEM_RD_OWN) { 1267 printf("gem_rint: completed descriptor " 1268 "still owned %d\n", i); 1269 /* 1270 * We have processed all of the receive buffers. 1271 */ 1272 break; 1273 } 1274 1275 if (rxstat & GEM_RD_BAD_CRC) { 1276 printf("%s: receive error: CRC error\n", 1277 sc->sc_dev.dv_xname); 1278 GEM_INIT_RXDESC(sc, i); 1279 continue; 1280 } 1281 1282 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1283 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1284 #ifdef GEM_DEBUG 1285 if (ifp->if_flags & IFF_DEBUG) { 1286 printf(" rxsoft %p descriptor %d: ", rxs, i); 1287 printf("gd_flags: 0x%016llx\t", (long long) 1288 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1289 printf("gd_addr: 0x%016llx\n", (long long) 1290 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1291 } 1292 #endif 1293 1294 /* 1295 * No errors; receive the packet. Note the Gem 1296 * includes the CRC with every packet. 1297 */ 1298 len = GEM_RD_BUFLEN(rxstat); 1299 1300 /* 1301 * Allocate a new mbuf cluster. If that fails, we are 1302 * out of memory, and must drop the packet and recycle 1303 * the buffer that's already attached to this descriptor. 1304 */ 1305 m = rxs->rxs_mbuf; 1306 if (gem_add_rxbuf(sc, i) != 0) { 1307 ifp->if_ierrors++; 1308 GEM_INIT_RXDESC(sc, i); 1309 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1310 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1311 continue; 1312 } 1313 m->m_data += 2; /* We're already off by two */ 1314 1315 ifp->if_ipackets++; 1316 eh = mtod(m, struct ether_header *); 1317 m->m_flags |= M_HASFCS; 1318 m->m_pkthdr.rcvif = ifp; 1319 m->m_pkthdr.len = m->m_len = len; 1320 1321 #if NBPFILTER > 0 1322 /* 1323 * Pass this up to any BPF listeners, but only 1324 * pass it up the stack if its for us. 1325 */ 1326 if (ifp->if_bpf) 1327 bpf_mtap(ifp->if_bpf, m); 1328 #endif /* NPBFILTER > 0 */ 1329 1330 /* Pass it on. */ 1331 (*ifp->if_input)(ifp, m); 1332 } 1333 1334 /* Update the receive pointer. */ 1335 sc->sc_rxptr = i; 1336 bus_space_write_4(t, h, GEM_RX_KICK, i); 1337 1338 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1339 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1340 1341 return (1); 1342 } 1343 1344 1345 /* 1346 * gem_add_rxbuf: 1347 * 1348 * Add a receive buffer to the indicated descriptor. 1349 */ 1350 int 1351 gem_add_rxbuf(struct gem_softc *sc, int idx) 1352 { 1353 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1354 struct mbuf *m; 1355 int error; 1356 1357 MGETHDR(m, M_DONTWAIT, MT_DATA); 1358 if (m == NULL) 1359 return (ENOBUFS); 1360 1361 MCLGET(m, M_DONTWAIT); 1362 if ((m->m_flags & M_EXT) == 0) { 1363 m_freem(m); 1364 return (ENOBUFS); 1365 } 1366 1367 #ifdef GEM_DEBUG 1368 /* bzero the packet to check dma */ 1369 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1370 #endif 1371 1372 if (rxs->rxs_mbuf != NULL) 1373 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1374 1375 rxs->rxs_mbuf = m; 1376 1377 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1378 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1379 BUS_DMA_READ|BUS_DMA_NOWAIT); 1380 if (error) { 1381 printf("%s: can't load rx DMA map %d, error = %d\n", 1382 sc->sc_dev.dv_xname, idx, error); 1383 panic("gem_add_rxbuf"); /* XXX */ 1384 } 1385 1386 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1387 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1388 1389 GEM_INIT_RXDESC(sc, idx); 1390 1391 return (0); 1392 } 1393 1394 1395 int 1396 gem_eint(sc, status) 1397 struct gem_softc *sc; 1398 u_int status; 1399 { 1400 char bits[128]; 1401 1402 if ((status & GEM_INTR_MIF) != 0) { 1403 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1404 return (1); 1405 } 1406 1407 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1408 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1409 return (1); 1410 } 1411 1412 1413 int 1414 gem_intr(v) 1415 void *v; 1416 { 1417 struct gem_softc *sc = (struct gem_softc *)v; 1418 bus_space_tag_t t = sc->sc_bustag; 1419 bus_space_handle_t seb = sc->sc_h; 1420 u_int32_t status; 1421 int r = 0; 1422 #ifdef GEM_DEBUG 1423 char bits[128]; 1424 #endif 1425 1426 status = bus_space_read_4(t, seb, GEM_STATUS); 1427 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %s\n", 1428 sc->sc_dev.dv_xname, (status>>19), 1429 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1430 1431 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1432 r |= gem_eint(sc, status); 1433 1434 if ((status & 1435 (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) 1436 != 0) 1437 r |= gem_tint(sc); 1438 1439 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1440 r |= gem_rint(sc); 1441 1442 /* We should eventually do more than just print out error stats. */ 1443 if (status & GEM_INTR_TX_MAC) { 1444 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1445 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1446 printf("MAC tx fault, status %x\n", txstat); 1447 } 1448 if (status & GEM_INTR_RX_MAC) { 1449 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1450 if (rxstat & ~GEM_MAC_RX_DONE) 1451 printf("MAC rx fault, status %x\n", rxstat); 1452 } 1453 return (r); 1454 } 1455 1456 1457 void 1458 gem_watchdog(ifp) 1459 struct ifnet *ifp; 1460 { 1461 struct gem_softc *sc = ifp->if_softc; 1462 1463 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1464 "GEM_MAC_RX_CONFIG %x\n", 1465 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1466 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1467 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1468 1469 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1470 ++ifp->if_oerrors; 1471 1472 /* Try to get more packets going. */ 1473 gem_start(ifp); 1474 } 1475 1476 /* 1477 * Initialize the MII Management Interface 1478 */ 1479 void 1480 gem_mifinit(sc) 1481 struct gem_softc *sc; 1482 { 1483 bus_space_tag_t t = sc->sc_bustag; 1484 bus_space_handle_t mif = sc->sc_h; 1485 1486 /* Configure the MIF in frame mode */ 1487 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1488 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1489 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1490 } 1491 1492 /* 1493 * MII interface 1494 * 1495 * The GEM MII interface supports at least three different operating modes: 1496 * 1497 * Bitbang mode is implemented using data, clock and output enable registers. 1498 * 1499 * Frame mode is implemented by loading a complete frame into the frame 1500 * register and polling the valid bit for completion. 1501 * 1502 * Polling mode uses the frame register but completion is indicated by 1503 * an interrupt. 1504 * 1505 */ 1506 static int 1507 gem_mii_readreg(self, phy, reg) 1508 struct device *self; 1509 int phy, reg; 1510 { 1511 struct gem_softc *sc = (void *)self; 1512 bus_space_tag_t t = sc->sc_bustag; 1513 bus_space_handle_t mif = sc->sc_h; 1514 int n; 1515 u_int32_t v; 1516 1517 #ifdef GEM_DEBUG1 1518 if (sc->sc_debug) 1519 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1520 #endif 1521 1522 #if 0 1523 /* Select the desired PHY in the MIF configuration register */ 1524 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1525 /* Clear PHY select bit */ 1526 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1527 if (phy == GEM_PHYAD_EXTERNAL) 1528 /* Set PHY select bit to get at external device */ 1529 v |= GEM_MIF_CONFIG_PHY_SEL; 1530 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1531 #endif 1532 1533 /* Construct the frame command */ 1534 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1535 GEM_MIF_FRAME_READ; 1536 1537 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1538 for (n = 0; n < 100; n++) { 1539 DELAY(1); 1540 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1541 if (v & GEM_MIF_FRAME_TA0) 1542 return (v & GEM_MIF_FRAME_DATA); 1543 } 1544 1545 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1546 return (0); 1547 } 1548 1549 static void 1550 gem_mii_writereg(self, phy, reg, val) 1551 struct device *self; 1552 int phy, reg, val; 1553 { 1554 struct gem_softc *sc = (void *)self; 1555 bus_space_tag_t t = sc->sc_bustag; 1556 bus_space_handle_t mif = sc->sc_h; 1557 int n; 1558 u_int32_t v; 1559 1560 #ifdef GEM_DEBUG1 1561 if (sc->sc_debug) 1562 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1563 phy, reg, val); 1564 #endif 1565 1566 #if 0 1567 /* Select the desired PHY in the MIF configuration register */ 1568 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1569 /* Clear PHY select bit */ 1570 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1571 if (phy == GEM_PHYAD_EXTERNAL) 1572 /* Set PHY select bit to get at external device */ 1573 v |= GEM_MIF_CONFIG_PHY_SEL; 1574 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1575 #endif 1576 /* Construct the frame command */ 1577 v = GEM_MIF_FRAME_WRITE | 1578 (phy << GEM_MIF_PHY_SHIFT) | 1579 (reg << GEM_MIF_REG_SHIFT) | 1580 (val & GEM_MIF_FRAME_DATA); 1581 1582 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1583 for (n = 0; n < 100; n++) { 1584 DELAY(1); 1585 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1586 if (v & GEM_MIF_FRAME_TA0) 1587 return; 1588 } 1589 1590 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1591 } 1592 1593 static void 1594 gem_mii_statchg(dev) 1595 struct device *dev; 1596 { 1597 struct gem_softc *sc = (void *)dev; 1598 #ifdef GEM_DEBUG 1599 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1600 #endif 1601 bus_space_tag_t t = sc->sc_bustag; 1602 bus_space_handle_t mac = sc->sc_h; 1603 u_int32_t v; 1604 1605 #ifdef GEM_DEBUG 1606 if (sc->sc_debug) 1607 printf("gem_mii_statchg: status change: phy = %d\n", 1608 sc->sc_phys[instance];); 1609 #endif 1610 1611 1612 /* Set tx full duplex options */ 1613 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1614 delay(10000); /* reg must be cleared and delay before changing. */ 1615 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1616 GEM_MAC_TX_ENABLE; 1617 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1618 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1619 } 1620 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1621 1622 /* XIF Configuration */ 1623 /* We should really calculate all this rather than rely on defaults */ 1624 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1625 v = GEM_MAC_XIF_LINK_LED; 1626 v |= GEM_MAC_XIF_TX_MII_ENA; 1627 /* If an external transceiver is connected, enable its MII drivers */ 1628 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1629 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1630 /* External MII needs echo disable if half duplex. */ 1631 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1632 /* turn on full duplex LED */ 1633 v |= GEM_MAC_XIF_FDPLX_LED; 1634 else 1635 /* half duplex -- disable echo */ 1636 v |= GEM_MAC_XIF_ECHO_DISABL; 1637 } else 1638 /* Internal MII needs buf enable */ 1639 v |= GEM_MAC_XIF_MII_BUF_ENA; 1640 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1641 } 1642 1643 int 1644 gem_mediachange(ifp) 1645 struct ifnet *ifp; 1646 { 1647 struct gem_softc *sc = ifp->if_softc; 1648 1649 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1650 return (EINVAL); 1651 1652 return (mii_mediachg(&sc->sc_mii)); 1653 } 1654 1655 void 1656 gem_mediastatus(ifp, ifmr) 1657 struct ifnet *ifp; 1658 struct ifmediareq *ifmr; 1659 { 1660 struct gem_softc *sc = ifp->if_softc; 1661 1662 if ((ifp->if_flags & IFF_UP) == 0) 1663 return; 1664 1665 mii_pollstat(&sc->sc_mii); 1666 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1667 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1668 } 1669 1670 int gem_ioctldebug = 0; 1671 /* 1672 * Process an ioctl request. 1673 */ 1674 int 1675 gem_ioctl(ifp, cmd, data) 1676 struct ifnet *ifp; 1677 u_long cmd; 1678 caddr_t data; 1679 { 1680 struct gem_softc *sc = ifp->if_softc; 1681 struct ifreq *ifr = (struct ifreq *)data; 1682 int s, error = 0; 1683 1684 1685 switch (cmd) { 1686 case SIOCGIFMEDIA: 1687 case SIOCSIFMEDIA: 1688 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1689 break; 1690 1691 default: 1692 error = ether_ioctl(ifp, cmd, data); 1693 if (error == ENETRESET) { 1694 /* 1695 * Multicast list has changed; set the hardware filter 1696 * accordingly. 1697 */ 1698 if (gem_ioctldebug) printf("reset1\n"); 1699 gem_init(ifp); 1700 delay(50000); 1701 error = 0; 1702 } 1703 break; 1704 } 1705 1706 /* Try to get things going again */ 1707 if (ifp->if_flags & IFF_UP) { 1708 if (gem_ioctldebug) printf("start\n"); 1709 gem_start(ifp); 1710 } 1711 splx(s); 1712 return (error); 1713 } 1714 1715 1716 void 1717 gem_shutdown(arg) 1718 void *arg; 1719 { 1720 struct gem_softc *sc = (struct gem_softc *)arg; 1721 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1722 1723 gem_stop(ifp, 1); 1724 } 1725 1726 /* 1727 * Set up the logical address filter. 1728 */ 1729 void 1730 gem_setladrf(sc) 1731 struct gem_softc *sc; 1732 { 1733 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1734 struct ether_multi *enm; 1735 struct ether_multistep step; 1736 struct ethercom *ec = &sc->sc_ethercom; 1737 bus_space_tag_t t = sc->sc_bustag; 1738 bus_space_handle_t h = sc->sc_h; 1739 u_char *cp; 1740 u_int32_t crc; 1741 u_int32_t hash[16]; 1742 u_int32_t v; 1743 int len; 1744 1745 /* Clear hash table */ 1746 memset(hash, 0, sizeof(hash)); 1747 1748 /* Get current RX configuration */ 1749 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1750 1751 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1752 /* Turn on promiscuous mode; turn off the hash filter */ 1753 v |= GEM_MAC_RX_PROMISCUOUS; 1754 v &= ~GEM_MAC_RX_HASH_FILTER; 1755 ifp->if_flags |= IFF_ALLMULTI; 1756 goto chipit; 1757 } 1758 1759 /* Turn off promiscuous mode; turn on the hash filter */ 1760 v &= ~GEM_MAC_RX_PROMISCUOUS; 1761 v |= GEM_MAC_RX_HASH_FILTER; 1762 1763 /* 1764 * Set up multicast address filter by passing all multicast addresses 1765 * through a crc generator, and then using the high order 6 bits as an 1766 * index into the 256 bit logical address filter. The high order bit 1767 * selects the word, while the rest of the bits select the bit within 1768 * the word. 1769 */ 1770 1771 ETHER_FIRST_MULTI(step, ec, enm); 1772 while (enm != NULL) { 1773 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1774 /* 1775 * We must listen to a range of multicast addresses. 1776 * For now, just accept all multicasts, rather than 1777 * trying to set only those filter bits needed to match 1778 * the range. (At this time, the only use of address 1779 * ranges is for IP multicast routing, for which the 1780 * range is big enough to require all bits set.) 1781 */ 1782 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1783 ifp->if_flags |= IFF_ALLMULTI; 1784 goto chipit; 1785 } 1786 1787 cp = enm->enm_addrlo; 1788 crc = 0xffffffff; 1789 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1790 int octet = *cp++; 1791 int i; 1792 1793 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1794 for (i = 0; i < 8; i++) { 1795 if ((crc & 1) ^ (octet & 1)) { 1796 crc >>= 1; 1797 crc ^= MC_POLY_LE; 1798 } else { 1799 crc >>= 1; 1800 } 1801 octet >>= 1; 1802 } 1803 } 1804 /* Just want the 8 most significant bits. */ 1805 crc >>= 24; 1806 1807 /* Set the corresponding bit in the filter. */ 1808 hash[crc >> 4] |= 1 << (crc & 0xf); 1809 1810 ETHER_NEXT_MULTI(step, enm); 1811 } 1812 1813 ifp->if_flags &= ~IFF_ALLMULTI; 1814 1815 chipit: 1816 /* Now load the hash table into the chip */ 1817 bus_space_write_4(t, h, GEM_MAC_HASH0, hash[0]); 1818 bus_space_write_4(t, h, GEM_MAC_HASH1, hash[1]); 1819 bus_space_write_4(t, h, GEM_MAC_HASH2, hash[2]); 1820 bus_space_write_4(t, h, GEM_MAC_HASH3, hash[3]); 1821 bus_space_write_4(t, h, GEM_MAC_HASH4, hash[4]); 1822 bus_space_write_4(t, h, GEM_MAC_HASH5, hash[5]); 1823 bus_space_write_4(t, h, GEM_MAC_HASH6, hash[6]); 1824 bus_space_write_4(t, h, GEM_MAC_HASH7, hash[7]); 1825 bus_space_write_4(t, h, GEM_MAC_HASH8, hash[8]); 1826 bus_space_write_4(t, h, GEM_MAC_HASH9, hash[9]); 1827 bus_space_write_4(t, h, GEM_MAC_HASH10, hash[10]); 1828 bus_space_write_4(t, h, GEM_MAC_HASH11, hash[11]); 1829 bus_space_write_4(t, h, GEM_MAC_HASH12, hash[12]); 1830 bus_space_write_4(t, h, GEM_MAC_HASH13, hash[13]); 1831 bus_space_write_4(t, h, GEM_MAC_HASH14, hash[14]); 1832 bus_space_write_4(t, h, GEM_MAC_HASH15, hash[15]); 1833 1834 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1835 } 1836 1837 #if notyet 1838 1839 /* 1840 * gem_power: 1841 * 1842 * Power management (suspend/resume) hook. 1843 */ 1844 void 1845 gem_power(why, arg) 1846 int why; 1847 void *arg; 1848 { 1849 struct gem_softc *sc = arg; 1850 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1851 int s; 1852 1853 s = splnet(); 1854 switch (why) { 1855 case PWR_SUSPEND: 1856 case PWR_STANDBY: 1857 gem_stop(ifp, 1); 1858 if (sc->sc_power != NULL) 1859 (*sc->sc_power)(sc, why); 1860 break; 1861 case PWR_RESUME: 1862 if (ifp->if_flags & IFF_UP) { 1863 if (sc->sc_power != NULL) 1864 (*sc->sc_power)(sc, why); 1865 gem_init(ifp); 1866 } 1867 break; 1868 case PWR_SOFTSUSPEND: 1869 case PWR_SOFTSTANDBY: 1870 case PWR_SOFTRESUME: 1871 break; 1872 } 1873 splx(s); 1874 } 1875 #endif 1876