1 /* $NetBSD: gcscpcib.c,v 1.1 2011/08/27 12:47:49 bouyer Exp $ */ 2 /* $OpenBSD: gcscpcib.c,v 1.6 2007/11/17 17:02:47 mbalmer Exp $ */ 3 4 /* 5 * Copyright (c) 2008 Yojiro UO <yuo@nui.org> 6 * Copyright (c) 2007 Marc Balmer <mbalmer@openbsd.org> 7 * Copyright (c) 2007 Michael Shalayeff 8 * All rights reserved. 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN 19 * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 20 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23 /* 24 * AMD CS5535/CS5536 series LPC bridge also containing timer, watchdog and GPIO. 25 */ 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: gcscpcib.c,v 1.1 2011/08/27 12:47:49 bouyer Exp $"); 28 29 #include "gpio.h" 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/device.h> 34 #include <sys/gpio.h> 35 #include <sys/sysctl.h> 36 #include <sys/timetc.h> 37 #include <sys/wdog.h> 38 39 #include <sys/bus.h> 40 41 #include <dev/gpio/gpiovar.h> 42 43 #include <dev/sysmon/sysmonvar.h> 44 45 #include <dev/ic/gcscpcibreg.h> 46 #include <dev/ic/gcscpcibvar.h> 47 48 /* define if you need to select MFGPT for watchdog manually (0-5). */ 49 /* #define AMD553X_WDT_FORCEUSEMFGPT 0 */ 50 /* select precision of watchdog timer (default value = 0.25sec (4Hz tick) */ 51 #define AMD553X_MFGPT_PRESCALE AMD553X_MFGPT_DIV_8K /* 32K/8K = 4Hz */ 52 53 /* #define GCSCPCIB_DEBUG */ 54 #ifdef GCSCPCIB_DEBUG 55 #define DPRINTF(x) printf x 56 #else 57 #define DPRINTF(x) 58 #endif 59 60 /* 1 bit replace (not support multiple bit)*/ 61 #define AMD553X_MFGPTx_NR_DISABLE(x, bit) \ 62 ( gcsc_wrmsr(AMD553X_MFGPT_NR, gcsc_rdmsr(AMD553X_MFGPT_NR) & ~((bit) << (x))) ) 63 #define AMD553X_MFGPTx_NR_ENABLE(x, bit) \ 64 ( gcsc_wrmsr(AMD553X_MFGPT_NR, gcsc_rdmsr(AMD553X_MFGPT_NR) | ((bit) << (x))) ) 65 66 /* caliculate watchdog timer setting */ 67 #define AMD553X_WDT_TICK (1<<(AMD553X_MFGPT_DIV_32K - AMD553X_MFGPT_PRESCALE)) 68 #define AMD553X_WDT_COUNTMAX (0xffff / AMD553X_WDT_TICK) 69 70 static u_int gcscpcib_get_timecount(struct timecounter *tc); 71 static int gscspcib_scan_mfgpt(struct gcscpcib_softc *sc); 72 static void gscspcib_wdog_update(struct gcscpcib_softc *, uint16_t); 73 static int gcscpcib_wdog_setmode(struct sysmon_wdog *smw); 74 static int gcscpcib_wdog_tickle(struct sysmon_wdog *smw); 75 static void gcscpcib_wdog_enable(struct gcscpcib_softc *sc); 76 static void gcscpcib_wdog_disable(struct gcscpcib_softc *sc); 77 static void gcscpcib_wdog_reset(struct gcscpcib_softc *sc); 78 79 #if NGPIO > 0 80 static int gcscpcib_gpio_pin_read(void *, int); 81 static void gcscpcib_gpio_pin_write(void *, int, int); 82 static void gcscpcib_gpio_pin_ctl(void *, int, int); 83 #endif 84 85 void 86 gcscpcib_attach(device_t self, struct gcscpcib_softc *sc, 87 bus_space_tag_t iot) 88 { 89 struct timecounter *tc = &sc->sc_timecounter; 90 bus_addr_t wdtbase; 91 int wdt = 0; 92 #if NGPIO > 0 93 struct gpiobus_attach_args gba; 94 bus_addr_t gpiobase; 95 int i, gpio; 96 #endif 97 98 sc->sc_iot = iot; 99 #if NGPIO > 0 100 sc->sc_gpio_iot = iot; 101 #endif 102 103 /* Attach the CS553[56] timer */ 104 tc->tc_get_timecount = gcscpcib_get_timecount; 105 tc->tc_counter_mask = 0xffffffff; 106 tc->tc_frequency = 3579545; 107 tc->tc_name = device_xname(self); 108 tc->tc_quality = 1000; 109 tc->tc_priv = sc; 110 tc_init(tc); 111 112 /* Attach the watchdog timer */ 113 wdtbase = gcsc_rdmsr(MSR_LBAR_MFGPT) & 0xffff; 114 if (bus_space_map(sc->sc_iot, wdtbase, 64, 0, &sc->sc_ioh)) { 115 aprint_error_dev(self, "can't map memory space for WDT\n"); 116 } else { 117 /* select a MFGPT timer for watchdog counter */ 118 if (!gscspcib_scan_mfgpt(sc)) { 119 aprint_error_dev(self, "can't alloc an MFGPT for WDT\n"); 120 goto gpio; 121 } 122 /* 123 * Note: MFGPGx_SETUP register is write once register 124 * except CNT_EN and CMP[12]EV bit. 125 */ 126 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 127 AMD553X_MFGPTX_SETUP(sc->sc_wdt_mfgpt), 128 AMD553X_MFGPT_CMP2EV | AMD553X_MFGPT_CMP2 | 129 AMD553X_MFGPT_PRESCALE); 130 131 /* disable watchdog action */ 132 AMD553X_MFGPTx_NR_DISABLE(sc->sc_wdt_mfgpt, 133 AMD553X_MFGPT0_C2_NMIM); 134 AMD553X_MFGPTx_NR_DISABLE(sc->sc_wdt_mfgpt, 135 AMD553X_MFGPT0_C2_RSTEN); 136 137 sc->sc_smw.smw_name = device_xname(self); 138 sc->sc_smw.smw_cookie = sc; 139 sc->sc_smw.smw_setmode = gcscpcib_wdog_setmode; 140 sc->sc_smw.smw_tickle = gcscpcib_wdog_tickle; 141 sc->sc_smw.smw_period = 32; 142 aprint_normal_dev(self, "Watchdog Timer via MFGPT%d", 143 sc->sc_wdt_mfgpt); 144 wdt = 1; 145 } 146 147 gpio: 148 #if NGPIO > 0 149 /* map GPIO I/O space */ 150 gpiobase = gcsc_rdmsr(MSR_LBAR_GPIO) & 0xffff; 151 if (!bus_space_map(sc->sc_gpio_iot, gpiobase, 0xff, 0, 152 &sc->sc_gpio_ioh)) { 153 aprint_normal(", GPIO"); 154 155 /* initialize pin array */ 156 for (i = 0; i < AMD553X_GPIO_NPINS; i++) { 157 sc->sc_gpio_pins[i].pin_num = i; 158 sc->sc_gpio_pins[i].pin_caps = GPIO_PIN_INPUT | 159 GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | 160 GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE | 161 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | 162 GPIO_PIN_INVIN | GPIO_PIN_INVOUT; 163 164 /* read initial state */ 165 sc->sc_gpio_pins[i].pin_state = 166 gcscpcib_gpio_pin_read(sc, i); 167 } 168 169 /* create controller tag */ 170 sc->sc_gpio_gc.gp_cookie = sc; 171 sc->sc_gpio_gc.gp_pin_read = gcscpcib_gpio_pin_read; 172 sc->sc_gpio_gc.gp_pin_write = gcscpcib_gpio_pin_write; 173 sc->sc_gpio_gc.gp_pin_ctl = gcscpcib_gpio_pin_ctl; 174 175 gba.gba_gc = &sc->sc_gpio_gc; 176 gba.gba_pins = sc->sc_gpio_pins; 177 gba.gba_npins = AMD553X_GPIO_NPINS; 178 gpio = 1; 179 } 180 #endif 181 aprint_normal("\n"); 182 183 #if NGPIO > 0 184 /* Attach GPIO framework */ 185 if (gpio) 186 config_found_ia(self, "gpiobus", &gba, gpiobus_print); 187 #endif 188 189 /* Register Watchdog timer to SMW */ 190 if (wdt) { 191 if (sysmon_wdog_register(&sc->sc_smw) != 0) 192 aprint_error_dev(self, 193 "cannot register wdog with sysmon\n"); 194 } 195 } 196 197 static u_int 198 gcscpcib_get_timecount(struct timecounter *tc) 199 { 200 return gcsc_rdmsr(AMD553X_TMC); 201 } 202 203 /* Watchdog timer support functions */ 204 static int 205 gscspcib_scan_mfgpt(struct gcscpcib_softc *sc) 206 { 207 int i; 208 209 #ifdef AMD553X_WDT_FORCEUSEMFGPT 210 if (AMD553X_WDT_FORCEUSEMFGPT >= AMD553X_MFGPT_MAX) 211 return 0; 212 sc->sc_wdt_mfgpt = AMD553X_WDT_FORCEUSEMFGPT; 213 return 1; 214 #endif /* AMD553X_WDT_FORCEUSEMFGPT */ 215 216 for (i = 0; i < AMD553X_MFGPT_MAX; i++){ 217 if (bus_space_read_2(sc->sc_iot, sc->sc_ioh, 218 AMD553X_MFGPTX_SETUP(i)) == 0) { 219 /* found unused MFGPT, use it. */ 220 sc->sc_wdt_mfgpt = i; 221 return 1; 222 } 223 } 224 /* no MFGPT for WDT found */ 225 return 0; 226 } 227 228 229 static void 230 gscspcib_wdog_update(struct gcscpcib_softc *sc, uint16_t count) 231 { 232 #ifdef GCSCPCIB_DEBUG 233 uint16_t cnt; 234 cnt = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 235 AMD553X_MFGPTX_CNT(sc->sc_wdt_mfgpt)); 236 #endif 237 if (count > AMD553X_WDT_COUNTMAX) 238 count = AMD553X_WDT_COUNTMAX; 239 /* 240 * CS553X databook recommend following sequence to re-initialize 241 * the counter and compare value. (See p165 on CS5536 databook) 242 * 1: suspend counter: clear counter enable bit to 0 243 * 2: reset (and NMI, if need) enable bit in MSRs 244 * 3: update counter & clear event flags 245 * 4: resume (2) operation 246 * 5: re-enable counter 247 */ 248 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 249 AMD553X_MFGPTX_SETUP(sc->sc_wdt_mfgpt), 0); 250 AMD553X_MFGPTx_NR_DISABLE(sc->sc_wdt_mfgpt, AMD553X_MFGPT0_C2_RSTEN); 251 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 252 AMD553X_MFGPTX_CNT(sc->sc_wdt_mfgpt), count); 253 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 254 AMD553X_MFGPTX_SETUP(sc->sc_wdt_mfgpt), 255 AMD553X_MFGPT_CMP1 | AMD553X_MFGPT_CMP2); 256 AMD553X_MFGPTx_NR_ENABLE(sc->sc_wdt_mfgpt, AMD553X_MFGPT0_C2_RSTEN); 257 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 258 AMD553X_MFGPTX_SETUP(sc->sc_wdt_mfgpt), 259 AMD553X_MFGPT_CNT_EN | AMD553X_MFGPT_CMP2); 260 261 DPRINTF(("%s: MFGPT%d_CNT= %d -> %d (expect: %d), MFGPT_NR=%#.8x\n", 262 __func__, sc->sc_wdt_mfgpt, cnt, 263 bus_space_read_2(sc->sc_iot, sc->sc_ioh, 264 AMD553X_MFGPTX_CNT(sc->sc_wdt_mfgpt)), count, 265 (uint32_t)(gcsc_rdmsr(AMD553X_MFGPT_NR)))); 266 } 267 268 static void 269 gcscpcib_wdog_disable(struct gcscpcib_softc *sc) 270 { 271 /* 272 * stop counter and reset counter value 273 * Note: as the MFGPTx_SETUP is write once register, the prescaler 274 * setting, clock select and compare mode are kept till reset. 275 */ 276 gscspcib_wdog_update(sc, 0); 277 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 278 AMD553X_MFGPTX_SETUP(sc->sc_wdt_mfgpt), 0); 279 280 /* disable watchdog action */ 281 DPRINTF(("%s: disable watchdog action\n", __func__)); 282 AMD553X_MFGPTx_NR_DISABLE(sc->sc_wdt_mfgpt, AMD553X_MFGPT0_C2_RSTEN); 283 } 284 285 static void 286 gcscpcib_wdog_enable(struct gcscpcib_softc *sc) 287 { 288 int period = sc->sc_smw.smw_period; 289 290 /* clear recent event flag and counter value, and start counter */ 291 gcscpcib_wdog_reset(sc); 292 /* set watchdog timer limit, counter tick is 0.5sec */ 293 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 294 AMD553X_MFGPTX_CMP2(sc->sc_wdt_mfgpt), 295 period * AMD553X_WDT_TICK); 296 297 /* enable watchdog action */ 298 DPRINTF(("%s: enable watchdog action. (MFGPT0_CMP2= %d)\n", __func__, 299 bus_space_read_2(sc->sc_iot, sc->sc_ioh, 300 AMD553X_MFGPTX_CMP2(sc->sc_wdt_mfgpt)))); 301 AMD553X_MFGPTx_NR_ENABLE(sc->sc_wdt_mfgpt, AMD553X_MFGPT0_C2_RSTEN); 302 } 303 304 static int 305 gcscpcib_wdog_setmode(struct sysmon_wdog *smw) 306 { 307 struct gcscpcib_softc *sc = smw->smw_cookie; 308 309 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 310 gcscpcib_wdog_disable(sc); 311 return 0; 312 } 313 314 if (smw->smw_period == WDOG_PERIOD_DEFAULT) 315 smw->smw_period = 32; 316 else if (smw->smw_period > AMD553X_WDT_COUNTMAX) /* too big */ 317 return EINVAL; 318 319 gcscpcib_wdog_enable(sc); 320 321 return 0; 322 } 323 324 static void 325 gcscpcib_wdog_reset(struct gcscpcib_softc *sc) 326 { 327 /* reset counter value */ 328 gscspcib_wdog_update(sc, 0); 329 /* start counter & clear recent event of CMP2 */ 330 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 331 AMD553X_MFGPTX_SETUP(sc->sc_wdt_mfgpt), 332 AMD553X_MFGPT_CNT_EN | AMD553X_MFGPT_CMP2); 333 } 334 335 static int 336 gcscpcib_wdog_tickle(struct sysmon_wdog *smw) 337 { 338 struct gcscpcib_softc *sc = smw->smw_cookie; 339 340 DPRINTF(("%s: update watchdog timer\n", __func__)); 341 gcscpcib_wdog_reset(sc); 342 return 0; 343 } 344 345 #if NGPIO > 0 346 /* GPIO support functions */ 347 static int 348 gcscpcib_gpio_pin_read(void *arg, int pin) 349 { 350 struct gcscpcib_softc *sc = arg; 351 uint32_t data; 352 int reg; 353 354 reg = AMD553X_GPIO_OUT_VAL; 355 if (pin > 15) { 356 pin &= 0x0f; 357 reg += AMD553X_GPIOH_OFFSET; 358 } 359 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 360 361 return data & 1 << pin ? GPIO_PIN_HIGH : GPIO_PIN_LOW; 362 } 363 364 static void 365 gcscpcib_gpio_pin_write(void *arg, int pin, int value) 366 { 367 struct gcscpcib_softc *sc = arg; 368 uint32_t data; 369 int reg; 370 371 reg = AMD553X_GPIO_OUT_VAL; 372 if (pin > 15) { 373 pin &= 0x0f; 374 reg += AMD553X_GPIOH_OFFSET; 375 } 376 if (value == 1) 377 data = 1 << pin; 378 else 379 data = 1 << (pin + 16); 380 381 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 382 } 383 384 static void 385 gcscpcib_gpio_pin_ctl(void *arg, int pin, int flags) 386 { 387 struct gcscpcib_softc *sc = arg; 388 int n, reg[7], val[7], nreg = 0, off = 0; 389 390 if (pin > 15) { 391 pin &= 0x0f; 392 off = AMD553X_GPIOH_OFFSET; 393 } 394 395 reg[nreg] = AMD553X_GPIO_IN_EN + off; 396 if (flags & GPIO_PIN_INPUT) 397 val[nreg++] = 1 << pin; 398 else 399 val[nreg++] = 1 << (pin + 16); 400 401 reg[nreg] = AMD553X_GPIO_OUT_EN + off; 402 if (flags & GPIO_PIN_OUTPUT) 403 val[nreg++] = 1 << pin; 404 else 405 val[nreg++] = 1 << (pin + 16); 406 407 reg[nreg] = AMD553X_GPIO_OD_EN + off; 408 if (flags & GPIO_PIN_OPENDRAIN) 409 val[nreg++] = 1 << pin; 410 else 411 val[nreg++] = 1 << (pin + 16); 412 413 reg[nreg] = AMD553X_GPIO_PU_EN + off; 414 if (flags & GPIO_PIN_PULLUP) 415 val[nreg++] = 1 << pin; 416 else 417 val[nreg++] = 1 << (pin + 16); 418 419 reg[nreg] = AMD553X_GPIO_PD_EN + off; 420 if (flags & GPIO_PIN_PULLDOWN) 421 val[nreg++] = 1 << pin; 422 else 423 val[nreg++] = 1 << (pin + 16); 424 425 reg[nreg] = AMD553X_GPIO_IN_INVRT_EN + off; 426 if (flags & GPIO_PIN_INVIN) 427 val[nreg++] = 1 << pin; 428 else 429 val[nreg++] = 1 << (pin + 16); 430 431 reg[nreg] = AMD553X_GPIO_OUT_INVRT_EN + off; 432 if (flags & GPIO_PIN_INVOUT) 433 val[nreg++] = 1 << pin; 434 else 435 val[nreg++] = 1 << (pin + 16); 436 437 /* set flags */ 438 for (n = 0; n < nreg; n++) 439 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg[n], 440 val[n]); 441 } 442 #endif /* NGPIO > 0 */ 443 444