1 /* $NetBSD: dwc_gmac_reg.h,v 1.16 2018/06/16 00:15:00 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2013, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry and Martin Husemann. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define AWIN_GMAC_MAC_CONF 0x0000 33 #define AWIN_GMAC_MAC_FFILT 0x0004 34 #define AWIN_GMAC_MAC_HTHIGH 0x0008 35 #define AWIN_GMAC_MAC_HTLOW 0x000c 36 #define AWIN_GMAC_MAC_MIIADDR 0x0010 37 #define AWIN_GMAC_MAC_MIIDATA 0x0014 38 #define AWIN_GMAC_MAC_FLOWCTRL 0x0018 39 #define AWIN_GMAC_MAC_VLANTAG 0x001c 40 #define AWIN_GMAC_MAC_VERSION 0x0020 /* not always implemented? */ 41 #define AWIN_GMAC_MAC_INTR 0x0038 42 #define AWIN_GMAC_MAC_INTMASK 0x003c 43 #define AWIN_GMAC_MAC_ADDR0HI 0x0040 44 #define AWIN_GMAC_MAC_ADDR0LO 0x0044 45 #define AWIN_GMAC_MII_STATUS 0x00D8 46 47 #define AWIN_GMAC_MAC_CONF_DISABLEJABBER __BIT(22) /* jabber disable */ 48 #define AWIN_GMAC_MAC_CONF_FRAMEBURST __BIT(21) /* allow TX frameburst when 49 in half duplex mode */ 50 #define AWIN_GMAC_MAC_CONF_MIISEL __BIT(15) /* select MII phy */ 51 #define AWIN_GMAC_MAC_CONF_FES100 __BIT(14) /* 100 mbit mode */ 52 #define AWIN_GMAC_MAC_CONF_DISABLERXOWN __BIT(13) /* do not receive our own 53 TX frames in half duplex 54 mode */ 55 #define AWIN_GMAC_MAC_CONF_FULLDPLX __BIT(11) /* select full duplex */ 56 #define AWIN_GMAC_MAC_CONF_ACS __BIT(7) /* auto pad/CRC stripping */ 57 #define AWIN_GMAC_MAC_CONF_TXENABLE __BIT(3) /* enable TX dma engine */ 58 #define AWIN_GMAC_MAC_CONF_RXENABLE __BIT(2) /* enable RX dma engine */ 59 60 #define AWIN_GMAC_MAC_FFILT_RA __BIT(31) /* receive all mode */ 61 #define AWIN_GMAC_MAC_FFILT_HPF __BIT(10) /* hash or perfect filter */ 62 #define AWIN_GMAC_MAC_FFILT_SAF __BIT(9) /* source address filter */ 63 #define AWIN_GMAC_MAC_FFILT_SAIF __BIT(8) /* inverse filtering */ 64 #define AWIN_GMAC_MAC_FFILT_DBF __BIT(5) /* disable broadcast frames */ 65 #define AWIN_GMAC_MAC_FFILT_PM __BIT(4) /* promiscious multicast */ 66 #define AWIN_GMAC_MAC_FFILT_DAIF __BIT(3) /* DA inverse filtering */ 67 #define AWIN_GMAC_MAC_FFILT_HMC __BIT(2) /* multicast hash compare */ 68 #define AWIN_GMAC_MAC_FFILT_HUC __BIT(1) /* unicast hash compare */ 69 #define AWIN_GMAC_MAC_FFILT_PR __BIT(0) /* promiscious mode */ 70 71 #define AWIN_GMAC_MAC_INT_LPI __BIT(10) 72 #define AWIN_GMAC_MAC_INT_TSI __BIT(9) 73 #define AWIN_GMAC_MAC_INT_ANEG __BIT(2) 74 #define AWIN_GMAC_MAC_INT_LINKCHG __BIT(1) 75 #define AWIN_GMAC_MAC_INT_RGSMII __BIT(0) 76 77 #define AWIN_GMAC_MAC_FLOWCTRL_PAUSE __BITS(31,16) 78 #define AWIN_GMAC_MAC_FLOWCTRL_RFE __BIT(2) 79 #define AWIN_GMAC_MAC_FLOWCTRL_TFE __BIT(1) 80 #define AWIN_GMAC_MAC_FLOWCTRL_BUSY __BIT(0) 81 82 #define AWIN_GMAC_DMA_BUSMODE 0x1000 83 #define AWIN_GMAC_DMA_TXPOLL 0x1004 84 #define AWIN_GMAC_DMA_RXPOLL 0x1008 85 #define AWIN_GMAC_DMA_RX_ADDR 0x100c 86 #define AWIN_GMAC_DMA_TX_ADDR 0x1010 87 #define AWIN_GMAC_DMA_STATUS 0x1014 88 #define AWIN_GMAC_DMA_OPMODE 0x1018 89 #define AWIN_GMAC_DMA_INTENABLE 0x101c 90 #define AWIN_GMAC_DMA_CUR_TX_DESC 0x1048 91 #define AWIN_GMAC_DMA_CUR_RX_DESC 0x104c 92 #define AWIN_GMAC_DMA_CUR_TX_BUFADDR 0x1050 93 #define AWIN_GMAC_DMA_CUR_RX_BUFADDR 0x1054 94 #define AWIN_GMAC_DMA_HWFEATURES 0x1058 /* not always implemented? */ 95 96 #define GMAC_MII_PHY_SHIFT 11 97 #define GMAC_MII_PHY_MASK __BITS(15,11) 98 #define GMAC_MII_REG_SHIFT 6 99 #define GMAC_MII_REG_MASK __BITS(10,6) 100 101 #define GMAC_MII_BUSY __BIT(0) 102 #define GMAC_MII_WRITE __BIT(1) 103 #define GMAC_MII_CLK_60_100M_DIV42 0x0 104 #define GMAC_MII_CLK_100_150M_DIV62 0x1 105 #define GMAC_MII_CLK_25_35M_DIV16 0x2 106 #define GMAC_MII_CLK_35_60M_DIV26 0x3 107 #define GMAC_MII_CLK_150_250M_DIV102 0x4 108 #define GMAC_MII_CLK_250_300M_DIV124 0x5 109 #define GMAC_MII_CLK_DIV4 0x8 110 #define GMAC_MII_CLK_DIV6 0x9 111 #define GMAC_MII_CLK_DIV8 0xa 112 #define GMAC_MII_CLK_DIV10 0xb 113 #define GMAC_MII_CLK_DIV12 0xc 114 #define GMAC_MII_CLK_DIV14 0xd 115 #define GMAC_MII_CLK_DIV16 0xe 116 #define GMAC_MII_CLK_DIV18 0xf 117 #define GMAC_MII_CLKMASK __BITS(5,2) 118 119 #define GMAC_BUSMODE_4PBL __BIT(24) 120 #define GMAC_BUSMODE_RPBL __BITS(22,17) 121 #define GMAC_BUSMODE_FIXEDBURST __BIT(16) 122 #define GMAC_BUSMODE_PRIORXTX __BITS(15,14) 123 #define GMAC_BUSMODE_PRIORXTX_41 3 124 #define GMAC_BUSMODE_PRIORXTX_31 2 125 #define GMAC_BUSMODE_PRIORXTX_21 1 126 #define GMAC_BUSMODE_PRIORXTX_11 0 127 #define GMAC_BUSMODE_PBL __BITS(13,8) /* possible DMA 128 burst len */ 129 #define GMAC_BUSMODE_RESET __BIT(0) 130 131 #define AWIN_GMAC_MII_IRQ __BIT(0) 132 133 134 #define GMAC_DMA_OP_DISABLECSDROP __BIT(26) /* disable dropping of 135 frames with TCP/IP 136 checksum errors */ 137 #define GMAC_DMA_OP_RXSTOREFORWARD __BIT(25) /* start RX when a 138 full frame is available */ 139 #define GMAC_DMA_OP_DISABLERXFLUSH __BIT(24) /* Do not drop frames 140 when out of RX descr. */ 141 #define GMAC_DMA_OP_TXSTOREFORWARD __BIT(21) /* start TX when a 142 full frame is available */ 143 #define GMAC_DMA_OP_FLUSHTX __BIT(20) /* flush TX fifo */ 144 #define GMAC_DMA_OP_TTC __BITS(16,14) /* TX thresh control */ 145 #define GMAC_DMA_OP_TXSTART __BIT(13) /* start TX DMA engine */ 146 #define GMAC_DMA_OP_RTC __BITS(4,3) /* RX thres control */ 147 #define GMAC_DMA_OP_RXSTART __BIT(1) /* start RX DMA engine */ 148 149 #define GMAC_DMA_INT_NIE __BIT(16) /* Normal/Summary */ 150 #define GMAC_DMA_INT_AIE __BIT(15) /* Abnormal/Summary */ 151 #define GMAC_DMA_INT_ERE __BIT(14) /* Early receive */ 152 #define GMAC_DMA_INT_FBE __BIT(13) /* Fatal bus error */ 153 #define GMAC_DMA_INT_ETE __BIT(10) /* Early transmit */ 154 #define GMAC_DMA_INT_RWE __BIT(9) /* Receive watchdog */ 155 #define GMAC_DMA_INT_RSE __BIT(8) /* Receive stopped */ 156 #define GMAC_DMA_INT_RUE __BIT(7) /* Receive buffer unavail. */ 157 #define GMAC_DMA_INT_RIE __BIT(6) /* Receive interrupt */ 158 #define GMAC_DMA_INT_UNE __BIT(5) /* Tx underflow */ 159 #define GMAC_DMA_INT_OVE __BIT(4) /* Receive overflow */ 160 #define GMAC_DMA_INT_TJE __BIT(3) /* Transmit jabber */ 161 #define GMAC_DMA_INT_TUE __BIT(2) /* Transmit buffer unavail. */ 162 #define GMAC_DMA_INT_TSE __BIT(1) /* Transmit stopped */ 163 #define GMAC_DMA_INT_TIE __BIT(0) /* Transmit interrupt */ 164 165 #define GMAC_DMA_INT_MASK __BITS(0,16) /* all possible intr bits */ 166 167 struct dwc_gmac_dev_dmadesc { 168 uint32_t ddesc_status; 169 /* both: */ 170 #define DDESC_STATUS_OWNEDBYDEV __BIT(31) 171 172 /* for RX descriptors */ 173 #define DDESC_STATUS_DAFILTERFAIL __BIT(30) 174 #define DDESC_STATUS_FRMLENMSK __BITS(29,16) 175 #define DDESC_STATUS_FRMLENSHIFT 16 176 #define DDESC_STATUS_RXERROR __BIT(15) 177 #define DDESC_STATUS_RXTRUNCATED __BIT(14) 178 #define DDESC_STATUS_SAFILTERFAIL __BIT(13) 179 #define DDESC_STATUS_RXIPC_GIANTFRAME __BIT(12) 180 #define DDESC_STATUS_RXDAMAGED __BIT(11) 181 #define DDESC_STATUS_RXVLANTAG __BIT(10) 182 #define DDESC_STATUS_RXFIRST __BIT(9) 183 #define DDESC_STATUS_RXLAST __BIT(8) 184 #define DDESC_STATUS_RXIPC_GIANT __BIT(7) 185 #define DDESC_STATUS_RXCOLLISION __BIT(6) 186 #define DDESC_STATUS_RXFRAMEETHER __BIT(5) 187 #define DDESC_STATUS_RXWATCHDOG __BIT(4) 188 #define DDESC_STATUS_RXMIIERROR __BIT(3) 189 #define DDESC_STATUS_RXDRIBBLING __BIT(2) 190 #define DDESC_STATUS_RXCRC __BIT(1) 191 192 uint32_t ddesc_cntl; 193 194 /* for TX descriptors */ 195 #define DDESC_CNTL_TXINT __BIT(31) 196 #define DDESC_CNTL_TXLAST __BIT(30) 197 #define DDESC_CNTL_TXFIRST __BIT(29) 198 #define DDESC_CNTL_TXCHECKINSCTRL __BITS(27,28) 199 200 #define DDESC_TXCHECK_DISABLED 0 201 #define DDESC_TXCHECK_IP 1 202 #define DDESC_TXCHECK_IP_NO_PSE 2 203 #define DDESC_TXCHECK_FULL 3 204 205 #define DDESC_CNTL_TXCRCDIS __BIT(26) 206 #define DDESC_CNTL_TXRINGEND __BIT(25) 207 #define DDESC_CNTL_TXCHAIN __BIT(24) 208 #define DDESC_CNTL_TXDISPAD __BIT(23) 209 210 /* for RX descriptors */ 211 #define DDESC_CNTL_RXINTDIS __BIT(31) 212 #define DDESC_CNTL_RXRINGEND __BIT(25) 213 #define DDESC_CNTL_RXCHAIN __BIT(24) 214 215 /* both */ 216 #define DDESC_CNTL_SIZE1MASK __BITS(10,0) 217 #define DDESC_CNTL_SIZE1SHIFT 0 218 #define DDESC_CNTL_SIZE2MASK __BITS(21,11) 219 #define DDESC_CNTL_SIZE2SHIFT 11 220 221 uint32_t ddesc_data; /* pointer to buffer data */ 222 uint32_t ddesc_next; /* link to next descriptor */ 223 }; 224