1 /* $NetBSD: dwc_eqos.c,v 1.6 2022/04/16 23:20:47 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2022 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * DesignWare Ethernet Quality-of-Service controller 31 */ 32 33 #include "opt_net_mpsafe.h" 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: dwc_eqos.c,v 1.6 2022/04/16 23:20:47 jmcneill Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/device.h> 41 #include <sys/intr.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/mutex.h> 45 #include <sys/callout.h> 46 #include <sys/cprng.h> 47 #include <sys/evcnt.h> 48 49 #include <sys/rndsource.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 #include <net/bpf.h> 56 57 #include <dev/mii/miivar.h> 58 59 #include <dev/ic/dwc_eqos_reg.h> 60 #include <dev/ic/dwc_eqos_var.h> 61 62 CTASSERT(MCLBYTES == 2048); 63 #ifdef EQOS_DEBUG 64 #define DPRINTF(...) printf(##__VA_ARGS__) 65 #else 66 #define DPRINTF(...) ((void)0) 67 #endif 68 69 #ifdef NET_MPSAFE 70 #define EQOS_MPSAFE 1 71 #define CALLOUT_FLAGS CALLOUT_MPSAFE 72 #else 73 #define CALLOUT_FLAGS 0 74 #endif 75 76 #define DESC_BOUNDARY (1ULL << 32) 77 #define DESC_ALIGN sizeof(struct eqos_dma_desc) 78 #define TX_DESC_COUNT EQOS_DMA_DESC_COUNT 79 #define TX_DESC_SIZE (TX_DESC_COUNT * DESC_ALIGN) 80 #define RX_DESC_COUNT EQOS_DMA_DESC_COUNT 81 #define RX_DESC_SIZE (RX_DESC_COUNT * DESC_ALIGN) 82 #define MII_BUSY_RETRY 1000 83 84 #define DESC_OFF(n) ((n) * sizeof(struct eqos_dma_desc)) 85 #define TX_SKIP(n, o) (((n) + (o)) % TX_DESC_COUNT) 86 #define TX_NEXT(n) TX_SKIP(n, 1) 87 #define RX_NEXT(n) (((n) + 1) % RX_DESC_COUNT) 88 89 #define TX_MAX_SEGS 128 90 91 #define EQOS_LOCK(sc) mutex_enter(&(sc)->sc_lock) 92 #define EQOS_UNLOCK(sc) mutex_exit(&(sc)->sc_lock) 93 #define EQOS_ASSERT_LOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_lock)) 94 95 #define EQOS_TXLOCK(sc) mutex_enter(&(sc)->sc_txlock) 96 #define EQOS_TXUNLOCK(sc) mutex_exit(&(sc)->sc_txlock) 97 #define EQOS_ASSERT_TXLOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_txlock)) 98 99 #define EQOS_HW_FEATURE_ADDR64_32BIT(sc) \ 100 (((sc)->sc_hw_feature[1] & GMAC_MAC_HW_FEATURE1_ADDR64_MASK) == \ 101 GMAC_MAC_HW_FEATURE1_ADDR64_32BIT) 102 103 104 #define RD4(sc, reg) \ 105 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 106 #define WR4(sc, reg, val) \ 107 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 108 109 #define STUB(...) \ 110 printf("%s: TODO\n", __func__); \ 111 112 static int 113 eqos_mii_readreg(device_t dev, int phy, int reg, uint16_t *val) 114 { 115 struct eqos_softc *sc = device_private(dev); 116 uint32_t addr; 117 int retry; 118 119 addr = sc->sc_clock_range | 120 (phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | 121 (reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) | 122 GMAC_MAC_MDIO_ADDRESS_GOC_READ | 123 GMAC_MAC_MDIO_ADDRESS_GB; 124 WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); 125 126 delay(10000); 127 128 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 129 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); 130 if ((addr & GMAC_MAC_MDIO_ADDRESS_GB) == 0) { 131 *val = RD4(sc, GMAC_MAC_MDIO_DATA) & 0xFFFF; 132 break; 133 } 134 delay(10); 135 } 136 if (retry == 0) { 137 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 138 phy, reg); 139 return ETIMEDOUT; 140 } 141 142 return 0; 143 } 144 145 static int 146 eqos_mii_writereg(device_t dev, int phy, int reg, uint16_t val) 147 { 148 struct eqos_softc *sc = device_private(dev); 149 uint32_t addr; 150 int retry; 151 152 WR4(sc, GMAC_MAC_MDIO_DATA, val); 153 154 addr = sc->sc_clock_range | 155 (phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | 156 (reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) | 157 GMAC_MAC_MDIO_ADDRESS_GOC_WRITE | 158 GMAC_MAC_MDIO_ADDRESS_GB; 159 WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); 160 161 delay(10000); 162 163 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 164 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); 165 if ((addr & GMAC_MAC_MDIO_ADDRESS_GB) == 0) { 166 break; 167 } 168 delay(10); 169 } 170 if (retry == 0) { 171 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 172 phy, reg); 173 return ETIMEDOUT; 174 } 175 176 return 0; 177 } 178 179 static void 180 eqos_update_link(struct eqos_softc *sc) 181 { 182 struct mii_data *mii = &sc->sc_mii; 183 uint64_t baudrate; 184 uint32_t conf; 185 186 baudrate = ifmedia_baudrate(mii->mii_media_active); 187 188 conf = RD4(sc, GMAC_MAC_CONFIGURATION); 189 switch (baudrate) { 190 case IF_Mbps(10): 191 conf |= GMAC_MAC_CONFIGURATION_PS; 192 conf &= ~GMAC_MAC_CONFIGURATION_FES; 193 break; 194 case IF_Mbps(100): 195 conf |= GMAC_MAC_CONFIGURATION_PS; 196 conf |= GMAC_MAC_CONFIGURATION_FES; 197 break; 198 case IF_Gbps(1): 199 conf &= ~GMAC_MAC_CONFIGURATION_PS; 200 conf &= ~GMAC_MAC_CONFIGURATION_FES; 201 break; 202 case IF_Mbps(2500ULL): 203 conf &= ~GMAC_MAC_CONFIGURATION_PS; 204 conf |= GMAC_MAC_CONFIGURATION_FES; 205 break; 206 } 207 208 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 209 conf |= GMAC_MAC_CONFIGURATION_DM; 210 } else { 211 conf &= ~GMAC_MAC_CONFIGURATION_DM; 212 } 213 214 WR4(sc, GMAC_MAC_CONFIGURATION, conf); 215 } 216 217 static void 218 eqos_mii_statchg(struct ifnet *ifp) 219 { 220 struct eqos_softc * const sc = ifp->if_softc; 221 222 eqos_update_link(sc); 223 } 224 225 static void 226 eqos_dma_sync(struct eqos_softc *sc, bus_dmamap_t map, 227 u_int start, u_int end, u_int total, int flags) 228 { 229 if (end > start) { 230 bus_dmamap_sync(sc->sc_dmat, map, DESC_OFF(start), 231 DESC_OFF(end) - DESC_OFF(start), flags); 232 } else { 233 bus_dmamap_sync(sc->sc_dmat, map, DESC_OFF(start), 234 DESC_OFF(total) - DESC_OFF(start), flags); 235 if (DESC_OFF(end) - DESC_OFF(0) > 0) { 236 bus_dmamap_sync(sc->sc_dmat, map, DESC_OFF(0), 237 DESC_OFF(end) - DESC_OFF(0), flags); 238 } 239 } 240 } 241 242 static void 243 eqos_setup_txdesc(struct eqos_softc *sc, int index, int flags, 244 bus_addr_t paddr, u_int len, u_int total_len) 245 { 246 uint32_t tdes2, tdes3; 247 248 if (paddr == 0 || len == 0) { 249 KASSERT(flags == 0); 250 tdes2 = 0; 251 tdes3 = 0; 252 --sc->sc_tx.queued; 253 } else { 254 tdes2 = (flags & EQOS_TDES3_LD) ? EQOS_TDES2_IOC : 0; 255 tdes3 = flags; 256 ++sc->sc_tx.queued; 257 } 258 259 KASSERT(!EQOS_HW_FEATURE_ADDR64_32BIT(sc) || (paddr >> 32) == 0); 260 261 sc->sc_tx.desc_ring[index].tdes0 = htole32((uint32_t)paddr); 262 sc->sc_tx.desc_ring[index].tdes1 = htole32((uint32_t)(paddr >> 32)); 263 sc->sc_tx.desc_ring[index].tdes2 = htole32(tdes2 | len); 264 sc->sc_tx.desc_ring[index].tdes3 = htole32(tdes3 | total_len); 265 } 266 267 static int 268 eqos_setup_txbuf(struct eqos_softc *sc, int index, struct mbuf *m) 269 { 270 bus_dma_segment_t *segs; 271 int error, nsegs, cur, i; 272 uint32_t flags; 273 bool nospace; 274 275 /* at least one descriptor free ? */ 276 if (sc->sc_tx.queued >= TX_DESC_COUNT - 1) 277 return -1; 278 279 error = bus_dmamap_load_mbuf(sc->sc_dmat, 280 sc->sc_tx.buf_map[index].map, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 281 if (error == EFBIG) { 282 device_printf(sc->sc_dev, 283 "TX packet needs too many DMA segments, dropping...\n"); 284 return -2; 285 } 286 if (error != 0) { 287 device_printf(sc->sc_dev, 288 "TX packet cannot be mapped, retried...\n"); 289 return 0; 290 } 291 292 segs = sc->sc_tx.buf_map[index].map->dm_segs; 293 nsegs = sc->sc_tx.buf_map[index].map->dm_nsegs; 294 295 nospace = sc->sc_tx.queued >= TX_DESC_COUNT - nsegs; 296 if (nospace) { 297 bus_dmamap_unload(sc->sc_dmat, 298 sc->sc_tx.buf_map[index].map); 299 /* XXX coalesce and retry ? */ 300 return -1; 301 } 302 303 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx.buf_map[index].map, 304 0, sc->sc_tx.buf_map[index].map->dm_mapsize, BUS_DMASYNC_PREWRITE); 305 306 /* stored in same index as loaded map */ 307 sc->sc_tx.buf_map[index].mbuf = m; 308 309 flags = EQOS_TDES3_FD; 310 311 for (cur = index, i = 0; i < nsegs; i++) { 312 if (i == nsegs - 1) 313 flags |= EQOS_TDES3_LD; 314 315 eqos_setup_txdesc(sc, cur, flags, segs[i].ds_addr, 316 segs[i].ds_len, m->m_pkthdr.len); 317 flags &= ~EQOS_TDES3_FD; 318 cur = TX_NEXT(cur); 319 320 flags |= EQOS_TDES3_OWN; 321 } 322 323 /* 324 * Defer setting OWN bit on the first descriptor until all 325 * descriptors have been updated. The hardware will not try to 326 * process any descriptors past the first one still owned by 327 * software (i.e., with the OWN bit clear). 328 */ 329 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx.desc_map, 330 DESC_OFF(index), offsetof(struct eqos_dma_desc, tdes3), 331 BUS_DMASYNC_PREWRITE); 332 sc->sc_tx.desc_ring[index].tdes3 |= htole32(EQOS_TDES3_OWN); 333 334 return nsegs; 335 } 336 337 static void 338 eqos_setup_rxdesc(struct eqos_softc *sc, int index, bus_addr_t paddr) 339 { 340 341 sc->sc_rx.desc_ring[index].tdes0 = htole32((uint32_t)paddr); 342 sc->sc_rx.desc_ring[index].tdes1 = htole32((uint32_t)(paddr >> 32)); 343 sc->sc_rx.desc_ring[index].tdes2 = htole32(0); 344 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx.desc_map, 345 DESC_OFF(index), offsetof(struct eqos_dma_desc, tdes3), 346 BUS_DMASYNC_PREWRITE); 347 sc->sc_rx.desc_ring[index].tdes3 = 348 htole32(EQOS_TDES3_OWN | EQOS_TDES3_IOC | EQOS_TDES3_BUF1V); 349 } 350 351 static int 352 eqos_setup_rxbuf(struct eqos_softc *sc, int index, struct mbuf *m) 353 { 354 int error; 355 356 m_adj(m, ETHER_ALIGN); 357 358 error = bus_dmamap_load_mbuf(sc->sc_dmat, 359 sc->sc_rx.buf_map[index].map, m, BUS_DMA_READ | BUS_DMA_NOWAIT); 360 if (error != 0) 361 return error; 362 363 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx.buf_map[index].map, 364 0, sc->sc_rx.buf_map[index].map->dm_mapsize, 365 BUS_DMASYNC_PREREAD); 366 367 sc->sc_rx.buf_map[index].mbuf = m; 368 eqos_setup_rxdesc(sc, index, 369 sc->sc_rx.buf_map[index].map->dm_segs[0].ds_addr); 370 371 return 0; 372 } 373 374 static struct mbuf * 375 eqos_alloc_mbufcl(struct eqos_softc *sc) 376 { 377 struct mbuf *m; 378 379 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 380 if (m != NULL) 381 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 382 383 return m; 384 } 385 386 static void 387 eqos_enable_intr(struct eqos_softc *sc) 388 { 389 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 390 GMAC_DMA_CHAN0_INTR_ENABLE_NIE | 391 GMAC_DMA_CHAN0_INTR_ENABLE_AIE | 392 GMAC_DMA_CHAN0_INTR_ENABLE_FBE | 393 GMAC_DMA_CHAN0_INTR_ENABLE_RIE | 394 GMAC_DMA_CHAN0_INTR_ENABLE_TIE); 395 } 396 397 static void 398 eqos_disable_intr(struct eqos_softc *sc) 399 { 400 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 0); 401 } 402 403 static void 404 eqos_tick(void *softc) 405 { 406 struct eqos_softc *sc = softc; 407 struct mii_data *mii = &sc->sc_mii; 408 #ifndef EQOS_MPSAFE 409 int s = splnet(); 410 #endif 411 412 EQOS_LOCK(sc); 413 mii_tick(mii); 414 callout_schedule(&sc->sc_stat_ch, hz); 415 EQOS_UNLOCK(sc); 416 417 #ifndef EQOS_MPSAFE 418 splx(s); 419 #endif 420 } 421 422 static uint32_t 423 eqos_bitrev32(uint32_t x) 424 { 425 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 426 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 427 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 428 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 429 430 return (x >> 16) | (x << 16); 431 } 432 433 static void 434 eqos_setup_rxfilter(struct eqos_softc *sc) 435 { 436 struct ethercom *ec = &sc->sc_ec; 437 struct ifnet *ifp = &ec->ec_if; 438 uint32_t pfil, crc, hashreg, hashbit, hash[2]; 439 struct ether_multi *enm; 440 struct ether_multistep step; 441 const uint8_t *eaddr; 442 uint32_t val; 443 444 EQOS_ASSERT_LOCKED(sc); 445 446 pfil = RD4(sc, GMAC_MAC_PACKET_FILTER); 447 pfil &= ~(GMAC_MAC_PACKET_FILTER_PR | 448 GMAC_MAC_PACKET_FILTER_PM | 449 GMAC_MAC_PACKET_FILTER_HMC | 450 GMAC_MAC_PACKET_FILTER_PCF_MASK); 451 hash[0] = hash[1] = ~0U; 452 453 if ((ifp->if_flags & IFF_PROMISC) != 0) { 454 pfil |= GMAC_MAC_PACKET_FILTER_PR | 455 GMAC_MAC_PACKET_FILTER_PCF_ALL; 456 } else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 457 pfil |= GMAC_MAC_PACKET_FILTER_PM; 458 } else { 459 hash[0] = hash[1] = 0; 460 pfil |= GMAC_MAC_PACKET_FILTER_HMC; 461 ETHER_LOCK(ec); 462 ETHER_FIRST_MULTI(step, ec, enm); 463 while (enm != NULL) { 464 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 465 crc &= 0x7f; 466 crc = eqos_bitrev32(~crc) >> 26; 467 hashreg = (crc >> 5); 468 hashbit = (crc & 0x1f); 469 hash[hashreg] |= (1 << hashbit); 470 ETHER_NEXT_MULTI(step, enm); 471 } 472 ETHER_UNLOCK(ec); 473 } 474 475 /* Write our unicast address */ 476 eaddr = CLLADDR(ifp->if_sadl); 477 val = eaddr[4] | (eaddr[5] << 8); 478 WR4(sc, GMAC_MAC_ADDRESS0_HIGH, val); 479 val = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | 480 (eaddr[3] << 24); 481 WR4(sc, GMAC_MAC_ADDRESS0_LOW, val); 482 483 /* Multicast hash filters */ 484 WR4(sc, GMAC_MAC_HASH_TABLE_REG0, hash[1]); 485 WR4(sc, GMAC_MAC_HASH_TABLE_REG1, hash[0]); 486 487 /* Packet filter config */ 488 WR4(sc, GMAC_MAC_PACKET_FILTER, pfil); 489 } 490 491 static int 492 eqos_reset(struct eqos_softc *sc) 493 { 494 uint32_t val; 495 int retry; 496 497 WR4(sc, GMAC_DMA_MODE, GMAC_DMA_MODE_SWR); 498 for (retry = 2000; retry > 0; retry--) { 499 delay(1000); 500 val = RD4(sc, GMAC_DMA_MODE); 501 if ((val & GMAC_DMA_MODE_SWR) == 0) { 502 return 0; 503 } 504 } 505 506 device_printf(sc->sc_dev, "reset timeout!\n"); 507 return ETIMEDOUT; 508 } 509 510 static void 511 eqos_init_rings(struct eqos_softc *sc, int qid) 512 { 513 sc->sc_tx.queued = 0; 514 515 WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR_HI, 516 (uint32_t)(sc->sc_tx.desc_ring_paddr >> 32)); 517 WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR, 518 (uint32_t)sc->sc_tx.desc_ring_paddr); 519 WR4(sc, GMAC_DMA_CHAN0_TX_RING_LEN, TX_DESC_COUNT - 1); 520 521 WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR_HI, 522 (uint32_t)(sc->sc_rx.desc_ring_paddr >> 32)); 523 WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR, 524 (uint32_t)sc->sc_rx.desc_ring_paddr); 525 WR4(sc, GMAC_DMA_CHAN0_RX_RING_LEN, RX_DESC_COUNT - 1); 526 WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR, 527 (uint32_t)sc->sc_rx.desc_ring_paddr + 528 DESC_OFF((sc->sc_rx.cur - 1) % RX_DESC_COUNT)); 529 } 530 531 static int 532 eqos_init_locked(struct eqos_softc *sc) 533 { 534 struct ifnet *ifp = &sc->sc_ec.ec_if; 535 struct mii_data *mii = &sc->sc_mii; 536 uint32_t val; 537 538 EQOS_ASSERT_LOCKED(sc); 539 EQOS_ASSERT_TXLOCKED(sc); 540 541 if ((ifp->if_flags & IFF_RUNNING) != 0) 542 return 0; 543 544 /* Setup TX/RX rings */ 545 eqos_init_rings(sc, 0); 546 547 /* Setup RX filter */ 548 eqos_setup_rxfilter(sc); 549 550 WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->sc_csr_clock / 1000000) - 1); 551 552 /* Enable transmit and receive DMA */ 553 val = RD4(sc, GMAC_DMA_CHAN0_CONTROL); 554 val &= ~GMAC_DMA_CHAN0_CONTROL_DSL_MASK; 555 val |= ((DESC_ALIGN - 16) / 8) << GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT; 556 val |= GMAC_DMA_CHAN0_CONTROL_PBLX8; 557 WR4(sc, GMAC_DMA_CHAN0_CONTROL, val); 558 val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL); 559 val |= GMAC_DMA_CHAN0_TX_CONTROL_OSP; 560 val |= GMAC_DMA_CHAN0_TX_CONTROL_START; 561 WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val); 562 val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL); 563 val &= ~GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_MASK; 564 val |= (MCLBYTES << GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT); 565 val |= GMAC_DMA_CHAN0_RX_CONTROL_START; 566 WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val); 567 568 /* Disable counters */ 569 WR4(sc, GMAC_MMC_CONTROL, 570 GMAC_MMC_CONTROL_CNTFREEZ | 571 GMAC_MMC_CONTROL_CNTPRST | 572 GMAC_MMC_CONTROL_CNTPRSTLVL); 573 574 /* Configure operation modes */ 575 WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, 576 GMAC_MTL_TXQ0_OPERATION_MODE_TSF | 577 GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_EN); 578 WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE, 579 GMAC_MTL_RXQ0_OPERATION_MODE_RSF | 580 GMAC_MTL_RXQ0_OPERATION_MODE_FEP | 581 GMAC_MTL_RXQ0_OPERATION_MODE_FUP); 582 583 /* Enable flow control */ 584 val = RD4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL); 585 val |= 0xFFFFU << GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT; 586 val |= GMAC_MAC_Q0_TX_FLOW_CTRL_TFE; 587 WR4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL, val); 588 val = RD4(sc, GMAC_MAC_RX_FLOW_CTRL); 589 val |= GMAC_MAC_RX_FLOW_CTRL_RFE; 590 WR4(sc, GMAC_MAC_RX_FLOW_CTRL, val); 591 592 /* Enable transmitter and receiver */ 593 val = RD4(sc, GMAC_MAC_CONFIGURATION); 594 val |= GMAC_MAC_CONFIGURATION_BE; 595 val |= GMAC_MAC_CONFIGURATION_JD; 596 val |= GMAC_MAC_CONFIGURATION_JE; 597 val |= GMAC_MAC_CONFIGURATION_DCRS; 598 val |= GMAC_MAC_CONFIGURATION_TE; 599 val |= GMAC_MAC_CONFIGURATION_RE; 600 WR4(sc, GMAC_MAC_CONFIGURATION, val); 601 602 /* Enable interrupts */ 603 eqos_enable_intr(sc); 604 605 ifp->if_flags |= IFF_RUNNING; 606 ifp->if_flags &= ~IFF_OACTIVE; 607 608 mii_mediachg(mii); 609 callout_schedule(&sc->sc_stat_ch, hz); 610 611 return 0; 612 } 613 614 static int 615 eqos_init(struct ifnet *ifp) 616 { 617 struct eqos_softc *sc = ifp->if_softc; 618 int error; 619 620 EQOS_LOCK(sc); 621 EQOS_TXLOCK(sc); 622 error = eqos_init_locked(sc); 623 EQOS_TXUNLOCK(sc); 624 EQOS_UNLOCK(sc); 625 626 return error; 627 } 628 629 static void 630 eqos_stop_locked(struct eqos_softc *sc, int disable) 631 { 632 struct ifnet *ifp = &sc->sc_ec.ec_if; 633 uint32_t val; 634 int retry; 635 636 EQOS_ASSERT_LOCKED(sc); 637 638 callout_stop(&sc->sc_stat_ch); 639 640 mii_down(&sc->sc_mii); 641 642 /* Disable receiver */ 643 val = RD4(sc, GMAC_MAC_CONFIGURATION); 644 val &= ~GMAC_MAC_CONFIGURATION_RE; 645 WR4(sc, GMAC_MAC_CONFIGURATION, val); 646 647 /* Stop receive DMA */ 648 val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL); 649 val &= ~GMAC_DMA_CHAN0_RX_CONTROL_START; 650 WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val); 651 652 /* Stop transmit DMA */ 653 val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL); 654 val &= ~GMAC_DMA_CHAN0_TX_CONTROL_START; 655 WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val); 656 657 if (disable) { 658 /* Flush data in the TX FIFO */ 659 val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE); 660 val |= GMAC_MTL_TXQ0_OPERATION_MODE_FTQ; 661 WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, val); 662 /* Wait for flush to complete */ 663 for (retry = 10000; retry > 0; retry--) { 664 val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE); 665 if ((val & GMAC_MTL_TXQ0_OPERATION_MODE_FTQ) == 0) { 666 break; 667 } 668 delay(1); 669 } 670 if (retry == 0) { 671 device_printf(sc->sc_dev, 672 "timeout flushing TX queue\n"); 673 } 674 } 675 676 /* Disable transmitter */ 677 val = RD4(sc, GMAC_MAC_CONFIGURATION); 678 val &= ~GMAC_MAC_CONFIGURATION_TE; 679 WR4(sc, GMAC_MAC_CONFIGURATION, val); 680 681 /* Disable interrupts */ 682 eqos_disable_intr(sc); 683 684 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 685 } 686 687 static void 688 eqos_stop(struct ifnet *ifp, int disable) 689 { 690 struct eqos_softc * const sc = ifp->if_softc; 691 692 EQOS_LOCK(sc); 693 eqos_stop_locked(sc, disable); 694 EQOS_UNLOCK(sc); 695 } 696 697 static void 698 eqos_rxintr(struct eqos_softc *sc, int qid) 699 { 700 struct ifnet *ifp = &sc->sc_ec.ec_if; 701 int error, index, len, pkts = 0; 702 struct mbuf *m, *m0; 703 uint32_t tdes3; 704 705 for (index = sc->sc_rx.cur; ; index = RX_NEXT(index)) { 706 eqos_dma_sync(sc, sc->sc_rx.desc_map, 707 index, index + 1, RX_DESC_COUNT, 708 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 709 710 tdes3 = le32toh(sc->sc_rx.desc_ring[index].tdes3); 711 if ((tdes3 & EQOS_TDES3_OWN) != 0) { 712 break; 713 } 714 715 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx.buf_map[index].map, 716 0, sc->sc_rx.buf_map[index].map->dm_mapsize, 717 BUS_DMASYNC_POSTREAD); 718 bus_dmamap_unload(sc->sc_dmat, 719 sc->sc_rx.buf_map[index].map); 720 721 len = tdes3 & EQOS_TDES3_LENGTH_MASK; 722 if (len != 0) { 723 m = sc->sc_rx.buf_map[index].mbuf; 724 m_set_rcvif(m, ifp); 725 m->m_flags |= M_HASFCS; 726 m->m_pkthdr.len = len; 727 m->m_len = len; 728 m->m_nextpkt = NULL; 729 730 if_percpuq_enqueue(ifp->if_percpuq, m); 731 ++pkts; 732 } 733 734 if ((m0 = eqos_alloc_mbufcl(sc)) != NULL) { 735 error = eqos_setup_rxbuf(sc, index, m0); 736 if (error != 0) { 737 /* XXX hole in RX ring */ 738 } 739 } else { 740 if_statinc(ifp, if_ierrors); 741 } 742 eqos_dma_sync(sc, sc->sc_rx.desc_map, 743 index, index + 1, RX_DESC_COUNT, 744 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 745 746 WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR, 747 (uint32_t)sc->sc_rx.desc_ring_paddr + 748 DESC_OFF(sc->sc_rx.cur)); 749 } 750 751 sc->sc_rx.cur = index; 752 753 if (pkts != 0) { 754 rnd_add_uint32(&sc->sc_rndsource, pkts); 755 } 756 } 757 758 static void 759 eqos_txintr(struct eqos_softc *sc, int qid) 760 { 761 struct ifnet *ifp = &sc->sc_ec.ec_if; 762 struct eqos_bufmap *bmap; 763 struct eqos_dma_desc *desc; 764 uint32_t tdes3; 765 int i, pkts = 0; 766 767 EQOS_ASSERT_LOCKED(sc); 768 769 for (i = sc->sc_tx.next; sc->sc_tx.queued > 0; i = TX_NEXT(i)) { 770 KASSERT(sc->sc_tx.queued > 0); 771 KASSERT(sc->sc_tx.queued <= TX_DESC_COUNT); 772 eqos_dma_sync(sc, sc->sc_tx.desc_map, 773 i, i + 1, TX_DESC_COUNT, 774 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 775 desc = &sc->sc_tx.desc_ring[i]; 776 tdes3 = le32toh(desc->tdes3); 777 if ((tdes3 & EQOS_TDES3_OWN) != 0) { 778 break; 779 } 780 bmap = &sc->sc_tx.buf_map[i]; 781 if (bmap->mbuf != NULL) { 782 bus_dmamap_sync(sc->sc_dmat, bmap->map, 783 0, bmap->map->dm_mapsize, 784 BUS_DMASYNC_POSTWRITE); 785 bus_dmamap_unload(sc->sc_dmat, bmap->map); 786 m_freem(bmap->mbuf); 787 bmap->mbuf = NULL; 788 ++pkts; 789 } 790 791 eqos_setup_txdesc(sc, i, 0, 0, 0, 0); 792 eqos_dma_sync(sc, sc->sc_tx.desc_map, 793 i, i + 1, TX_DESC_COUNT, 794 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 795 796 ifp->if_flags &= ~IFF_OACTIVE; 797 798 /* Last descriptor in a packet contains DMA status */ 799 if ((tdes3 & EQOS_TDES3_LD) != 0) { 800 if ((tdes3 & EQOS_TDES3_DE) != 0) { 801 device_printf(sc->sc_dev, 802 "TX [%u] desc error: 0x%08x\n", 803 i, tdes3); 804 if_statinc(ifp, if_oerrors); 805 } else if ((tdes3 & EQOS_TDES3_ES) != 0) { 806 device_printf(sc->sc_dev, 807 "TX [%u] tx error: 0x%08x\n", 808 i, tdes3); 809 if_statinc(ifp, if_oerrors); 810 } else { 811 if_statinc(ifp, if_opackets); 812 } 813 } 814 815 } 816 817 sc->sc_tx.next = i; 818 819 if (pkts != 0) { 820 rnd_add_uint32(&sc->sc_rndsource, pkts); 821 } 822 } 823 824 static void 825 eqos_start_locked(struct eqos_softc *sc) 826 { 827 struct ifnet *ifp = &sc->sc_ec.ec_if; 828 struct mbuf *m; 829 int cnt, nsegs, start; 830 831 EQOS_ASSERT_TXLOCKED(sc); 832 833 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 834 return; 835 836 for (cnt = 0, start = sc->sc_tx.cur; ; cnt++) { 837 if (sc->sc_tx.queued >= TX_DESC_COUNT - TX_MAX_SEGS) { 838 ifp->if_flags |= IFF_OACTIVE; 839 break; 840 } 841 842 IFQ_POLL(&ifp->if_snd, m); 843 if (m == NULL) { 844 break; 845 } 846 847 nsegs = eqos_setup_txbuf(sc, sc->sc_tx.cur, m); 848 if (nsegs <= 0) { 849 if (nsegs == -1) { 850 ifp->if_flags |= IFF_OACTIVE; 851 } else if (nsegs == -2) { 852 IFQ_DEQUEUE(&ifp->if_snd, m); 853 m_freem(m); 854 } 855 break; 856 } 857 858 IFQ_DEQUEUE(&ifp->if_snd, m); 859 bpf_mtap(ifp, m, BPF_D_OUT); 860 861 sc->sc_tx.cur = TX_SKIP(sc->sc_tx.cur, nsegs); 862 } 863 864 if (cnt != 0) { 865 eqos_dma_sync(sc, sc->sc_tx.desc_map, 866 start, sc->sc_tx.cur, TX_DESC_COUNT, 867 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 868 869 /* Start and run TX DMA */ 870 WR4(sc, GMAC_DMA_CHAN0_TX_END_ADDR, 871 (uint32_t)sc->sc_tx.desc_ring_paddr + 872 DESC_OFF(sc->sc_tx.cur)); 873 } 874 } 875 876 static void 877 eqos_start(struct ifnet *ifp) 878 { 879 struct eqos_softc *sc = ifp->if_softc; 880 881 EQOS_TXLOCK(sc); 882 eqos_start_locked(sc); 883 EQOS_TXUNLOCK(sc); 884 } 885 886 static void 887 eqos_intr_mtl(struct eqos_softc *sc, uint32_t mtl_status) 888 { 889 uint32_t debug_data __unused = 0, ictrl = 0; 890 891 if (mtl_status == 0) 892 return; 893 894 /* Drain the errors reported by MTL_INTERRUPT_STATUS */ 895 sc->sc_ev_mtl.ev_count++; 896 897 if ((mtl_status & GMAC_MTL_INTERRUPT_STATUS_DBGIS) != 0) { 898 debug_data = RD4(sc, GMAC_MTL_FIFO_DEBUG_DATA); 899 sc->sc_ev_mtl_debugdata.ev_count++; 900 } 901 if ((mtl_status & GMAC_MTL_INTERRUPT_STATUS_Q0IS) != 0) { 902 uint32_t new_status = 0; 903 904 ictrl = RD4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS); 905 if ((ictrl & GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS) != 0) { 906 new_status |= GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS; 907 sc->sc_ev_mtl_rxovfis.ev_count++; 908 } 909 if ((ictrl & GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS) != 0) { 910 new_status |= GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS; 911 sc->sc_ev_mtl_txovfis.ev_count++; 912 } 913 if (new_status) { 914 new_status |= (ictrl & 915 (GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE| 916 GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE)); 917 WR4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS, new_status); 918 } 919 } 920 #ifdef DEBUG_LOUD 921 device_printf(sc->sc_dev, 922 "GMAC_MTL_INTERRUPT_STATUS = 0x%08X, " 923 "GMAC_MTL_FIFO_DEBUG_DATA = 0x%08X, " 924 "GMAC_MTL_INTERRUPT_STATUS_Q0IS = 0x%08X\n", 925 mtl_status, debug_data, ictrl); 926 #endif 927 } 928 929 int 930 eqos_intr(void *arg) 931 { 932 struct eqos_softc *sc = arg; 933 struct ifnet *ifp = &sc->sc_ec.ec_if; 934 uint32_t mac_status, mtl_status, dma_status, rx_tx_status; 935 936 sc->sc_ev_intr.ev_count++; 937 938 mac_status = RD4(sc, GMAC_MAC_INTERRUPT_STATUS); 939 mac_status &= RD4(sc, GMAC_MAC_INTERRUPT_ENABLE); 940 941 if (mac_status) { 942 sc->sc_ev_mac.ev_count++; 943 #ifdef DEBUG_LOUD 944 device_printf(sc->sc_dev, 945 "GMAC_MAC_INTERRUPT_STATUS = 0x%08X\n", mac_status); 946 #endif 947 } 948 949 mtl_status = RD4(sc, GMAC_MTL_INTERRUPT_STATUS); 950 eqos_intr_mtl(sc, mtl_status); 951 952 dma_status = RD4(sc, GMAC_DMA_CHAN0_STATUS); 953 dma_status &= RD4(sc, GMAC_DMA_CHAN0_INTR_ENABLE); 954 if (dma_status) { 955 WR4(sc, GMAC_DMA_CHAN0_STATUS, dma_status); 956 } 957 958 EQOS_LOCK(sc); 959 if ((dma_status & GMAC_DMA_CHAN0_STATUS_RI) != 0) { 960 eqos_rxintr(sc, 0); 961 sc->sc_ev_rxintr.ev_count++; 962 } 963 964 if ((dma_status & GMAC_DMA_CHAN0_STATUS_TI) != 0) { 965 eqos_txintr(sc, 0); 966 if_schedule_deferred_start(ifp); 967 sc->sc_ev_txintr.ev_count++; 968 } 969 EQOS_UNLOCK(sc); 970 971 #ifdef DEBUG_LOUD 972 if ((mac_status | mtl_status | dma_status) == 0) { 973 device_printf(sc->sc_dev, "spurious interrupt?!\n"); 974 } 975 #endif 976 977 rx_tx_status = RD4(sc, GMAC_MAC_RX_TX_STATUS); 978 if (rx_tx_status) { 979 sc->sc_ev_status.ev_count++; 980 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_RWT) != 0) 981 sc->sc_ev_rwt.ev_count++; 982 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_EXCOL) != 0) 983 sc->sc_ev_excol.ev_count++; 984 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_LCOL) != 0) 985 sc->sc_ev_lcol.ev_count++; 986 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_EXDEF) != 0) 987 sc->sc_ev_exdef.ev_count++; 988 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_LCARR) != 0) 989 sc->sc_ev_lcarr.ev_count++; 990 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_NCARR) != 0) 991 sc->sc_ev_ncarr.ev_count++; 992 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_TJT) != 0) 993 sc->sc_ev_tjt.ev_count++; 994 #ifdef DEBUG_LOUD 995 device_printf(sc->sc_dev, "GMAC_MAC_RX_TX_STATUS = 0x%08x\n", 996 rx_tx_status); 997 #endif 998 } 999 1000 return 1; 1001 } 1002 1003 static int 1004 eqos_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1005 { 1006 struct eqos_softc *sc = ifp->if_softc; 1007 int error, s; 1008 1009 #ifndef EQOS_MPSAFE 1010 s = splnet(); 1011 #endif 1012 1013 switch (cmd) { 1014 default: 1015 #ifdef EQOS_MPSAFE 1016 s = splnet(); 1017 #endif 1018 error = ether_ioctl(ifp, cmd, data); 1019 #ifdef EQOS_MPSAFE 1020 splx(s); 1021 #endif 1022 if (error != ENETRESET) 1023 break; 1024 1025 error = 0; 1026 1027 if (cmd == SIOCSIFCAP) 1028 error = (*ifp->if_init)(ifp); 1029 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1030 ; 1031 else if ((ifp->if_flags & IFF_RUNNING) != 0) { 1032 EQOS_LOCK(sc); 1033 eqos_setup_rxfilter(sc); 1034 EQOS_UNLOCK(sc); 1035 } 1036 break; 1037 } 1038 1039 #ifndef EQOS_MPSAFE 1040 splx(s); 1041 #endif 1042 1043 return error; 1044 } 1045 1046 static void 1047 eqos_get_eaddr(struct eqos_softc *sc, uint8_t *eaddr) 1048 { 1049 prop_dictionary_t prop = device_properties(sc->sc_dev); 1050 uint32_t maclo, machi; 1051 prop_data_t eaprop; 1052 1053 eaprop = prop_dictionary_get(prop, "mac-address"); 1054 if (eaprop != NULL) { 1055 KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA); 1056 KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN); 1057 memcpy(eaddr, prop_data_value(eaprop), 1058 ETHER_ADDR_LEN); 1059 return; 1060 } 1061 1062 maclo = htobe32(RD4(sc, GMAC_MAC_ADDRESS0_LOW)); 1063 machi = htobe16(RD4(sc, GMAC_MAC_ADDRESS0_HIGH) & 0xFFFF); 1064 1065 if (maclo == 0xFFFFFFFF && machi == 0xFFFF) { 1066 /* Create one */ 1067 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 1068 machi = cprng_strong32() & 0xffff; 1069 } 1070 1071 eaddr[0] = maclo & 0xff; 1072 eaddr[1] = (maclo >> 8) & 0xff; 1073 eaddr[2] = (maclo >> 16) & 0xff; 1074 eaddr[3] = (maclo >> 24) & 0xff; 1075 eaddr[4] = machi & 0xff; 1076 eaddr[5] = (machi >> 8) & 0xff; 1077 } 1078 1079 static void 1080 eqos_axi_configure(struct eqos_softc *sc) 1081 { 1082 prop_dictionary_t prop = device_properties(sc->sc_dev); 1083 uint32_t val; 1084 u_int uival; 1085 bool bval; 1086 1087 val = RD4(sc, GMAC_DMA_SYSBUS_MODE); 1088 if (prop_dictionary_get_bool(prop, "snps,mixed-burst", &bval) && bval) { 1089 val |= GMAC_DMA_SYSBUS_MODE_MB; 1090 } 1091 if (prop_dictionary_get_bool(prop, "snps,fixed-burst", &bval) && bval) { 1092 val |= GMAC_DMA_SYSBUS_MODE_FB; 1093 } 1094 if (prop_dictionary_get_uint(prop, "snps,wr_osr_lmt", &uival)) { 1095 val &= ~GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK; 1096 val |= uival << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT; 1097 } 1098 if (prop_dictionary_get_uint(prop, "snps,rd_osr_lmt", &uival)) { 1099 val &= ~GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK; 1100 val |= uival << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT; 1101 } 1102 1103 if (!EQOS_HW_FEATURE_ADDR64_32BIT(sc)) { 1104 val |= GMAC_DMA_SYSBUS_MODE_EAME; 1105 } 1106 1107 /* XXX */ 1108 val |= GMAC_DMA_SYSBUS_MODE_BLEN16; 1109 val |= GMAC_DMA_SYSBUS_MODE_BLEN8; 1110 val |= GMAC_DMA_SYSBUS_MODE_BLEN4; 1111 1112 WR4(sc, GMAC_DMA_SYSBUS_MODE, val); 1113 } 1114 1115 static int 1116 eqos_setup_dma(struct eqos_softc *sc, int qid) 1117 { 1118 struct mbuf *m; 1119 int error, nsegs, i; 1120 1121 /* Setup TX ring */ 1122 error = bus_dmamap_create(sc->sc_dmat, TX_DESC_SIZE, 1, TX_DESC_SIZE, 1123 DESC_BOUNDARY, BUS_DMA_WAITOK, &sc->sc_tx.desc_map); 1124 if (error) { 1125 return error; 1126 } 1127 error = bus_dmamem_alloc(sc->sc_dmat, TX_DESC_SIZE, DESC_ALIGN, 1128 DESC_BOUNDARY, &sc->sc_tx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1129 if (error) { 1130 return error; 1131 } 1132 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_tx.desc_dmaseg, nsegs, 1133 TX_DESC_SIZE, (void *)&sc->sc_tx.desc_ring, BUS_DMA_WAITOK); 1134 if (error) { 1135 return error; 1136 } 1137 error = bus_dmamap_load(sc->sc_dmat, sc->sc_tx.desc_map, 1138 sc->sc_tx.desc_ring, TX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1139 if (error) { 1140 return error; 1141 } 1142 sc->sc_tx.desc_ring_paddr = sc->sc_tx.desc_map->dm_segs[0].ds_addr; 1143 1144 memset(sc->sc_tx.desc_ring, 0, TX_DESC_SIZE); 1145 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx.desc_map, 0, TX_DESC_SIZE, 1146 BUS_DMASYNC_PREWRITE); 1147 1148 sc->sc_tx.queued = TX_DESC_COUNT; 1149 for (i = 0; i < TX_DESC_COUNT; i++) { 1150 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1151 TX_MAX_SEGS, MCLBYTES, 0, BUS_DMA_WAITOK, 1152 &sc->sc_tx.buf_map[i].map); 1153 if (error != 0) { 1154 device_printf(sc->sc_dev, 1155 "cannot create TX buffer map\n"); 1156 return error; 1157 } 1158 eqos_setup_txdesc(sc, i, 0, 0, 0, 0); 1159 } 1160 1161 /* Setup RX ring */ 1162 error = bus_dmamap_create(sc->sc_dmat, RX_DESC_SIZE, 1, RX_DESC_SIZE, 1163 DESC_BOUNDARY, BUS_DMA_WAITOK, &sc->sc_rx.desc_map); 1164 if (error) { 1165 return error; 1166 } 1167 error = bus_dmamem_alloc(sc->sc_dmat, RX_DESC_SIZE, DESC_ALIGN, 1168 DESC_BOUNDARY, &sc->sc_rx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1169 if (error) { 1170 return error; 1171 } 1172 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_rx.desc_dmaseg, nsegs, 1173 RX_DESC_SIZE, (void *)&sc->sc_rx.desc_ring, BUS_DMA_WAITOK); 1174 if (error) { 1175 return error; 1176 } 1177 error = bus_dmamap_load(sc->sc_dmat, sc->sc_rx.desc_map, 1178 sc->sc_rx.desc_ring, RX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1179 if (error) { 1180 return error; 1181 } 1182 sc->sc_rx.desc_ring_paddr = sc->sc_rx.desc_map->dm_segs[0].ds_addr; 1183 1184 memset(sc->sc_rx.desc_ring, 0, RX_DESC_SIZE); 1185 1186 for (i = 0; i < RX_DESC_COUNT; i++) { 1187 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1188 RX_DESC_COUNT, MCLBYTES, 0, BUS_DMA_WAITOK, 1189 &sc->sc_rx.buf_map[i].map); 1190 if (error != 0) { 1191 device_printf(sc->sc_dev, 1192 "cannot create RX buffer map\n"); 1193 return error; 1194 } 1195 if ((m = eqos_alloc_mbufcl(sc)) == NULL) { 1196 device_printf(sc->sc_dev, "cannot allocate RX mbuf\n"); 1197 return ENOMEM; 1198 } 1199 error = eqos_setup_rxbuf(sc, i, m); 1200 if (error != 0) { 1201 device_printf(sc->sc_dev, "cannot create RX buffer\n"); 1202 return error; 1203 } 1204 } 1205 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx.desc_map, 1206 0, sc->sc_rx.desc_map->dm_mapsize, 1207 BUS_DMASYNC_PREWRITE); 1208 1209 aprint_debug_dev(sc->sc_dev, "TX ring @ 0x%lX, RX ring @ 0x%lX\n", 1210 sc->sc_tx.desc_ring_paddr, sc->sc_rx.desc_ring_paddr); 1211 1212 return 0; 1213 } 1214 1215 int 1216 eqos_attach(struct eqos_softc *sc) 1217 { 1218 struct mii_data *mii = &sc->sc_mii; 1219 struct ifnet *ifp = &sc->sc_ec.ec_if; 1220 uint8_t eaddr[ETHER_ADDR_LEN]; 1221 u_int userver, snpsver; 1222 int mii_flags = 0; 1223 int error; 1224 int n; 1225 1226 const uint32_t ver = RD4(sc, GMAC_MAC_VERSION); 1227 userver = (ver & GMAC_MAC_VERSION_USERVER_MASK) >> 1228 GMAC_MAC_VERSION_USERVER_SHIFT; 1229 snpsver = ver & GMAC_MAC_VERSION_SNPSVER_MASK; 1230 1231 if (snpsver != 0x51) { 1232 aprint_error(": EQOS version 0x%02xx not supported\n", 1233 snpsver); 1234 return ENXIO; 1235 } 1236 1237 if (sc->sc_csr_clock < 20000000) { 1238 aprint_error(": CSR clock too low\n"); 1239 return EINVAL; 1240 } else if (sc->sc_csr_clock < 35000000) { 1241 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_20_35; 1242 } else if (sc->sc_csr_clock < 60000000) { 1243 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_35_60; 1244 } else if (sc->sc_csr_clock < 100000000) { 1245 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_60_100; 1246 } else if (sc->sc_csr_clock < 150000000) { 1247 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_100_150; 1248 } else if (sc->sc_csr_clock < 250000000) { 1249 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_150_250; 1250 } else if (sc->sc_csr_clock < 300000000) { 1251 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_300_500; 1252 } else if (sc->sc_csr_clock < 800000000) { 1253 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_500_800; 1254 } else { 1255 aprint_error(": CSR clock too high\n"); 1256 return EINVAL; 1257 } 1258 1259 for (n = 0; n < 4; n++) { 1260 sc->sc_hw_feature[n] = RD4(sc, GMAC_MAC_HW_FEATURE(n)); 1261 } 1262 1263 aprint_naive("\n"); 1264 aprint_normal(": DesignWare EQOS ver 0x%02x (0x%02x)\n", 1265 snpsver, userver); 1266 aprint_verbose_dev(sc->sc_dev, "hw features %08x %08x %08x %08x\n", 1267 sc->sc_hw_feature[0], sc->sc_hw_feature[1], 1268 sc->sc_hw_feature[2], sc->sc_hw_feature[3]); 1269 1270 if (EQOS_HW_FEATURE_ADDR64_32BIT(sc)) { 1271 bus_dma_tag_t ntag; 1272 1273 error = bus_dmatag_subregion(sc->sc_dmat, 0, UINT32_MAX, 1274 &ntag, 0); 1275 if (error) { 1276 aprint_error_dev(sc->sc_dev, 1277 "failed to restrict DMA: %d\n", error); 1278 return error; 1279 } 1280 aprint_verbose_dev(sc->sc_dev, "using 32-bit DMA\n"); 1281 sc->sc_dmat = ntag; 1282 } 1283 1284 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NET); 1285 mutex_init(&sc->sc_txlock, MUTEX_DEFAULT, IPL_NET); 1286 callout_init(&sc->sc_stat_ch, CALLOUT_FLAGS); 1287 callout_setfunc(&sc->sc_stat_ch, eqos_tick, sc); 1288 1289 eqos_get_eaddr(sc, eaddr); 1290 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", ether_sprintf(eaddr)); 1291 1292 /* Soft reset EMAC core */ 1293 error = eqos_reset(sc); 1294 if (error != 0) { 1295 return error; 1296 } 1297 1298 /* Configure AXI Bus mode parameters */ 1299 eqos_axi_configure(sc); 1300 1301 /* Setup DMA descriptors */ 1302 if (eqos_setup_dma(sc, 0) != 0) { 1303 aprint_error_dev(sc->sc_dev, "failed to setup DMA descriptors\n"); 1304 return EINVAL; 1305 } 1306 1307 /* Setup ethernet interface */ 1308 ifp->if_softc = sc; 1309 snprintf(ifp->if_xname, IFNAMSIZ, "%s", device_xname(sc->sc_dev)); 1310 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1311 #ifdef EQOS_MPSAFE 1312 ifp->if_extflags = IFEF_MPSAFE; 1313 #endif 1314 ifp->if_start = eqos_start; 1315 ifp->if_ioctl = eqos_ioctl; 1316 ifp->if_init = eqos_init; 1317 ifp->if_stop = eqos_stop; 1318 ifp->if_capabilities = 0; 1319 ifp->if_capenable = ifp->if_capabilities; 1320 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 1321 IFQ_SET_READY(&ifp->if_snd); 1322 1323 /* 802.1Q VLAN-sized frames are supported */ 1324 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1325 1326 /* Attach MII driver */ 1327 sc->sc_ec.ec_mii = mii; 1328 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1329 mii->mii_ifp = ifp; 1330 mii->mii_readreg = eqos_mii_readreg; 1331 mii->mii_writereg = eqos_mii_writereg; 1332 mii->mii_statchg = eqos_mii_statchg; 1333 mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id, MII_OFFSET_ANY, 1334 mii_flags); 1335 1336 if (LIST_EMPTY(&mii->mii_phys)) { 1337 aprint_error_dev(sc->sc_dev, "no PHY found!\n"); 1338 return ENOENT; 1339 } 1340 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1341 1342 /* Master interrupt evcnt */ 1343 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 1344 NULL, device_xname(sc->sc_dev), "interrupts"); 1345 1346 /* Per-interrupt type, using main interrupt */ 1347 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1348 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rxintr"); 1349 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 1350 &sc->sc_ev_intr, device_xname(sc->sc_dev), "txintr"); 1351 evcnt_attach_dynamic(&sc->sc_ev_mac, EVCNT_TYPE_INTR, 1352 &sc->sc_ev_intr, device_xname(sc->sc_dev), "macstatus"); 1353 evcnt_attach_dynamic(&sc->sc_ev_mtl, EVCNT_TYPE_INTR, 1354 &sc->sc_ev_intr, device_xname(sc->sc_dev), "intrstatus"); 1355 evcnt_attach_dynamic(&sc->sc_ev_status, EVCNT_TYPE_INTR, 1356 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rxtxstatus"); 1357 1358 /* MAC Status specific type, using macstatus interrupt */ 1359 evcnt_attach_dynamic(&sc->sc_ev_mtl_debugdata, EVCNT_TYPE_INTR, 1360 &sc->sc_ev_mtl, device_xname(sc->sc_dev), "debugdata"); 1361 evcnt_attach_dynamic(&sc->sc_ev_mtl_rxovfis, EVCNT_TYPE_INTR, 1362 &sc->sc_ev_mtl, device_xname(sc->sc_dev), "rxovfis"); 1363 evcnt_attach_dynamic(&sc->sc_ev_mtl_txovfis, EVCNT_TYPE_INTR, 1364 &sc->sc_ev_mtl, device_xname(sc->sc_dev), "txovfis"); 1365 1366 /* RX/TX Status specific type, using rxtxstatus interrupt */ 1367 evcnt_attach_dynamic(&sc->sc_ev_rwt, EVCNT_TYPE_INTR, 1368 &sc->sc_ev_status, device_xname(sc->sc_dev), "rwt"); 1369 evcnt_attach_dynamic(&sc->sc_ev_excol, EVCNT_TYPE_INTR, 1370 &sc->sc_ev_status, device_xname(sc->sc_dev), "excol"); 1371 evcnt_attach_dynamic(&sc->sc_ev_lcol, EVCNT_TYPE_INTR, 1372 &sc->sc_ev_status, device_xname(sc->sc_dev), "lcol"); 1373 evcnt_attach_dynamic(&sc->sc_ev_exdef, EVCNT_TYPE_INTR, 1374 &sc->sc_ev_status, device_xname(sc->sc_dev), "exdef"); 1375 evcnt_attach_dynamic(&sc->sc_ev_lcarr, EVCNT_TYPE_INTR, 1376 &sc->sc_ev_status, device_xname(sc->sc_dev), "lcarr"); 1377 evcnt_attach_dynamic(&sc->sc_ev_ncarr, EVCNT_TYPE_INTR, 1378 &sc->sc_ev_status, device_xname(sc->sc_dev), "ncarr"); 1379 evcnt_attach_dynamic(&sc->sc_ev_tjt, EVCNT_TYPE_INTR, 1380 &sc->sc_ev_status, device_xname(sc->sc_dev), "tjt"); 1381 1382 /* Attach interface */ 1383 if_attach(ifp); 1384 if_deferred_start_init(ifp, NULL); 1385 1386 /* Attach ethernet interface */ 1387 ether_ifattach(ifp, eaddr); 1388 1389 rnd_attach_source(&sc->sc_rndsource, ifp->if_xname, RND_TYPE_NET, 1390 RND_FLAG_DEFAULT); 1391 1392 return 0; 1393 } 1394