1 /* $NetBSD: dm9000.c,v 1.2 2010/09/10 08:58:36 ahoka Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Paul Fleischer 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* based on sys/dev/ic/cs89x0.c */ 30 /* 31 * Copyright (c) 2004 Christopher Gilbert 32 * All rights reserved. 33 * 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 3. The name of the company nor the name of the author may be used to 40 * endorse or promote products derived from this software without specific 41 * prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 46 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 51 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 52 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 53 * SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright 1997 58 * Digital Equipment Corporation. All rights reserved. 59 * 60 * This software is furnished under license and may be used and 61 * copied only in accordance with the following terms and conditions. 62 * Subject to these conditions, you may download, copy, install, 63 * use, modify and distribute this software in source and/or binary 64 * form. No title or ownership is transferred hereby. 65 * 66 * 1) Any source code used, modified or distributed must reproduce 67 * and retain this copyright notice and list of conditions as 68 * they appear in the source file. 69 * 70 * 2) No right is granted to use any trade name, trademark, or logo of 71 * Digital Equipment Corporation. Neither the "Digital Equipment 72 * Corporation" name nor any trademark or logo of Digital Equipment 73 * Corporation may be used to endorse or promote products derived 74 * from this software without the prior written permission of 75 * Digital Equipment Corporation. 76 * 77 * 3) This software is provided "AS-IS" and any express or implied 78 * warranties, including but not limited to, any implied warranties 79 * of merchantability, fitness for a particular purpose, or 80 * non-infringement are disclaimed. In no event shall DIGITAL be 81 * liable for any damages whatsoever, and in particular, DIGITAL 82 * shall not be liable for special, indirect, consequential, or 83 * incidental damages or damages for lost profits, loss of 84 * revenue or loss of use, whether such damages arise in contract, 85 * negligence, tort, under statute, in equity, at law or otherwise, 86 * even if advised of the possibility of such damage. 87 */ 88 89 #include <sys/cdefs.h> 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/mbuf.h> 94 #include <sys/syslog.h> 95 #include <sys/socket.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 #include <sys/ioctl.h> 99 #include <sys/errno.h> 100 101 #include <net/if.h> 102 #include <net/if_ether.h> 103 #include <net/if_media.h> 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/if_inarp.h> 107 #endif 108 109 #include <net/bpf.h> 110 #include <net/bpfdesc.h> 111 112 #include <sys/bus.h> 113 #include <sys/intr.h> 114 115 #include <dev/ic/dm9000var.h> 116 #include <dev/ic/dm9000reg.h> 117 118 #if 1 119 #undef DM9000_DEBUG 120 #undef DM9000_TX_DEBUG 121 #undef DM9000_TX_DATA_DEBUG 122 #undef DM9000_RX_DEBUG 123 #undef DM9000_RX_DATA_DEBUG 124 #else 125 #define DM9000_DEBUG 126 #define DM9000_TX_DEBUG 127 #define DM9000_TX_DATA_DEBUG 128 #define DM9000_RX_DEBUG 129 #define DM9000_RX_DATA_DEBUG 130 #endif 131 132 #ifdef DM9000_DEBUG 133 #define DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 134 #else 135 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 136 #endif 137 138 #ifdef DM9000_TX_DEBUG 139 #define TX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 140 #else 141 #define TX_DPRINTF(s) do {} while (/*CONSTCOND*/0) 142 #endif 143 144 #ifdef DM9000_RX_DEBUG 145 #define RX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 146 #else 147 #define RX_DPRINTF(s) do {} while (/*CONSTCOND*/0) 148 #endif 149 150 #ifdef DM9000_RX_DATA_DEBUG 151 #define RX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 152 #else 153 #define RX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0) 154 #endif 155 156 #ifdef DM9000_TX_DATA_DEBUG 157 #define TX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 158 #else 159 #define TX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0) 160 #endif 161 162 163 uint16_t dme_phy_read(struct dme_softc *sc, int reg); 164 void dme_phy_write(struct dme_softc *sc, int reg, uint16_t value); 165 166 /*** Methods registered in struct ifnet ***/ 167 void dme_start_output(struct ifnet *ifp); 168 int dme_init(struct ifnet *ifp); 169 int dme_ioctl(struct ifnet *ifp, u_long cmd, void *data); 170 void dme_stop(struct ifnet *ifp, int disable); 171 172 int dme_mediachange(struct ifnet *ifp); 173 void dme_mediastatus(struct ifnet *ufp, struct ifmediareq *ifmr); 174 175 /*** Internal methods ***/ 176 177 /* Prepare data to be transmitted (i.e. dequeue and load it into the DM9000) */ 178 void dme_prepare(struct dme_softc *sc, struct ifnet *ifp); 179 180 /* Transmit prepared data */ 181 void dme_transmit(struct dme_softc *sc); 182 183 /* Receive data */ 184 void dme_receive(struct dme_softc *sc, struct ifnet *ifp); 185 186 /* Software Initialize/Reset of the DM9000 */ 187 void dme_reset(struct dme_softc *sc); 188 189 uint16_t 190 dme_phy_read(struct dme_softc *sc, int reg) 191 { 192 uint16_t val; 193 /* Select Register to read*/ 194 dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY + 195 (reg & DM9000_EPAR_EROA_MASK)); 196 /* Select read operation (DM9000_EPCR_ERPRR) from the PHY */ 197 dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRR + DM9000_EPCR_EPOS_PHY); 198 199 /* Wait until access to PHY has completed */ 200 while (dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE); 201 202 /* XXX: The delay is probably not necessary as we just busy-waited */ 203 delay(200); 204 205 /* Reset ERPRR-bit */ 206 dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY); 207 208 val = dme_read(sc, DM9000_EPDRL); 209 val += dme_read(sc, DM9000_EPDRH) << 8; 210 211 return val; 212 } 213 214 void 215 dme_phy_write(struct dme_softc *sc, int reg, uint16_t value) 216 { 217 /* Select Register to write*/ 218 dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY + 219 (reg & DM9000_EPAR_EROA_MASK)); 220 221 /* Write data to the two data registers */ 222 dme_write(sc, DM9000_EPDRL, value & 0xFF); 223 dme_write(sc, DM9000_EPDRH, (value >> 8) & 0xFF); 224 225 /* Select write operation (DM9000_EPCR_ERPRW) from the PHY */ 226 dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRW + DM9000_EPCR_EPOS_PHY); 227 228 /* Wait until access to PHY has completed */ 229 while(dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE); 230 231 232 /* XXX: The delay is probably not necessary as we just busy-waited */ 233 delay(200); 234 235 /* Reset ERPRR-bit */ 236 dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY); 237 } 238 239 int 240 dme_attach(struct dme_softc *sc, uint8_t *enaddr) 241 { 242 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 243 uint8_t b[2]; 244 245 dme_read_c(sc, DM9000_VID0, b, 2); 246 #if BYTE_ORDER == BIG_ENDIAN 247 sc->sc_vendor_id = (b[0] << 8) | b[1]; 248 #else 249 sc->sc_vendor_id = b[0] | (b[1] << 8); 250 #endif 251 dme_read_c(sc, DM9000_PID0, b, 2); 252 #if BYTE_ORDER == BIG_ENDIAN 253 sc->sc_product_id = (b[0] << 8) | b[1]; 254 #else 255 sc->sc_product_id = b[0] | (b[1] << 8); 256 #endif 257 /* TODO: Check the vendor ID as well */ 258 if (sc->sc_product_id != 0x9000) { 259 panic("dme_attach: product id mismatch (0x%hx != 0x9000)", 260 sc->sc_product_id); 261 } 262 263 #if 0 264 { 265 /* Force 10Mbps to test dme_phy_write */ 266 uint16_t bmcr; 267 bmcr = dme_phy_read(sc, DM9000_PHY_BMCR); 268 bmcr &= ~DM9000_PHY_BMCR_AUTO_NEG_EN; 269 bmcr &= ~DM9000_PHY_BMCR_SPEED_SELECT; /* select 100Mbps */ 270 dme_phy_write(sc, DM9000_PHY_BMCR, bmcr); 271 } 272 #endif 273 /* Initialize ifnet structure. */ 274 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 275 ifp->if_softc = sc; 276 ifp->if_start = dme_start_output; 277 ifp->if_init = dme_init; 278 ifp->if_ioctl = dme_ioctl; 279 ifp->if_stop = dme_stop; 280 ifp->if_watchdog = NULL; /* no watchdog at this stage */ 281 ifp->if_flags = IFF_SIMPLEX | IFF_NOTRAILERS | 282 IFF_BROADCAST; /* No multicast support for now */ 283 IFQ_SET_READY(&ifp->if_snd); 284 285 /* Initialize ifmedia structures. */ 286 ifmedia_init(&sc->sc_media, 0, dme_mediachange, dme_mediastatus); 287 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_100_TX, 0, NULL); 288 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_100_TX); 289 290 if (enaddr != NULL) 291 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 292 293 /* Configure DM9000 with the MAC address */ 294 dme_write_c(sc, DM9000_PAB0, sc->sc_enaddr, 6); 295 296 #ifdef DM9000_DEBUG 297 { 298 uint8_t macAddr[6]; 299 dme_read_c(sc, DM9000_PAB0, macAddr, 6); 300 printf("DM9000 configured with MAC address: "); 301 for (int i = 0; i < 6; i++) { 302 printf("%02X:", macAddr[i]); 303 } 304 printf("\n"); 305 } 306 #endif 307 308 if_attach(ifp); 309 ether_ifattach(ifp, sc->sc_enaddr); 310 311 #ifdef DM9000_DEBUG 312 { 313 uint8_t network_state; 314 network_state = dme_read(sc, DM9000_NSR); 315 printf("DM9000 Link status: "); 316 if (network_state & DM9000_NSR_LINKST) { 317 if (network_state & DM9000_NSR_SPEED) 318 printf("10Mbps"); 319 else 320 printf("100Mbps"); 321 } else { 322 printf("Down"); 323 } 324 printf("\n"); 325 } 326 #endif 327 328 sc->io_mode = (dme_read(sc, DM9000_ISR) & 329 DM9000_IOMODE_MASK) >> DM9000_IOMODE_SHIFT; 330 if (sc->io_mode != DM9000_MODE_16BIT ) 331 panic("DM9000: Only 16-bit mode is supported!\n"); 332 #ifdef DM9000_DEBUG 333 printf("DM9000 Operation Mode: "); 334 switch( sc->io_mode) { 335 case DM9000_MODE_16BIT: 336 printf("16-bit mode"); 337 break; 338 case DM9000_MODE_32BIT: 339 printf("32-bit mode"); 340 break; 341 case DM9000_MODE_8BIT: 342 printf("8-bit mode"); 343 break; 344 case 3: 345 printf("Invalid mode"); 346 break; 347 } 348 printf("\n"); 349 #endif 350 351 return 0; 352 } 353 354 int dme_intr(void *arg) 355 { 356 struct dme_softc *sc = arg; 357 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 358 uint8_t status; 359 360 /* Disable interrupts */ 361 dme_write(sc, DM9000_IMR, DM9000_IMR_PAR ); 362 363 status = dme_read(sc, DM9000_ISR); 364 dme_write(sc, DM9000_ISR, status); 365 366 if (status & DM9000_ISR_PRS) { 367 if (ifp->if_flags & IFF_RUNNING ) 368 dme_receive(sc, ifp); 369 } 370 if (status & DM9000_ISR_PTS) { 371 uint8_t nsr; 372 uint8_t tx_status = 0x01; /* Initialize to an error value */ 373 374 /* A packet has been transmitted */ 375 sc->txbusy = 0; 376 377 nsr = dme_read(sc, DM9000_NSR); 378 379 if (nsr & DM9000_NSR_TX1END) { 380 tx_status = dme_read(sc, DM9000_TSR1); 381 TX_DPRINTF(("dme_intr: Sent using channel 0\n")); 382 } else if (nsr & DM9000_NSR_TX2END) { 383 tx_status = dme_read(sc, DM9000_TSR2); 384 TX_DPRINTF(("dme_intr: Sent using channel 1\n")); 385 } 386 387 if (tx_status == 0x0) { 388 /* Frame successfully sent */ 389 ifp->if_opackets++; 390 } else { 391 ifp->if_oerrors++; 392 } 393 394 /* If we have nothing ready to transmit, prepare something */ 395 if (!sc->txready) { 396 dme_prepare(sc, ifp); 397 } 398 399 if (sc->txready) 400 dme_transmit(sc); 401 402 /* Prepare the next frame */ 403 dme_prepare(sc, ifp); 404 405 } 406 #ifdef notyet 407 if (status & DM9000_ISR_LNKCHNG) { 408 } 409 #endif 410 411 /* Enable interrupts again */ 412 dme_write(sc, DM9000_IMR, DM9000_IMR_PAR | DM9000_IMR_PRM | 413 DM9000_IMR_PTM); 414 415 return 1; 416 } 417 418 void 419 dme_start_output(struct ifnet *ifp) 420 { 421 struct dme_softc *sc; 422 423 sc = ifp->if_softc; 424 425 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 426 printf("No output\n"); 427 return; 428 } 429 430 if (sc->txbusy && sc->txready) { 431 panic("DM9000: Internal error, trying to send without" 432 " any empty queue\n"); 433 } 434 435 dme_prepare(sc, ifp); 436 437 if (sc->txbusy == 0) { 438 /* We are ready to transmit right away */ 439 dme_transmit(sc); 440 dme_prepare(sc, ifp); /* Prepare next one */ 441 } else { 442 /* We need to wait until the current packet has 443 * been transmitted. 444 */ 445 ifp->if_flags |= IFF_OACTIVE; 446 } 447 } 448 449 void 450 dme_prepare(struct dme_softc *sc, struct ifnet *ifp) 451 { 452 struct mbuf *buf; 453 struct mbuf *bufChain; 454 uint16_t length; 455 uint8_t *write_ptr; 456 457 TX_DPRINTF(("dme_prepare: Entering\n")); 458 459 if (sc->txready) 460 panic("dme_prepare: Someone called us with txready set\n"); 461 462 IFQ_DEQUEUE(&ifp->if_snd, bufChain); 463 if (bufChain == NULL) { 464 TX_DPRINTF(("dme_prepare: Nothing to transmit\n")); 465 ifp->if_flags &= ~IFF_OACTIVE; /* Clear OACTIVE bit */ 466 return; /* Nothing to transmit */ 467 } 468 469 /* Element has now been removed from the queue, so we better send it */ 470 471 if (ifp->if_bpf) 472 bpf_mtap(ifp, bufChain); 473 474 475 length = 0; 476 477 /* XXX: This support 16-bit I/O mode only. */ 478 /* XXX: This code must be factored out, such that architecture 479 dependant versions can be supplied */ 480 481 int left_over_count = 0; /* Number of bytes from previous mbuf, which 482 need to be written with the next.*/ 483 uint16_t left_over_buf = 0; 484 485 /* Setup the DM9000 to accept the writes, and then write each buf in 486 the chain. */ 487 488 TX_DATA_DPRINTF(("dme_prepare: Writing data: ")); 489 bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, DM9000_MWCMD); 490 for (buf = bufChain; buf != NULL; buf = buf->m_next) { 491 int to_write = buf->m_len; 492 493 length += to_write; 494 495 write_ptr = buf->m_data; 496 while (to_write > 0 || 497 (buf->m_next == NULL && left_over_count > 0) 498 ) { 499 if (left_over_count > 0) { 500 uint8_t b = 0; 501 DPRINTF(("dme_prepare: " 502 "Writing left over byte\n")); 503 504 if (to_write > 0) { 505 b = *write_ptr; 506 to_write--; 507 write_ptr++; 508 509 DPRINTF(("Took single byte\n")); 510 } else { 511 DPRINTF(("Leftover in last run\n")); 512 length++; 513 } 514 515 /* Does shift direction depend on endianess? */ 516 left_over_buf = left_over_buf | (b << 8); 517 518 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 519 sc->dme_data, left_over_buf); 520 TX_DATA_DPRINTF(("%02X ", left_over_buf)); 521 left_over_count = 0; 522 } else if ((long)write_ptr % 2 != 0) { 523 /* Misaligned data */ 524 DPRINTF(("dme_prepare: " 525 "Detected misaligned data\n")); 526 left_over_buf = *write_ptr; 527 left_over_count = 1; 528 write_ptr++; 529 to_write--; 530 } else { 531 int i; 532 uint16_t *dptr = (uint16_t*)write_ptr; 533 534 /* A block of aligned data. */ 535 for(i = 0; i < to_write/2; i++) { 536 /* buf will be half-word aligned 537 * all the time 538 */ 539 bus_space_write_2(sc->sc_iot, 540 sc->sc_ioh, sc->dme_data, *dptr); 541 TX_DATA_DPRINTF(("%02X %02X ", 542 *dptr & 0xFF, (*dptr>>8) & 0xFF)); 543 dptr++; 544 } 545 546 write_ptr += i*2; 547 if (to_write % 2 != 0) { 548 DPRINTF(("dme_prepare: " 549 "to_write %% 2: %d\n", 550 to_write % 2)); 551 left_over_count = 1; 552 /* XXX: Does this depend on 553 * the endianess? 554 */ 555 left_over_buf = *write_ptr; 556 557 write_ptr++; 558 to_write--; 559 DPRINTF(("dme_prepare: " 560 "to_write (after): %d\n", 561 to_write)); 562 DPRINTF(("dme_prepare: i*2: %d\n", 563 i*2)); 564 } 565 to_write -= i*2; 566 } 567 } /* while(...) */ 568 } /* for(...) */ 569 570 TX_DATA_DPRINTF(("\n")); 571 572 if (length % 2 == 1) { 573 panic("dme_prepare: length is not a word-length"); 574 } 575 576 sc->txready_length = length; 577 sc->txready = 1; 578 579 TX_DPRINTF(("dme_prepare: txbusy: %d\ndme_prepare: " 580 "txready: %d, txready_length: %d\n", 581 sc->txbusy, sc->txready, sc->txready_length)); 582 583 m_freem(bufChain); 584 585 TX_DPRINTF(("dme_prepare: Leaving\n")); 586 } 587 588 int 589 dme_init(struct ifnet *ifp) 590 { 591 int s; 592 struct dme_softc *sc = ifp->if_softc; 593 594 dme_stop(ifp, 0); 595 596 s = splnet(); 597 598 dme_reset(sc); 599 600 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 601 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 602 sc->sc_ethercom.ec_if.if_timer = 0; 603 604 splx(s); 605 606 return 0; 607 } 608 609 int 610 dme_ioctl(struct ifnet *ifp, u_long cmd, void *data) 611 { 612 struct dme_softc *sc = ifp->if_softc; 613 struct ifreq *ifr = data; 614 int s, error = 0; 615 616 s = splnet(); 617 618 switch(cmd) { 619 case SIOCGIFMEDIA: 620 case SIOCSIFMEDIA: 621 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 622 break; 623 default: 624 error = ether_ioctl(ifp, cmd, data); 625 break; 626 } 627 628 splx(s); 629 return error; 630 } 631 632 void 633 dme_stop(struct ifnet *ifp, int disable) 634 { 635 struct dme_softc *sc = ifp->if_softc; 636 637 /* Not quite sure what to do when called with disable == 0 */ 638 if (disable) { 639 /* Disable RX */ 640 dme_write(sc, DM9000_RCR, 0x0); 641 } 642 643 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 644 ifp->if_timer = 0; 645 } 646 647 int 648 dme_mediachange(struct ifnet *ifp) 649 { 650 /* TODO: Make this function do something useful. */ 651 return 0; 652 } 653 654 void 655 dme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 656 { 657 /* TODO: Make this function do something useful. */ 658 struct dme_softc *sc = ifp->if_softc; 659 ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media; 660 661 if (ifp->if_flags & IFF_UP) { 662 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 663 } else { 664 ifmr->ifm_status = 0; 665 } 666 } 667 668 void 669 dme_transmit(struct dme_softc *sc) 670 { 671 uint8_t status; 672 673 TX_DPRINTF(("dme_transmit: PRE: txready: %d, txbusy: %d\n", 674 sc->txready, sc->txbusy)); 675 676 dme_write(sc, DM9000_TXPLL, sc->txready_length & 0xff); 677 dme_write(sc, DM9000_TXPLH, (sc->txready_length >> 8) & 0xff ); 678 679 /* Request to send the packet */ 680 status = dme_read(sc, DM9000_ISR); 681 682 dme_write(sc, DM9000_TCR, DM9000_TCR_TXREQ); 683 684 sc->txready = 0; 685 sc->txbusy = 1; 686 sc->txready_length = 0; 687 } 688 689 void 690 dme_receive(struct dme_softc *sc, struct ifnet *ifp) 691 { 692 uint8_t ready = 0x01; 693 694 DPRINTF(("inside dme_receive\n")); 695 696 while (ready == 0x01) { 697 /* Packet received, retrieve it */ 698 699 /* Read without address increment to get the ready byte without moving past it. */ 700 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 701 sc->dme_io, DM9000_MRCMDX); 702 /* Dummy ready */ 703 ready = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 704 ready = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 705 ready &= 0x03; /* we only want bits 1:0 */ 706 if (ready == 0x01) { 707 uint8_t rx_status; 708 709 uint16_t data; 710 uint16_t frame_length; 711 uint16_t i; 712 struct mbuf *m; 713 uint16_t *buf; 714 int pad; 715 716 /* TODO: Add support for 8-bit and 717 * 32-bit transfer modes. 718 */ 719 720 /* Read with address increment. */ 721 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 722 sc->dme_io, DM9000_MRCMD); 723 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 724 sc->dme_data); 725 726 rx_status = data & 0xFF; 727 frame_length = bus_space_read_2(sc->sc_iot, 728 sc->sc_ioh, sc->dme_data); 729 730 RX_DPRINTF(("dme_receive: " 731 "rx_statux: 0x%x, frame_length: %d\n", 732 rx_status, frame_length)); 733 734 735 MGETHDR(m, M_DONTWAIT, MT_DATA); 736 m->m_pkthdr.rcvif = ifp; 737 /* Ensure that we always allocate an even number of 738 * bytes in order to avoid writing beyond the buffer 739 */ 740 m->m_pkthdr.len = frame_length + (frame_length % 2); 741 pad = ALIGN(sizeof(struct ether_header)) - 742 sizeof(struct ether_header); 743 /* All our frames have the CRC attached */ 744 m->m_flags |= M_HASFCS; 745 if (m->m_pkthdr.len + pad > MHLEN ) 746 MCLGET(m, M_DONTWAIT); 747 748 m->m_data += pad; 749 m->m_len = frame_length + (frame_length % 2); 750 buf = mtod(m, uint16_t*); 751 752 RX_DPRINTF(("dme_receive: ")); 753 754 for(i=0; i< frame_length; i+=2 ) { 755 data = bus_space_read_2(sc->sc_iot, 756 sc->sc_ioh, sc->dme_data); 757 if ( (frame_length % 2 != 0) && 758 (i == frame_length-1) ) { 759 data = data & 0xff; 760 RX_DPRINTF((" L ")); 761 } 762 *buf = data; 763 buf++; 764 RX_DATA_DPRINTF(("%02X %02X ", data & 0xff, 765 (data>>8) & 0xff)); 766 } 767 768 RX_DATA_DPRINTF(("\n")); 769 RX_DPRINTF(("Read %d bytes\n", i)); 770 771 if (rx_status & (DM9000_RSR_CE | DM9000_RSR_PLE)) { 772 /* Error while receiving the packet, 773 * discard it and keep track of counters 774 */ 775 ifp->if_ierrors++; 776 RX_DPRINTF(("dme_receive: " 777 "Error reciving packet\n")); 778 } else if (rx_status & DM9000_RSR_LCS) { 779 ifp->if_collisions++; 780 } else { 781 if (ifp->if_bpf) 782 bpf_mtap(ifp, m); 783 ifp->if_ipackets++; 784 (*ifp->if_input)(ifp, m); 785 } 786 787 } else if (ready != 0x00) { 788 /* Should this be logged somehow? */ 789 DPRINTF(("DM9000: Resetting chip\n")); 790 dme_reset(sc); 791 } 792 } 793 } 794 795 void 796 dme_reset(struct dme_softc *sc) 797 { 798 uint8_t var; 799 800 /* Enable PHY */ 801 var = dme_read(sc, DM9000_GPCR); 802 dme_write(sc, DM9000_GPCR, var | DM9000_GPCR_GPIO0_OUT); 803 var = dme_read(sc, DM9000_GPR); 804 dme_write(sc, DM9000_GPR, var & ~DM9000_GPR_PHY_PWROFF); 805 806 /* Reset the DM9000 twice, as describe din section 5.2 of the 807 * Application Notes 808 */ 809 dme_write(sc, DM9000_NCR, 810 DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL); 811 812 delay(20); 813 dme_write(sc, DM9000_NCR, 0x0); 814 dme_write(sc, DM9000_NCR, 815 DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL); 816 817 delay(20); 818 dme_write(sc, DM9000_NCR, 0x0); 819 820 /* Select internal PHY, no wakeup event, no collosion mode, 821 * normal loopback mode, and no full duplex mode 822 */ 823 dme_write(sc, DM9000_NCR, DM9000_NCR_LBK_NORMAL ); 824 825 /* Will clear TX1END, TX2END, and WAKEST fields by reading DM9000_NSR*/ 826 dme_read(sc, DM9000_NSR); 827 828 /* Enable wraparound of read/write pointer, packet received latch, 829 * and packet transmitted latch. 830 */ 831 dme_write(sc, DM9000_IMR, 832 DM9000_IMR_PAR | DM9000_IMR_PRM | DM9000_IMR_PTM); 833 834 /* Enable RX without watchdog */ 835 dme_write(sc, DM9000_RCR, DM9000_RCR_RXEN | DM9000_RCR_WTDIS); 836 837 sc->txbusy = 0; 838 sc->txready = 0; 839 } 840