1 /* $NetBSD: cs89x0.c,v 1.31 2010/04/05 07:19:33 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Christopher Gilbert 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright 1997 31 * Digital Equipment Corporation. All rights reserved. 32 * 33 * This software is furnished under license and may be used and 34 * copied only in accordance with the following terms and conditions. 35 * Subject to these conditions, you may download, copy, install, 36 * use, modify and distribute this software in source and/or binary 37 * form. No title or ownership is transferred hereby. 38 * 39 * 1) Any source code used, modified or distributed must reproduce 40 * and retain this copyright notice and list of conditions as 41 * they appear in the source file. 42 * 43 * 2) No right is granted to use any trade name, trademark, or logo of 44 * Digital Equipment Corporation. Neither the "Digital Equipment 45 * Corporation" name nor any trademark or logo of Digital Equipment 46 * Corporation may be used to endorse or promote products derived 47 * from this software without the prior written permission of 48 * Digital Equipment Corporation. 49 * 50 * 3) This software is provided "AS-IS" and any express or implied 51 * warranties, including but not limited to, any implied warranties 52 * of merchantability, fitness for a particular purpose, or 53 * non-infringement are disclaimed. In no event shall DIGITAL be 54 * liable for any damages whatsoever, and in particular, DIGITAL 55 * shall not be liable for special, indirect, consequential, or 56 * incidental damages or damages for lost profits, loss of 57 * revenue or loss of use, whether such damages arise in contract, 58 * negligence, tort, under statute, in equity, at law or otherwise, 59 * even if advised of the possibility of such damage. 60 */ 61 62 /* 63 **++ 64 ** FACILITY 65 ** 66 ** Device Driver for the Crystal CS8900 ISA Ethernet Controller. 67 ** 68 ** ABSTRACT 69 ** 70 ** This module provides standard ethernet access for INET protocols 71 ** only. 72 ** 73 ** AUTHORS 74 ** 75 ** Peter Dettori SEA - Software Engineering. 76 ** 77 ** CREATION DATE: 78 ** 79 ** 13-Feb-1997. 80 ** 81 ** MODIFICATION HISTORY (Digital): 82 ** 83 ** Revision 1.27 1998/01/20 17:59:40 cgd 84 ** update for moved headers 85 ** 86 ** Revision 1.26 1998/01/12 19:29:36 cgd 87 ** use arm32/isa versions of isadma code. 88 ** 89 ** Revision 1.25 1997/12/12 01:35:27 cgd 90 ** convert to use new arp code (from Brini) 91 ** 92 ** Revision 1.24 1997/12/10 22:31:56 cgd 93 ** trim some fat (get rid of ability to explicitly supply enet addr, since 94 ** it was never used and added a bunch of code which really doesn't belong in 95 ** an enet driver), and clean up slightly. 96 ** 97 ** Revision 1.23 1997/10/06 16:42:12 cgd 98 ** copyright notices 99 ** 100 ** Revision 1.22 1997/06/20 19:38:01 chaiken 101 ** fixes some smartcard problems 102 ** 103 ** Revision 1.21 1997/06/10 02:56:20 grohn 104 ** Added call to ledNetActive 105 ** 106 ** Revision 1.20 1997/06/05 00:47:06 dettori 107 ** Changed cs_process_rx_dma to reset and re-initialise the 108 ** ethernet chip when DMA gets out of sync, or mbufs 109 ** can't be allocated. 110 ** 111 ** Revision 1.19 1997/06/03 03:09:58 dettori 112 ** Turn off sc_txbusy flag when a transmit underrun 113 ** occurs. 114 ** 115 ** Revision 1.18 1997/06/02 00:04:35 dettori 116 ** redefined the transmit table to get around the nfs_timer bug while we are 117 ** looking into it further. 118 ** 119 ** Also changed interrupts from EDGE to LEVEL. 120 ** 121 ** Revision 1.17 1997/05/27 23:31:01 dettori 122 ** Pulled out changes to DMAMODE defines. 123 ** 124 ** Revision 1.16 1997/05/23 04:25:16 cgd 125 ** reformat log so it fits in 80cols 126 ** 127 ** Revision 1.15 1997/05/23 04:22:18 cgd 128 ** remove the existing copyright notice (which Peter Dettori indicated 129 ** was incorrect, copied from an existing NetBSD file only so that the 130 ** file would have a copyright notice on it, and which he'd intended to 131 ** replace). Replace it with a Digital copyright notice, cloned from 132 ** ess.c. It's not really correct either (it indicates that the source 133 ** is Digital confidential!), but is better than nothing and more 134 ** correct than what was there before. 135 ** 136 ** Revision 1.14 1997/05/23 04:12:50 cgd 137 ** use an adaptive transmit start algorithm: start by telling the chip 138 ** to start transmitting after 381 bytes have been fed to it. if that 139 ** gets transmit underruns, ramp down to 1021 bytes then "whole 140 ** packet." If successful at a given level for a while, try the next 141 ** more agressive level. This code doesn't ever try to start 142 ** transmitting after 5 bytes have been sent to the NIC, because 143 ** that underruns rather regularly. The back-off and ramp-up mechanism 144 ** could probably be tuned a little bit, but this works well enough to 145 ** support > 1MB/s transmit rates on a clear ethernet (which is about 146 ** 20-25% better than the driver had previously been getting). 147 ** 148 ** Revision 1.13 1997/05/22 21:06:54 cgd 149 ** redo cs_copy_tx_frame() from scratch. It had a fatal flaw: it was blindly 150 ** casting from u_int8_t * to u_int16_t * without worrying about alignment 151 ** issues. This would cause bogus data to be spit out for mbufs with 152 ** misaligned data. For instance, it caused the following bits to appear 153 ** on the wire: 154 ** ... etBND 1S2C .SHA(K) R ... 155 ** 11112222333344445555 156 ** which should have appeared as: 157 ** ... NetBSD 1.2C (SHARK) ... 158 ** 11112222333344445555 159 ** Note the apparent 'rotate' of the bytes in the word, which was due to 160 ** incorrect unaligned accesses. This data corruption was the cause of 161 ** incoming telnet/rlogin hangs. 162 ** 163 ** Revision 1.12 1997/05/22 01:55:32 cgd 164 ** reformat log so it fits in 80cols 165 ** 166 ** Revision 1.11 1997/05/22 01:50:27 cgd 167 ** * enable input packet address checking in the BPF+IFF_PROMISCUOUS case, 168 ** so packets aimed at other hosts don't get sent to ether_input(). 169 ** * Add a static const char *rcsid initialized with an RCS Id tag, so that 170 ** you can easily tell (`strings`) what version of the driver is in your 171 ** kernel binary. 172 ** * get rid of ether_cmp(). It was inconsistently used, not necessarily 173 ** safe, and not really a performance win anyway. (It was only used when 174 ** setting up the multicast logical address filter, which is an 175 ** infrequent event. It could have been used in the IFF_PROMISCUOUS 176 ** address check above, but the benefit of it vs. memcmp would be 177 ** inconsequential, there.) Use memcmp() instead. 178 ** * restructure csStartOuput to avoid the following bugs in the case where 179 ** txWait was being set: 180 ** * it would accidentally drop the outgoing packet if told to wait 181 ** but the outgoing packet queue was empty. 182 ** * it would bpf_mtap() the outgoing packet multiple times (once for 183 ** each time it was told to wait), and would also recalculate 184 ** the length of the outgoing packet each time it was told to 185 ** wait. 186 ** While there, rename txWait to txLoop, since with the new structure of 187 ** the code, the latter name makes more sense. 188 ** 189 ** Revision 1.10 1997/05/19 02:03:20 cgd 190 ** Set RX_CTL in cs_set_ladr_filt(), rather than cs_initChip(). cs_initChip() 191 ** is the only caller of cs_set_ladr_filt(), and always calls it, so this 192 ** ends up being logically the same. In cs_set_ladr_filt(), if IFF_PROMISC 193 ** is set, enable promiscuous mode (and set IFF_ALLMULTI), otherwise behave 194 ** as before. 195 ** 196 ** Revision 1.9 1997/05/19 01:45:37 cgd 197 ** create a new function, cs_ether_input(), which does received-packet 198 ** BPF and ether_input processing. This code used to be in three places, 199 ** and centralizing it will make adding IFF_PROMISC support much easier. 200 ** Also, in cs_copy_tx_frame(), put it some (currently disabled) code to 201 ** do copies with bus_space_write_region_2(). It's more correct, and 202 ** potentially more efficient. That function needs to be gutted (to 203 ** deal properly with alignment issues, which it currently does wrong), 204 ** however, and the change doesn't gain much, so there's no point in 205 ** enabling it now. 206 ** 207 ** Revision 1.8 1997/05/19 01:17:10 cgd 208 ** fix a comment re: the setting of the TxConfig register. Clean up 209 ** interface counter maintenance (make it use standard idiom). 210 ** 211 **-- 212 */ 213 214 #include <sys/cdefs.h> 215 __KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.31 2010/04/05 07:19:33 joerg Exp $"); 216 217 #include "opt_inet.h" 218 219 #include <sys/param.h> 220 #include <sys/systm.h> 221 #include <sys/mbuf.h> 222 #include <sys/syslog.h> 223 #include <sys/socket.h> 224 #include <sys/device.h> 225 #include <sys/malloc.h> 226 #include <sys/ioctl.h> 227 #include <sys/errno.h> 228 229 #include "rnd.h" 230 #if NRND > 0 231 #include <sys/rnd.h> 232 #endif 233 234 #include <net/if.h> 235 #include <net/if_ether.h> 236 #include <net/if_media.h> 237 #ifdef INET 238 #include <netinet/in.h> 239 #include <netinet/if_inarp.h> 240 #endif 241 242 #include <net/bpf.h> 243 #include <net/bpfdesc.h> 244 245 #include <uvm/uvm_extern.h> 246 247 #include <sys/bus.h> 248 #include <sys/intr.h> 249 250 #include <dev/ic/cs89x0reg.h> 251 #include <dev/ic/cs89x0var.h> 252 253 #ifdef SHARK 254 #include <shark/shark/sequoia.h> 255 #endif 256 257 /* 258 * MACRO DEFINITIONS 259 */ 260 #define CS_OUTPUT_LOOP_MAX 100 /* max times round notorious tx loop */ 261 262 /* 263 * FUNCTION PROTOTYPES 264 */ 265 static void cs_get_default_media(struct cs_softc *); 266 static int cs_get_params(struct cs_softc *); 267 static int cs_get_enaddr(struct cs_softc *); 268 static int cs_reset_chip(struct cs_softc *); 269 static void cs_reset(struct cs_softc *); 270 static int cs_ioctl(struct ifnet *, u_long, void *); 271 static void cs_initChip(struct cs_softc *); 272 static void cs_buffer_event(struct cs_softc *, u_int16_t); 273 static void cs_transmit_event(struct cs_softc *, u_int16_t); 274 static void cs_receive_event(struct cs_softc *, u_int16_t); 275 static void cs_process_receive(struct cs_softc *); 276 static void cs_process_rx_early(struct cs_softc *); 277 static void cs_start_output(struct ifnet *); 278 static void cs_copy_tx_frame(struct cs_softc *, struct mbuf *); 279 static void cs_set_ladr_filt(struct cs_softc *, struct ethercom *); 280 static u_int16_t cs_hash_index(char *); 281 static void cs_counter_event(struct cs_softc *, u_int16_t); 282 283 static int cs_mediachange(struct ifnet *); 284 static void cs_mediastatus(struct ifnet *, struct ifmediareq *); 285 286 static bool cs_shutdown(device_t, int); 287 static int cs_enable(struct cs_softc *); 288 static void cs_disable(struct cs_softc *); 289 static void cs_stop(struct ifnet *, int); 290 static int cs_scan_eeprom(struct cs_softc *); 291 static int cs_read_pktpg_from_eeprom(struct cs_softc *, int, u_int16_t *); 292 293 294 /* 295 * GLOBAL DECLARATIONS 296 */ 297 298 /* 299 * Xmit-early table. 300 * 301 * To get better performance, we tell the chip to start packet 302 * transmission before the whole packet is copied to the chip. 303 * However, this can fail under load. When it fails, we back off 304 * to a safer setting for a little while. 305 * 306 * txcmd is the value of txcmd used to indicate when to start transmission. 307 * better is the next 'better' state in the table. 308 * better_count is the number of output packets before transition to the 309 * better state. 310 * worse is the next 'worse' state in the table. 311 * 312 * Transition to the next worse state happens automatically when a 313 * transmittion underrun occurs. 314 */ 315 struct cs_xmit_early { 316 u_int16_t txcmd; 317 int better; 318 int better_count; 319 int worse; 320 } cs_xmit_early_table[3] = { 321 { TX_CMD_START_381, 0, INT_MAX, 1, }, 322 { TX_CMD_START_1021, 0, 50000, 2, }, 323 { TX_CMD_START_ALL, 1, 5000, 2, }, 324 }; 325 326 int cs_default_media[] = { 327 IFM_ETHER|IFM_10_2, 328 IFM_ETHER|IFM_10_5, 329 IFM_ETHER|IFM_10_T, 330 IFM_ETHER|IFM_10_T|IFM_FDX, 331 }; 332 int cs_default_nmedia = sizeof(cs_default_media) / sizeof(cs_default_media[0]); 333 334 int 335 cs_attach(struct cs_softc *sc, u_int8_t *enaddr, int *media, 336 int nmedia, int defmedia) 337 { 338 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 339 const char *chipname, *medname; 340 u_int16_t reg; 341 int i; 342 343 /* Start out in IO mode */ 344 sc->sc_memorymode = FALSE; 345 346 /* make sure we're right */ 347 for (i = 0; i < 10000; i++) { 348 reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 349 if (reg == EISA_NUM_CRYSTAL) { 350 break; 351 } 352 } 353 if (i == 10000) { 354 aprint_error_dev(sc->sc_dev, "wrong id(0x%x)\n", reg); 355 return 1; /* XXX should panic? */ 356 } 357 358 reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID); 359 sc->sc_prodid = reg & PROD_ID_MASK; 360 sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8; 361 362 switch (sc->sc_prodid) { 363 case PROD_ID_CS8900: 364 chipname = "CS8900"; 365 break; 366 case PROD_ID_CS8920: 367 chipname = "CS8920"; 368 break; 369 case PROD_ID_CS8920M: 370 chipname = "CS8920M"; 371 break; 372 default: 373 panic("cs_attach: impossible"); 374 } 375 376 /* 377 * the first thing to do is check that the mbuf cluster size is 378 * greater than the MTU for an ethernet frame. The code depends on 379 * this and to port this to a OS where this was not the case would 380 * not be straightforward. 381 * 382 * we need 1 byte spare because our 383 * packet read loop can overrun. 384 * and we may need pad bytes to align ip header. 385 */ 386 if (MCLBYTES < ETHER_MAX_LEN + 1 + 387 ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header)) { 388 printf("%s: MCLBYTES too small for Ethernet frame\n", 389 device_xname(sc->sc_dev)); 390 return 1; 391 } 392 393 /* Start out not transmitting */ 394 sc->sc_txbusy = FALSE; 395 396 /* Set up early transmit threshhold */ 397 sc->sc_xe_ent = 0; 398 sc->sc_xe_togo = cs_xmit_early_table[sc->sc_xe_ent].better_count; 399 400 /* Initialize ifnet structure. */ 401 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 402 ifp->if_softc = sc; 403 ifp->if_start = cs_start_output; 404 ifp->if_init = cs_init; 405 ifp->if_ioctl = cs_ioctl; 406 ifp->if_stop = cs_stop; 407 ifp->if_watchdog = NULL; /* no watchdog at this stage */ 408 ifp->if_flags = IFF_SIMPLEX | IFF_NOTRAILERS | 409 IFF_BROADCAST | IFF_MULTICAST; 410 IFQ_SET_READY(&ifp->if_snd); 411 412 /* Initialize ifmedia structures. */ 413 ifmedia_init(&sc->sc_media, 0, cs_mediachange, cs_mediastatus); 414 415 if (media != NULL) { 416 for (i = 0; i < nmedia; i++) 417 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 418 ifmedia_set(&sc->sc_media, defmedia); 419 } else { 420 for (i = 0; i < cs_default_nmedia; i++) 421 ifmedia_add(&sc->sc_media, cs_default_media[i], 422 0, NULL); 423 cs_get_default_media(sc); 424 } 425 426 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 427 if (cs_scan_eeprom(sc) == CS_ERROR) { 428 /* failed to scan the eeprom, pretend there isn't an eeprom */ 429 aprint_error_dev(sc->sc_dev, "unable to scan EEPROM\n"); 430 sc->sc_cfgflags |= CFGFLG_NOT_EEPROM; 431 } 432 } 433 434 if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 435 /* Get parameters from the EEPROM */ 436 if (cs_get_params(sc) == CS_ERROR) { 437 aprint_error_dev(sc->sc_dev, 438 "unable to get settings from EEPROM\n"); 439 return 1; 440 } 441 } 442 443 if (enaddr != NULL) 444 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 445 else if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 446 /* Get and store the Ethernet address */ 447 if (cs_get_enaddr(sc) == CS_ERROR) { 448 aprint_error_dev(sc->sc_dev, 449 "unable to read Ethernet address\n"); 450 return 1; 451 } 452 } else { 453 #if 1 454 int j; 455 uint v; 456 457 for (j = 0; j < 6; j += 2) { 458 v = CS_READ_PACKET_PAGE(sc, PKTPG_IND_ADDR + j); 459 sc->sc_enaddr[j + 0] = v; 460 sc->sc_enaddr[j + 1] = v >> 8; 461 } 462 #else 463 printf("%s: no Ethernet address!\n", device_xname(sc->sc_dev)); 464 return 1; 465 #endif 466 } 467 468 switch (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media)) { 469 case IFM_10_2: 470 medname = "BNC"; 471 break; 472 case IFM_10_5: 473 medname = "AUI"; 474 break; 475 case IFM_10_T: 476 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 477 medname = "UTP <full-duplex>"; 478 else 479 medname = "UTP"; 480 break; 481 default: 482 panic("cs_attach: impossible"); 483 } 484 printf("%s: %s rev. %c, address %s, media %s\n", 485 device_xname(sc->sc_dev), 486 chipname, sc->sc_prodrev + 'A', ether_sprintf(sc->sc_enaddr), 487 medname); 488 489 if (sc->sc_dma_attach) 490 (*sc->sc_dma_attach)(sc); 491 492 /* Attach the interface. */ 493 if_attach(ifp); 494 ether_ifattach(ifp, sc->sc_enaddr); 495 496 #if NRND > 0 497 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 498 RND_TYPE_NET, 0); 499 #endif 500 sc->sc_cfgflags |= CFGFLG_ATTACHED; 501 502 if (pmf_device_register1(sc->sc_dev, NULL, NULL, cs_shutdown)) 503 pmf_class_network_register(sc->sc_dev, ifp); 504 else 505 aprint_error_dev(sc->sc_dev, 506 "couldn't establish power handler\n"); 507 508 /* Reset the chip */ 509 if (cs_reset_chip(sc) == CS_ERROR) { 510 aprint_error_dev(sc->sc_dev, "reset failed\n"); 511 cs_detach(sc); 512 return 1; 513 } 514 515 return 0; 516 } 517 518 int 519 cs_detach(struct cs_softc *sc) 520 { 521 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 522 523 if (sc->sc_cfgflags & CFGFLG_ATTACHED) { 524 #if NRND > 0 525 rnd_detach_source(&sc->rnd_source); 526 #endif 527 ether_ifdetach(ifp); 528 if_detach(ifp); 529 sc->sc_cfgflags &= ~CFGFLG_ATTACHED; 530 } 531 532 #if 0 533 /* 534 * XXX not necessary 535 */ 536 if (sc->sc_cfgflags & CFGFLG_DMA_MODE) { 537 isa_dmamem_unmap(sc->sc_ic, sc->sc_drq, sc->sc_dmabase, sc->sc_dmasize); 538 isa_dmamem_free(sc->sc_ic, sc->sc_drq, sc->sc_dmaaddr, sc->sc_dmasize); 539 isa_dmamap_destroy(sc->sc_ic, sc->sc_drq); 540 sc->sc_cfgflags &= ~CFGFLG_DMA_MODE; 541 } 542 #endif 543 544 pmf_device_deregister(sc->sc_dev); 545 546 return 0; 547 } 548 549 bool 550 cs_shutdown(device_t self, int howto) 551 { 552 struct cs_softc *sc; 553 554 sc = device_private(self); 555 cs_reset(sc); 556 557 return true; 558 } 559 560 void 561 cs_get_default_media(struct cs_softc *sc) 562 { 563 u_int16_t adp_cfg, xmit_ctl; 564 565 if (cs_verify_eeprom(sc) == CS_ERROR) { 566 aprint_error_dev(sc->sc_dev, 567 "cs_get_default_media: EEPROM missing or bad\n"); 568 goto fakeit; 569 } 570 571 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adp_cfg) == CS_ERROR) { 572 aprint_error_dev(sc->sc_dev, 573 "unable to read adapter config from EEPROM\n"); 574 goto fakeit; 575 } 576 577 if (cs_read_eeprom(sc, EEPROM_XMIT_CTL, &xmit_ctl) == CS_ERROR) { 578 aprint_error_dev(sc->sc_dev, 579 "unable to read transmit control from EEPROM\n"); 580 goto fakeit; 581 } 582 583 switch (adp_cfg & ADPTR_CFG_MEDIA) { 584 case ADPTR_CFG_AUI: 585 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_5); 586 break; 587 case ADPTR_CFG_10BASE2: 588 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_2); 589 break; 590 case ADPTR_CFG_10BASET: 591 default: 592 if (xmit_ctl & XMIT_CTL_FDX) 593 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX); 594 else 595 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 596 break; 597 } 598 return; 599 600 fakeit: 601 aprint_error_dev(sc->sc_dev, 602 "WARNING: default media setting may be inaccurate\n"); 603 /* XXX Arbitrary... */ 604 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 605 } 606 607 /* 608 * cs_scan_eeprom 609 * 610 * Attempt to take a complete copy of the eeprom into main memory. 611 * this will allow faster parsing of the eeprom data. 612 * 613 * Only tested against a 8920M's eeprom, but the data sheet for the 614 * 8920A indicates that is uses the same layout. 615 */ 616 int 617 cs_scan_eeprom(struct cs_softc *sc) 618 { 619 u_int16_t result; 620 int i; 621 int eeprom_size; 622 u_int8_t checksum = 0; 623 624 if (cs_verify_eeprom(sc) == CS_ERROR) { 625 aprint_error_dev(sc->sc_dev, 626 "cs_scan_params: EEPROM missing or bad\n"); 627 return (CS_ERROR); 628 } 629 630 /* 631 * read the 0th word from the eeprom, it will tell us the length 632 * and if the eeprom is valid 633 */ 634 cs_read_eeprom(sc, 0, &result); 635 636 /* check the eeprom signature */ 637 if ((result & 0xE000) != 0xA000) { 638 /* empty eeprom */ 639 return (CS_ERROR); 640 } 641 642 /* 643 * take the eeprom size (note the read value doesn't include the header 644 * word) 645 */ 646 eeprom_size = (result & 0xff) + 2; 647 648 sc->eeprom_data = malloc(eeprom_size, M_DEVBUF, M_WAITOK); 649 if (sc->eeprom_data == NULL) { 650 /* no memory, treat this as if there's no eeprom */ 651 return (CS_ERROR); 652 } 653 654 sc->eeprom_size = eeprom_size; 655 656 /* read the eeprom into the buffer, also calculate the checksum */ 657 for (i = 0; i < (eeprom_size >> 1); i++) { 658 cs_read_eeprom(sc, i, &(sc->eeprom_data[i])); 659 checksum += (sc->eeprom_data[i] & 0xff00) >> 8; 660 checksum += (sc->eeprom_data[i] & 0x00ff); 661 } 662 663 /* 664 * validate checksum calculation, the sum of all the bytes should be 0, 665 * as the high byte of the last word is the 2's complement of the 666 * sum to that point. 667 */ 668 if (checksum != 0) { 669 aprint_error_dev(sc->sc_dev, "eeprom checksum failure\n"); 670 return (CS_ERROR); 671 } 672 673 return (CS_OK); 674 } 675 676 static int 677 cs_read_pktpg_from_eeprom(struct cs_softc *sc, int pktpg, u_int16_t *pValue) 678 { 679 int x, maxword; 680 681 /* Check that we have eeprom data */ 682 if ((sc->eeprom_data == NULL) || (sc->eeprom_size < 2)) 683 return (CS_ERROR); 684 685 /* 686 * We only want to read the data words, the last word contains the 687 * checksum 688 */ 689 maxword = (sc->eeprom_size - 2) >> 1; 690 691 /* start 1 word in, as the first word is the length and signature */ 692 x = 1; 693 694 while ( x < (maxword)) { 695 u_int16_t header; 696 int group_size; 697 int offset; 698 int offset_max; 699 700 /* read in the group header word */ 701 header = sc->eeprom_data[x]; 702 x++; /* skip group header */ 703 704 /* 705 * size of group in words is in the top 4 bits, note that it 706 * is one less than the number of words 707 */ 708 group_size = header & 0xF000; 709 710 /* 711 * CS8900 Data sheet says this should be 0x01ff, 712 * but my cs8920 eeprom has higher offsets, 713 * perhaps the 8920 allows higher offsets, otherwise 714 * it's writing to places that it shouldn't 715 */ 716 /* work out the offsets this group covers */ 717 offset = header & 0x0FFF; 718 offset_max = offset + (group_size << 1); 719 720 /* check if the pkgpg we're after is in this group */ 721 if ((offset <= pktpg) && (pktpg <= offset_max)) { 722 /* the pkgpg value we want is in here */ 723 int eeprom_location; 724 725 eeprom_location = ((pktpg - offset) >> 1) ; 726 727 *pValue = sc->eeprom_data[x + eeprom_location]; 728 return (CS_OK); 729 } else { 730 /* skip this group (+ 1 for first entry) */ 731 x += group_size + 1; 732 } 733 } 734 735 /* 736 * if we've fallen out here then we don't have a value in the EEPROM 737 * for this pktpg so return an error 738 */ 739 return (CS_ERROR); 740 } 741 742 int 743 cs_get_params(struct cs_softc *sc) 744 { 745 u_int16_t isaConfig; 746 u_int16_t adapterConfig; 747 748 if (cs_verify_eeprom(sc) == CS_ERROR) { 749 aprint_error_dev(sc->sc_dev, 750 "cs_get_params: EEPROM missing or bad\n"); 751 return (CS_ERROR); 752 } 753 754 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 755 /* Get ISA configuration from the EEPROM */ 756 if (cs_read_pktpg_from_eeprom(sc, PKTPG_BUS_CTL, &isaConfig) 757 == CS_ERROR) { 758 /* eeprom doesn't have this value, use data sheet default */ 759 isaConfig = 0x0017; 760 } 761 762 /* Get adapter configuration from the EEPROM */ 763 if (cs_read_pktpg_from_eeprom(sc, PKTPG_SELF_CTL, &adapterConfig) 764 == CS_ERROR) { 765 /* eeprom doesn't have this value, use data sheet default */ 766 adapterConfig = 0x0015; 767 } 768 769 /* Copy the USE_SA flag */ 770 if (isaConfig & BUS_CTL_USE_SA) 771 sc->sc_cfgflags |= CFGFLG_USE_SA; 772 773 /* Copy the IO Channel Ready flag */ 774 if (isaConfig & BUS_CTL_IOCHRDY) 775 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 776 777 /* Copy the DC/DC Polarity flag */ 778 if (adapterConfig & SELF_CTL_HCB1) 779 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 780 } else { 781 /* Get ISA configuration from the EEPROM */ 782 if (cs_read_eeprom(sc, EEPROM_ISA_CFG, &isaConfig) == CS_ERROR) 783 goto eeprom_bad; 784 785 /* Get adapter configuration from the EEPROM */ 786 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adapterConfig) == CS_ERROR) 787 goto eeprom_bad; 788 789 /* Copy the USE_SA flag */ 790 if (isaConfig & ISA_CFG_USE_SA) 791 sc->sc_cfgflags |= CFGFLG_USE_SA; 792 793 /* Copy the IO Channel Ready flag */ 794 if (isaConfig & ISA_CFG_IOCHRDY) 795 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 796 797 /* Copy the DC/DC Polarity flag */ 798 if (adapterConfig & ADPTR_CFG_DCDC_POL) 799 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 800 } 801 802 return (CS_OK); 803 eeprom_bad: 804 aprint_error_dev(sc->sc_dev, 805 "cs_get_params: unable to read from EEPROM\n"); 806 return (CS_ERROR); 807 } 808 809 int 810 cs_get_enaddr(struct cs_softc *sc) 811 { 812 uint16_t myea[ETHER_ADDR_LEN / sizeof(uint16_t)]; 813 int i; 814 815 if (cs_verify_eeprom(sc) == CS_ERROR) { 816 aprint_error_dev(sc->sc_dev, 817 "cs_get_enaddr: EEPROM missing or bad\n"); 818 return (CS_ERROR); 819 } 820 821 /* Get Ethernet address from the EEPROM */ 822 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 823 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR, &myea[0]) 824 == CS_ERROR) 825 goto eeprom_bad; 826 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 2, &myea[1]) 827 == CS_ERROR) 828 goto eeprom_bad; 829 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 4, &myea[2]) 830 == CS_ERROR) 831 goto eeprom_bad; 832 } else { 833 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_H, &myea[0]) == CS_ERROR) 834 goto eeprom_bad; 835 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_M, &myea[1]) == CS_ERROR) 836 goto eeprom_bad; 837 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_L, &myea[2]) == CS_ERROR) 838 goto eeprom_bad; 839 } 840 841 for (i = 0; i < __arraycount(myea); i++) { 842 sc->sc_enaddr[i * 2 + 0] = myea[i]; 843 sc->sc_enaddr[i * 2 + 1] = myea[i] >> 8; 844 } 845 846 return (CS_OK); 847 848 eeprom_bad: 849 aprint_error_dev(sc->sc_dev, 850 "cs_get_enaddr: unable to read from EEPROM\n"); 851 return (CS_ERROR); 852 } 853 854 int 855 cs_reset_chip(struct cs_softc *sc) 856 { 857 int intState; 858 int x; 859 860 /* Disable interrupts at the CPU so reset command is atomic */ 861 intState = splnet(); 862 863 /* 864 * We are now resetting the chip 865 * 866 * A spurious interrupt is generated by the chip when it is reset. This 867 * variable informs the interrupt handler to ignore this interrupt. 868 */ 869 sc->sc_resetting = TRUE; 870 871 /* Issue a reset command to the chip */ 872 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, SELF_CTL_RESET); 873 874 /* Re-enable interrupts at the CPU */ 875 splx(intState); 876 877 /* The chip is always in IO mode after a reset */ 878 sc->sc_memorymode = FALSE; 879 880 /* If transmission was in progress, it is not now */ 881 sc->sc_txbusy = FALSE; 882 883 /* 884 * there was a delay(125); here, but it seems uneccesary 125 usec is 885 * 1/8000 of a second, not 1/8 of a second. the data sheet advises 886 * 1/10 of a second here, but the SI_BUSY and INIT_DONE loops below 887 * should be sufficient. 888 */ 889 890 /* Transition SBHE to switch chip from 8-bit to 16-bit */ 891 IO_READ_1(sc, PORT_PKTPG_PTR + 0); 892 IO_READ_1(sc, PORT_PKTPG_PTR + 1); 893 IO_READ_1(sc, PORT_PKTPG_PTR + 0); 894 IO_READ_1(sc, PORT_PKTPG_PTR + 1); 895 896 /* Wait until the EEPROM is not busy */ 897 for (x = 0; x < MAXLOOP; x++) { 898 if (!(CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY)) 899 break; 900 } 901 902 if (x == MAXLOOP) 903 return CS_ERROR; 904 905 /* Wait until initialization is done */ 906 for (x = 0; x < MAXLOOP; x++) { 907 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_INIT_DONE) 908 break; 909 } 910 911 if (x == MAXLOOP) 912 return CS_ERROR; 913 914 /* Reset is no longer in progress */ 915 sc->sc_resetting = FALSE; 916 917 return CS_OK; 918 } 919 920 int 921 cs_verify_eeprom(struct cs_softc *sc) 922 { 923 u_int16_t self_status; 924 925 /* Verify that the EEPROM is present and OK */ 926 self_status = CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST); 927 if (((self_status & SELF_ST_EEP_PRES) && 928 (self_status & SELF_ST_EEP_OK)) == 0) 929 return (CS_ERROR); 930 931 return (CS_OK); 932 } 933 934 int 935 cs_read_eeprom(struct cs_softc *sc, int offset, u_int16_t *pValue) 936 { 937 int x; 938 939 /* Ensure that the EEPROM is not busy */ 940 for (x = 0; x < MAXLOOP; x++) { 941 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) & 942 SELF_ST_SI_BUSY)) 943 break; 944 } 945 946 if (x == MAXLOOP) 947 return (CS_ERROR); 948 949 /* Issue the command to read the offset within the EEPROM */ 950 CS_WRITE_PACKET_PAGE_IO(sc, PKTPG_EEPROM_CMD, 951 offset | EEPROM_CMD_READ); 952 953 /* Wait until the command is completed */ 954 for (x = 0; x < MAXLOOP; x++) { 955 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) & 956 SELF_ST_SI_BUSY)) 957 break; 958 } 959 960 if (x == MAXLOOP) 961 return (CS_ERROR); 962 963 /* Get the EEPROM data from the EEPROM Data register */ 964 *pValue = CS_READ_PACKET_PAGE_IO(sc, PKTPG_EEPROM_DATA); 965 966 return (CS_OK); 967 } 968 969 void 970 cs_initChip(struct cs_softc *sc) 971 { 972 u_int16_t busCtl; 973 u_int16_t selfCtl; 974 u_int16_t v; 975 u_int16_t isaId; 976 int i; 977 int media = IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media); 978 979 /* Disable reception and transmission of frames */ 980 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 981 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) & 982 ~LINE_CTL_RX_ON & ~LINE_CTL_TX_ON); 983 984 /* Disable interrupt at the chip */ 985 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 986 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & ~BUS_CTL_INT_ENBL); 987 988 /* If IOCHRDY is enabled then clear the bit in the busCtl register */ 989 busCtl = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL); 990 if (sc->sc_cfgflags & CFGFLG_IOCHRDY) { 991 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 992 busCtl & ~BUS_CTL_IOCHRDY); 993 } else { 994 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 995 busCtl | BUS_CTL_IOCHRDY); 996 } 997 998 /* Set the Line Control register to match the media type */ 999 if (media == IFM_10_T) 1000 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_10BASET); 1001 else 1002 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY); 1003 1004 /* 1005 * Set the BSTATUS/HC1 pin to be used as HC1. HC1 is used to 1006 * enable the DC/DC converter 1007 */ 1008 selfCtl = SELF_CTL_HC1E; 1009 1010 /* If the media type is 10Base2 */ 1011 if (media == IFM_10_2) { 1012 /* 1013 * Enable the DC/DC converter if it has a low enable. 1014 */ 1015 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) == 0) 1016 /* 1017 * Set the HCB1 bit, which causes the HC1 pin to go 1018 * low. 1019 */ 1020 selfCtl |= SELF_CTL_HCB1; 1021 } else { /* Media type is 10BaseT or AUI */ 1022 /* 1023 * Disable the DC/DC converter if it has a high enable. 1024 */ 1025 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) != 0) { 1026 /* 1027 * Set the HCB1 bit, which causes the HC1 pin to go 1028 * low. 1029 */ 1030 selfCtl |= SELF_CTL_HCB1; 1031 } 1032 } 1033 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, selfCtl); 1034 1035 /* enable normal link pulse */ 1036 if (sc->sc_prodid == PROD_ID_CS8920 || sc->sc_prodid == PROD_ID_CS8920M) 1037 CS_WRITE_PACKET_PAGE(sc, PKTPG_AUTONEG_CTL, AUTOCTL_NLP_ENABLE); 1038 1039 /* Enable full-duplex, if appropriate */ 1040 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 1041 CS_WRITE_PACKET_PAGE(sc, PKTPG_TEST_CTL, TEST_CTL_FDX); 1042 1043 /* RX_CTL set in cs_set_ladr_filt(), below */ 1044 1045 /* enable all transmission interrupts */ 1046 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, TX_CFG_ALL_IE); 1047 1048 /* Accept all receive interrupts */ 1049 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, RX_CFG_ALL_IE); 1050 1051 /* 1052 * Configure Operational Modes 1053 * 1054 * I have turned off the BUF_CFG_RX_MISS_IE, to speed things up, this is 1055 * a better way to do it because the card has a counter which can be 1056 * read to update the RX_MISS counter. This saves many interrupts. 1057 * 1058 * I have turned on the tx and rx overflow interrupts to counter using 1059 * the receive miss interrupt. This is a better estimate of errors 1060 * and requires lower system overhead. 1061 */ 1062 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, BUF_CFG_TX_UNDR_IE | 1063 BUF_CFG_RX_DMA_IE); 1064 1065 if (sc->sc_dma_chipinit) 1066 (*sc->sc_dma_chipinit)(sc); 1067 1068 /* If memory mode is enabled */ 1069 if (sc->sc_cfgflags & CFGFLG_MEM_MODE) { 1070 /* If external logic is present for address decoding */ 1071 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_EL_PRES) { 1072 /* 1073 * Program the external logic to decode address bits 1074 * SA20-SA23 1075 */ 1076 CS_WRITE_PACKET_PAGE(sc, PKTPG_EEPROM_CMD, 1077 ((sc->sc_pktpgaddr & 0xffffff) >> 20) | 1078 EEPROM_CMD_ELSEL); 1079 } 1080 1081 /* 1082 * Write the packet page base physical address to the memory 1083 * base register. 1084 */ 1085 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 0, 1086 sc->sc_pktpgaddr & 0xFFFF); 1087 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 2, 1088 sc->sc_pktpgaddr >> 16); 1089 busCtl = BUS_CTL_MEM_MODE; 1090 1091 /* tell the chip to read the addresses off the SA pins */ 1092 if (sc->sc_cfgflags & CFGFLG_USE_SA) { 1093 busCtl |= BUS_CTL_USE_SA; 1094 } 1095 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 1096 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | busCtl); 1097 1098 /* We are in memory mode now! */ 1099 sc->sc_memorymode = TRUE; 1100 1101 /* 1102 * wait here (10ms) for the chip to swap over. this is the 1103 * maximum time that this could take. 1104 */ 1105 delay(10000); 1106 1107 /* Verify that we can read from the chip */ 1108 isaId = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 1109 1110 /* 1111 * As a last minute sanity check before actually using mapped 1112 * memory we verify that we can read the isa number from the 1113 * chip in memory mode. 1114 */ 1115 if (isaId != EISA_NUM_CRYSTAL) { 1116 aprint_error_dev(sc->sc_dev, 1117 "failed to enable memory mode\n"); 1118 sc->sc_memorymode = FALSE; 1119 } else { 1120 /* 1121 * we are in memory mode so if we aren't using DMA, 1122 * then program the chip to interrupt early. 1123 */ 1124 if ((sc->sc_cfgflags & CFGFLG_DMA_MODE) == 0) { 1125 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 1126 BUF_CFG_RX_DEST_IE | 1127 BUF_CFG_RX_MISS_OVER_IE | 1128 BUF_CFG_TX_COL_OVER_IE); 1129 } 1130 } 1131 1132 } 1133 1134 /* Put Ethernet address into the Individual Address register */ 1135 for (i = 0; i < 6; i += 2) { 1136 v = sc->sc_enaddr[i + 0] | (sc->sc_enaddr[i + 1]) << 8; 1137 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + i, v); 1138 } 1139 1140 if (sc->sc_irq != -1) { 1141 /* Set the interrupt level in the chip */ 1142 if (sc->sc_prodid == PROD_ID_CS8900) { 1143 if (sc->sc_irq == 5) { 1144 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 3); 1145 } else { 1146 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, (sc->sc_irq) - 10); 1147 } 1148 } 1149 else { /* CS8920 */ 1150 CS_WRITE_PACKET_PAGE(sc, PKTPG_8920_INT_NUM, sc->sc_irq); 1151 } 1152 } 1153 1154 /* write the multicast mask to the address filter register */ 1155 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1156 1157 /* Enable reception and transmission of frames */ 1158 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 1159 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) | 1160 LINE_CTL_RX_ON | LINE_CTL_TX_ON); 1161 1162 /* Enable interrupt at the chip */ 1163 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 1164 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | BUS_CTL_INT_ENBL); 1165 } 1166 1167 int 1168 cs_init(struct ifnet *ifp) 1169 { 1170 int intState; 1171 int error = CS_OK; 1172 struct cs_softc *sc = ifp->if_softc; 1173 1174 if (cs_enable(sc)) 1175 goto out; 1176 1177 cs_stop(ifp, 0); 1178 1179 intState = splnet(); 1180 1181 #if 0 1182 /* Mark the interface as down */ 1183 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_UP | IFF_RUNNING); 1184 #endif 1185 1186 #ifdef CS_DEBUG 1187 /* Enable debugging */ 1188 sc->sc_ethercom.ec_if.if_flags |= IFF_DEBUG; 1189 #endif 1190 1191 /* Reset the chip */ 1192 if ((error = cs_reset_chip(sc)) == CS_OK) { 1193 /* Initialize the chip */ 1194 cs_initChip(sc); 1195 1196 /* Mark the interface as running */ 1197 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 1198 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1199 sc->sc_ethercom.ec_if.if_timer = 0; 1200 1201 /* Assume we have carrier until we are told otherwise. */ 1202 sc->sc_carrier = 1; 1203 } else { 1204 aprint_error_dev(sc->sc_dev, "unable to reset chip\n"); 1205 } 1206 1207 splx(intState); 1208 out: 1209 if (error == CS_OK) 1210 return 0; 1211 return EIO; 1212 } 1213 1214 void 1215 cs_set_ladr_filt(struct cs_softc *sc, struct ethercom *ec) 1216 { 1217 struct ifnet *ifp = &ec->ec_if; 1218 struct ether_multi *enm; 1219 struct ether_multistep step; 1220 u_int16_t af[4]; 1221 u_int16_t port, mask, index; 1222 1223 /* 1224 * Set up multicast address filter by passing all multicast addresses 1225 * through a crc generator, and then using the high order 6 bits as an 1226 * index into the 64 bit logical address filter. The high order bit 1227 * selects the word, while the rest of the bits select the bit within 1228 * the word. 1229 */ 1230 if (ifp->if_flags & IFF_PROMISC) { 1231 /* accept all valid frames. */ 1232 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1233 RX_CTL_PROMISC_A | RX_CTL_RX_OK_A | 1234 RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1235 ifp->if_flags |= IFF_ALLMULTI; 1236 return; 1237 } 1238 1239 /* 1240 * accept frames if a. crc valid, b. individual address match c. 1241 * broadcast address,and d. multicast addresses matched in the hash 1242 * filter 1243 */ 1244 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1245 RX_CTL_RX_OK_A | RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1246 1247 1248 /* 1249 * start off with all multicast flag clear, set it if we need to 1250 * later, otherwise we will leave it. 1251 */ 1252 ifp->if_flags &= ~IFF_ALLMULTI; 1253 af[0] = af[1] = af[2] = af[3] = 0x0000; 1254 1255 /* 1256 * Loop through all the multicast addresses unless we get a range of 1257 * addresses, in which case we will just accept all packets. 1258 * Justification for this is given in the next comment. 1259 */ 1260 ETHER_FIRST_MULTI(step, ec, enm); 1261 while (enm != NULL) { 1262 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1263 sizeof enm->enm_addrlo)) { 1264 /* 1265 * We must listen to a range of multicast addresses. 1266 * For now, just accept all multicasts, rather than 1267 * trying to set only those filter bits needed to match 1268 * the range. (At this time, the only use of address 1269 * ranges is for IP multicast routing, for which the 1270 * range is big enough to require all bits set.) 1271 */ 1272 ifp->if_flags |= IFF_ALLMULTI; 1273 af[0] = af[1] = af[2] = af[3] = 0xffff; 1274 break; 1275 } else { 1276 /* 1277 * we have got an individual address so just set that 1278 * bit. 1279 */ 1280 index = cs_hash_index(enm->enm_addrlo); 1281 1282 /* Set the bit the Logical address filter. */ 1283 port = (u_int16_t) (index >> 4); 1284 mask = (u_int16_t) (1 << (index & 0xf)); 1285 af[port] |= mask; 1286 1287 ETHER_NEXT_MULTI(step, enm); 1288 } 1289 } 1290 1291 /* now program the chip with the addresses */ 1292 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 0, af[0]); 1293 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 2, af[1]); 1294 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 4, af[2]); 1295 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 6, af[3]); 1296 return; 1297 } 1298 1299 u_int16_t 1300 cs_hash_index(char *addr) 1301 { 1302 uint32_t crc; 1303 uint16_t hash_code; 1304 1305 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1306 1307 hash_code = crc >> 26; 1308 return (hash_code); 1309 } 1310 1311 void 1312 cs_reset(struct cs_softc *sc) 1313 { 1314 1315 /* Mark the interface as down */ 1316 sc->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1317 1318 /* Reset the chip */ 1319 cs_reset_chip(sc); 1320 } 1321 1322 int 1323 cs_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1324 { 1325 struct cs_softc *sc = ifp->if_softc; 1326 struct ifreq *ifr = data; 1327 int state; 1328 int result; 1329 1330 state = splnet(); 1331 1332 result = 0; /* only set if something goes wrong */ 1333 1334 switch (cmd) { 1335 case SIOCGIFMEDIA: 1336 case SIOCSIFMEDIA: 1337 result = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1338 break; 1339 1340 default: 1341 result = ether_ioctl(ifp, cmd, data); 1342 if (result == ENETRESET) { 1343 if (ifp->if_flags & IFF_RUNNING) { 1344 /* 1345 * Multicast list has changed. Set the 1346 * hardware filter accordingly. 1347 */ 1348 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1349 } 1350 result = 0; 1351 } 1352 break; 1353 } 1354 1355 splx(state); 1356 1357 return result; 1358 } 1359 1360 int 1361 cs_mediachange(struct ifnet *ifp) 1362 { 1363 1364 /* 1365 * Current media is already set up. Just reset the interface 1366 * to let the new value take hold. 1367 */ 1368 cs_init(ifp); 1369 return (0); 1370 } 1371 1372 void 1373 cs_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1374 { 1375 struct cs_softc *sc = ifp->if_softc; 1376 1377 /* 1378 * The currently selected media is always the active media. 1379 */ 1380 ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media; 1381 1382 if (ifp->if_flags & IFF_UP) { 1383 /* Interface up, status is valid. */ 1384 ifmr->ifm_status = IFM_AVALID | 1385 (sc->sc_carrier ? IFM_ACTIVE : 0); 1386 } 1387 else ifmr->ifm_status = 0; 1388 } 1389 1390 int 1391 cs_intr(void *arg) 1392 { 1393 struct cs_softc *sc = arg; 1394 u_int16_t Event; 1395 #if NRND > 0 1396 u_int16_t rndEvent; 1397 #endif 1398 1399 /*printf("cs_intr %p\n", sc);*/ 1400 /* Ignore any interrupts that happen while the chip is being reset */ 1401 if (sc->sc_resetting) { 1402 printf("%s: cs_intr: reset in progress\n", 1403 device_xname(sc->sc_dev)); 1404 return 1; 1405 } 1406 1407 /* Read an event from the Interrupt Status Queue */ 1408 if (sc->sc_memorymode) 1409 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1410 else 1411 Event = CS_READ_PORT(sc, PORT_ISQ); 1412 1413 if ((Event & REG_NUM_MASK) == 0 || Event == 0xffff) 1414 return 0; /* not ours */ 1415 1416 #if NRND > 0 1417 rndEvent = Event; 1418 #endif 1419 1420 /* Process all the events in the Interrupt Status Queue */ 1421 while ((Event & REG_NUM_MASK) != 0 && Event != 0xffff) { 1422 /* Dispatch to an event handler based on the register number */ 1423 switch (Event & REG_NUM_MASK) { 1424 case REG_NUM_RX_EVENT: 1425 cs_receive_event(sc, Event); 1426 break; 1427 case REG_NUM_TX_EVENT: 1428 cs_transmit_event(sc, Event); 1429 break; 1430 case REG_NUM_BUF_EVENT: 1431 cs_buffer_event(sc, Event); 1432 break; 1433 case REG_NUM_TX_COL: 1434 case REG_NUM_RX_MISS: 1435 cs_counter_event(sc, Event); 1436 break; 1437 default: 1438 printf("%s: unknown interrupt event 0x%x\n", 1439 device_xname(sc->sc_dev), Event); 1440 break; 1441 } 1442 1443 /* Read another event from the Interrupt Status Queue */ 1444 if (sc->sc_memorymode) 1445 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1446 else 1447 Event = CS_READ_PORT(sc, PORT_ISQ); 1448 } 1449 1450 /* have handled the interrupt */ 1451 #if NRND > 0 1452 rnd_add_uint32(&sc->rnd_source, rndEvent); 1453 #endif 1454 return 1; 1455 } 1456 1457 void 1458 cs_counter_event(struct cs_softc *sc, u_int16_t cntEvent) 1459 { 1460 struct ifnet *ifp; 1461 u_int16_t errorCount; 1462 1463 ifp = &sc->sc_ethercom.ec_if; 1464 1465 switch (cntEvent & REG_NUM_MASK) { 1466 case REG_NUM_TX_COL: 1467 /* 1468 * the count should be read before an overflow occurs. 1469 */ 1470 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_TX_COL); 1471 /* 1472 * the tramsit event routine always checks the number of 1473 * collisions for any packet so we don't increment any 1474 * counters here, as they should already have been 1475 * considered. 1476 */ 1477 break; 1478 case REG_NUM_RX_MISS: 1479 /* 1480 * the count should be read before an overflow occurs. 1481 */ 1482 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_RX_MISS); 1483 /* 1484 * Increment the input error count, the first 6bits are the 1485 * register id. 1486 */ 1487 ifp->if_ierrors += ((errorCount & 0xffC0) >> 6); 1488 break; 1489 default: 1490 /* do nothing */ 1491 break; 1492 } 1493 } 1494 1495 void 1496 cs_buffer_event(struct cs_softc *sc, u_int16_t bufEvent) 1497 { 1498 1499 /* 1500 * multiple events can be in the buffer event register at one time so 1501 * a standard switch statement will not suffice, here every event 1502 * must be checked. 1503 */ 1504 1505 /* 1506 * if 128 bits have been rxed by the time we get here, the dest event 1507 * will be cleared and 128 event will be set. 1508 */ 1509 if ((bufEvent & (BUF_EVENT_RX_DEST | BUF_EVENT_RX_128)) != 0) { 1510 cs_process_rx_early(sc); 1511 } 1512 1513 if (bufEvent & BUF_EVENT_RX_DMA) { 1514 /* process the receive data */ 1515 if (sc->sc_dma_process_rx) 1516 (*sc->sc_dma_process_rx)(sc); 1517 else 1518 /* should panic? */ 1519 aprint_error_dev(sc->sc_dev, "unexpected DMA event\n"); 1520 } 1521 1522 if (bufEvent & BUF_EVENT_TX_UNDR) { 1523 #if 0 1524 /* 1525 * This can happen occasionally, and it's not worth worrying 1526 * about. 1527 */ 1528 printf("%s: transmit underrun (%d -> %d)\n", 1529 device_xname(sc->sc_dev), sc->sc_xe_ent, 1530 cs_xmit_early_table[sc->sc_xe_ent].worse); 1531 #endif 1532 sc->sc_xe_ent = cs_xmit_early_table[sc->sc_xe_ent].worse; 1533 sc->sc_xe_togo = 1534 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1535 1536 /* had an underrun, transmit is finished */ 1537 sc->sc_txbusy = FALSE; 1538 } 1539 1540 if (bufEvent & BUF_EVENT_SW_INT) { 1541 printf("%s: software initiated interrupt\n", 1542 device_xname(sc->sc_dev)); 1543 } 1544 } 1545 1546 void 1547 cs_transmit_event(struct cs_softc *sc, u_int16_t txEvent) 1548 { 1549 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1550 1551 /* If there were any errors transmitting this frame */ 1552 if (txEvent & (TX_EVENT_LOSS_CRS | TX_EVENT_SQE_ERR | TX_EVENT_OUT_WIN | 1553 TX_EVENT_JABBER | TX_EVENT_16_COLL)) { 1554 /* Increment the output error count */ 1555 ifp->if_oerrors++; 1556 1557 /* Note carrier loss. */ 1558 if (txEvent & TX_EVENT_LOSS_CRS) 1559 sc->sc_carrier = 0; 1560 1561 /* If debugging is enabled then log error messages */ 1562 if (ifp->if_flags & IFF_DEBUG) { 1563 if (txEvent & TX_EVENT_LOSS_CRS) { 1564 aprint_error_dev(sc->sc_dev, "lost carrier\n"); 1565 } 1566 if (txEvent & TX_EVENT_SQE_ERR) { 1567 aprint_error_dev(sc->sc_dev, "SQE error\n"); 1568 } 1569 if (txEvent & TX_EVENT_OUT_WIN) { 1570 aprint_error_dev(sc->sc_dev, 1571 "out-of-window collision\n"); 1572 } 1573 if (txEvent & TX_EVENT_JABBER) { 1574 aprint_error_dev(sc->sc_dev, "jabber\n"); 1575 } 1576 if (txEvent & TX_EVENT_16_COLL) { 1577 aprint_error_dev(sc->sc_dev, "16 collisions\n"); 1578 } 1579 } 1580 } 1581 else { 1582 /* Transmission successful, carrier is up. */ 1583 sc->sc_carrier = 1; 1584 #ifdef SHARK 1585 ledNetActive(); 1586 #endif 1587 } 1588 1589 /* Add the number of collisions for this frame */ 1590 if (txEvent & TX_EVENT_16_COLL) { 1591 ifp->if_collisions += 16; 1592 } else { 1593 ifp->if_collisions += ((txEvent & TX_EVENT_COLL_MASK) >> 11); 1594 } 1595 1596 ifp->if_opackets++; 1597 1598 /* Transmission is no longer in progress */ 1599 sc->sc_txbusy = FALSE; 1600 1601 /* If there is more to transmit */ 1602 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 1603 /* Start the next transmission */ 1604 cs_start_output(ifp); 1605 } 1606 } 1607 1608 void 1609 cs_print_rx_errors(struct cs_softc *sc, u_int16_t rxEvent) 1610 { 1611 1612 if (rxEvent & RX_EVENT_RUNT) 1613 aprint_error_dev(sc->sc_dev, "runt\n"); 1614 1615 if (rxEvent & RX_EVENT_X_DATA) 1616 aprint_error_dev(sc->sc_dev, "extra data\n"); 1617 1618 if (rxEvent & RX_EVENT_CRC_ERR) { 1619 if (rxEvent & RX_EVENT_DRIBBLE) 1620 aprint_error_dev(sc->sc_dev, "alignment error\n"); 1621 else 1622 aprint_error_dev(sc->sc_dev, "CRC error\n"); 1623 } else { 1624 if (rxEvent & RX_EVENT_DRIBBLE) 1625 aprint_error_dev(sc->sc_dev, "dribble bits\n"); 1626 } 1627 } 1628 1629 void 1630 cs_receive_event(struct cs_softc *sc, u_int16_t rxEvent) 1631 { 1632 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1633 1634 /* If the frame was not received OK */ 1635 if (!(rxEvent & RX_EVENT_RX_OK)) { 1636 /* Increment the input error count */ 1637 ifp->if_ierrors++; 1638 1639 /* 1640 * If debugging is enabled then log error messages. 1641 */ 1642 if (ifp->if_flags & IFF_DEBUG) { 1643 if (rxEvent != REG_NUM_RX_EVENT) { 1644 cs_print_rx_errors(sc, rxEvent); 1645 1646 /* 1647 * Must read the length of all received 1648 * frames 1649 */ 1650 CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1651 1652 /* Skip the received frame */ 1653 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1654 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | 1655 RX_CFG_SKIP); 1656 } else { 1657 aprint_error_dev(sc->sc_dev, "implied skip\n"); 1658 } 1659 } 1660 } else { 1661 /* 1662 * process the received frame and pass it up to the upper 1663 * layers. 1664 */ 1665 cs_process_receive(sc); 1666 } 1667 } 1668 1669 void 1670 cs_ether_input(struct cs_softc *sc, struct mbuf *m) 1671 { 1672 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1673 1674 ifp->if_ipackets++; 1675 1676 /* 1677 * Check if there's a BPF listener on this interface. 1678 * If so, hand off the raw packet to BPF. 1679 */ 1680 bpf_mtap(ifp, m); 1681 1682 /* Pass the packet up. */ 1683 (*ifp->if_input)(ifp, m); 1684 } 1685 1686 void 1687 cs_process_receive(struct cs_softc *sc) 1688 { 1689 struct ifnet *ifp; 1690 struct mbuf *m; 1691 int totlen; 1692 u_int16_t *pBuff, *pBuffLimit; 1693 int pad; 1694 unsigned int frameOffset = 0; /* XXX: gcc */ 1695 1696 #ifdef SHARK 1697 ledNetActive(); 1698 #endif 1699 1700 ifp = &sc->sc_ethercom.ec_if; 1701 1702 /* Received a packet; carrier is up. */ 1703 sc->sc_carrier = 1; 1704 1705 if (sc->sc_memorymode) { 1706 /* Initialize the frame offset */ 1707 frameOffset = PKTPG_RX_LENGTH; 1708 1709 /* Get the length of the received frame */ 1710 totlen = CS_READ_PACKET_PAGE(sc, frameOffset); 1711 frameOffset += 2; 1712 } 1713 else { 1714 /* drop status */ 1715 CS_READ_PORT(sc, PORT_RXTX_DATA); 1716 1717 /* Get the length of the received frame */ 1718 totlen = CS_READ_PORT(sc, PORT_RXTX_DATA); 1719 } 1720 1721 if (totlen > ETHER_MAX_LEN) { 1722 aprint_error_dev(sc->sc_dev, "invalid packet length %d\n", 1723 totlen); 1724 1725 /* skip the received frame */ 1726 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1727 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1728 return; 1729 } 1730 1731 MGETHDR(m, M_DONTWAIT, MT_DATA); 1732 if (m == 0) { 1733 aprint_error_dev(sc->sc_dev, 1734 "cs_process_receive: unable to allocate mbuf\n"); 1735 ifp->if_ierrors++; 1736 /* 1737 * couldn't allocate an mbuf so things are not good, may as 1738 * well drop the packet I think. 1739 * 1740 * have already read the length so we should be right to skip 1741 * the packet. 1742 */ 1743 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1744 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1745 return; 1746 } 1747 m->m_pkthdr.rcvif = ifp; 1748 m->m_pkthdr.len = totlen; 1749 1750 /* number of bytes to align ip header on word boundary for ipintr */ 1751 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1752 1753 /* 1754 * alloc mbuf cluster if we need. 1755 * we need 1 byte spare because following 1756 * packet read loop can overrun. 1757 */ 1758 if (totlen + pad + 1 > MHLEN) { 1759 MCLGET(m, M_DONTWAIT); 1760 if ((m->m_flags & M_EXT) == 0) { 1761 /* couldn't allocate an mbuf cluster */ 1762 aprint_error_dev(sc->sc_dev, 1763 "cs_process_receive: " 1764 "unable to allocate a cluster\n"); 1765 m_freem(m); 1766 1767 /* skip the received frame */ 1768 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1769 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1770 return; 1771 } 1772 } 1773 1774 /* align ip header on word boundary for ipintr */ 1775 m->m_data += pad; 1776 1777 m->m_len = totlen; 1778 pBuff = mtod(m, u_int16_t *); 1779 1780 /* now read the data from the chip */ 1781 if (sc->sc_memorymode) { 1782 pBuffLimit = pBuff + (totlen + 1) / 2; /* don't want to go over */ 1783 while (pBuff < pBuffLimit) { 1784 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1785 frameOffset += 2; 1786 } 1787 } 1788 else { 1789 IO_READ_MULTI_2(sc, PORT_RXTX_DATA, pBuff, (totlen + 1)>>1); 1790 } 1791 1792 cs_ether_input(sc, m); 1793 } 1794 1795 void 1796 cs_process_rx_early(struct cs_softc *sc) 1797 { 1798 struct ifnet *ifp; 1799 struct mbuf *m; 1800 u_int16_t frameCount, oldFrameCount; 1801 u_int16_t rxEvent; 1802 u_int16_t *pBuff; 1803 int pad; 1804 unsigned int frameOffset; 1805 1806 1807 ifp = &sc->sc_ethercom.ec_if; 1808 1809 /* Initialize the frame offset */ 1810 frameOffset = PKTPG_RX_FRAME; 1811 frameCount = 0; 1812 1813 MGETHDR(m, M_DONTWAIT, MT_DATA); 1814 if (m == 0) { 1815 aprint_error_dev(sc->sc_dev, 1816 "cs_process_rx_early: unable to allocate mbuf\n"); 1817 ifp->if_ierrors++; 1818 /* 1819 * couldn't allocate an mbuf so things are not good, may as 1820 * well drop the packet I think. 1821 * 1822 * have already read the length so we should be right to skip 1823 * the packet. 1824 */ 1825 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1826 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1827 return; 1828 } 1829 m->m_pkthdr.rcvif = ifp; 1830 /* 1831 * save processing by always using a mbuf cluster, guaranteed to fit 1832 * packet 1833 */ 1834 MCLGET(m, M_DONTWAIT); 1835 if ((m->m_flags & M_EXT) == 0) { 1836 /* couldn't allocate an mbuf cluster */ 1837 aprint_error_dev(sc->sc_dev, 1838 "cs_process_rx_early: unable to allocate a cluster\n"); 1839 m_freem(m); 1840 /* skip the frame */ 1841 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1842 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1843 return; 1844 } 1845 1846 /* align ip header on word boundary for ipintr */ 1847 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1848 m->m_data += pad; 1849 1850 /* set up the buffer pointer to point to the data area */ 1851 pBuff = mtod(m, u_int16_t *); 1852 1853 /* 1854 * now read the frame byte counter until we have finished reading the 1855 * frame 1856 */ 1857 oldFrameCount = 0; 1858 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1859 while ((frameCount != 0) && (frameCount < MCLBYTES)) { 1860 for (; oldFrameCount < frameCount; oldFrameCount += 2) { 1861 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1862 frameOffset += 2; 1863 } 1864 1865 /* read the new count from the chip */ 1866 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1867 } 1868 1869 /* update the mbuf counts */ 1870 m->m_len = oldFrameCount; 1871 m->m_pkthdr.len = oldFrameCount; 1872 1873 /* now check the Rx Event register */ 1874 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1875 1876 if ((rxEvent & RX_EVENT_RX_OK) != 0) { 1877 /* 1878 * do an implied skip, it seems to be more reliable than a 1879 * forced skip. 1880 */ 1881 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_STATUS); 1882 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1883 1884 /* 1885 * now read the RX_EVENT register to perform an implied skip. 1886 */ 1887 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1888 1889 cs_ether_input(sc, m); 1890 } else { 1891 m_freem(m); 1892 ifp->if_ierrors++; 1893 } 1894 } 1895 1896 void 1897 cs_start_output(struct ifnet *ifp) 1898 { 1899 struct cs_softc *sc; 1900 struct mbuf *pMbuf; 1901 struct mbuf *pMbufChain; 1902 u_int16_t BusStatus; 1903 u_int16_t Length; 1904 int txLoop = 0; 1905 int dropout = 0; 1906 1907 sc = ifp->if_softc; 1908 1909 /* check that the interface is up and running */ 1910 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1911 return; 1912 } 1913 1914 /* Don't interrupt a transmission in progress */ 1915 if (sc->sc_txbusy) { 1916 return; 1917 } 1918 1919 /* this loop will only run through once if transmission is successful */ 1920 /* 1921 * While there are packets to transmit and a transmit is not in 1922 * progress 1923 */ 1924 while (sc->sc_txbusy == 0 && dropout == 0) { 1925 IFQ_DEQUEUE(&ifp->if_snd, pMbufChain); 1926 if (pMbufChain == NULL) 1927 break; 1928 1929 /* 1930 * If BPF is listening on this interface, let it see the packet 1931 * before we commit it to the wire. 1932 */ 1933 bpf_mtap(ifp, pMbufChain); 1934 1935 /* Find the total length of the data to transmit */ 1936 Length = 0; 1937 for (pMbuf = pMbufChain; pMbuf != NULL; pMbuf = pMbuf->m_next) 1938 Length += pMbuf->m_len; 1939 1940 do { 1941 /* 1942 * Request that the transmit be started after all 1943 * data has been copied 1944 * 1945 * In IO mode must write to the IO port not the packet 1946 * page address 1947 * 1948 * If this is changed to start transmission after a 1949 * small amount of data has been copied you tend to 1950 * get packet missed errors i think because the ISA 1951 * bus is too slow. Or possibly the copy routine is 1952 * not streamlined enough. 1953 */ 1954 if (sc->sc_memorymode) { 1955 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CMD, 1956 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1957 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_LENGTH, Length); 1958 } 1959 else { 1960 CS_WRITE_PORT(sc, PORT_TX_CMD, 1961 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1962 CS_WRITE_PORT(sc, PORT_TX_LENGTH, Length); 1963 } 1964 1965 /* 1966 * Adjust early-transmit machinery. 1967 */ 1968 if (--sc->sc_xe_togo == 0) { 1969 sc->sc_xe_ent = 1970 cs_xmit_early_table[sc->sc_xe_ent].better; 1971 sc->sc_xe_togo = 1972 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1973 } 1974 /* 1975 * Read the BusStatus register which indicates 1976 * success of the request 1977 */ 1978 BusStatus = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_ST); 1979 1980 /* 1981 * If there was an error in the transmit bid free the 1982 * mbuf and go on. This is presuming that mbuf is 1983 * corrupt. 1984 */ 1985 if (BusStatus & BUS_ST_TX_BID_ERR) { 1986 aprint_error_dev(sc->sc_dev, 1987 "transmit bid error (too big)"); 1988 1989 /* Discard the bad mbuf chain */ 1990 m_freem(pMbufChain); 1991 sc->sc_ethercom.ec_if.if_oerrors++; 1992 1993 /* Loop up to transmit the next chain */ 1994 txLoop = 0; 1995 } else { 1996 if (BusStatus & BUS_ST_RDY4TXNOW) { 1997 /* 1998 * The chip is ready for transmission 1999 * now 2000 */ 2001 /* 2002 * Copy the frame to the chip to 2003 * start transmission 2004 */ 2005 cs_copy_tx_frame(sc, pMbufChain); 2006 2007 /* Free the mbuf chain */ 2008 m_freem(pMbufChain); 2009 2010 /* Transmission is now in progress */ 2011 sc->sc_txbusy = TRUE; 2012 txLoop = 0; 2013 } else { 2014 /* 2015 * if we get here we want to try 2016 * again with the same mbuf, until 2017 * the chip lets us transmit. 2018 */ 2019 txLoop++; 2020 if (txLoop > CS_OUTPUT_LOOP_MAX) { 2021 /* Free the mbuf chain */ 2022 m_freem(pMbufChain); 2023 /* 2024 * Transmission is not in 2025 * progress 2026 */ 2027 sc->sc_txbusy = FALSE; 2028 /* 2029 * Increment the output error 2030 * count 2031 */ 2032 ifp->if_oerrors++; 2033 /* 2034 * exit the routine and drop 2035 * the packet. 2036 */ 2037 txLoop = 0; 2038 dropout = 1; 2039 } 2040 } 2041 } 2042 } while (txLoop); 2043 } 2044 } 2045 2046 void 2047 cs_copy_tx_frame(struct cs_softc *sc, struct mbuf *m0) 2048 { 2049 struct mbuf *m; 2050 int len, leftover, frameoff; 2051 u_int16_t dbuf; 2052 u_int8_t *p; 2053 #ifdef DIAGNOSTIC 2054 u_int8_t *lim; 2055 #endif 2056 2057 /* Initialize frame pointer and data port address */ 2058 frameoff = PKTPG_TX_FRAME; 2059 2060 /* start out with no leftover data */ 2061 leftover = 0; 2062 dbuf = 0; 2063 2064 /* Process the chain of mbufs */ 2065 for (m = m0; m != NULL; m = m->m_next) { 2066 /* 2067 * Process all of the data in a single mbuf. 2068 */ 2069 p = mtod(m, u_int8_t *); 2070 len = m->m_len; 2071 #ifdef DIAGNOSTIC 2072 lim = p + len; 2073 #endif 2074 2075 while (len > 0) { 2076 if (leftover) { 2077 /* 2078 * Data left over (from mbuf or realignment). 2079 * Buffer the next byte, and write it and 2080 * the leftover data out. 2081 */ 2082 dbuf |= *p++ << 8; 2083 len--; 2084 if (sc->sc_memorymode) { 2085 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 2086 frameoff += 2; 2087 } 2088 else { 2089 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 2090 } 2091 leftover = 0; 2092 } else if ((long) p & 1) { 2093 /* 2094 * Misaligned data. Buffer the next byte. 2095 */ 2096 dbuf = *p++; 2097 len--; 2098 leftover = 1; 2099 } else { 2100 /* 2101 * Aligned data. This is the case we like. 2102 * 2103 * Write-region out as much as we can, then 2104 * buffer the remaining byte (if any). 2105 */ 2106 leftover = len & 1; 2107 len &= ~1; 2108 if (sc->sc_memorymode) { 2109 MEM_WRITE_REGION_2(sc, frameoff, 2110 (u_int16_t *) p, len >> 1); 2111 frameoff += len; 2112 } 2113 else { 2114 IO_WRITE_MULTI_2(sc, 2115 PORT_RXTX_DATA, (u_int16_t *)p, len >> 1); 2116 } 2117 p += len; 2118 2119 if (leftover) 2120 dbuf = *p++; 2121 len = 0; 2122 } 2123 } 2124 if (len < 0) 2125 panic("cs_copy_tx_frame: negative len"); 2126 #ifdef DIAGNOSTIC 2127 if (p != lim) 2128 panic("cs_copy_tx_frame: p != lim"); 2129 #endif 2130 } 2131 if (leftover) { 2132 if (sc->sc_memorymode) { 2133 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 2134 } 2135 else { 2136 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 2137 } 2138 } 2139 } 2140 2141 static int 2142 cs_enable(struct cs_softc *sc) 2143 { 2144 2145 if (CS_IS_ENABLED(sc) == 0) { 2146 if (sc->sc_enable != NULL) { 2147 int error; 2148 2149 error = (*sc->sc_enable)(sc); 2150 if (error) 2151 return (error); 2152 } 2153 sc->sc_cfgflags |= CFGFLG_ENABLED; 2154 } 2155 2156 return (0); 2157 } 2158 2159 static void 2160 cs_disable(struct cs_softc *sc) 2161 { 2162 2163 if (CS_IS_ENABLED(sc)) { 2164 if (sc->sc_disable != NULL) 2165 (*sc->sc_disable)(sc); 2166 2167 sc->sc_cfgflags &= ~CFGFLG_ENABLED; 2168 } 2169 } 2170 2171 static void 2172 cs_stop(struct ifnet *ifp, int disable) 2173 { 2174 struct cs_softc *sc = ifp->if_softc; 2175 2176 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 0); 2177 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, 0); 2178 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 0); 2179 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 0); 2180 2181 if (disable) { 2182 cs_disable(sc); 2183 } 2184 2185 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2186 } 2187 2188 int 2189 cs_activate(device_t self, enum devact act) 2190 { 2191 struct cs_softc *sc = device_private(self); 2192 2193 switch (act) { 2194 case DVACT_DEACTIVATE: 2195 if_deactivate(&sc->sc_ethercom.ec_if); 2196 return 0; 2197 default: 2198 return EOPNOTSUPP; 2199 } 2200 } 2201