1 /* $NetBSD: cpc700.c,v 1.22 2021/04/24 23:36:55 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart@augustsson.net) at Sandburst Corp. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * The IBM CPC700 is a bridge chip for the PowerPC. It contains 34 * - CPU interface 35 * - DRAM controller 36 * - PCI bus master & slave controller 37 * - interrupt controller 38 * - timer 39 * - two UARTs 40 * - two IIC ports 41 * 42 * This driver handles the overall device and enumeration of the 43 * supported subdevices. NetBSD knows how to handle: 44 * - PCI master 45 * - interrupt controller 46 * - UARTs 47 * Skeleton drivers are provided for the timer and IIC. 48 * 49 * XXX This driver assumes that there is only one instance of it. 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: cpc700.c,v 1.22 2021/04/24 23:36:55 thorpej Exp $"); 54 55 #include "pci.h" 56 #include "opt_pci.h" 57 58 #include <sys/param.h> 59 #include <sys/device.h> 60 #include <sys/malloc.h> 61 #include <sys/systm.h> 62 63 #include <sys/bus.h> 64 #include "locators.h" 65 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pciconf.h> 69 70 #include <dev/ic/cpc700reg.h> 71 #include <dev/ic/cpc700var.h> 72 #include <dev/ic/cpc700uic.h> 73 74 union attach_args { 75 struct pcibus_attach_args pba; 76 struct cpcbus_attach_args cba; 77 }; 78 79 80 void 81 cpc_attach(device_t self, pci_chipset_tag_t pc, bus_space_tag_t mem, 82 bus_space_tag_t pciio, bus_dma_tag_t tag, int attachpci, 83 uint freq); 84 85 static bus_space_tag_t the_cpc_tag; 86 static bus_space_handle_t the_cpc_handle; 87 #define INL(a) bus_space_read_stream_4(the_cpc_tag, the_cpc_handle, (a)) 88 #define OUTL(a, d) bus_space_write_stream_4(the_cpc_tag, the_cpc_handle, (a), d) 89 90 #define PCI_IO_START CPC_PCI_IO_START 91 #define PCI_IO_END CPC_PCI_IO_END 92 #define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1) 93 94 #define PCI_MEM_START CPC_PCI_MEM_BASE 95 #define PCI_MEM_END CPC_PCI_MEM_END 96 #define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1) 97 98 static int 99 cpc_print(void *aux, const char *pnp) 100 { 101 struct cpcbus_attach_args *caa = aux; 102 103 if (pnp) 104 aprint_normal("%s at %s", caa->cpca_name, pnp); 105 106 aprint_normal(" addr 0x%08x", caa->cpca_addr); 107 if (caa->cpca_irq != CPCBUSCF_IRQ_DEFAULT) 108 aprint_normal(" irq %d", caa->cpca_irq); 109 110 return (UNCONF); 111 } 112 113 static int 114 cpc_submatch(device_t parent, cfdata_t cf, 115 const int *ldesc, void *aux) 116 { 117 struct cpcbus_attach_args *caa = aux; 118 119 if (cf->cf_loc[CPCBUSCF_ADDR] != caa->cpca_addr) 120 return (0); 121 122 return (config_match(parent, cf, aux)); 123 } 124 125 /* 126 * Attach the cpc. 127 */ 128 void 129 cpc_attach(device_t self, pci_chipset_tag_t pc, bus_space_tag_t mem, 130 bus_space_tag_t pciio, bus_dma_tag_t dma, int attachpci, 131 uint freq) 132 { 133 union attach_args aa; 134 int i; 135 pcitag_t tag; 136 pcireg_t erren; 137 pcireg_t v; 138 static struct { 139 const char *name; 140 bus_addr_t addr; 141 int irq; 142 } devs[] = { 143 { "com", CPC_COM0, CPC_IB_UART_0 }, 144 { "com", CPC_COM1, CPC_IB_UART_1 }, 145 { "cpctim", CPC_TIMER, CPCBUSCF_IRQ_DEFAULT }, 146 { "cpciic", CPC_IIC0, CPC_IB_IIC_0 }, 147 { "cpciic", CPC_IIC1, CPC_IB_IIC_1 }, 148 { NULL, 0 } 149 }; 150 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 151 #ifdef PCI_CONFIGURE_VERBOSE 152 extern int pci_conf_debug; 153 154 pci_conf_debug = 1; 155 #endif 156 #endif 157 158 printf(": IBM CPC700\n"); 159 160 the_cpc_tag = mem; 161 if (bus_space_map(mem, CPC_UIC_BASE, CPC_UIC_SIZE, 0, 162 &the_cpc_handle)) { 163 aprint_error_dev(self, "can't map i/o space\n"); 164 return; 165 } 166 167 aa.cba.cpca_tag = mem; 168 aa.cba.cpca_freq = freq; 169 for (i = 0; devs[i].name; i++) { 170 aa.cba.cpca_name = devs[i].name; 171 aa.cba.cpca_addr = devs[i].addr; 172 aa.cba.cpca_irq = devs[i].irq; 173 config_found(self, &aa.cba, cpc_print, 174 CFARG_SUBMATCH, cpc_submatch, 175 CFARG_IATTR, "cpcbus", 176 CFARG_EOL); 177 } 178 179 tag = pci_make_tag(pc, 0, 0, 0); 180 181 aa.pba.pba_iot = pciio; 182 aa.pba.pba_memt = mem; 183 aa.pba.pba_dmat = dma; 184 aa.pba.pba_pc = pc; 185 aa.pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY; 186 aa.pba.pba_bus = 0; 187 188 /* Save PCI error condition reg. */ 189 erren = pci_conf_read(pc, tag, CPC_PCI_BRDGERR); 190 /* Don't generate errors during probe. */ 191 pci_conf_write(pc, tag, CPC_PCI_BRDGERR, 0); 192 193 /* Program MITL */ 194 v = pci_conf_read(pc, tag, CPC_BRIDGE_OPTIONS2); 195 v &= ~(CPC_BRIDGE_O2_ILAT_MASK | CPC_BRIDGE_O2_SLAT_MASK); 196 v |= (CPC_BRIDGE_O2_ILAT_PRIM_ASYNC << CPC_BRIDGE_O2_ILAT_SHIFT) | 197 (CPC_BRIDGE_O2_2LAT_PRIM_ASYNC << CPC_BRIDGE_O2_SLAT_SHIFT); 198 pci_conf_write(pc, tag, CPC_BRIDGE_OPTIONS2, v); 199 200 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 201 struct pciconf_resources *pcires = pciconf_resource_init(); 202 203 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, 204 PCI_IO_START, PCI_IO_SIZE); 205 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 206 PCI_MEM_START, PCI_MEM_SIZE); 207 208 pci_configure_bus(0, pcires, 0, 32); 209 #endif 210 211 config_found(self, &aa.pba, pcibusprint, 212 CFARG_IATTR, "pcibus", 213 CFARG_EOL); 214 215 /* Restore error triggers, and clear errors */ 216 pci_conf_write(pc, tag, CPC_PCI_BRDGERR, erren | CPC_PCI_CLEARERR); 217 } 218 219 /***************************************************************************/ 220 221 /* 222 * Interrupt controller. 223 */ 224 225 void 226 cpc700_init_intr(bus_space_tag_t bt, bus_space_handle_t bh, 227 u_int32_t active, u_int32_t level) 228 { 229 /* XXX */ 230 the_cpc_tag = bt; 231 the_cpc_handle = bh; 232 /* 233 * See CPC700 manual for information about what 234 * interrupts have which properties. 235 */ 236 OUTL(CPC_UIC_SR, 0xffffffff); /* clear all intrs */ 237 OUTL(CPC_UIC_ER, 0x00000000); /* disable all intrs */ 238 OUTL(CPC_UIC_CR, 0xffffffff); /* gen INT not MCP */ 239 OUTL(CPC_UIC_PR, 0xffff8000 | active); /* 0 = active low */ 240 OUTL(CPC_UIC_TR, 0xc0000000 | level); /* 0 = level intr */ 241 OUTL(CPC_UIC_VR, CPC_UIC_CVR_PRI); /* intr 0 is highest */ 242 } 243 244 int 245 cpc700_read_irq(void) 246 { 247 int irq; 248 u_int32_t irqs; 249 250 irqs = INL(CPC_UIC_MSR); 251 for (irq = 0; irq < ICU_LEN; irq++) { 252 if (irqs & CPC_INTR_MASK(irq)) 253 return (irq); 254 } 255 return (-1); 256 } 257 258 void 259 cpc700_eoi(int irq) 260 { 261 OUTL(CPC_UIC_SR, CPC_INTR_MASK(irq)); 262 } 263 264 void 265 cpc700_disable_irq(int irq) 266 { 267 u_int32_t reg; 268 269 reg = INL(CPC_UIC_ER); 270 reg &= ~CPC_INTR_MASK(irq); 271 OUTL(CPC_UIC_ER, reg); 272 } 273 274 void 275 cpc700_enable_irq(int irq) 276 { 277 u_int32_t reg; 278 279 reg = INL(CPC_UIC_ER); 280 reg |= CPC_INTR_MASK(irq); 281 OUTL(CPC_UIC_ER, reg); 282 } 283